You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.

7753 lines
285 KiB

  1. \input texinfo @c -*-texinfo-*-
  2. @c %**start of header
  3. @setfilename
  4. @settitle OpenOCD User's Guide
  5. @dircategory Development
  6. @direntry
  7. * OpenOCD: (openocd). OpenOCD User's Guide
  8. @end direntry
  9. @paragraphindent 0
  10. @c %**end of header
  11. @include version.texi
  12. @copying
  13. This User's Guide documents
  14. release @value{VERSION},
  15. dated @value{UPDATED},
  16. of the Open On-Chip Debugger (OpenOCD).
  17. @itemize @bullet
  18. @item Copyright @copyright{} 2008 The OpenOCD Project
  19. @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{}
  20. @item Copyright @copyright{} 2008 Oyvind Harboe @email{}
  21. @item Copyright @copyright{} 2008 Duane Ellis @email{}
  22. @item Copyright @copyright{} 2009-2010 David Brownell
  23. @end itemize
  24. @quotation
  25. Permission is granted to copy, distribute and/or modify this document
  26. under the terms of the GNU Free Documentation License, Version 1.2 or
  27. any later version published by the Free Software Foundation; with no
  28. Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
  29. Texts. A copy of the license is included in the section entitled ``GNU
  30. Free Documentation License''.
  31. @end quotation
  32. @end copying
  33. @titlepage
  34. @titlefont{@emph{Open On-Chip Debugger:}}
  35. @sp 1
  36. @title OpenOCD User's Guide
  37. @subtitle for release @value{VERSION}
  38. @subtitle @value{UPDATED}
  39. @page
  40. @vskip 0pt plus 1filll
  41. @insertcopying
  42. @end titlepage
  43. @summarycontents
  44. @contents
  45. @ifnottex
  46. @node Top
  47. @top OpenOCD User's Guide
  48. @insertcopying
  49. @end ifnottex
  50. @menu
  51. * About:: About OpenOCD
  52. * Developers:: OpenOCD Developer Resources
  53. * JTAG Hardware Dongles:: JTAG Hardware Dongles
  54. * About JIM-Tcl:: About JIM-Tcl
  55. * Running:: Running OpenOCD
  56. * OpenOCD Project Setup:: OpenOCD Project Setup
  57. * Config File Guidelines:: Config File Guidelines
  58. * Daemon Configuration:: Daemon Configuration
  59. * Interface - Dongle Configuration:: Interface - Dongle Configuration
  60. * Reset Configuration:: Reset Configuration
  61. * TAP Declaration:: TAP Declaration
  62. * CPU Configuration:: CPU Configuration
  63. * Flash Commands:: Flash Commands
  64. * NAND Flash Commands:: NAND Flash Commands
  65. * PLD/FPGA Commands:: PLD/FPGA Commands
  66. * General Commands:: General Commands
  67. * Architecture and Core Commands:: Architecture and Core Commands
  68. * JTAG Commands:: JTAG Commands
  69. * Boundary Scan Commands:: Boundary Scan Commands
  70. * TFTP:: TFTP
  71. * GDB and OpenOCD:: Using GDB and OpenOCD
  72. * Tcl Scripting API:: Tcl Scripting API
  73. * FAQ:: Frequently Asked Questions
  74. * Tcl Crash Course:: Tcl Crash Course
  75. * License:: GNU Free Documentation License
  76. @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
  77. @comment case issue with ``Index.html'' and ``index.html''
  78. @comment Occurs when creating ``--html --no-split'' output
  79. @comment This fix is based on:
  80. * OpenOCD Concept Index:: Concept Index
  81. * Command and Driver Index:: Command and Driver Index
  82. @end menu
  83. @node About
  84. @unnumbered About
  85. @cindex about
  86. OpenOCD was created by Dominic Rath as part of a diploma thesis written at the
  87. University of Applied Sciences Augsburg (@uref{}).
  88. Since that time, the project has grown into an active open-source project,
  89. supported by a diverse community of software and hardware developers from
  90. around the world.
  91. @section What is OpenOCD?
  92. @cindex TAP
  93. @cindex JTAG
  94. The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
  95. in-system programming and boundary-scan testing for embedded target
  96. devices.
  97. @b{JTAG:} OpenOCD uses a ``hardware interface dongle'' to communicate
  98. with the JTAG (IEEE 1149.1) compliant TAPs on your target board.
  99. A @dfn{TAP} is a ``Test Access Port'', a module which processes
  100. special instructions and data. TAPs are daisy-chained within and
  101. between chips and boards.
  102. @b{Dongles:} OpenOCD currently supports many types of hardware dongles: USB
  103. based, parallel port based, and other standalone boxes that run
  104. OpenOCD internally. @xref{JTAG Hardware Dongles}.
  105. @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
  106. ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x) and
  107. Cortex-M3 (Stellaris LM3 and ST STM32) based cores to be
  108. debugged via the GDB protocol.
  109. @b{Flash Programing:} Flash writing is supported for external CFI
  110. compatible NOR flashes (Intel and AMD/Spansion command set) and several
  111. internal flashes (LPC1700, LPC2000, AT91SAM7, AT91SAM3U, STR7x, STR9x, LM3, and
  112. STM32x). Preliminary support for various NAND flash controllers
  113. (LPC3180, Orion, S3C24xx, more) controller is included.
  114. @section OpenOCD Web Site
  115. The OpenOCD web site provides the latest public news from the community:
  116. @uref{}
  117. @section Latest User's Guide:
  118. The user's guide you are now reading may not be the latest one
  119. available. A version for more recent code may be available.
  120. Its HTML form is published irregularly at:
  121. @uref{}
  122. PDF form is likewise published at:
  123. @uref{}
  124. @section OpenOCD User's Forum
  125. There is an OpenOCD forum (phpBB) hosted by SparkFun,
  126. which might be helpful to you. Note that if you want
  127. anything to come to the attention of developers, you
  128. should post it to the OpenOCD Developer Mailing List
  129. instead of this forum.
  130. @uref{}
  131. @node Developers
  132. @chapter OpenOCD Developer Resources
  133. @cindex developers
  134. If you are interested in improving the state of OpenOCD's debugging and
  135. testing support, new contributions will be welcome. Motivated developers
  136. can produce new target, flash or interface drivers, improve the
  137. documentation, as well as more conventional bug fixes and enhancements.
  138. The resources in this chapter are available for developers wishing to explore
  139. or expand the OpenOCD source code.
  140. @section OpenOCD GIT Repository
  141. During the 0.3.x release cycle, OpenOCD switched from Subversion to
  142. a GIT repository hosted at SourceForge. The repository URL is:
  143. @uref{git://}
  144. You may prefer to use a mirror and the HTTP protocol:
  145. @uref{}
  146. With standard GIT tools, use @command{git clone} to initialize
  147. a local repository, and @command{git pull} to update it.
  148. There are also gitweb pages letting you browse the repository
  149. with a web browser, or download arbitrary snapshots without
  150. needing a GIT client:
  151. @uref{}
  152. @uref{}
  153. The @file{README} file contains the instructions for building the project
  154. from the repository or a snapshot.
  155. Developers that want to contribute patches to the OpenOCD system are
  156. @b{strongly} encouraged to work against mainline.
  157. Patches created against older versions may require additional
  158. work from their submitter in order to be updated for newer releases.
  159. @section Doxygen Developer Manual
  160. During the 0.2.x release cycle, the OpenOCD project began
  161. providing a Doxygen reference manual. This document contains more
  162. technical information about the software internals, development
  163. processes, and similar documentation:
  164. @uref{}
  165. This document is a work-in-progress, but contributions would be welcome
  166. to fill in the gaps. All of the source files are provided in-tree,
  167. listed in the Doxyfile configuration in the top of the source tree.
  168. @section OpenOCD Developer Mailing List
  169. The OpenOCD Developer Mailing List provides the primary means of
  170. communication between developers:
  171. @uref{}
  172. Discuss and submit patches to this list.
  173. The @file{PATCHES.txt} file contains basic information about how
  174. to prepare patches.
  175. @section OpenOCD Bug Database
  176. During the 0.4.x release cycle the OpenOCD project team began
  177. using Trac for its bug database:
  178. @uref{}
  179. @node JTAG Hardware Dongles
  180. @chapter JTAG Hardware Dongles
  181. @cindex dongles
  182. @cindex FTDI
  183. @cindex wiggler
  184. @cindex zy1000
  185. @cindex printer port
  186. @cindex USB Adapter
  187. @cindex RTCK
  188. Defined: @b{dongle}: A small device that plugins into a computer and serves as
  189. an adapter .... [snip]
  190. In the OpenOCD case, this generally refers to @b{a small adapater} one
  191. attaches to your computer via USB or the Parallel Printer Port. The
  192. execption being the Zylin ZY1000 which is a small box you attach via
  193. an ethernet cable. The Zylin ZY1000 has the advantage that it does not
  194. require any drivers to be installed on the developer PC. It also has
  195. a built in web interface. It supports RTCK/RCLK or adaptive clocking
  196. and has a built in relay to power cycle targets remotely.
  197. @section Choosing a Dongle
  198. There are several things you should keep in mind when choosing a dongle.
  199. @enumerate
  200. @item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
  201. Does your dongle support it? You might need a level converter.
  202. @item @b{Pinout} What pinout does your target board use?
  203. Does your dongle support it? You may be able to use jumper
  204. wires, or an "octopus" connector, to convert pinouts.
  205. @item @b{Connection} Does your computer have the USB, printer, or
  206. Ethernet port needed?
  207. @item @b{RTCK} Do you require RTCK? Also known as ``adaptive clocking''
  208. @end enumerate
  209. @section Stand alone Systems
  210. @b{ZY1000} See: @url{} Technically, not a
  211. dongle, but a standalone box. The ZY1000 has the advantage that it does
  212. not require any drivers installed on the developer PC. It also has
  213. a built in web interface. It supports RTCK/RCLK or adaptive clocking
  214. and has a built in relay to power cycle targets remotely.
  215. @section USB FT2232 Based
  216. There are many USB JTAG dongles on the market, many of them are based
  217. on a chip from ``Future Technology Devices International'' (FTDI)
  218. known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
  219. See: @url{} for more information.
  220. In summer 2009, USB high speed (480 Mbps) versions of these FTDI
  221. chips are starting to become available in JTAG adapters.
  222. @itemize @bullet
  223. @item @b{usbjtag}
  224. @* Link @url{}
  225. @item @b{jtagkey}
  226. @* See: @url{}
  227. @item @b{jtagkey2}
  228. @* See: @url{}
  229. @item @b{oocdlink}
  230. @* See: @url{} By Joern Kaipf
  231. @item @b{signalyzer}
  232. @* See: @url{}
  233. @item @b{Stellaris Eval Boards}
  234. @* See: @url{} - The Stellaris eval boards
  235. bundle FT2232-based JTAG and SWD support, which can be used to debug
  236. the Stellaris chips. Using separate JTAG adapters is optional.
  237. These boards can also be used as JTAG adapters to other target boards,
  238. disabling the Stellaris chip.
  239. @item @b{Luminary ICDI}
  240. @* See: @url{} - Luminary In-Circuit Debug
  241. Interface (ICDI) Boards are included in Stellaris LM3S9B90 and LM3S9B92
  242. Evaluation Kits. Like the non-detachable FT2232 support on the other
  243. Stellaris eval boards, they can be used to debug other target boards.
  244. @item @b{olimex-jtag}
  245. @* See: @url{}
  246. @item @b{flyswatter}
  247. @* See: @url{}
  248. @item @b{turtelizer2}
  249. @* See:
  250. @uref{, Turtelizer 2}, or
  251. @url{}
  252. @item @b{comstick}
  253. @* Link: @url{}
  254. @item @b{stm32stick}
  255. @* Link @url{}
  256. @item @b{axm0432_jtag}
  257. @* Axiom AXM-0432 Link @url{}
  258. @item @b{cortino}
  259. @* Link @url{}
  260. @end itemize
  261. @section USB-JTAG / Altera USB-Blaster compatibles
  262. These devices also show up as FTDI devices, but are not
  263. protocol-compatible with the FT2232 devices. They are, however,
  264. protocol-compatible among themselves. USB-JTAG devices typically consist
  265. of a FT245 followed by a CPLD that understands a particular protocol,
  266. or emulate this protocol using some other hardware.
  267. They may appear under different USB VID/PID depending on the particular
  268. product. The driver can be configured to search for any VID/PID pair
  269. (see the section on driver commands).
  270. @itemize
  271. @item @b{USB-JTAG} Kolja Waschk's USB Blaster-compatible adapter
  272. @* Link: @url{}
  273. @item @b{Altera USB-Blaster}
  274. @* Link: @url{}
  275. @end itemize
  276. @section USB JLINK based
  277. There are several OEM versions of the Segger @b{JLINK} adapter. It is
  278. an example of a micro controller based JTAG adapter, it uses an
  279. AT91SAM764 internally.
  280. @itemize @bullet
  281. @item @b{ATMEL SAMICE} Only works with ATMEL chips!
  282. @* Link: @url{}
  283. @item @b{SEGGER JLINK}
  284. @* Link: @url{}
  285. @item @b{IAR J-Link}
  286. @* Link: @url{}
  287. @end itemize
  288. @section USB RLINK based
  289. Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer, permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for SWD and not JTAG, thus not supported.
  290. @itemize @bullet
  291. @item @b{Raisonance RLink}
  292. @* Link: @url{}
  293. @item @b{STM32 Primer}
  294. @* Link: @url{}
  295. @item @b{STM32 Primer2}
  296. @* Link: @url{}
  297. @end itemize
  298. @section USB Other
  299. @itemize @bullet
  300. @item @b{USBprog}
  301. @* Link: @url{} - which uses an Atmel MEGA32 and a UBN9604
  302. @item @b{USB - Presto}
  303. @* Link: @url{}
  304. @item @b{Versaloon-Link}
  305. @* Link: @url{}
  306. @item @b{ARM-JTAG-EW}
  307. @* Link: @url{}
  308. @end itemize
  309. @section IBM PC Parallel Printer Port Based
  310. The two well known ``JTAG Parallel Ports'' cables are the Xilnx DLC5
  311. and the MacGraigor Wiggler. There are many clones and variations of
  312. these on the market.
  313. Note that parallel ports are becoming much less common, so if you
  314. have the choice you should probably avoid these adapters in favor
  315. of USB-based ones.
  316. @itemize @bullet
  317. @item @b{Wiggler} - There are many clones of this.
  318. @* Link: @url{}
  319. @item @b{DLC5} - From XILINX - There are many clones of this
  320. @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
  321. produced, PDF schematics are easily found and it is easy to make.
  322. @item @b{Amontec - JTAG Accelerator}
  323. @* Link: @url{}
  324. @item @b{GW16402}
  325. @* Link: @url{}
  326. @item @b{Wiggler2}
  327. @*@uref{,
  328. Improved parallel-port wiggler-style JTAG adapter}
  329. @item @b{Wiggler_ntrst_inverted}
  330. @* Yet another variation - See the source code, src/jtag/parport.c
  331. @item @b{old_amt_wiggler}
  332. @* Unknown - probably not on the market today
  333. @item @b{arm-jtag}
  334. @* Link: Most likely @url{} [another wiggler clone]
  335. @item @b{chameleon}
  336. @* Link: @url{}
  337. @item @b{Triton}
  338. @* Unknown.
  339. @item @b{Lattice}
  340. @* ispDownload from Lattice Semiconductor
  341. @url{}
  342. @item @b{flashlink}
  343. @* From ST Microsystems;
  344. @uref{,
  345. FlashLINK JTAG programing cable for PSD and uPSD}
  346. @end itemize
  347. @section Other...
  348. @itemize @bullet
  349. @item @b{ep93xx}
  350. @* An EP93xx based Linux machine using the GPIO pins directly.
  351. @item @b{at91rm9200}
  352. @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
  353. @end itemize
  354. @node About JIM-Tcl
  355. @chapter About JIM-Tcl
  356. @cindex JIM Tcl
  357. @cindex tcl
  358. OpenOCD includes a small ``Tcl Interpreter'' known as JIM-Tcl.
  359. This programming language provides a simple and extensible
  360. command interpreter.
  361. All commands presented in this Guide are extensions to JIM-Tcl.
  362. You can use them as simple commands, without needing to learn
  363. much of anything about Tcl.
  364. Alternatively, can write Tcl programs with them.
  365. You can learn more about JIM at its website, @url{}.
  366. @itemize @bullet
  367. @item @b{JIM vs. Tcl}
  368. @* JIM-TCL is a stripped down version of the well known Tcl language,
  369. which can be found here: @url{}. JIM-Tcl has far
  370. fewer features. JIM-Tcl is a single .C file and a single .H file and
  371. implements the basic Tcl command set. In contrast: Tcl 8.6 is a
  372. 4.2 MB .zip file containing 1540 files.
  373. @item @b{Missing Features}
  374. @* Our practice has been: Add/clone the real Tcl feature if/when
  375. needed. We welcome JIM Tcl improvements, not bloat.
  376. @item @b{Scripts}
  377. @* OpenOCD configuration scripts are JIM Tcl Scripts. OpenOCD's
  378. command interpreter today is a mixture of (newer)
  379. JIM-Tcl commands, and (older) the orginal command interpreter.
  380. @item @b{Commands}
  381. @* At the OpenOCD telnet command line (or via the GDB mon command) one
  382. can type a Tcl for() loop, set variables, etc.
  383. Some of the commands documented in this guide are implemented
  384. as Tcl scripts, from a @file{startup.tcl} file internal to the server.
  385. @item @b{Historical Note}
  386. @* JIM-Tcl was introduced to OpenOCD in spring 2008.
  387. @item @b{Need a crash course in Tcl?}
  388. @*@xref{Tcl Crash Course}.
  389. @end itemize
  390. @node Running
  391. @chapter Running
  392. @cindex command line options
  393. @cindex logfile
  394. @cindex directory search
  395. The @option{--help} option shows:
  396. @verbatim
  397. bash$ openocd --help
  398. --help | -h display this help
  399. --version | -v display OpenOCD version
  400. --file | -f use configuration file <name>
  401. --search | -s dir to search for config files and scripts
  402. --debug | -d set debug level <0-3>
  403. --log_output | -l redirect log output to file <name>
  404. --command | -c run <command>
  405. --pipe | -p use pipes when talking to gdb
  406. @end verbatim
  407. If you don't give any @option{-f} or @option{-c} options,
  408. OpenOCD tries to read the configuration file @file{openocd.cfg}.
  409. To specify one or more different
  410. configuration files, use @option{-f} options. For example:
  411. @example
  412. openocd -f config1.cfg -f config2.cfg -f config3.cfg
  413. @end example
  414. Configuration files and scripts are searched for in
  415. @enumerate
  416. @item the current directory,
  417. @item any search dir specified on the command line using the @option{-s} option,
  418. @item @file{$HOME/.openocd} (not on Windows),
  419. @item the site wide script library @file{$pkgdatadir/site} and
  420. @item the OpenOCD-supplied script library @file{$pkgdatadir/scripts}.
  421. @end enumerate
  422. The first found file with a matching file name will be used.
  423. @section Simple setup, no customization
  424. In the best case, you can use two scripts from one of the script
  425. libraries, hook up your JTAG adapter, and start the server ... and
  426. your JTAG setup will just work "out of the box". Always try to
  427. start by reusing those scripts, but assume you'll need more
  428. customization even if this works. @xref{OpenOCD Project Setup}.
  429. If you find a script for your JTAG adapter, and for your board or
  430. target, you may be able to hook up your JTAG adapter then start
  431. the server like:
  432. @example
  433. openocd -f interface/ADAPTER.cfg -f board/MYBOARD.cfg
  434. @end example
  435. You might also need to configure which reset signals are present,
  436. using @option{-c 'reset_config trst_and_srst'} or something similar.
  437. If all goes well you'll see output something like
  438. @example
  439. Open On-Chip Debugger 0.4.0 (2010-01-14-15:06)
  440. For bug reports, read
  442. Info : JTAG tap: lm3s.cpu tap/device found: 0x3ba00477
  443. (mfg: 0x23b, part: 0xba00, ver: 0x3)
  444. @end example
  445. Seeing that "tap/device found" message, and no warnings, means
  446. the JTAG communication is working. That's a key milestone, but
  447. you'll probably need more project-specific setup.
  448. @section What OpenOCD does as it starts
  449. OpenOCD starts by processing the configuration commands provided
  450. on the command line or, if there were no @option{-c command} or
  451. @option{-f file.cfg} options given, in @file{openocd.cfg}.
  452. @xref{Configuration Stage}.
  453. At the end of the configuration stage it verifies the JTAG scan
  454. chain defined using those commands; your configuration should
  455. ensure that this always succeeds.
  456. Normally, OpenOCD then starts running as a daemon.
  457. Alternatively, commands may be used to terminate the configuration
  458. stage early, perform work (such as updating some flash memory),
  459. and then shut down without acting as a daemon.
  460. Once OpenOCD starts running as a daemon, it waits for connections from
  461. clients (Telnet, GDB, Other) and processes the commands issued through
  462. those channels.
  463. If you are having problems, you can enable internal debug messages via
  464. the @option{-d} option.
  465. Also it is possible to interleave JIM-Tcl commands w/config scripts using the
  466. @option{-c} command line switch.
  467. To enable debug output (when reporting problems or working on OpenOCD
  468. itself), use the @option{-d} command line switch. This sets the
  469. @option{debug_level} to "3", outputting the most information,
  470. including debug messages. The default setting is "2", outputting only
  471. informational messages, warnings and errors. You can also change this
  472. setting from within a telnet or gdb session using @command{debug_level
  473. <n>} (@pxref{debug_level}).
  474. You can redirect all output from the daemon to a file using the
  475. @option{-l <logfile>} switch.
  476. For details on the @option{-p} option. @xref{Connecting to GDB}.
  477. Note! OpenOCD will launch the GDB & telnet server even if it can not
  478. establish a connection with the target. In general, it is possible for
  479. the JTAG controller to be unresponsive until the target is set up
  480. correctly via e.g. GDB monitor commands in a GDB init script.
  481. @node OpenOCD Project Setup
  482. @chapter OpenOCD Project Setup
  483. To use OpenOCD with your development projects, you need to do more than
  484. just connecting the JTAG adapter hardware (dongle) to your development board
  485. and then starting the OpenOCD server.
  486. You also need to configure that server so that it knows
  487. about that adapter and board, and helps your work.
  488. You may also want to connect OpenOCD to GDB, possibly
  489. using Eclipse or some other GUI.
  490. @section Hooking up the JTAG Adapter
  491. Today's most common case is a dongle with a JTAG cable on one side
  492. (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
  493. and a USB cable on the other.
  494. Instead of USB, some cables use Ethernet;
  495. older ones may use a PC parallel port, or even a serial port.
  496. @enumerate
  497. @item @emph{Start with power to your target board turned off},
  498. and nothing connected to your JTAG adapter.
  499. If you're particularly paranoid, unplug power to the board.
  500. It's important to have the ground signal properly set up,
  501. unless you are using a JTAG adapter which provides
  502. galvanic isolation between the target board and the
  503. debugging host.
  504. @item @emph{Be sure it's the right kind of JTAG connector.}
  505. If your dongle has a 20-pin ARM connector, you need some kind
  506. of adapter (or octopus, see below) to hook it up to
  507. boards using 14-pin or 10-pin connectors ... or to 20-pin
  508. connectors which don't use ARM's pinout.
  509. In the same vein, make sure the voltage levels are compatible.
  510. Not all JTAG adapters have the level shifters needed to work
  511. with 1.2 Volt boards.
  512. @item @emph{Be certain the cable is properly oriented} or you might
  513. damage your board. In most cases there are only two possible
  514. ways to connect the cable.
  515. Connect the JTAG cable from your adapter to the board.
  516. Be sure it's firmly connected.
  517. In the best case, the connector is keyed to physically
  518. prevent you from inserting it wrong.
  519. This is most often done using a slot on the board's male connector
  520. housing, which must match a key on the JTAG cable's female connector.
  521. If there's no housing, then you must look carefully and
  522. make sure pin 1 on the cable hooks up to pin 1 on the board.
  523. Ribbon cables are frequently all grey except for a wire on one
  524. edge, which is red. The red wire is pin 1.
  525. Sometimes dongles provide cables where one end is an ``octopus'' of
  526. color coded single-wire connectors, instead of a connector block.
  527. These are great when converting from one JTAG pinout to another,
  528. but are tedious to set up.
  529. Use these with connector pinout diagrams to help you match up the
  530. adapter signals to the right board pins.
  531. @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
  532. A USB, parallel, or serial port connector will go to the host which
  533. you are using to run OpenOCD.
  534. For Ethernet, consult the documentation and your network administrator.
  535. For USB based JTAG adapters you have an easy sanity check at this point:
  536. does the host operating system see the JTAG adapter? If that host is an
  537. MS-Windows host, you'll need to install a driver before OpenOCD works.
  538. @item @emph{Connect the adapter's power supply, if needed.}
  539. This step is primarily for non-USB adapters,
  540. but sometimes USB adapters need extra power.
  541. @item @emph{Power up the target board.}
  542. Unless you just let the magic smoke escape,
  543. you're now ready to set up the OpenOCD server
  544. so you can use JTAG to work with that board.
  545. @end enumerate
  546. Talk with the OpenOCD server using
  547. telnet (@code{telnet localhost 4444} on many systems) or GDB.
  548. @xref{GDB and OpenOCD}.
  549. @section Project Directory
  550. There are many ways you can configure OpenOCD and start it up.
  551. A simple way to organize them all involves keeping a
  552. single directory for your work with a given board.
  553. When you start OpenOCD from that directory,
  554. it searches there first for configuration files, scripts,
  555. files accessed through semihosting,
  556. and for code you upload to the target board.
  557. It is also the natural place to write files,
  558. such as log files and data you download from the board.
  559. @section Configuration Basics
  560. There are two basic ways of configuring OpenOCD, and
  561. a variety of ways you can mix them.
  562. Think of the difference as just being how you start the server:
  563. @itemize
  564. @item Many @option{-f file} or @option{-c command} options on the command line
  565. @item No options, but a @dfn{user config file}
  566. in the current directory named @file{openocd.cfg}
  567. @end itemize
  568. Here is an example @file{openocd.cfg} file for a setup
  569. using a Signalyzer FT2232-based JTAG adapter to talk to
  570. a board with an Atmel AT91SAM7X256 microcontroller:
  571. @example
  572. source [find interface/signalyzer.cfg]
  573. # GDB can also flash my flash!
  574. gdb_memory_map enable
  575. gdb_flash_program enable
  576. source [find target/sam7x256.cfg]
  577. @end example
  578. Here is the command line equivalent of that configuration:
  579. @example
  580. openocd -f interface/signalyzer.cfg \
  581. -c "gdb_memory_map enable" \
  582. -c "gdb_flash_program enable" \
  583. -f target/sam7x256.cfg
  584. @end example
  585. You could wrap such long command lines in shell scripts,
  586. each supporting a different development task.
  587. One might re-flash the board with a specific firmware version.
  588. Another might set up a particular debugging or run-time environment.
  589. @quotation Important
  590. At this writing (October 2009) the command line method has
  591. problems with how it treats variables.
  592. For example, after @option{-c "set VAR value"}, or doing the
  593. same in a script, the variable @var{VAR} will have no value
  594. that can be tested in a later script.
  595. @end quotation
  596. Here we will focus on the simpler solution: one user config
  597. file, including basic configuration plus any TCL procedures
  598. to simplify your work.
  599. @section User Config Files
  600. @cindex config file, user
  601. @cindex user config file
  602. @cindex config file, overview
  603. A user configuration file ties together all the parts of a project
  604. in one place.
  605. One of the following will match your situation best:
  606. @itemize
  607. @item Ideally almost everything comes from configuration files
  608. provided by someone else.
  609. For example, OpenOCD distributes a @file{scripts} directory
  610. (probably in @file{/usr/share/openocd/scripts} on Linux).
  611. Board and tool vendors can provide these too, as can individual
  612. user sites; the @option{-s} command line option lets you say
  613. where to find these files. (@xref{Running}.)
  614. The AT91SAM7X256 example above works this way.
  615. Three main types of non-user configuration file each have their
  616. own subdirectory in the @file{scripts} directory:
  617. @enumerate
  618. @item @b{interface} -- one for each kind of JTAG adapter/dongle
  619. @item @b{board} -- one for each different board
  620. @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
  621. @end enumerate
  622. Best case: include just two files, and they handle everything else.
  623. The first is an interface config file.
  624. The second is board-specific, and it sets up the JTAG TAPs and
  625. their GDB targets (by deferring to some @file{target.cfg} file),
  626. declares all flash memory, and leaves you nothing to do except
  627. meet your deadline:
  628. @example
  629. source [find interface/olimex-jtag-tiny.cfg]
  630. source [find board/csb337.cfg]
  631. @end example
  632. Boards with a single microcontroller often won't need more
  633. than the target config file, as in the AT91SAM7X256 example.
  634. That's because there is no external memory (flash, DDR RAM), and
  635. the board differences are encapsulated by application code.
  636. @item Maybe you don't know yet what your board looks like to JTAG.
  637. Once you know the @file{interface.cfg} file to use, you may
  638. need help from OpenOCD to discover what's on the board.
  639. Once you find the TAPs, you can just search for appropriate
  640. configuration files ... or write your own, from the bottom up.
  641. @xref{Autoprobing}.
  642. @item You can often reuse some standard config files but
  643. need to write a few new ones, probably a @file{board.cfg} file.
  644. You will be using commands described later in this User's Guide,
  645. and working with the guidelines in the next chapter.
  646. For example, there may be configuration files for your JTAG adapter
  647. and target chip, but you need a new board-specific config file
  648. giving access to your particular flash chips.
  649. Or you might need to write another target chip configuration file
  650. for a new chip built around the Cortex M3 core.
  651. @quotation Note
  652. When you write new configuration files, please submit
  653. them for inclusion in the next OpenOCD release.
  654. For example, a @file{board/newboard.cfg} file will help the
  655. next users of that board, and a @file{target/newcpu.cfg}
  656. will help support users of any board using that chip.
  657. @end quotation
  658. @item
  659. You may may need to write some C code.
  660. It may be as simple as a supporting a new ft2232 or parport
  661. based dongle; a bit more involved, like a NAND or NOR flash
  662. controller driver; or a big piece of work like supporting
  663. a new chip architecture.
  664. @end itemize
  665. Reuse the existing config files when you can.
  666. Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
  667. You may find a board configuration that's a good example to follow.
  668. When you write config files, separate the reusable parts
  669. (things every user of that interface, chip, or board needs)
  670. from ones specific to your environment and debugging approach.
  671. @itemize
  672. @item
  673. For example, a @code{gdb-attach} event handler that invokes
  674. the @command{reset init} command will interfere with debugging
  675. early boot code, which performs some of the same actions
  676. that the @code{reset-init} event handler does.
  677. @item
  678. Likewise, the @command{arm9 vector_catch} command (or
  679. @cindex vector_catch
  680. its siblings @command{xscale vector_catch}
  681. and @command{cortex_m3 vector_catch}) can be a timesaver
  682. during some debug sessions, but don't make everyone use that either.
  683. Keep those kinds of debugging aids in your user config file,
  684. along with messaging and tracing setup.
  685. (@xref{Software Debug Messages and Tracing}.)
  686. @item
  687. You might need to override some defaults.
  688. For example, you might need to move, shrink, or back up the target's
  689. work area if your application needs much SRAM.
  690. @item
  691. TCP/IP port configuration is another example of something which
  692. is environment-specific, and should only appear in
  693. a user config file. @xref{TCP/IP Ports}.
  694. @end itemize
  695. @section Project-Specific Utilities
  696. A few project-specific utility
  697. routines may well speed up your work.
  698. Write them, and keep them in your project's user config file.
  699. For example, if you are making a boot loader work on a
  700. board, it's nice to be able to debug the ``after it's
  701. loaded to RAM'' parts separately from the finicky early
  702. code which sets up the DDR RAM controller and clocks.
  703. A script like this one, or a more GDB-aware sibling,
  704. may help:
  705. @example
  706. proc ramboot @{ @} @{
  707. # Reset, running the target's "reset-init" scripts
  708. # to initialize clocks and the DDR RAM controller.
  709. # Leave the CPU halted.
  710. reset init
  711. # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
  712. load_image u-boot.bin 0x20000000
  713. # Start running.
  714. resume 0x20000000
  715. @}
  716. @end example
  717. Then once that code is working you will need to make it
  718. boot from NOR flash; a different utility would help.
  719. Alternatively, some developers write to flash using GDB.
  720. (You might use a similar script if you're working with a flash
  721. based microcontroller application instead of a boot loader.)
  722. @example
  723. proc newboot @{ @} @{
  724. # Reset, leaving the CPU halted. The "reset-init" event
  725. # proc gives faster access to the CPU and to NOR flash;
  726. # "reset halt" would be slower.
  727. reset init
  728. # Write standard version of U-Boot into the first two
  729. # sectors of NOR flash ... the standard version should
  730. # do the same lowlevel init as "reset-init".
  731. flash protect 0 0 1 off
  732. flash erase_sector 0 0 1
  733. flash write_bank 0 u-boot.bin 0x0
  734. flash protect 0 0 1 on
  735. # Reboot from scratch using that new boot loader.
  736. reset run
  737. @}
  738. @end example
  739. You may need more complicated utility procedures when booting
  740. from NAND.
  741. That often involves an extra bootloader stage,
  742. running from on-chip SRAM to perform DDR RAM setup so it can load
  743. the main bootloader code (which won't fit into that SRAM).
  744. Other helper scripts might be used to write production system images,
  745. involving considerably more than just a three stage bootloader.
  746. @section Target Software Changes
  747. Sometimes you may want to make some small changes to the software
  748. you're developing, to help make JTAG debugging work better.
  749. For example, in C or assembly language code you might
  750. use @code{#ifdef JTAG_DEBUG} (or its converse) around code
  751. handling issues like:
  752. @itemize @bullet
  753. @item @b{Watchdog Timers}...
  754. Watchog timers are typically used to automatically reset systems if
  755. some application task doesn't periodically reset the timer. (The
  756. assumption is that the system has locked up if the task can't run.)
  757. When a JTAG debugger halts the system, that task won't be able to run
  758. and reset the timer ... potentially causing resets in the middle of
  759. your debug sessions.
  760. It's rarely a good idea to disable such watchdogs, since their usage
  761. needs to be debugged just like all other parts of your firmware.
  762. That might however be your only option.
  763. Look instead for chip-specific ways to stop the watchdog from counting
  764. while the system is in a debug halt state. It may be simplest to set
  765. that non-counting mode in your debugger startup scripts. You may however
  766. need a different approach when, for example, a motor could be physically
  767. damaged by firmware remaining inactive in a debug halt state. That might
  768. involve a type of firmware mode where that "non-counting" mode is disabled
  769. at the beginning then re-enabled at the end; a watchdog reset might fire
  770. and complicate the debug session, but hardware (or people) would be
  771. protected.@footnote{Note that many systems support a "monitor mode" debug
  772. that is a somewhat cleaner way to address such issues. You can think of
  773. it as only halting part of the system, maybe just one task,
  774. instead of the whole thing.
  775. At this writing, January 2010, OpenOCD based debugging does not support
  776. monitor mode debug, only "halt mode" debug.}
  777. @item @b{ARM Semihosting}...
  778. @cindex ARM semihosting
  779. When linked with a special runtime library provided with many
  780. toolchains@footnote{See chapter 8 "Semihosting" in
  781. @uref{,
  782. ARM DUI 0203I}, the "RealView Compilation Tools Developer Guide".
  783. The CodeSourcery EABI toolchain also includes a semihosting library.},
  784. your target code can use I/O facilities on the debug host. That library
  785. provides a small set of system calls which are handled by OpenOCD.
  786. It can let the debugger provide your system console and a file system,
  787. helping with early debugging or providing a more capable environment
  788. for sometimes-complex tasks like installing system firmware onto
  789. NAND or SPI flash.
  790. @item @b{ARM Wait-For-Interrupt}...
  791. Many ARM chips synchronize the JTAG clock using the core clock.
  792. Low power states which stop that core clock thus prevent JTAG access.
  793. Idle loops in tasking environments often enter those low power states
  794. via the @code{WFI} instruction (or its coprocessor equivalent, before ARMv7).
  795. You may want to @emph{disable that instruction} in source code,
  796. or otherwise prevent using that state,
  797. to ensure you can get JTAG access at any time.@footnote{As a more
  798. polite alternative, some processors have special debug-oriented
  799. registers which can be used to change various features including
  800. how the low power states are clocked while debugging.
  801. The STM32 DBGMCU_CR register is an example; at the cost of extra
  802. power consumption, JTAG can be used during low power states.}
  803. For example, the OpenOCD @command{halt} command may not
  804. work for an idle processor otherwise.
  805. @item @b{Delay after reset}...
  806. Not all chips have good support for debugger access
  807. right after reset; many LPC2xxx chips have issues here.
  808. Similarly, applications that reconfigure pins used for
  809. JTAG access as they start will also block debugger access.
  810. To work with boards like this, @emph{enable a short delay loop}
  811. the first thing after reset, before "real" startup activities.
  812. For example, one second's delay is usually more than enough
  813. time for a JTAG debugger to attach, so that
  814. early code execution can be debugged
  815. or firmware can be replaced.
  816. @item @b{Debug Communications Channel (DCC)}...
  817. Some processors include mechanisms to send messages over JTAG.
  818. Many ARM cores support these, as do some cores from other vendors.
  819. (OpenOCD may be able to use this DCC internally, speeding up some
  820. operations like writing to memory.)
  821. Your application may want to deliver various debugging messages
  822. over JTAG, by @emph{linking with a small library of code}
  823. provided with OpenOCD and using the utilities there to send
  824. various kinds of message.
  825. @xref{Software Debug Messages and Tracing}.
  826. @end itemize
  827. @section Target Hardware Setup
  828. Chip vendors often provide software development boards which
  829. are highly configurable, so that they can support all options
  830. that product boards may require. @emph{Make sure that any
  831. jumpers or switches match the system configuration you are
  832. working with.}
  833. Common issues include:
  834. @itemize @bullet
  835. @item @b{JTAG setup} ...
  836. Boards may support more than one JTAG configuration.
  837. Examples include jumpers controlling pullups versus pulldowns
  838. on the nTRST and/or nSRST signals, and choice of connectors
  839. (e.g. which of two headers on the base board,
  840. or one from a daughtercard).
  841. For some Texas Instruments boards, you may need to jumper the
  842. EMU0 and EMU1 signals (which OpenOCD won't currently control).
  843. @item @b{Boot Modes} ...
  844. Complex chips often support multiple boot modes, controlled
  845. by external jumpers. Make sure this is set up correctly.
  846. For example many i.MX boards from NXP need to be jumpered
  847. to "ATX mode" to start booting using the on-chip ROM, when
  848. using second stage bootloader code stored in a NAND flash chip.
  849. Such explicit configuration is common, and not limited to
  850. booting from NAND. You might also need to set jumpers to
  851. start booting using code loaded from an MMC/SD card; external
  852. SPI flash; Ethernet, UART, or USB links; NOR flash; OneNAND
  853. flash; some external host; or various other sources.
  854. @item @b{Memory Addressing} ...
  855. Boards which support multiple boot modes may also have jumpers
  856. to configure memory addressing. One board, for example, jumpers
  857. external chipselect 0 (used for booting) to address either
  858. a large SRAM (which must be pre-loaded via JTAG), NOR flash,
  859. or NAND flash. When it's jumpered to address NAND flash, that
  860. board must also be told to start booting from on-chip ROM.
  861. Your @file{board.cfg} file may also need to be told this jumper
  862. configuration, so that it can know whether to declare NOR flash
  863. using @command{flash bank} or instead declare NAND flash with
  864. @command{nand device}; and likewise which probe to perform in
  865. its @code{reset-init} handler.
  866. A closely related issue is bus width. Jumpers might need to
  867. distinguish between 8 bit or 16 bit bus access for the flash
  868. used to start booting.
  869. @item @b{Peripheral Access} ...
  870. Development boards generally provide access to every peripheral
  871. on the chip, sometimes in multiple modes (such as by providing
  872. multiple audio codec chips).
  873. This interacts with software
  874. configuration of pin multiplexing, where for example a
  875. given pin may be routed either to the MMC/SD controller
  876. or the GPIO controller. It also often interacts with
  877. configuration jumpers. One jumper may be used to route
  878. signals to an MMC/SD card slot or an expansion bus (which
  879. might in turn affect booting); others might control which
  880. audio or video codecs are used.
  881. @end itemize
  882. Plus you should of course have @code{reset-init} event handlers
  883. which set up the hardware to match that jumper configuration.
  884. That includes in particular any oscillator or PLL used to clock
  885. the CPU, and any memory controllers needed to access external
  886. memory and peripherals. Without such handlers, you won't be
  887. able to access those resources without working target firmware
  888. which can do that setup ... this can be awkward when you're
  889. trying to debug that target firmware. Even if there's a ROM
  890. bootloader which handles a few issues, it rarely provides full
  891. access to all board-specific capabilities.
  892. @node Config File Guidelines
  893. @chapter Config File Guidelines
  894. This chapter is aimed at any user who needs to write a config file,
  895. including developers and integrators of OpenOCD and any user who
  896. needs to get a new board working smoothly.
  897. It provides guidelines for creating those files.
  898. You should find the following directories under @t{$(INSTALLDIR)/scripts},
  899. with files including the ones listed here.
  900. Use them as-is where you can; or as models for new files.
  901. @itemize @bullet
  902. @item @file{interface} ...
  903. think JTAG Dongle. Files that configure JTAG adapters go here.
  904. @example
  905. $ ls interface
  906. arm-jtag-ew.cfg hitex_str9-comstick.cfg oocdlink.cfg
  907. arm-usb-ocd.cfg icebear.cfg openocd-usb.cfg
  908. at91rm9200.cfg jlink.cfg parport.cfg
  909. axm0432.cfg jtagkey2.cfg parport_dlc5.cfg
  910. calao-usb-a9260-c01.cfg jtagkey.cfg rlink.cfg
  911. calao-usb-a9260-c02.cfg jtagkey-tiny.cfg sheevaplug.cfg
  912. calao-usb-a9260.cfg luminary.cfg signalyzer.cfg
  913. chameleon.cfg luminary-icdi.cfg stm32-stick.cfg
  914. cortino.cfg luminary-lm3s811.cfg turtelizer2.cfg
  915. dummy.cfg olimex-arm-usb-ocd.cfg usbprog.cfg
  916. flyswatter.cfg olimex-jtag-tiny.cfg vsllink.cfg
  917. $
  918. @end example
  919. @item @file{board} ...
  920. think Circuit Board, PWA, PCB, they go by many names. Board files
  921. contain initialization items that are specific to a board.
  922. They reuse target configuration files, since the same
  923. microprocessor chips are used on many boards,
  924. but support for external parts varies widely. For
  925. example, the SDRAM initialization sequence for the board, or the type
  926. of external flash and what address it uses. Any initialization
  927. sequence to enable that external flash or SDRAM should be found in the
  928. board file. Boards may also contain multiple targets: two CPUs; or
  929. a CPU and an FPGA.
  930. @example
  931. $ ls board
  932. arm_evaluator7t.cfg keil_mcb1700.cfg
  933. at91rm9200-dk.cfg keil_mcb2140.cfg
  934. at91sam9g20-ek.cfg linksys_nslu2.cfg
  935. atmel_at91sam7s-ek.cfg logicpd_imx27.cfg
  936. atmel_at91sam9260-ek.cfg mini2440.cfg
  937. atmel_sam3u_ek.cfg olimex_LPC2378STK.cfg
  938. crossbow_tech_imote2.cfg olimex_lpc_h2148.cfg
  939. csb337.cfg olimex_sam7_ex256.cfg
  940. csb732.cfg olimex_sam9_l9260.cfg
  941. digi_connectcore_wi-9c.cfg olimex_stm32_h103.cfg
  942. dm355evm.cfg omap2420_h4.cfg
  943. dm365evm.cfg osk5912.cfg
  944. dm6446evm.cfg pic-p32mx.cfg
  945. eir.cfg propox_mmnet1001.cfg
  946. ek-lm3s1968.cfg pxa255_sst.cfg
  947. ek-lm3s3748.cfg sheevaplug.cfg
  948. ek-lm3s811.cfg stm3210e_eval.cfg
  949. ek-lm3s9b9x.cfg stm32f10x_128k_eval.cfg
  950. hammer.cfg str910-eval.cfg
  951. hitex_lpc2929.cfg telo.cfg
  952. hitex_stm32-performancestick.cfg ti_beagleboard.cfg
  953. hitex_str9-comstick.cfg topas910.cfg
  954. iar_str912_sk.cfg topasa900.cfg
  955. imx27ads.cfg unknown_at91sam9260.cfg
  956. imx27lnst.cfg x300t.cfg
  957. imx31pdk.cfg zy1000.cfg
  958. $
  959. @end example
  960. @item @file{target} ...
  961. think chip. The ``target'' directory represents the JTAG TAPs
  962. on a chip
  963. which OpenOCD should control, not a board. Two common types of targets
  964. are ARM chips and FPGA or CPLD chips.
  965. When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
  966. the target config file defines all of them.
  967. @example
  968. $ ls target
  969. aduc702x.cfg imx27.cfg pxa255.cfg
  970. ar71xx.cfg imx31.cfg pxa270.cfg
  971. at91eb40a.cfg imx35.cfg readme.txt
  972. at91r40008.cfg is5114.cfg sam7se512.cfg
  973. at91rm9200.cfg ixp42x.cfg sam7x256.cfg
  974. at91sam3u1c.cfg lm3s1968.cfg samsung_s3c2410.cfg
  975. at91sam3u1e.cfg lm3s3748.cfg samsung_s3c2440.cfg
  976. at91sam3u2c.cfg lm3s6965.cfg samsung_s3c2450.cfg
  977. at91sam3u2e.cfg lm3s811.cfg samsung_s3c4510.cfg
  978. at91sam3u4c.cfg lm3s9b9x.cfg samsung_s3c6410.cfg
  979. at91sam3u4e.cfg lpc1768.cfg sharp_lh79532.cfg
  980. at91sam3uXX.cfg lpc2103.cfg smdk6410.cfg
  981. at91sam7sx.cfg lpc2124.cfg smp8634.cfg
  982. at91sam9260.cfg lpc2129.cfg stm32.cfg
  983. c100.cfg lpc2148.cfg str710.cfg
  984. c100config.tcl lpc2294.cfg str730.cfg
  985. c100helper.tcl lpc2378.cfg str750.cfg
  986. c100regs.tcl lpc2478.cfg str912.cfg
  987. cs351x.cfg lpc2900.cfg telo.cfg
  988. davinci.cfg mega128.cfg ti_dm355.cfg
  989. dragonite.cfg netx500.cfg ti_dm365.cfg
  990. epc9301.cfg omap2420.cfg ti_dm6446.cfg
  991. feroceon.cfg omap3530.cfg tmpa900.cfg
  992. icepick.cfg omap5912.cfg tmpa910.cfg
  993. imx21.cfg pic32mx.cfg xba_revA3.cfg
  994. $
  995. @end example
  996. @item @emph{more} ... browse for other library files which may be useful.
  997. For example, there are various generic and CPU-specific utilities.
  998. @end itemize
  999. The @file{openocd.cfg} user config
  1000. file may override features in any of the above files by
  1001. setting variables before sourcing the target file, or by adding
  1002. commands specific to their situation.
  1003. @section Interface Config Files
  1004. The user config file
  1005. should be able to source one of these files with a command like this:
  1006. @example
  1007. source [find interface/FOOBAR.cfg]
  1008. @end example
  1009. A preconfigured interface file should exist for every interface in use
  1010. today, that said, perhaps some interfaces have only been used by the
  1011. sole developer who created it.
  1012. A separate chapter gives information about how to set these up.
  1013. @xref{Interface - Dongle Configuration}.
  1014. Read the OpenOCD source code if you have a new kind of hardware interface
  1015. and need to provide a driver for it.
  1016. @section Board Config Files
  1017. @cindex config file, board
  1018. @cindex board config file
  1019. The user config file
  1020. should be able to source one of these files with a command like this:
  1021. @example
  1022. source [find board/FOOBAR.cfg]
  1023. @end example
  1024. The point of a board config file is to package everything
  1025. about a given board that user config files need to know.
  1026. In summary the board files should contain (if present)
  1027. @enumerate
  1028. @item One or more @command{source [target/...cfg]} statements
  1029. @item NOR flash configuration (@pxref{NOR Configuration})
  1030. @item NAND flash configuration (@pxref{NAND Configuration})
  1031. @item Target @code{reset} handlers for SDRAM and I/O configuration
  1032. @item JTAG adapter reset configuration (@pxref{Reset Configuration})
  1033. @item All things that are not ``inside a chip''
  1034. @end enumerate
  1035. Generic things inside target chips belong in target config files,
  1036. not board config files. So for example a @code{reset-init} event
  1037. handler should know board-specific oscillator and PLL parameters,
  1038. which it passes to target-specific utility code.
  1039. The most complex task of a board config file is creating such a
  1040. @code{reset-init} event handler.
  1041. Define those handlers last, after you verify the rest of the board
  1042. configuration works.
  1043. @subsection Communication Between Config files
  1044. In addition to target-specific utility code, another way that
  1045. board and target config files communicate is by following a
  1046. convention on how to use certain variables.
  1047. The full Tcl/Tk language supports ``namespaces'', but JIM-Tcl does not.
  1048. Thus the rule we follow in OpenOCD is this: Variables that begin with
  1049. a leading underscore are temporary in nature, and can be modified and
  1050. used at will within a target configuration file.
  1051. Complex board config files can do the things like this,
  1052. for a board with three chips:
  1053. @example
  1054. # Chip #1: PXA270 for network side, big endian
  1055. set CHIPNAME network
  1056. set ENDIAN big
  1057. source [find target/pxa270.cfg]
  1058. # on return: _TARGETNAME = network.cpu
  1059. # other commands can refer to the "network.cpu" target.
  1060. $_TARGETNAME configure .... events for this CPU..
  1061. # Chip #2: PXA270 for video side, little endian
  1062. set CHIPNAME video
  1063. set ENDIAN little
  1064. source [find target/pxa270.cfg]
  1065. # on return: _TARGETNAME = video.cpu
  1066. # other commands can refer to the "video.cpu" target.
  1067. $_TARGETNAME configure .... events for this CPU..
  1068. # Chip #3: Xilinx FPGA for glue logic
  1069. set CHIPNAME xilinx
  1070. unset ENDIAN
  1071. source [find target/spartan3.cfg]
  1072. @end example
  1073. That example is oversimplified because it doesn't show any flash memory,
  1074. or the @code{reset-init} event handlers to initialize external DRAM
  1075. or (assuming it needs it) load a configuration into the FPGA.
  1076. Such features are usually needed for low-level work with many boards,
  1077. where ``low level'' implies that the board initialization software may
  1078. not be working. (That's a common reason to need JTAG tools. Another
  1079. is to enable working with microcontroller-based systems, which often
  1080. have no debugging support except a JTAG connector.)
  1081. Target config files may also export utility functions to board and user
  1082. config files. Such functions should use name prefixes, to help avoid
  1083. naming collisions.
  1084. Board files could also accept input variables from user config files.
  1085. For example, there might be a @code{J4_JUMPER} setting used to identify
  1086. what kind of flash memory a development board is using, or how to set
  1087. up other clocks and peripherals.
  1088. @subsection Variable Naming Convention
  1089. @cindex variable names
  1090. Most boards have only one instance of a chip.
  1091. However, it should be easy to create a board with more than
  1092. one such chip (as shown above).
  1093. Accordingly, we encourage these conventions for naming
  1094. variables associated with different @file{target.cfg} files,
  1095. to promote consistency and
  1096. so that board files can override target defaults.
  1097. Inputs to target config files include:
  1098. @itemize @bullet
  1099. @item @code{CHIPNAME} ...
  1100. This gives a name to the overall chip, and is used as part of
  1101. tap identifier dotted names.
  1102. While the default is normally provided by the chip manufacturer,
  1103. board files may need to distinguish between instances of a chip.
  1104. @item @code{ENDIAN} ...
  1105. By default @option{little} - although chips may hard-wire @option{big}.
  1106. Chips that can't change endianness don't need to use this variable.
  1107. @item @code{CPUTAPID} ...
  1108. When OpenOCD examines the JTAG chain, it can be told verify the
  1109. chips against the JTAG IDCODE register.
  1110. The target file will hold one or more defaults, but sometimes the
  1111. chip in a board will use a different ID (perhaps a newer revision).
  1112. @end itemize
  1113. Outputs from target config files include:
  1114. @itemize @bullet
  1115. @item @code{_TARGETNAME} ...
  1116. By convention, this variable is created by the target configuration
  1117. script. The board configuration file may make use of this variable to
  1118. configure things like a ``reset init'' script, or other things
  1119. specific to that board and that target.
  1120. If the chip has 2 targets, the names are @code{_TARGETNAME0},
  1121. @code{_TARGETNAME1}, ... etc.
  1122. @end itemize
  1123. @subsection The reset-init Event Handler
  1124. @cindex event, reset-init
  1125. @cindex reset-init handler
  1126. Board config files run in the OpenOCD configuration stage;
  1127. they can't use TAPs or targets, since they haven't been
  1128. fully set up yet.
  1129. This means you can't write memory or access chip registers;
  1130. you can't even verify that a flash chip is present.
  1131. That's done later in event handlers, of which the target @code{reset-init}
  1132. handler is one of the most important.
  1133. Except on microcontrollers, the basic job of @code{reset-init} event
  1134. handlers is setting up flash and DRAM, as normally handled by boot loaders.
  1135. Microcontrollers rarely use boot loaders; they run right out of their
  1136. on-chip flash and SRAM memory. But they may want to use one of these
  1137. handlers too, if just for developer convenience.
  1138. @quotation Note
  1139. Because this is so very board-specific, and chip-specific, no examples
  1140. are included here.
  1141. Instead, look at the board config files distributed with OpenOCD.
  1142. If you have a boot loader, its source code will help; so will
  1143. configuration files for other JTAG tools
  1144. (@pxref{Translating Configuration Files}).
  1145. @end quotation
  1146. Some of this code could probably be shared between different boards.
  1147. For example, setting up a DRAM controller often doesn't differ by
  1148. much except the bus width (16 bits or 32?) and memory timings, so a
  1149. reusable TCL procedure loaded by the @file{target.cfg} file might take
  1150. those as parameters.
  1151. Similarly with oscillator, PLL, and clock setup;
  1152. and disabling the watchdog.
  1153. Structure the code cleanly, and provide comments to help
  1154. the next developer doing such work.
  1155. (@emph{You might be that next person} trying to reuse init code!)
  1156. The last thing normally done in a @code{reset-init} handler is probing
  1157. whatever flash memory was configured. For most chips that needs to be
  1158. done while the associated target is halted, either because JTAG memory
  1159. access uses the CPU or to prevent conflicting CPU access.
  1160. @subsection JTAG Clock Rate
  1161. Before your @code{reset-init} handler has set up
  1162. the PLLs and clocking, you may need to run with
  1163. a low JTAG clock rate.
  1164. @xref{JTAG Speed}.
  1165. Then you'd increase that rate after your handler has
  1166. made it possible to use the faster JTAG clock.
  1167. When the initial low speed is board-specific, for example
  1168. because it depends on a board-specific oscillator speed, then
  1169. you should probably set it up in the board config file;
  1170. if it's target-specific, it belongs in the target config file.
  1171. For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
  1172. @uref{} gives details.}
  1173. is one sixth of the CPU clock; or one eighth for ARM11 cores.
  1174. Consult chip documentation to determine the peak JTAG clock rate,
  1175. which might be less than that.
  1176. @quotation Warning
  1177. On most ARMs, JTAG clock detection is coupled to the core clock, so
  1178. software using a @option{wait for interrupt} operation blocks JTAG access.
  1179. Adaptive clocking provides a partial workaround, but a more complete
  1180. solution just avoids using that instruction with JTAG debuggers.
  1181. @end quotation
  1182. If the board supports adaptive clocking, use the @command{jtag_rclk}
  1183. command, in case your board is used with JTAG adapter which
  1184. also supports it. Otherwise use @command{jtag_khz}.
  1185. Set the slow rate at the beginning of the reset sequence,
  1186. and the faster rate as soon as the clocks are at full speed.
  1187. @section Target Config Files
  1188. @cindex config file, target
  1189. @cindex target config file
  1190. Board config files communicate with target config files using
  1191. naming conventions as described above, and may source one or
  1192. more target config files like this:
  1193. @example
  1194. source [find target/FOOBAR.cfg]
  1195. @end example
  1196. The point of a target config file is to package everything
  1197. about a given chip that board config files need to know.
  1198. In summary the target files should contain
  1199. @enumerate
  1200. @item Set defaults
  1201. @item Add TAPs to the scan chain
  1202. @item Add CPU targets (includes GDB support)
  1203. @item CPU/Chip/CPU-Core specific features
  1204. @item On-Chip flash
  1205. @end enumerate
  1206. As a rule of thumb, a target file sets up only one chip.
  1207. For a microcontroller, that will often include a single TAP,
  1208. which is a CPU needing a GDB target, and its on-chip flash.
  1209. More complex chips may include multiple TAPs, and the target
  1210. config file may need to define them all before OpenOCD
  1211. can talk to the chip.
  1212. For example, some phone chips have JTAG scan chains that include
  1213. an ARM core for operating system use, a DSP,
  1214. another ARM core embedded in an image processing engine,
  1215. and other processing engines.
  1216. @subsection Default Value Boiler Plate Code
  1217. All target configuration files should start with code like this,
  1218. letting board config files express environment-specific
  1219. differences in how things should be set up.
  1220. @example
  1221. # Boards may override chip names, perhaps based on role,
  1222. # but the default should match what the vendor uses
  1223. if @{ [info exists CHIPNAME] @} @{
  1225. @} else @{
  1226. set _CHIPNAME sam7x256
  1227. @}
  1228. # ONLY use ENDIAN with targets that can change it.
  1229. if @{ [info exists ENDIAN] @} @{
  1230. set _ENDIAN $ENDIAN
  1231. @} else @{
  1232. set _ENDIAN little
  1233. @}
  1234. # TAP identifiers may change as chips mature, for example with
  1235. # new revision fields (the "3" here). Pick a good default; you
  1236. # can pass several such identifiers to the "jtag newtap" command.
  1237. if @{ [info exists CPUTAPID ] @} @{
  1239. @} else @{
  1240. set _CPUTAPID 0x3f0f0f0f
  1241. @}
  1242. @end example
  1243. @c but 0x3f0f0f0f is for an str73x part ...
  1244. @emph{Remember:} Board config files may include multiple target
  1245. config files, or the same target file multiple times
  1246. (changing at least @code{CHIPNAME}).
  1247. Likewise, the target configuration file should define
  1248. @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
  1249. use it later on when defining debug targets:
  1250. @example
  1251. set _TARGETNAME $_CHIPNAME.cpu
  1252. target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
  1253. @end example
  1254. @subsection Adding TAPs to the Scan Chain
  1255. After the ``defaults'' are set up,
  1256. add the TAPs on each chip to the JTAG scan chain.
  1257. @xref{TAP Declaration}, and the naming convention
  1258. for taps.
  1259. In the simplest case the chip has only one TAP,
  1260. probably for a CPU or FPGA.
  1261. The config file for the Atmel AT91SAM7X256
  1262. looks (in part) like this:
  1263. @example
  1264. jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
  1265. @end example
  1266. A board with two such at91sam7 chips would be able
  1267. to source such a config file twice, with different
  1268. values for @code{CHIPNAME}, so
  1269. it adds a different TAP each time.
  1270. If there are nonzero @option{-expected-id} values,
  1271. OpenOCD attempts to verify the actual tap id against those values.
  1272. It will issue error messages if there is mismatch, which
  1273. can help to pinpoint problems in OpenOCD configurations.
  1274. @example
  1275. JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
  1276. (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
  1277. ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
  1278. ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
  1279. ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
  1280. @end example
  1281. There are more complex examples too, with chips that have
  1282. multiple TAPs. Ones worth looking at include:
  1283. @itemize
  1284. @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
  1285. plus a JRC to enable them
  1286. @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
  1287. @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
  1288. is not currently used)
  1289. @end itemize
  1290. @subsection Add CPU targets
  1291. After adding a TAP for a CPU, you should set it up so that
  1292. GDB and other commands can use it.
  1293. @xref{CPU Configuration}.
  1294. For the at91sam7 example above, the command can look like this;
  1295. note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
  1296. to little endian, and this chip doesn't support changing that.
  1297. @example
  1298. set _TARGETNAME $_CHIPNAME.cpu
  1299. target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
  1300. @end example
  1301. Work areas are small RAM areas associated with CPU targets.
  1302. They are used by OpenOCD to speed up downloads,
  1303. and to download small snippets of code to program flash chips.
  1304. If the chip includes a form of ``on-chip-ram'' - and many do - define
  1305. a work area if you can.
  1306. Again using the at91sam7 as an example, this can look like:
  1307. @example
  1308. $_TARGETNAME configure -work-area-phys 0x00200000 \
  1309. -work-area-size 0x4000 -work-area-backup 0
  1310. @end example
  1311. @subsection Chip Reset Setup
  1312. As a rule, you should put the @command{reset_config} command
  1313. into the board file. Most things you think you know about a
  1314. chip can be tweaked by the board.
  1315. Some chips have specific ways the TRST and SRST signals are
  1316. managed. In the unusual case that these are @emph{chip specific}
  1317. and can never be changed by board wiring, they could go here.
  1318. For example, some chips can't support JTAG debugging without
  1319. both signals.
  1320. Provide a @code{reset-assert} event handler if you can.
  1321. Such a handler uses JTAG operations to reset the target,
  1322. letting this target config be used in systems which don't
  1323. provide the optional SRST signal, or on systems where you
  1324. don't want to reset all targets at once.
  1325. Such a handler might write to chip registers to force a reset,
  1326. use a JRC to do that (preferable -- the target may be wedged!),
  1327. or force a watchdog timer to trigger.
  1328. (For Cortex-M3 targets, this is not necessary. The target
  1329. driver knows how to use trigger an NVIC reset when SRST is
  1330. not available.)
  1331. Some chips need special attention during reset handling if
  1332. they're going to be used with JTAG.
  1333. An example might be needing to send some commands right
  1334. after the target's TAP has been reset, providing a
  1335. @code{reset-deassert-post} event handler that writes a chip
  1336. register to report that JTAG debugging is being done.
  1337. Another would be reconfiguring the watchdog so that it stops
  1338. counting while the core is halted in the debugger.
  1339. JTAG clocking constraints often change during reset, and in
  1340. some cases target config files (rather than board config files)
  1341. are the right places to handle some of those issues.
  1342. For example, immediately after reset most chips run using a
  1343. slower clock than they will use later.
  1344. That means that after reset (and potentially, as OpenOCD
  1345. first starts up) they must use a slower JTAG clock rate
  1346. than they will use later.
  1347. @xref{JTAG Speed}.
  1348. @quotation Important
  1349. When you are debugging code that runs right after chip
  1350. reset, getting these issues right is critical.
  1351. In particular, if you see intermittent failures when
  1352. OpenOCD verifies the scan chain after reset,
  1353. look at how you are setting up JTAG clocking.
  1354. @end quotation
  1355. @subsection ARM Core Specific Hacks
  1356. If the chip has a DCC, enable it. If the chip is an ARM9 with some
  1357. special high speed download features - enable it.
  1358. If present, the MMU, the MPU and the CACHE should be disabled.
  1359. Some ARM cores are equipped with trace support, which permits
  1360. examination of the instruction and data bus activity. Trace
  1361. activity is controlled through an ``Embedded Trace Module'' (ETM)
  1362. on one of the core's scan chains. The ETM emits voluminous data
  1363. through a ``trace port''. (@xref{ARM Hardware Tracing}.)
  1364. If you are using an external trace port,
  1365. configure it in your board config file.
  1366. If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
  1367. configure it in your target config file.
  1368. @example
  1369. etm config $_TARGETNAME 16 normal full etb
  1370. etb config $_TARGETNAME $_CHIPNAME.etb
  1371. @end example
  1372. @subsection Internal Flash Configuration
  1373. This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
  1374. @b{Never ever} in the ``target configuration file'' define any type of
  1375. flash that is external to the chip. (For example a BOOT flash on
  1376. Chip Select 0.) Such flash information goes in a board file - not
  1377. the TARGET (chip) file.
  1378. Examples:
  1379. @itemize @bullet
  1380. @item at91sam7x256 - has 256K flash YES enable it.
  1381. @item str912 - has flash internal YES enable it.
  1382. @item imx27 - uses boot flash on CS0 - it goes in the board file.
  1383. @item pxa270 - again - CS0 flash - it goes in the board file.
  1384. @end itemize
  1385. @anchor{Translating Configuration Files}
  1386. @section Translating Configuration Files
  1387. @cindex translation
  1388. If you have a configuration file for another hardware debugger
  1389. or toolset (Abatron, BDI2000, BDI3000, CCS,
  1390. Lauterbach, Segger, Macraigor, etc.), translating
  1391. it into OpenOCD syntax is often quite straightforward. The most tricky
  1392. part of creating a configuration script is oftentimes the reset init
  1393. sequence where e.g. PLLs, DRAM and the like is set up.
  1394. One trick that you can use when translating is to write small
  1395. Tcl procedures to translate the syntax into OpenOCD syntax. This
  1396. can avoid manual translation errors and make it easier to
  1397. convert other scripts later on.
  1398. Example of transforming quirky arguments to a simple search and
  1399. replace job:
  1400. @example
  1401. # Lauterbach syntax(?)
  1402. #
  1403. # Data.Set c15:0x042f %long 0x40000015
  1404. #
  1405. # OpenOCD syntax when using procedure below.
  1406. #
  1407. # setc15 0x01 0x00050078
  1408. proc setc15 @{regs value@} @{
  1409. global TARGETNAME
  1410. echo [format "set p15 0x%04x, 0x%08x" $regs $value]
  1411. arm mcr 15 [expr ($regs>>12)&0x7] \
  1412. [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] \
  1413. [expr ($regs>>8)&0x7] $value
  1414. @}
  1415. @end example
  1416. @node Daemon Configuration
  1417. @chapter Daemon Configuration
  1418. @cindex initialization
  1419. The commands here are commonly found in the openocd.cfg file and are
  1420. used to specify what TCP/IP ports are used, and how GDB should be
  1421. supported.
  1422. @anchor{Configuration Stage}
  1423. @section Configuration Stage
  1424. @cindex configuration stage
  1425. @cindex config command
  1426. When the OpenOCD server process starts up, it enters a
  1427. @emph{configuration stage} which is the only time that
  1428. certain commands, @emph{configuration commands}, may be issued.
  1429. Normally, configuration commands are only available
  1430. inside startup scripts.
  1431. In this manual, the definition of a configuration command is
  1432. presented as a @emph{Config Command}, not as a @emph{Command}
  1433. which may be issued interactively.
  1434. The runtime @command{help} command also highlights configuration
  1435. commands, and those which may be issued at any time.
  1436. Those configuration commands include declaration of TAPs,
  1437. flash banks,
  1438. the interface used for JTAG communication,
  1439. and other basic setup.
  1440. The server must leave the configuration stage before it
  1441. may access or activate TAPs.
  1442. After it leaves this stage, configuration commands may no
  1443. longer be issued.
  1444. @section Entering the Run Stage
  1445. The first thing OpenOCD does after leaving the configuration
  1446. stage is to verify that it can talk to the scan chain
  1447. (list of TAPs) which has been configured.
  1448. It will warn if it doesn't find TAPs it expects to find,
  1449. or finds TAPs that aren't supposed to be there.
  1450. You should see no errors at this point.
  1451. If you see errors, resolve them by correcting the
  1452. commands you used to configure the server.
  1453. Common errors include using an initial JTAG speed that's too
  1454. fast, and not providing the right IDCODE values for the TAPs
  1455. on the scan chain.
  1456. Once OpenOCD has entered the run stage, a number of commands
  1457. become available.
  1458. A number of these relate to the debug targets you may have declared.
  1459. For example, the @command{mww} command will not be available until
  1460. a target has been successfuly instantiated.
  1461. If you want to use those commands, you may need to force
  1462. entry to the run stage.
  1463. @deffn {Config Command} init
  1464. This command terminates the configuration stage and
  1465. enters the run stage. This helps when you need to have
  1466. the startup scripts manage tasks such as resetting the target,
  1467. programming flash, etc. To reset the CPU upon startup, add "init" and
  1468. "reset" at the end of the config script or at the end of the OpenOCD
  1469. command line using the @option{-c} command line switch.
  1470. If this command does not appear in any startup/configuration file
  1471. OpenOCD executes the command for you after processing all
  1472. configuration files and/or command line options.
  1473. @b{NOTE:} This command normally occurs at or near the end of your
  1474. openocd.cfg file to force OpenOCD to ``initialize'' and make the
  1475. targets ready. For example: If your openocd.cfg file needs to
  1476. read/write memory on your target, @command{init} must occur before
  1477. the memory read/write commands. This includes @command{nand probe}.
  1478. @end deffn
  1479. @deffn {Overridable Procedure} jtag_init
  1480. This is invoked at server startup to verify that it can talk
  1481. to the scan chain (list of TAPs) which has been configured.
  1482. The default implementation first tries @command{jtag arp_init},
  1483. which uses only a lightweight JTAG reset before examining the
  1484. scan chain.
  1485. If that fails, it tries again, using a harder reset
  1486. from the overridable procedure @command{init_reset}.
  1487. Implementations must have verified the JTAG scan chain before
  1488. they return.
  1489. This is done by calling @command{jtag arp_init}
  1490. (or @command{jtag arp_init-reset}).
  1491. @end deffn
  1492. @anchor{TCP/IP Ports}
  1493. @section TCP/IP Ports
  1494. @cindex TCP port
  1495. @cindex server
  1496. @cindex port
  1497. @cindex security
  1498. The OpenOCD server accepts remote commands in several syntaxes.
  1499. Each syntax uses a different TCP/IP port, which you may specify
  1500. only during configuration (before those ports are opened).
  1501. For reasons including security, you may wish to prevent remote
  1502. access using one or more of these ports.
  1503. In such cases, just specify the relevant port number as zero.
  1504. If you disable all access through TCP/IP, you will need to
  1505. use the command line @option{-pipe} option.
  1506. @deffn {Command} gdb_port [number]
  1507. @cindex GDB server
  1508. Specify or query the first port used for incoming GDB connections.
  1509. The GDB port for the
  1510. first target will be gdb_port, the second target will listen on gdb_port + 1, and so on.
  1511. When not specified during the configuration stage,
  1512. the port @var{number} defaults to 3333.
  1513. When specified as zero, GDB remote access ports are not activated.
  1514. @end deffn
  1515. @deffn {Command} tcl_port [number]
  1516. Specify or query the port used for a simplified RPC
  1517. connection that can be used by clients to issue TCL commands and get the
  1518. output from the Tcl engine.
  1519. Intended as a machine interface.
  1520. When not specified during the configuration stage,
  1521. the port @var{number} defaults to 6666.
  1522. When specified as zero, this port is not activated.
  1523. @end deffn
  1524. @deffn {Command} telnet_port [number]
  1525. Specify or query the
  1526. port on which to listen for incoming telnet connections.
  1527. This port is intended for interaction with one human through TCL commands.
  1528. When not specified during the configuration stage,
  1529. the port @var{number} defaults to 4444.
  1530. When specified as zero, this port is not activated.
  1531. @end deffn
  1532. @anchor{GDB Configuration}
  1533. @section GDB Configuration
  1534. @cindex GDB
  1535. @cindex GDB configuration
  1536. You can reconfigure some GDB behaviors if needed.
  1537. The ones listed here are static and global.
  1538. @xref{Target Configuration}, about configuring individual targets.
  1539. @xref{Target Events}, about configuring target-specific event handling.
  1540. @anchor{gdb_breakpoint_override}
  1541. @deffn {Command} gdb_breakpoint_override [@option{hard}|@option{soft}|@option{disable}]
  1542. Force breakpoint type for gdb @command{break} commands.
  1543. This option supports GDB GUIs which don't
  1544. distinguish hard versus soft breakpoints, if the default OpenOCD and
  1545. GDB behaviour is not sufficient. GDB normally uses hardware
  1546. breakpoints if the memory map has been set up for flash regions.
  1547. @end deffn
  1548. @anchor{gdb_flash_program}
  1549. @deffn {Config Command} gdb_flash_program (@option{enable}|@option{disable})
  1550. Set to @option{enable} to cause OpenOCD to program the flash memory when a
  1551. vFlash packet is received.
  1552. The default behaviour is @option{enable}.
  1553. @end deffn
  1554. @deffn {Config Command} gdb_memory_map (@option{enable}|@option{disable})
  1555. Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
  1556. requested. GDB will then know when to set hardware breakpoints, and program flash
  1557. using the GDB load command. @command{gdb_flash_program enable} must also be enabled
  1558. for flash programming to work.
  1559. Default behaviour is @option{enable}.
  1560. @xref{gdb_flash_program}.
  1561. @end deffn
  1562. @deffn {Config Command} gdb_report_data_abort (@option{enable}|@option{disable})
  1563. Specifies whether data aborts cause an error to be reported
  1564. by GDB memory read packets.
  1565. The default behaviour is @option{disable};
  1566. use @option{enable} see these errors reported.
  1567. @end deffn
  1568. @anchor{Event Polling}
  1569. @section Event Polling
  1570. Hardware debuggers are parts of asynchronous systems,
  1571. where significant events can happen at any time.
  1572. The OpenOCD server needs to detect some of these events,
  1573. so it can report them to through TCL command line
  1574. or to GDB.
  1575. Examples of such events include:
  1576. @itemize
  1577. @item One of the targets can stop running ... maybe it triggers
  1578. a code breakpoint or data watchpoint, or halts itself.
  1579. @item Messages may be sent over ``debug message'' channels ... many
  1580. targets support such messages sent over JTAG,
  1581. for receipt by the person debugging or tools.
  1582. @item Loss of power ... some adapters can detect these events.
  1583. @item Resets not issued through JTAG ... such reset sources
  1584. can include button presses or other system hardware, sometimes
  1585. including the target itself (perhaps through a watchdog).
  1586. @item Debug instrumentation sometimes supports event triggering
  1587. such as ``trace buffer full'' (so it can quickly be emptied)
  1588. or other signals (to correlate with code behavior).
  1589. @end itemize
  1590. None of those events are signaled through standard JTAG signals.
  1591. However, most conventions for JTAG connectors include voltage
  1592. level and system reset (SRST) signal detection.
  1593. Some connectors also include instrumentation signals, which
  1594. can imply events when those signals are inputs.
  1595. In general, OpenOCD needs to periodically check for those events,
  1596. either by looking at the status of signals on the JTAG connector
  1597. or by sending synchronous ``tell me your status'' JTAG requests
  1598. to the various active targets.
  1599. There is a command to manage and monitor that polling,
  1600. which is normally done in the background.
  1601. @deffn Command poll [@option{on}|@option{off}]
  1602. Poll the current target for its current state.
  1603. (Also, @pxref{target curstate}.)
  1604. If that target is in debug mode, architecture
  1605. specific information about the current state is printed.
  1606. An optional parameter
  1607. allows background polling to be enabled and disabled.
  1608. You could use this from the TCL command shell, or
  1609. from GDB using @command{monitor poll} command.
  1610. Leave background polling enabled while you're using GDB.
  1611. @example
  1612. > poll
  1613. background polling: on
  1614. target state: halted
  1615. target halted in ARM state due to debug-request, \
  1616. current mode: Supervisor
  1617. cpsr: 0x800000d3 pc: 0x11081bfc
  1618. MMU: disabled, D-Cache: disabled, I-Cache: enabled
  1619. >
  1620. @end example
  1621. @end deffn
  1622. @node Interface - Dongle Configuration
  1623. @chapter Interface - Dongle Configuration
  1624. @cindex config file, interface
  1625. @cindex interface config file
  1626. JTAG Adapters/Interfaces/Dongles are normally configured
  1627. through commands in an interface configuration
  1628. file which is sourced by your @file{openocd.cfg} file, or
  1629. through a command line @option{-f interface/....cfg} option.
  1630. @example
  1631. source [find interface/olimex-jtag-tiny.cfg]
  1632. @end example
  1633. These commands tell
  1634. OpenOCD what type of JTAG adapter you have, and how to talk to it.
  1635. A few cases are so simple that you only need to say what driver to use:
  1636. @example
  1637. # jlink interface
  1638. interface jlink
  1639. @end example
  1640. Most adapters need a bit more configuration than that.
  1641. @section Interface Configuration
  1642. The interface command tells OpenOCD what type of JTAG dongle you are
  1643. using. Depending on the type of dongle, you may need to have one or
  1644. more additional commands.
  1645. @deffn {Config Command} {interface} name
  1646. Use the interface driver @var{name} to connect to the
  1647. target.
  1648. @end deffn
  1649. @deffn Command {interface_list}
  1650. List the interface drivers that have been built into
  1651. the running copy of OpenOCD.
  1652. @end deffn
  1653. @deffn Command {jtag interface}
  1654. Returns the name of the interface driver being used.
  1655. @end deffn
  1656. @section Interface Drivers
  1657. Each of the interface drivers listed here must be explicitly
  1658. enabled when OpenOCD is configured, in order to be made
  1659. available at run time.
  1660. @deffn {Interface Driver} {amt_jtagaccel}
  1661. Amontec Chameleon in its JTAG Accelerator configuration,
  1662. connected to a PC's EPP mode parallel port.
  1663. This defines some driver-specific commands:
  1664. @deffn {Config Command} {parport_port} number
  1665. Specifies either the address of the I/O port (default: 0x378 for LPT1) or
  1666. the number of the @file{/dev/parport} device.
  1667. @end deffn
  1668. @deffn {Config Command} rtck [@option{enable}|@option{disable}]
  1669. Displays status of RTCK option.
  1670. Optionally sets that option first.
  1671. @end deffn
  1672. @end deffn
  1673. @deffn {Interface Driver} {arm-jtag-ew}
  1674. Olimex ARM-JTAG-EW USB adapter
  1675. This has one driver-specific command:
  1676. @deffn Command {armjtagew_info}
  1677. Logs some status
  1678. @end deffn
  1679. @end deffn
  1680. @deffn {Interface Driver} {at91rm9200}
  1681. Supports bitbanged JTAG from the local system,
  1682. presuming that system is an Atmel AT91rm9200
  1683. and a specific set of GPIOs is used.
  1684. @c command: at91rm9200_device NAME
  1685. @c chooses among list of bit configs ... only one option
  1686. @end deffn
  1687. @deffn {Interface Driver} {dummy}
  1688. A dummy software-only driver for debugging.
  1689. @end deffn
  1690. @deffn {Interface Driver} {ep93xx}
  1691. Cirrus Logic EP93xx based single-board computer bit-banging (in development)
  1692. @end deffn
  1693. @deffn {Interface Driver} {ft2232}
  1694. FTDI FT2232 (USB) based devices over one of the userspace libraries.
  1695. These interfaces have several commands, used to configure the driver
  1696. before initializing the JTAG scan chain:
  1697. @deffn {Config Command} {ft2232_device_desc} description
  1698. Provides the USB device description (the @emph{iProduct string})
  1699. of the FTDI FT2232 device. If not
  1700. specified, the FTDI default value is used. This setting is only valid
  1701. if compiled with FTD2XX support.
  1702. @end deffn
  1703. @deffn {Config Command} {ft2232_serial} serial-number
  1704. Specifies the @var{serial-number} of the FTDI FT2232 device to use,
  1705. in case the vendor provides unique IDs and more than one FT2232 device
  1706. is connected to the host.
  1707. If not specified, serial numbers are not considered.
  1708. (Note that USB serial numbers can be arbitrary Unicode strings,
  1709. and are not restricted to containing only decimal digits.)
  1710. @end deffn
  1711. @deffn {Config Command} {ft2232_layout} name
  1712. Each vendor's FT2232 device can use different GPIO signals
  1713. to control output-enables, reset signals, and LEDs.
  1714. Currently valid layout @var{name} values include:
  1715. @itemize @minus
  1716. @item @b{axm0432_jtag} Axiom AXM-0432
  1717. @item @b{comstick} Hitex STR9 comstick
  1718. @item @b{cortino} Hitex Cortino JTAG interface
  1719. @item @b{evb_lm3s811} Luminary Micro EVB_LM3S811 as a JTAG interface,
  1720. either for the local Cortex-M3 (SRST only)
  1721. or in a passthrough mode (neither SRST nor TRST)
  1722. This layout can not support the SWO trace mechanism, and should be
  1723. used only for older boards (before rev C).
  1724. @item @b{luminary_icdi} This layout should be used with most Luminary
  1725. eval boards, including Rev C LM3S811 eval boards and the eponymous
  1726. ICDI boards, to debug either the local Cortex-M3 or in passthrough mode
  1727. to debug some other target. It can support the SWO trace mechanism.
  1728. @item @b{flyswatter} Tin Can Tools Flyswatter
  1729. @item @b{icebear} ICEbear JTAG adapter from Section 5
  1730. @item @b{jtagkey} Amontec JTAGkey and JTAGkey-Tiny (and compatibles)
  1731. @item @b{jtagkey2} Amontec JTAGkey2 (and compatibles)
  1732. @item @b{m5960} American Microsystems M5960
  1733. @item @b{olimex-jtag} Olimex ARM-USB-OCD and ARM-USB-Tiny
  1734. @item @b{oocdlink} OOCDLink
  1735. @c oocdlink ~= jtagkey_prototype_v1
  1736. @item @b{sheevaplug} Marvell Sheevaplug development kit
  1737. @item @b{signalyzer} Xverve Signalyzer
  1738. @item @b{stm32stick} Hitex STM32 Performance Stick
  1739. @item @b{turtelizer2} egnite Software turtelizer2
  1740. @item @b{usbjtag} "USBJTAG-1" layout described in the OpenOCD diploma thesis
  1741. @end itemize
  1742. @end deffn
  1743. @deffn {Config Command} {ft2232_vid_pid} [vid pid]+
  1744. The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
  1745. default values are used.
  1746. Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
  1747. @example
  1748. ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
  1749. @end example
  1750. @end deffn
  1751. @deffn {Config Command} {ft2232_latency} ms
  1752. On some systems using FT2232 based JTAG interfaces the FT_Read function call in
  1753. ft2232_read() fails to return the expected number of bytes. This can be caused by
  1754. USB communication delays and has proved hard to reproduce and debug. Setting the
  1755. FT2232 latency timer to a larger value increases delays for short USB packets but it
  1756. also reduces the risk of timeouts before receiving the expected number of bytes.
  1757. The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
  1758. @end deffn
  1759. For example, the interface config file for a
  1760. Turtelizer JTAG Adapter looks something like this:
  1761. @example
  1762. interface ft2232
  1763. ft2232_device_desc "Turtelizer JTAG/RS232 Adapter"
  1764. ft2232_layout turtelizer2
  1765. ft2232_vid_pid 0x0403 0xbdc8
  1766. @end example
  1767. @end deffn
  1768. @deffn {Interface Driver} {usb_blaster}
  1769. USB JTAG/USB-Blaster compatibles over one of the userspace libraries
  1770. for FTDI chips. These interfaces have several commands, used to
  1771. configure the driver before initializing the JTAG scan chain:
  1772. @deffn {Config Command} {usb_blaster_device_desc} description
  1773. Provides the USB device description (the @emph{iProduct string})
  1774. of the FTDI FT245 device. If not
  1775. specified, the FTDI default value is used. This setting is only valid
  1776. if compiled with FTD2XX support.
  1777. @end deffn
  1778. @deffn {Config Command} {usb_blaster_vid_pid} vid pid
  1779. The vendor ID and product ID of the FTDI FT245 device. If not specified,
  1780. default values are used.
  1781. Currently, only one @var{vid}, @var{pid} pair may be given, e.g. for
  1782. Altera USB-Blaster (default):
  1783. @example
  1784. ft2232_vid_pid 0x09FB 0x6001
  1785. @end example
  1786. The following VID/PID is for Kolja Waschk's USB JTAG:
  1787. @example
  1788. ft2232_vid_pid 0x16C0 0x06AD
  1789. @end example
  1790. @end deffn
  1791. @deffn {Command} {usb_blaster} (@option{pin6}|@option{pin8}) (@option{0}|@option{1})
  1792. Sets the state of the unused GPIO pins on USB-Blasters (pins 6 and 8 on the
  1793. female JTAG header). These pins can be used as SRST and/or TRST provided the
  1794. appropriate connections are made on the target board.
  1795. For example, to use pin 6 as SRST (as with an AVR board):
  1796. @example
  1797. $_TARGETNAME configure -event reset-assert \
  1798. "usb_blaster pin6 1; wait 1; usb_blaster pin6 0"
  1799. @end example
  1800. @end deffn
  1801. @end deffn
  1802. @deffn {Interface Driver} {gw16012}
  1803. Gateworks GW16012 JTAG programmer.
  1804. This has one driver-specific command:
  1805. @deffn {Config Command} {parport_port} [port_number]
  1806. Display either the address of the I/O port
  1807. (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
  1808. If a parameter is provided, first switch to use that port.
  1809. This is a write-once setting.
  1810. @end deffn
  1811. @end deffn
  1812. @deffn {Interface Driver} {jlink}
  1813. Segger jlink USB adapter
  1814. @c command: jlink_info
  1815. @c dumps status
  1816. @c command: jlink_hw_jtag (2|3)
  1817. @c sets version 2 or 3
  1818. @end deffn
  1819. @deffn {Interface Driver} {parport}
  1820. Supports PC parallel port bit-banging cables:
  1821. Wigglers, PLD download cable, and more.
  1822. These interfaces have several commands, used to configure the driver
  1823. before initializing the JTAG scan chain:
  1824. @deffn {Config Command} {parport_cable} name
  1825. Set the layout of the parallel port cable used to connect to the target.
  1826. This is a write-once setting.
  1827. Currently valid cable @var{name} values include:
  1828. @itemize @minus
  1829. @item @b{altium} Altium Universal JTAG cable.
  1830. @item @b{arm-jtag} Same as original wiggler except SRST and
  1831. TRST connections reversed and TRST is also inverted.
  1832. @item @b{chameleon} The Amontec Chameleon's CPLD when operated
  1833. in configuration mode. This is only used to
  1834. program the Chameleon itself, not a connected target.
  1835. @item @b{dlc5} The Xilinx Parallel cable III.
  1836. @item @b{flashlink} The ST Parallel cable.
  1837. @item @b{lattice} Lattice ispDOWNLOAD Cable
  1838. @item @b{old_amt_wiggler} The Wiggler configuration that comes with
  1839. some versions of
  1840. Amontec's Chameleon Programmer. The new version available from
  1841. the website uses the original Wiggler layout ('@var{wiggler}')
  1842. @item @b{triton} The parallel port adapter found on the
  1843. ``Karo Triton 1 Development Board''.
  1844. This is also the layout used by the HollyGates design
  1845. (see @uref{}).
  1846. @item @b{wiggler} The original Wiggler layout, also supported by
  1847. several clones, such as the Olimex ARM-JTAG
  1848. @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
  1849. @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
  1850. @end itemize
  1851. @end deffn
  1852. @deffn {Config Command} {parport_port} [port_number]
  1853. Display either the address of the I/O port
  1854. (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
  1855. If a parameter is provided, first switch to use that port.
  1856. This is a write-once setting.
  1857. When using PPDEV to access the parallel port, use the number of the parallel port:
  1858. @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
  1859. you may encounter a problem.
  1860. @end deffn
  1861. @deffn Command {parport_toggling_time} [nanoseconds]
  1862. Displays how many nanoseconds the hardware needs to toggle TCK;
  1863. the parport driver uses this value to obey the
  1864. @command{jtag_khz} configuration.
  1865. When the optional @var{nanoseconds} parameter is given,
  1866. that setting is changed before displaying the current value.
  1867. The default setting should work reasonably well on commodity PC hardware.
  1868. However, you may want to calibrate for your specific hardware.
  1869. @quotation Tip
  1870. To measure the toggling time with a logic analyzer or a digital storage
  1871. oscilloscope, follow the procedure below:
  1872. @example
  1873. > parport_toggling_time 1000
  1874. > jtag_khz 500
  1875. @end example
  1876. This sets the maximum JTAG clock speed of the hardware, but
  1877. the actual speed probably deviates from the requested 500 kHz.
  1878. Now, measure the time between the two closest spaced TCK transitions.
  1879. You can use @command{runtest 1000} or something similar to generate a
  1880. large set of samples.
  1881. Update the setting to match your measurement:
  1882. @example
  1883. > parport_toggling_time <measured nanoseconds>
  1884. @end example
  1885. Now the clock speed will be a better match for @command{jtag_khz rate}
  1886. commands given in OpenOCD scripts and event handlers.
  1887. You can do something similar with many digital multimeters, but note
  1888. that you'll probably need to run the clock continuously for several
  1889. seconds before it decides what clock rate to show. Adjust the
  1890. toggling time up or down until the measured clock rate is a good
  1891. match for the jtag_khz rate you specified; be conservative.
  1892. @end quotation
  1893. @end deffn
  1894. @deffn {Config Command} {parport_write_on_exit} (@option{on}|@option{off})
  1895. This will configure the parallel driver to write a known
  1896. cable-specific value to the parallel interface on exiting OpenOCD.
  1897. @end deffn
  1898. For example, the interface configuration file for a
  1899. classic ``Wiggler'' cable on LPT2 might look something like this:
  1900. @example
  1901. interface parport
  1902. parport_port 0x278
  1903. parport_cable wiggler
  1904. @end example
  1905. @end deffn
  1906. @deffn {Interface Driver} {presto}
  1907. ASIX PRESTO USB JTAG programmer.
  1908. @deffn {Config Command} {presto_serial} serial_string
  1909. Configures the USB serial number of the Presto device to use.
  1910. @end deffn
  1911. @end deffn
  1912. @deffn {Interface Driver} {rlink}
  1913. Raisonance RLink USB adapter
  1914. @end deffn
  1915. @deffn {Interface Driver} {usbprog}
  1916. usbprog is a freely programmable USB adapter.
  1917. @end deffn
  1918. @deffn {Interface Driver} {vsllink}
  1919. vsllink is part of Versaloon which is a versatile USB programmer.
  1920. @quotation Note
  1921. This defines quite a few driver-specific commands,
  1922. which are not currently documented here.
  1923. @end quotation
  1924. @end deffn
  1925. @deffn {Interface Driver} {ZY1000}
  1926. This is the Zylin ZY1000 JTAG debugger.
  1927. @quotation Note
  1928. This defines some driver-specific commands,
  1929. which are not currently documented here.
  1930. @end quotation
  1931. @deffn Command power [@option{on}|@option{off}]
  1932. Turn power switch to target on/off.
  1933. No arguments: print status.
  1934. @end deffn
  1935. @end deffn
  1936. @anchor{JTAG Speed}
  1937. @section JTAG Speed
  1938. JTAG clock setup is part of system setup.
  1939. It @emph{does not belong with interface setup} since any interface
  1940. only knows a few of the constraints for the JTAG clock speed.
  1941. Sometimes the JTAG speed is
  1942. changed during the target initialization process: (1) slow at
  1943. reset, (2) program the CPU clocks, (3) run fast.
  1944. Both the "slow" and "fast" clock rates are functions of the
  1945. oscillators used, the chip, the board design, and sometimes
  1946. power management software that may be active.
  1947. The speed used during reset, and the scan chain verification which
  1948. follows reset, can be adjusted using a @code{reset-start}
  1949. target event handler.
  1950. It can then be reconfigured to a faster speed by a
  1951. @code{reset-init} target event handler after it reprograms those
  1952. CPU clocks, or manually (if something else, such as a boot loader,
  1953. sets up those clocks).
  1954. @xref{Target Events}.
  1955. When the initial low JTAG speed is a chip characteristic, perhaps
  1956. because of a required oscillator speed, provide such a handler
  1957. in the target config file.
  1958. When that speed is a function of a board-specific characteristic
  1959. such as which speed oscillator is used, it belongs in the board
  1960. config file instead.
  1961. In both cases it's safest to also set the initial JTAG clock rate
  1962. to that same slow speed, so that OpenOCD never starts up using a
  1963. clock speed that's faster than the scan chain can support.
  1964. @example
  1965. jtag_rclk 3000
  1966. $_TARGET.cpu configure -event reset-start @{ jtag_rclk 3000 @}
  1967. @end example
  1968. If your system supports adaptive clocking (RTCK), configuring
  1969. JTAG to use that is probably the most robust approach.
  1970. However, it introduces delays to synchronize clocks; so it
  1971. may not be the fastest solution.
  1972. @b{NOTE:} Script writers should consider using @command{jtag_rclk}
  1973. instead of @command{jtag_khz}.
  1974. @deffn {Command} jtag_khz max_speed_kHz
  1975. A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
  1976. JTAG interfaces usually support a limited number of
  1977. speeds. The speed actually used won't be faster
  1978. than the speed specified.
  1979. Chip data sheets generally include a top JTAG clock rate.
  1980. The actual rate is often a function of a CPU core clock,
  1981. and is normally less than that peak rate.
  1982. For example, most ARM cores accept at most one sixth of the CPU clock.
  1983. Speed 0 (khz) selects RTCK method.
  1984. @xref{FAQ RTCK}.
  1985. If your system uses RTCK, you won't need to change the
  1986. JTAG clocking after setup.
  1987. Not all interfaces, boards, or targets support ``rtck''.
  1988. If the interface device can not
  1989. support it, an error is returned when you try to use RTCK.
  1990. @end deffn
  1991. @defun jtag_rclk fallback_speed_kHz
  1992. @cindex adaptive clocking
  1993. @cindex RTCK
  1994. This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
  1995. If that fails (maybe the interface, board, or target doesn't
  1996. support it), falls back to the specified frequency.
  1997. @example
  1998. # Fall back to 3mhz if RTCK is not supported
  1999. jtag_rclk 3000
  2000. @end example
  2001. @end defun
  2002. @node Reset Configuration
  2003. @chapter Reset Configuration
  2004. @cindex Reset Configuration
  2005. Every system configuration may require a different reset
  2006. configuration. This can also be quite confusing.
  2007. Resets also interact with @var{reset-init} event handlers,
  2008. which do things like setting up clocks and DRAM, and
  2009. JTAG clock rates. (@xref{JTAG Speed}.)
  2010. They can also interact with JTAG routers.
  2011. Please see the various board files for examples.
  2012. @quotation Note
  2013. To maintainers and integrators:
  2014. Reset configuration touches several things at once.
  2015. Normally the board configuration file
  2016. should define it and assume that the JTAG adapter supports
  2017. everything that's wired up to the board's JTAG connector.
  2018. However, the target configuration file could also make note
  2019. of something the silicon vendor has done inside the chip,
  2020. which will be true for most (or all) boards using that chip.
  2021. And when the JTAG adapter doesn't support everything, the
  2022. user configuration file will need to override parts of
  2023. the reset configuration provided by other files.
  2024. @end quotation
  2025. @section Types of Reset
  2026. There are many kinds of reset possible through JTAG, but
  2027. they may not all work with a given board and adapter.
  2028. That's part of why reset configuration can be error prone.
  2029. @itemize @bullet
  2030. @item
  2031. @emph{System Reset} ... the @emph{SRST} hardware signal
  2032. resets all chips connected to the JTAG adapter, such as processors,
  2033. power management chips, and I/O controllers. Normally resets triggered
  2034. with this signal behave exactly like pressing a RESET button.
  2035. @item
  2036. @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
  2037. just the TAP controllers connected to the JTAG adapter.
  2038. Such resets should not be visible to the rest of the system; resetting a
  2039. device's the TAP controller just puts that controller into a known state.
  2040. @item
  2041. @emph{Emulation Reset} ... many devices can be reset through JTAG
  2042. commands. These resets are often distinguishable from system
  2043. resets, either explicitly (a "reset reason" register says so)
  2044. or implicitly (not all parts of the chip get reset).
  2045. @item
  2046. @emph{Other Resets} ... system-on-chip devices often support
  2047. several other types of reset.
  2048. You may need to arrange that a watchdog timer stops
  2049. while debugging, preventing a watchdog reset.
  2050. There may be individual module resets.
  2051. @end itemize
  2052. In the best case, OpenOCD can hold SRST, then reset
  2053. the TAPs via TRST and send commands through JTAG to halt the
  2054. CPU at the reset vector before the 1st instruction is executed.
  2055. Then when it finally releases the SRST signal, the system is
  2056. halted under debugger control before any code has executed.
  2057. This is the behavior required to support the @command{reset halt}
  2058. and @command{reset init} commands; after @command{reset init} a
  2059. board-specific script might do things like setting up DRAM.
  2060. (@xref{Reset Command}.)
  2061. @anchor{SRST and TRST Issues}
  2062. @section SRST and TRST Issues
  2063. Because SRST and TRST are hardware signals, they can have a
  2064. variety of system-specific constraints. Some of the most
  2065. common issues are:
  2066. @itemize @bullet
  2067. @item @emph{Signal not available} ... Some boards don't wire
  2068. SRST or TRST to the JTAG connector. Some JTAG adapters don't
  2069. support such signals even if they are wired up.
  2070. Use the @command{reset_config} @var{signals} options to say
  2071. when either of those signals is not connected.
  2072. When SRST is not available, your code might not be able to rely
  2073. on controllers having been fully reset during code startup.
  2074. Missing TRST is not a problem, since JTAG level resets can
  2075. be triggered using with TMS signaling.
  2076. @item @emph{Signals shorted} ... Sometimes a chip, board, or
  2077. adapter will connect SRST to TRST, instead of keeping them separate.
  2078. Use the @command{reset_config} @var{combination} options to say
  2079. when those signals aren't properly independent.
  2080. @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
  2081. delay circuit, reset supervisor, or on-chip features can extend
  2082. the effect of a JTAG adapter's reset for some time after the adapter
  2083. stops issuing the reset. For example, there may be chip or board
  2084. requirements that all reset pulses last for at least a
  2085. certain amount of time; and reset buttons commonly have
  2086. hardware debouncing.
  2087. Use the @command{jtag_nsrst_delay} and @command{jtag_ntrst_delay}
  2088. commands to say when extra delays are needed.
  2089. @item @emph{Drive type} ... Reset lines often have a pullup
  2090. resistor, letting the JTAG interface treat them as open-drain
  2091. signals. But that's not a requirement, so the adapter may need
  2092. to use push/pull output drivers.
  2093. Also, with weak pullups it may be advisable to drive
  2094. signals to both levels (push/pull) to minimize rise times.
  2095. Use the @command{reset_config} @var{trst_type} and
  2096. @var{srst_type} parameters to say how to drive reset signals.
  2097. @item @emph{Special initialization} ... Targets sometimes need
  2098. special JTAG initialization sequences to handle chip-specific
  2099. issues (not limited to errata).
  2100. For example, certain JTAG commands might need to be issued while
  2101. the system as a whole is in a reset state (SRST active)
  2102. but the JTAG scan chain is usable (TRST inactive).
  2103. Many systems treat combined assertion of SRST and TRST as a
  2104. trigger for a harder reset than SRST alone.
  2105. Such custom reset handling is discussed later in this chapter.
  2106. @end itemize
  2107. There can also be other issues.
  2108. Some devices don't fully conform to the JTAG specifications.
  2109. Trivial system-specific differences are common, such as
  2110. SRST and TRST using slightly different names.
  2111. There are also vendors who distribute key JTAG documentation for
  2112. their chips only to developers who have signed a Non-Disclosure
  2113. Agreement (NDA).
  2114. Sometimes there are chip-specific extensions like a requirement to use
  2115. the normally-optional TRST signal (precluding use of JTAG adapters which
  2116. don't pass TRST through), or needing extra steps to complete a TAP reset.
  2117. In short, SRST and especially TRST handling may be very finicky,
  2118. needing to cope with both architecture and board specific constraints.
  2119. @section Commands for Handling Resets
  2120. @deffn {Command} jtag_nsrst_assert_width milliseconds
  2121. Minimum amount of time (in milliseconds) OpenOCD should wait
  2122. after asserting nSRST (active-low system reset) before
  2123. allowing it to be deasserted.
  2124. @end deffn
  2125. @deffn {Command} jtag_nsrst_delay milliseconds
  2126. How long (in milliseconds) OpenOCD should wait after deasserting
  2127. nSRST (active-low system reset) before starting new JTAG operations.
  2128. When a board has a reset button connected to SRST line it will
  2129. probably have hardware debouncing, implying you should use this.
  2130. @end deffn
  2131. @deffn {Command} jtag_ntrst_assert_width milliseconds
  2132. Minimum amount of time (in milliseconds) OpenOCD should wait
  2133. after asserting nTRST (active-low JTAG TAP reset) before
  2134. allowing it to be deasserted.
  2135. @end deffn
  2136. @deffn {Command} jtag_ntrst_delay milliseconds
  2137. How long (in milliseconds) OpenOCD should wait after deasserting
  2138. nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
  2139. @end deffn
  2140. @deffn {Command} reset_config mode_flag ...
  2141. This command displays or modifies the reset configuration
  2142. of your combination of JTAG board and target in target
  2143. configuration scripts.
  2144. Information earlier in this section describes the kind of problems
  2145. the command is intended to address (@pxref{SRST and TRST Issues}).
  2146. As a rule this command belongs only in board config files,
  2147. describing issues like @emph{board doesn't connect TRST};
  2148. or in user config files, addressing limitations derived
  2149. from a particular combination of interface and board.
  2150. (An unlikely example would be using a TRST-only adapter
  2151. with a board that only wires up SRST.)
  2152. The @var{mode_flag} options can be specified in any order, but only one
  2153. of each type -- @var{signals}, @var{combination},
  2154. @var{gates},
  2155. @var{trst_type},
  2156. and @var{srst_type} -- may be specified at a time.
  2157. If you don't provide a new value for a given type, its previous
  2158. value (perhaps the default) is unchanged.
  2159. For example, this means that you don't need to say anything at all about
  2160. TRST just to declare that if the JTAG adapter should want to drive SRST,
  2161. it must explicitly be driven high (@option{srst_push_pull}).
  2162. @itemize
  2163. @item
  2164. @var{signals} can specify which of the reset signals are connected.
  2165. For example, If the JTAG interface provides SRST, but the board doesn't
  2166. connect that signal properly, then OpenOCD can't use it.
  2167. Possible values are @option{none} (the default), @option{trst_only},
  2168. @option{srst_only} and @option{trst_and_srst}.
  2169. @quotation Tip
  2170. If your board provides SRST and/or TRST through the JTAG connector,
  2171. you must declare that so those signals can be used.
  2172. @end quotation
  2173. @item
  2174. The @var{combination} is an optional value specifying broken reset
  2175. signal implementations.
  2176. The default behaviour if no option given is @option{separate},
  2177. indicating everything behaves normally.
  2178. @option{srst_pulls_trst} states that the
  2179. test logic is reset together with the reset of the system (e.g. NXP
  2180. LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
  2181. the system is reset together with the test logic (only hypothetical, I
  2182. haven't seen hardware with such a bug, and can be worked around).
  2183. @option{combined} implies both @option{srst_pulls_trst} and
  2184. @option{trst_pulls_srst}.
  2185. @item
  2186. The @var{gates} tokens control flags that describe some cases where
  2187. JTAG may be unvailable during reset.
  2188. @option{srst_gates_jtag} (default)
  2189. indicates that asserting SRST gates the
  2190. JTAG clock. This means that no communication can happen on JTAG
  2191. while SRST is asserted.
  2192. Its converse is @option{srst_nogate}, indicating that JTAG commands
  2193. can safely be issued while SRST is active.
  2194. @end itemize
  2195. The optional @var{trst_type} and @var{srst_type} parameters allow the
  2196. driver mode of each reset line to be specified. These values only affect
  2197. JTAG interfaces with support for different driver modes, like the Amontec
  2198. JTAGkey and JTAG Accelerator. Also, they are necessarily ignored if the
  2199. relevant signal (TRST or SRST) is not connected.
  2200. @itemize
  2201. @item
  2202. Possible @var{trst_type} driver modes for the test reset signal (TRST)
  2203. are the default @option{trst_push_pull}, and @option{trst_open_drain}.
  2204. Most boards connect this signal to a pulldown, so the JTAG TAPs
  2205. never leave reset unless they are hooked up to a JTAG adapter.
  2206. @item
  2207. Possible @var{srst_type} driver modes for the system reset signal (SRST)
  2208. are the default @option{srst_open_drain}, and @option{srst_push_pull}.
  2209. Most boards connect this signal to a pullup, and allow the
  2210. signal to be pulled low by various events including system
  2211. powerup and pressing a reset button.
  2212. @end itemize
  2213. @end deffn
  2214. @section Custom Reset Handling
  2215. @cindex events
  2216. OpenOCD has several ways to help support the various reset
  2217. mechanisms provided by chip and board vendors.
  2218. The commands shown in the previous section give standard parameters.
  2219. There are also @emph{event handlers} associated with TAPs or Targets.
  2220. Those handlers are Tcl procedures you can provide, which are invoked
  2221. at particular points in the reset sequence.
  2222. @emph{When SRST is not an option} you must set
  2223. up a @code{reset-assert} event handler for your target.
  2224. For example, some JTAG adapters don't include the SRST signal;
  2225. and some boards have multiple targets, and you won't always
  2226. want to reset everything at once.
  2227. After configuring those mechanisms, you might still
  2228. find your board doesn't start up or reset correctly.
  2229. For example, maybe it needs a slightly different sequence
  2230. of SRST and/or TRST manipulations, because of quirks that
  2231. the @command{reset_config} mechanism doesn't address;
  2232. or asserting both might trigger a stronger reset, which
  2233. needs special attention.
  2234. Experiment with lower level operations, such as @command{jtag_reset}
  2235. and the @command{jtag arp_*} operations shown here,
  2236. to find a sequence of operations that works.
  2237. @xref{JTAG Commands}.
  2238. When you find a working sequence, it can be used to override
  2239. @command{jtag_init}, which fires during OpenOCD startup
  2240. (@pxref{Configuration Stage});
  2241. or @command{init_reset}, which fires during reset processing.
  2242. You might also want to provide some project-specific reset
  2243. schemes. For example, on a multi-target board the standard
  2244. @command{reset} command would reset all targets, but you
  2245. may need the ability to reset only one target at time and
  2246. thus want to avoid using the board-wide SRST signal.
  2247. @deffn {Overridable Procedure} init_reset mode
  2248. This is invoked near the beginning of the @command{reset} command,
  2249. usually to provide as much of a cold (power-up) reset as practical.
  2250. By default it is also invoked from @command{jtag_init} if
  2251. the scan chain does not respond to pure JTAG operations.
  2252. The @var{mode} parameter is the parameter given to the
  2253. low level reset command (@option{halt},
  2254. @option{init}, or @option{run}), @option{setup},
  2255. or potentially some other value.
  2256. The default implementation just invokes @command{jtag arp_init-reset}.
  2257. Replacements will normally build on low level JTAG
  2258. operations such as @command{jtag_reset}.
  2259. Operations here must not address individual TAPs
  2260. (or their associated targets)
  2261. until the JTAG scan chain has first been verified to work.
  2262. Implementations must have verified the JTAG scan chain before
  2263. they return.
  2264. This is done by calling @command{jtag arp_init}
  2265. (or @command{jtag arp_init-reset}).
  2266. @end deffn
  2267. @deffn Command {jtag arp_init}
  2268. This validates the scan chain using just the four
  2269. standard JTAG signals (TMS, TCK, TDI, TDO).
  2270. It starts by issuing a JTAG-only reset.
  2271. Then it performs checks to verify that the scan chain configuration
  2272. matches the TAPs it can observe.
  2273. Those checks include checking IDCODE values for each active TAP,
  2274. and verifying the length of their instruction registers using
  2275. TAP @code{-ircapture} and @code{-irmask} values.
  2276. If these tests all pass, TAP @code{setup} events are
  2277. issued to all TAPs with handlers for that event.
  2278. @end deffn
  2279. @deffn Command {jtag arp_init-reset}
  2280. This uses TRST and SRST to try resetting
  2281. everything on the JTAG scan chain
  2282. (and anything else connected to SRST).
  2283. It then invokes the logic of @command{jtag arp_init}.
  2284. @end deffn
  2285. @node TAP Declaration
  2286. @chapter TAP Declaration
  2287. @cindex TAP declaration
  2288. @cindex TAP configuration
  2289. @emph{Test Access Ports} (TAPs) are the core of JTAG.
  2290. TAPs serve many roles, including:
  2291. @itemize @bullet
  2292. @item @b{Debug Target} A CPU TAP can be used as a GDB debug target
  2293. @item @b{Flash Programing} Some chips program the flash directly via JTAG.
  2294. Others do it indirectly, making a CPU do it.
  2295. @item @b{Program Download} Using the same CPU support GDB uses,
  2296. you can initialize a DRAM controller, download code to DRAM, and then
  2297. start running that code.
  2298. @item @b{Boundary Scan} Most chips support boundary scan, which
  2299. helps test for board assembly problems like solder bridges
  2300. and missing connections
  2301. @end itemize
  2302. OpenOCD must know about the active TAPs on your board(s).
  2303. Setting up the TAPs is the core task of your configuration files.
  2304. Once those TAPs are set up, you can pass their names to code
  2305. which sets up CPUs and exports them as GDB targets,
  2306. probes flash memory, performs low-level JTAG operations, and more.
  2307. @section Scan Chains
  2308. @cindex scan chain
  2309. TAPs are part of a hardware @dfn{scan chain},
  2310. which is daisy chain of TAPs.
  2311. They also need to be added to
  2312. OpenOCD's software mirror of that hardware list,
  2313. giving each member a name and associating other data with it.
  2314. Simple scan chains, with a single TAP, are common in
  2315. systems with a single microcontroller or microprocessor.
  2316. More complex chips may have several TAPs internally.
  2317. Very complex scan chains might have a dozen or more TAPs:
  2318. several in one chip, more in the next, and connecting
  2319. to other boards with their own chips and TAPs.
  2320. You can display the list with the @command{scan_chain} command.
  2321. (Don't confuse this with the list displayed by the @command{targets}
  2322. command, presented in the next chapter.
  2323. That only displays TAPs for CPUs which are configured as
  2324. debugging targets.)
  2325. Here's what the scan chain might look like for a chip more than one TAP:
  2326. @verbatim
  2327. TapName Enabled IdCode Expected IrLen IrCap IrMask
  2328. -- ------------------ ------- ---------- ---------- ----- ----- ------
  2329. 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0x01 0x03
  2330. 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x01 0x0f
  2331. 2 omap5912.unknown Y 0x00000000 0x00000000 8 0x01 0x03
  2332. @end verbatim
  2333. OpenOCD can detect some of that information, but not all
  2334. of it. @xref{Autoprobing}.
  2335. Unfortunately those TAPs can't always be autoconfigured,
  2336. because not all devices provide good support for that.
  2337. JTAG doesn't require supporting IDCODE instructions, and
  2338. chips with JTAG routers may not link TAPs into the chain
  2339. until they are told to do so.
  2340. The configuration mechanism currently supported by OpenOCD
  2341. requires explicit configuration of all TAP devices using
  2342. @command{jtag newtap} commands, as detailed later in this chapter.
  2343. A command like this would declare one tap and name it @code{chip1.cpu}:
  2344. @example
  2345. jtag newtap chip1 cpu -irlen 4 -expected-id 0x3ba00477
  2346. @end example
  2347. Each target configuration file lists the TAPs provided
  2348. by a given chip.
  2349. Board configuration files combine all the targets on a board,
  2350. and so forth.
  2351. Note that @emph{the order in which TAPs are declared is very important.}
  2352. It must match the order in the JTAG scan chain, both inside
  2353. a single chip and between them.
  2354. @xref{FAQ TAP Order}.
  2355. For example, the ST Microsystems STR912 chip has
  2356. three separate TAPs@footnote{See the ST
  2357. document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
  2358. 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
  2359. @url{}}.
  2360. To configure those taps, @file{target/str912.cfg}
  2361. includes commands something like this:
  2362. @example
  2363. jtag newtap str912 flash ... params ...
  2364. jtag newtap str912 cpu ... params ...
  2365. jtag newtap str912 bs ... params ...
  2366. @end example
  2367. Actual config files use a variable instead of literals like
  2368. @option{str912}, to support more than one chip of each type.
  2369. @xref{Config File Guidelines}.
  2370. @deffn Command {jtag names}
  2371. Returns the names of all current TAPs in the scan chain.
  2372. Use @command{jtag cget} or @command{jtag tapisenabled}
  2373. to examine attributes and state of each TAP.
  2374. @example
  2375. foreach t [jtag names] @{
  2376. puts [format "TAP: %s\n" $t]
  2377. @}
  2378. @end example
  2379. @end deffn
  2380. @deffn Command {scan_chain}
  2381. Displays the TAPs in the scan chain configuration,
  2382. and their status.
  2383. The set of TAPs listed by this command is fixed by
  2384. exiting the OpenOCD configuration stage,
  2385. but systems with a JTAG router can
  2386. enable or disable TAPs dynamically.
  2387. @end deffn
  2388. @c FIXME! "jtag cget" should be able to return all TAP
  2389. @c attributes, like "$target_name cget" does for targets.
  2390. @c Probably want "jtag eventlist", and a "tap-reset" event
  2391. @c (on entry to RESET state).
  2392. @section TAP Names
  2393. @cindex dotted name
  2394. When TAP objects are declared with @command{jtag newtap},
  2395. a @dfn{} is created for the TAP, combining the
  2396. name of a module (usually a chip) and a label for the TAP.
  2397. For example: @code{xilinx.tap}, @code{str912.flash},
  2398. @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
  2399. Many other commands use that to manipulate or
  2400. refer to the TAP. For example, CPU configuration uses the
  2401. name, as does declaration of NAND or NOR flash banks.
  2402. The components of a dotted name should follow ``C'' symbol
  2403. name rules: start with an alphabetic character, then numbers
  2404. and underscores are OK; while others (including dots!) are not.
  2405. @quotation Tip
  2406. In older code, JTAG TAPs were numbered from 0..N.
  2407. This feature is still present.
  2408. However its use is highly discouraged, and
  2409. should not be relied on; it will be removed by mid-2010.
  2410. Update all of your scripts to use TAP names rather than numbers,
  2411. by paying attention to the runtime warnings they trigger.
  2412. Using TAP numbers in target configuration scripts prevents
  2413. reusing those scripts on boards with multiple targets.
  2414. @end quotation
  2415. @section TAP Declaration Commands
  2416. @c shouldn't this be(come) a {Config Command}?
  2417. @anchor{jtag newtap}
  2418. @deffn Command {jtag newtap} chipname tapname configparams...
  2419. Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
  2420. and configured according to the various @var{configparams}.
  2421. The @var{chipname} is a symbolic name for the chip.
  2422. Conventionally target config files use @code{$_CHIPNAME},
  2423. defaulting to the model name given by the chip vendor but
  2424. overridable.
  2425. @cindex TAP naming convention
  2426. The @var{tapname} reflects the role of that TAP,
  2427. and should follow this convention:
  2428. @itemize @bullet
  2429. @item @code{bs} -- For boundary scan if this is a seperate TAP;
  2430. @item @code{cpu} -- The main CPU of the chip, alternatively
  2431. @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
  2432. @code{arm1} and @code{arm2} on chips two ARMs, and so forth;
  2433. @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
  2434. @item @code{flash} -- If the chip has a flash TAP, like the str912;
  2435. @item @code{jrc} -- For JTAG route controller (example: the ICEpick modules
  2436. on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
  2437. @item @code{tap} -- Should be used only FPGA or CPLD like devices
  2438. with a single TAP;
  2439. @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
  2440. @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
  2441. For example, the Freescale IMX31 has a SDMA (Smart DMA) with
  2442. a JTAG TAP; that TAP should be named @code{sdma}.
  2443. @end itemize
  2444. Every TAP requires at least the following @var{configparams}:
  2445. @itemize @bullet
  2446. @item @code{-irlen} @var{NUMBER}
  2447. @*The length in bits of the
  2448. instruction register, such as 4 or 5 bits.
  2449. @end itemize
  2450. A TAP may also provide optional @var{configparams}:
  2451. @itemize @bullet
  2452. @item @code{-disable} (or @code{-enable})
  2453. @*Use the @code{-disable} parameter to flag a TAP which is not
  2454. linked in to the scan chain after a reset using either TRST
  2455. or the JTAG state machine's @sc{reset} state.
  2456. You may use @code{-enable} to highlight the default state
  2457. (the TAP is linked in).
  2458. @xref{Enabling and Disabling TAPs}.
  2459. @item @code{-expected-id} @var{number}
  2460. @*A non-zero @var{number} represents a 32-bit IDCODE
  2461. which you expect to find when the scan chain is examined.
  2462. These codes are not required by all JTAG devices.
  2463. @emph{Repeat the option} as many times as required if more than one
  2464. ID code could appear (for example, multiple versions).
  2465. Specify @var{number} as zero to suppress warnings about IDCODE
  2466. values that were found but not included in the list.
  2467. Provide this value if at all possible, since it lets OpenOCD
  2468. tell when the scan chain it sees isn't right. These values
  2469. are provided in vendors' chip documentation, usually a technical
  2470. reference manual. Sometimes you may need to probe the JTAG
  2471. hardware to find these values.
  2472. @xref{Autoprobing}.
  2473. @item @code{-ignore-version}
  2474. @*Specify this to ignore the JTAG version field in the @code{-expected-id}
  2475. option. When vendors put out multiple versions of a chip, or use the same
  2476. JTAG-level ID for several largely-compatible chips, it may be more practical
  2477. to ignore the version field than to update config files to handle all of
  2478. the various chip IDs.
  2479. @item @code{-ircapture} @var{NUMBER}
  2480. @*The bit pattern loaded by the TAP into the JTAG shift register
  2481. on entry to the @sc{ircapture} state, such as 0x01.
  2482. JTAG requires the two LSBs of this value to be 01.
  2483. By default, @code{-ircapture} and @code{-irmask} are set
  2484. up to verify that two-bit value. You may provide
  2485. additional bits, if you know them, or indicate that
  2486. a TAP doesn't conform to the JTAG specification.
  2487. @item @code{-irmask} @var{NUMBER}
  2488. @*A mask used with @code{-ircapture}
  2489. to verify that instruction scans work correctly.
  2490. Such scans are not used by OpenOCD except to verify that
  2491. there seems to be no problems with JTAG scan chain operations.
  2492. @end itemize
  2493. @end deffn
  2494. @section Other TAP commands
  2495. @deffn Command {jtag cget} @option{-event} name
  2496. @deffnx Command {jtag configure} @option{-event} name string
  2497. At this writing this TAP attribute
  2498. mechanism is used only for event handling.
  2499. (It is not a direct analogue of the @code{cget}/@code{configure}
  2500. mechanism for debugger targets.)
  2501. See the next section for information about the available events.
  2502. The @code{configure} subcommand assigns an event handler,
  2503. a TCL string which is evaluated when the event is triggered.
  2504. The @code{cget} subcommand returns that handler.
  2505. @end deffn
  2506. @anchor{TAP Events}
  2507. @section TAP Events
  2508. @cindex events
  2509. @cindex TAP events
  2510. OpenOCD includes two event mechanisms.
  2511. The one presented here applies to all JTAG TAPs.
  2512. The other applies to debugger targets,
  2513. which are associated with certain TAPs.
  2514. The TAP events currently defined are:
  2515. @itemize @bullet
  2516. @item @b{post-reset}
  2517. @* The TAP has just completed a JTAG reset.
  2518. The tap may still be in the JTAG @sc{reset} state.
  2519. Handlers for these events might perform initialization sequences
  2520. such as issuing TCK cycles, TMS sequences to ensure
  2521. exit from the ARM SWD mode, and more.
  2522. Because the scan chain has not yet been verified, handlers for these events
  2523. @emph{should not issue commands which scan the JTAG IR or DR registers}
  2524. of any particular target.
  2525. @b{NOTE:} As this is written (September 2009), nothing prevents such access.
  2526. @item @b{setup}
  2527. @* The scan chain has been reset and verified.
  2528. This handler may enable TAPs as needed.
  2529. @item @b{tap-disable}
  2530. @* The TAP needs to be disabled. This handler should
  2531. implement @command{jtag tapdisable}
  2532. by issuing the relevant JTAG commands.
  2533. @item @b{tap-enable}
  2534. @* The TAP needs to be enabled. This handler should
  2535. implement @command{jtag tapenable}
  2536. by issuing the relevant JTAG commands.
  2537. @end itemize
  2538. If you need some action after each JTAG reset, which isn't actually
  2539. specific to any TAP (since you can't yet trust the scan chain's
  2540. contents to be accurate), you might:
  2541. @example
  2542. jtag configure CHIP.jrc -event post-reset @{
  2543. echo "JTAG Reset done"
  2544. ... non-scan jtag operations to be done after reset
  2545. @}
  2546. @end example
  2547. @anchor{Enabling and Disabling TAPs}
  2548. @section Enabling and Disabling TAPs
  2549. @cindex JTAG Route Controller
  2550. @cindex jrc
  2551. In some systems, a @dfn{JTAG Route Controller} (JRC)
  2552. is used to enable and/or disable specific JTAG TAPs.
  2553. Many ARM based chips from Texas Instruments include
  2554. an ``ICEpick'' module, which is a JRC.
  2555. Such chips include DaVinci and OMAP3 processors.
  2556. A given TAP may not be visible until the JRC has been
  2557. told to link it into the scan chain; and if the JRC
  2558. has been told to unlink that TAP, it will no longer
  2559. be visible.
  2560. Such routers address problems that JTAG ``bypass mode''
  2561. ignores, such as:
  2562. @itemize
  2563. @item The scan chain can only go as fast as its slowest TAP.
  2564. @item Having many TAPs slows instruction scans, since all
  2565. TAPs receive new instructions.
  2566. @item TAPs in the scan chain must be powered up, which wastes
  2567. power and prevents debugging some power management mechanisms.
  2568. @end itemize
  2569. The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
  2570. as implied by the existence of JTAG routers.
  2571. However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
  2572. does include a kind of JTAG router functionality.
  2573. @c (a) currently the event handlers don't seem to be able to
  2574. @c fail in a way that could lead to no-change-of-state.
  2575. In OpenOCD, tap enabling/disabling is invoked by the Tcl commands
  2576. shown below, and is implemented using TAP event handlers.
  2577. So for example, when defining a TAP for a CPU connected to
  2578. a JTAG router, your @file{target.cfg} file
  2579. should define TAP event handlers using
  2580. code that looks something like this:
  2581. @example
  2582. jtag configure CHIP.cpu -event tap-enable @{
  2583. ... jtag operations using CHIP.jrc
  2584. @}
  2585. jtag configure CHIP.cpu -event tap-disable @{
  2586. ... jtag operations using CHIP.jrc
  2587. @}
  2588. @end example
  2589. Then you might want that CPU's TAP enabled almost all the time:
  2590. @example
  2591. jtag configure $CHIP.jrc -event setup "jtag tapenable $CHIP.cpu"
  2592. @end example
  2593. Note how that particular setup event handler declaration
  2594. uses quotes to evaluate @code{$CHIP} when the event is configured.
  2595. Using brackets @{ @} would cause it to be evaluated later,
  2596. at runtime, when it might have a different value.
  2597. @deffn Command {jtag tapdisable}
  2598. If necessary, disables the tap
  2599. by sending it a @option{tap-disable} event.
  2600. Returns the string "1" if the tap
  2601. specified by @var{} is enabled,
  2602. and "0" if it is disabled.
  2603. @end deffn
  2604. @deffn Command {jtag tapenable}
  2605. If necessary, enables the tap
  2606. by sending it a @option{tap-enable} event.
  2607. Returns the string "1" if the tap
  2608. specified by @var{} is enabled,
  2609. and "0" if it is disabled.
  2610. @end deffn
  2611. @deffn Command {jtag tapisenabled}
  2612. Returns the string "1" if the tap
  2613. specified by @var{} is enabled,
  2614. and "0" if it is disabled.
  2615. @quotation Note
  2616. Humans will find the @command{scan_chain} command more helpful
  2617. for querying the state of the JTAG taps.
  2618. @end quotation
  2619. @end deffn
  2620. @anchor{Autoprobing}
  2621. @section Autoprobing
  2622. @cindex autoprobe
  2623. @cindex JTAG autoprobe
  2624. TAP configuration is the first thing that needs to be done
  2625. after interface and reset configuration. Sometimes it's
  2626. hard finding out what TAPs exist, or how they are identified.
  2627. Vendor documentation is not always easy to find and use.
  2628. To help you get past such problems, OpenOCD has a limited
  2629. @emph{autoprobing} ability to look at the scan chain, doing
  2630. a @dfn{blind interrogation} and then reporting the TAPs it finds.
  2631. To use this mechanism, start the OpenOCD server with only data
  2632. that configures your JTAG interface, and arranges to come up
  2633. with a slow clock (many devices don't support fast JTAG clocks
  2634. right when they come out of reset).
  2635. For example, your @file{openocd.cfg} file might have:
  2636. @example
  2637. source [find interface/olimex-arm-usb-tiny-h.cfg]
  2638. reset_config trst_and_srst
  2639. jtag_rclk 8
  2640. @end example
  2641. When you start the server without any TAPs configured, it will
  2642. attempt to autoconfigure the TAPs. There are two parts to this:
  2643. @enumerate
  2644. @item @emph{TAP discovery} ...
  2645. After a JTAG reset (sometimes a system reset may be needed too),
  2646. each TAP's data registers will hold the contents of either the
  2647. IDCODE or BYPASS register.
  2648. If JTAG communication is working, OpenOCD will see each TAP,
  2649. and report what @option{-expected-id} to use with it.
  2650. @item @emph{IR Length discovery} ...
  2651. Unfortunately JTAG does not provide a reliable way to find out
  2652. the value of the @option{-irlen} parameter to use with a TAP
  2653. that is discovered.
  2654. If OpenOCD can discover the length of a TAP's instruction
  2655. register, it will report it.
  2656. Otherwise you may need to consult vendor documentation, such
  2657. as chip data sheets or BSDL files.
  2658. @end enumerate
  2659. In many cases your board will have a simple scan chain with just
  2660. a single device. Here's what OpenOCD reported with one board
  2661. that's a bit more complex:
  2662. @example
  2663. clock speed 8 kHz
  2664. There are no enabled taps. AUTO PROBING MIGHT NOT WORK!!
  2665. AUTO auto0.tap - use "jtag newtap auto0 tap -expected-id 0x2b900f0f ..."
  2666. AUTO auto1.tap - use "jtag newtap auto1 tap -expected-id 0x07926001 ..."
  2667. AUTO auto2.tap - use "jtag newtap auto2 tap -expected-id 0x0b73b02f ..."
  2668. AUTO auto0.tap - use "... -irlen 4"
  2669. AUTO auto1.tap - use "... -irlen 4"
  2670. AUTO auto2.tap - use "... -irlen 6"
  2671. no gdb ports allocated as no target has been specified
  2672. @end example
  2673. Given that information, you should be able to either find some existing
  2674. config files to use, or create your own. If you create your own, you
  2675. would configure from the bottom up: first a @file{target.cfg} file
  2676. with these TAPs, any targets associated with them, and any on-chip
  2677. resources; then a @file{board.cfg} with off-chip resources, clocking,
  2678. and so forth.
  2679. @node CPU Configuration
  2680. @chapter CPU Configuration
  2681. @cindex GDB target
  2682. This chapter discusses how to set up GDB debug targets for CPUs.
  2683. You can also access these targets without GDB
  2684. (@pxref{Architecture and Core Commands},
  2685. and @ref{Target State handling}) and
  2686. through various kinds of NAND and NOR flash commands.
  2687. If you have multiple CPUs you can have multiple such targets.
  2688. We'll start by looking at how to examine the targets you have,
  2689. then look at how to add one more target and how to configure it.
  2690. @section Target List
  2691. @cindex target, current
  2692. @cindex target, list
  2693. All targets that have been set up are part of a list,
  2694. where each member has a name.
  2695. That name should normally be the same as the TAP name.
  2696. You can display the list with the @command{targets}
  2697. (plural!) command.
  2698. This display often has only one CPU; here's what it might
  2699. look like with more than one:
  2700. @verbatim
  2701. TargetName Type Endian TapName State
  2702. -- ------------------ ---------- ------ ------------------ ------------
  2703. 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
  2704. 1 MyTarget cortex_m3 little tap-disabled
  2705. @end verbatim
  2706. One member of that list is the @dfn{current target}, which
  2707. is implicitly referenced by many commands.
  2708. It's the one marked with a @code{*} near the target name.
  2709. In particular, memory addresses often refer to the address
  2710. space seen by that current target.
  2711. Commands like @command{mdw} (memory display words)
  2712. and @command{flash erase_address} (erase NOR flash blocks)
  2713. are examples; and there are many more.
  2714. Several commands let you examine the list of targets:
  2715. @deffn Command {target count}
  2716. @emph{Note: target numbers are deprecated; don't use them.
  2717. They will be removed shortly after August 2010, including this command.
  2718. Iterate target using @command{target names}, not by counting.}
  2719. Returns the number of targets, @math{N}.
  2720. The highest numbered target is @math{N - 1}.
  2721. @example
  2722. set c [target count]
  2723. for @{ set x 0 @} @{ $x < $c @} @{ incr x @} @{
  2724. # Assuming you have created this function
  2725. print_target_details $x
  2726. @}
  2727. @end example
  2728. @end deffn
  2729. @deffn Command {target current}
  2730. Returns the name of the current target.
  2731. @end deffn
  2732. @deffn Command {target names}
  2733. Lists the names of all current targets in the list.
  2734. @example
  2735. foreach t [target names] @{
  2736. puts [format "Target: %s\n" $t]
  2737. @}
  2738. @end example
  2739. @end deffn
  2740. @deffn Command {target number} number
  2741. @emph{Note: target numbers are deprecated; don't use them.
  2742. They will be removed shortly after August 2010, including this command.}
  2743. The list of targets is numbered starting at zero.
  2744. This command returns the name of the target at index @var{number}.
  2745. @example
  2746. set thename [target number $x]
  2747. puts [format "Target %d is: %s\n" $x $thename]
  2748. @end example
  2749. @end deffn
  2750. @c yep, "target list" would have been better.
  2751. @c plus maybe "target setdefault".
  2752. @deffn Command targets [name]
  2753. @emph{Note: the name of this command is plural. Other target
  2754. command names are singular.}
  2755. With no parameter, this command displays a table of all known
  2756. targets in a user friendly form.
  2757. With a parameter, this command sets the current target to
  2758. the given target with the given @var{name}; this is
  2759. only relevant on boards which have more than one target.
  2760. @end deffn
  2761. @section Target CPU Types and Variants
  2762. @cindex target type
  2763. @cindex CPU type
  2764. @cindex CPU variant
  2765. Each target has a @dfn{CPU type}, as shown in the output of
  2766. the @command{targets} command. You need to specify that type
  2767. when calling @command{target create}.
  2768. The CPU type indicates more than just the instruction set.
  2769. It also indicates how that instruction set is implemented,
  2770. what kind of debug support it integrates,
  2771. whether it has an MMU (and if so, what kind),
  2772. what core-specific commands may be available
  2773. (@pxref{Architecture and Core Commands}),
  2774. and more.
  2775. For some CPU types, OpenOCD also defines @dfn{variants} which
  2776. indicate differences that affect their handling.
  2777. For example, a particular implementation bug might need to be
  2778. worked around in some chip versions.
  2779. It's easy to see what target types are supported,
  2780. since there's a command to list them.
  2781. However, there is currently no way to list what target variants
  2782. are supported (other than by reading the OpenOCD source code).
  2783. @anchor{target types}
  2784. @deffn Command {target types}
  2785. Lists all supported target types.
  2786. At this writing, the supported CPU types and variants are:
  2787. @itemize @bullet
  2788. @item @code{arm11} -- this is a generation of ARMv6 cores
  2789. @item @code{arm720t} -- this is an ARMv4 core with an MMU
  2790. @item @code{arm7tdmi} -- this is an ARMv4 core
  2791. @item @code{arm920t} -- this is an ARMv5 core with an MMU
  2792. @item @code{arm926ejs} -- this is an ARMv5 core with an MMU
  2793. @item @code{arm966e} -- this is an ARMv5 core
  2794. @item @code{arm9tdmi} -- this is an ARMv4 core
  2795. @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
  2796. (Support for this is preliminary and incomplete.)
  2797. @item @code{cortex_a8} -- this is an ARMv7 core with an MMU
  2798. @item @code{cortex_m3} -- this is an ARMv7 core, supporting only the
  2799. compact Thumb2 instruction set. It supports one variant:
  2800. @itemize @minus
  2801. @item @code{lm3s} ... Use this when debugging older Stellaris LM3S targets.
  2802. This will cause OpenOCD to use a software reset rather than asserting
  2803. SRST, to avoid a issue with clearing the debug registers.
  2804. This is fixed in Fury Rev B, DustDevil Rev B, Tempest; these revisions will
  2805. be detected and the normal reset behaviour used.
  2806. @end itemize
  2807. @item @code{dragonite} -- resembles arm966e
  2808. @item @code{dsp563xx} -- implements Freescale's 24-bit DSP.
  2809. (Support for this is still incomplete.)
  2810. @item @code{fa526} -- resembles arm920 (w/o Thumb)
  2811. @item @code{feroceon} -- resembles arm926
  2812. @item @code{mips_m4k} -- a MIPS core. This supports one variant:
  2813. @itemize @minus
  2814. @item @code{ejtag_srst} ... Use this when debugging targets that do not
  2815. provide a functional SRST line on the EJTAG connector. This causes
  2816. OpenOCD to instead use an EJTAG software reset command to reset the
  2817. processor.
  2818. You still need to enable @option{srst} on the @command{reset_config}
  2819. command to enable OpenOCD hardware reset functionality.
  2820. @end itemize
  2821. @item @code{xscale} -- this is actually an architecture,
  2822. not a CPU type. It is based on the ARMv5 architecture.
  2823. There are several variants defined:
  2824. @itemize @minus
  2825. @item @code{ixp42x}, @code{ixp45x}, @code{ixp46x},
  2826. @code{pxa27x} ... instruction register length is 7 bits
  2827. @item @code{pxa250}, @code{pxa255},
  2828. @code{pxa26x} ... instruction register length is 5 bits
  2829. @item @code{pxa3xx} ... instruction register length is 11 bits
  2830. @end itemize
  2831. @end itemize
  2832. @end deffn
  2833. To avoid being confused by the variety of ARM based cores, remember
  2834. this key point: @emph{ARM is a technology licencing company}.
  2835. (See: @url{}.)
  2836. The CPU name used by OpenOCD will reflect the CPU design that was
  2837. licenced, not a vendor brand which incorporates that design.
  2838. Name prefixes like arm7, arm9, arm11, and cortex
  2839. reflect design generations;
  2840. while names like ARMv4, ARMv5, ARMv6, and ARMv7
  2841. reflect an architecture version implemented by a CPU design.
  2842. @anchor{Target Configuration}
  2843. @section Target Configuration
  2844. Before creating a ``target'', you must have added its TAP to the scan chain.
  2845. When you've added that TAP, you will have a @code{}
  2846. which is used to set up the CPU support.
  2847. The chip-specific configuration file will normally configure its CPU(s)
  2848. right after it adds all of the chip's TAPs to the scan chain.
  2849. Although you can set up a target in one step, it's often clearer if you
  2850. use shorter commands and do it in two steps: create it, then configure
  2851. optional parts.
  2852. All operations on the target after it's created will use a new
  2853. command, created as part of target creation.
  2854. The two main things to configure after target creation are
  2855. a work area, which usually has target-specific defaults even
  2856. if the board setup code overrides them later;
  2857. and event handlers (@pxref{Target Events}), which tend
  2858. to be much more board-specific.
  2859. The key steps you use might look something like this
  2860. @example
  2861. target create MyTarget cortex_m3 -chain-position mychip.cpu
  2862. $MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
  2863. $MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
  2864. $MyTarget configure -event reset-init @{ myboard_reinit @}
  2865. @end example
  2866. You should specify a working area if you can; typically it uses some
  2867. on-chip SRAM.
  2868. Such a working area can speed up many things, including bulk
  2869. writes to target memory;
  2870. flash operations like checking to see if memory needs to be erased;
  2871. GDB memory checksumming;
  2872. and more.
  2873. @quotation Warning
  2874. On more complex chips, the work area can become
  2875. inaccessible when application code
  2876. (such as an operating system)
  2877. enables or disables the MMU.
  2878. For example, the particular MMU context used to acess the virtual
  2879. address will probably matter ... and that context might not have
  2880. easy access to other addresses needed.
  2881. At this writing, OpenOCD doesn't have much MMU intelligence.
  2882. @end quotation
  2883. It's often very useful to define a @code{reset-init} event handler.
  2884. For systems that are normally used with a boot loader,
  2885. common tasks include updating clocks and initializing memory
  2886. controllers.
  2887. That may be needed to let you write the boot loader into flash,
  2888. in order to ``de-brick'' your board; or to load programs into
  2889. external DDR memory without having run the boot loader.
  2890. @deffn Command {target create} target_name type configparams...
  2891. This command creates a GDB debug target that refers to a specific JTAG tap.
  2892. It enters that target into a list, and creates a new
  2893. command (@command{@var{target_name}}) which is used for various
  2894. purposes including additional configuration.
  2895. @itemize @bullet
  2896. @item @var{target_name} ... is the name of the debug target.
  2897. By convention this should be the same as the @emph{}
  2898. of the TAP associated with this target, which must be specified here
  2899. using the @code{-chain-position @var{}} configparam.
  2900. This name is also used to create the target object command,
  2901. referred to here as @command{$target_name},
  2902. and in other places the target needs to be identified.
  2903. @item @var{type} ... specifies the target type. @xref{target types}.
  2904. @item @var{configparams} ... all parameters accepted by
  2905. @command{$target_name configure} are permitted.
  2906. If the target is big-endian, set it here with @code{-endian big}.
  2907. If the variant matters, set it here with @code{-variant}.
  2908. You @emph{must} set the @code{-chain-position @var{}} here.
  2909. @end itemize
  2910. @end deffn
  2911. @deffn Command {$target_name configure} configparams...
  2912. The options accepted by this command may also be
  2913. specified as parameters to @command{target create}.
  2914. Their values can later be queried one at a time by
  2915. using the @command{$target_name cget} command.
  2916. @emph{Warning:} changing some of these after setup is dangerous.
  2917. For example, moving a target from one TAP to another;
  2918. and changing its endianness or variant.
  2919. @itemize @bullet
  2920. @item @code{-chain-position} @var{} -- names the TAP
  2921. used to access this target.
  2922. @item @code{-endian} (@option{big}|@option{little}) -- specifies
  2923. whether the CPU uses big or little endian conventions
  2924. @item @code{-event} @var{event_name} @var{event_body} --
  2925. @xref{Target Events}.
  2926. Note that this updates a list of named event handlers.
  2927. Calling this twice with two different event names assigns
  2928. two different handlers, but calling it twice with the
  2929. same event name assigns only one handler.
  2930. @item @code{-variant} @var{name} -- specifies a variant of the target,
  2931. which OpenOCD needs to know about.
  2932. @item @code{-work-area-backup} (@option{0}|@option{1}) -- says
  2933. whether the work area gets backed up; by default,
  2934. @emph{it is not backed up.}
  2935. When possible, use a working_area that doesn't need to be backed up,
  2936. since performing a backup slows down operations.
  2937. For example, the beginning of an SRAM block is likely to
  2938. be used by most build systems, but the end is often unused.
  2939. @item @code{-work-area-size} @var{size} -- specify work are size,
  2940. in bytes. The same size applies regardless of whether its physical
  2941. or virtual address is being used.
  2942. @item @code{-work-area-phys} @var{address} -- set the work area
  2943. base @var{address} to be used when no MMU is active.
  2944. @item @code{-work-area-virt} @var{address} -- set the work area
  2945. base @var{address} to be used when an MMU is active.
  2946. @emph{Do not specify a value for this except on targets with an MMU.}
  2947. The value should normally correspond to a static mapping for the
  2948. @code{-work-area-phys} address, set up by the current operating system.
  2949. @end itemize
  2950. @end deffn
  2951. @section Other $target_name Commands
  2952. @cindex object command
  2953. The Tcl/Tk language has the concept of object commands,
  2954. and OpenOCD adopts that same model for targets.
  2955. A good Tk example is a on screen button.
  2956. Once a button is created a button
  2957. has a name (a path in Tk terms) and that name is useable as a first
  2958. class command. For example in Tk, one can create a button and later
  2959. configure it like this:
  2960. @example
  2961. # Create
  2962. button .foobar -background red -command @{ foo @}
  2963. # Modify
  2964. .foobar configure -foreground blue
  2965. # Query
  2966. set x [.foobar cget -background]
  2967. # Report
  2968. puts [format "The button is %s" $x]
  2969. @end example
  2970. In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
  2971. button, and its object commands are invoked the same way.
  2972. @example
  2973. str912.cpu mww 0x1234 0x42
  2974. omap3530.cpu mww 0x5555 123
  2975. @end example
  2976. The commands supported by OpenOCD target objects are:
  2977. @deffn Command {$target_name arp_examine}
  2978. @deffnx Command {$target_name arp_halt}
  2979. @deffnx Command {$target_name arp_poll}
  2980. @deffnx Command {$target_name arp_reset}
  2981. @deffnx Command {$target_name arp_waitstate}
  2982. Internal OpenOCD scripts (most notably @file{startup.tcl})
  2983. use these to deal with specific reset cases.
  2984. They are not otherwise documented here.
  2985. @end deffn
  2986. @deffn Command {$target_name array2mem} arrayname width address count
  2987. @deffnx Command {$target_name mem2array} arrayname width address count
  2988. These provide an efficient script-oriented interface to memory.
  2989. The @code{array2mem} primitive writes bytes, halfwords, or words;
  2990. while @code{mem2array} reads them.
  2991. In both cases, the TCL side uses an array, and
  2992. the target side uses raw memory.
  2993. The efficiency comes from enabling the use of
  2994. bulk JTAG data transfer operations.
  2995. The script orientation comes from working with data
  2996. values that are packaged for use by TCL scripts;
  2997. @command{mdw} type primitives only print data they retrieve,
  2998. and neither store nor return those values.
  2999. @itemize
  3000. @item @var{arrayname} ... is the name of an array variable
  3001. @item @var{width} ... is 8/16/32 - indicating the memory access size
  3002. @item @var{address} ... is the target memory address
  3003. @item @var{count} ... is the number of elements to process
  3004. @end itemize
  3005. @end deffn
  3006. @deffn Command {$target_name cget} queryparm
  3007. Each configuration parameter accepted by
  3008. @command{$target_name configure}
  3009. can be individually queried, to return its current value.
  3010. The @var{queryparm} is a parameter name
  3011. accepted by that command, such as @code{-work-area-phys}.
  3012. There are a few special cases:
  3013. @itemize @bullet
  3014. @item @code{-event} @var{event_name} -- returns the handler for the
  3015. event named @var{event_name}.
  3016. This is a special case because setting a handler requires
  3017. two parameters.
  3018. @item @code{-type} -- returns the target type.
  3019. This is a special case because this is set using
  3020. @command{target create} and can't be changed
  3021. using @command{$target_name configure}.
  3022. @end itemize
  3023. For example, if you wanted to summarize information about
  3024. all the targets you might use something like this:
  3025. @example
  3026. foreach name [target names] @{
  3027. set y [$name cget -endian]
  3028. set z [$name cget -type]
  3029. puts [format "Chip %d is %s, Endian: %s, type: %s" \
  3030. $x $name $y $z]
  3031. @}
  3032. @end example
  3033. @end deffn
  3034. @anchor{target curstate}
  3035. @deffn Command {$target_name curstate}
  3036. Displays the current target state:
  3037. @code{debug-running},
  3038. @code{halted},
  3039. @code{reset},
  3040. @code{running}, or @code{unknown}.
  3041. (Also, @pxref{Event Polling}.)
  3042. @end deffn
  3043. @deffn Command {$target_name eventlist}
  3044. Displays a table listing all event handlers
  3045. currently associated with this target.
  3046. @xref{Target Events}.
  3047. @end deffn
  3048. @deffn Command {$target_name invoke-event} event_name
  3049. Invokes the handler for the event named @var{event_name}.
  3050. (This is primarily intended for use by OpenOCD framework
  3051. code, for example by the reset code in @file{startup.tcl}.)
  3052. @end deffn
  3053. @deffn Command {$target_name mdw} addr [count]
  3054. @deffnx Command {$target_name mdh} addr [count]
  3055. @deffnx Command {$target_name mdb} addr [count]
  3056. Display contents of address @var{addr}, as
  3057. 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
  3058. or 8-bit bytes (@command{mdb}).
  3059. If @var{count} is specified, displays that many units.
  3060. (If you want to manipulate the data instead of displaying it,
  3061. see the @code{mem2array} primitives.)
  3062. @end deffn
  3063. @deffn Command {$target_name mww} addr word
  3064. @deffnx Command {$target_name mwh} addr halfword
  3065. @deffnx Command {$target_name mwb} addr byte
  3066. Writes the specified @var{word} (32 bits),
  3067. @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
  3068. at the specified address @var{addr}.
  3069. @end deffn
  3070. @anchor{Target Events}
  3071. @section Target Events
  3072. @cindex target events
  3073. @cindex events
  3074. At various times, certain things can happen, or you want them to happen.
  3075. For example:
  3076. @itemize @bullet
  3077. @item What should happen when GDB connects? Should your target reset?
  3078. @item When GDB tries to flash the target, do you need to enable the flash via a special command?
  3079. @item Is using SRST appropriate (and possible) on your system?
  3080. Or instead of that, do you need to issue JTAG commands to trigger reset?
  3081. SRST usually resets everything on the scan chain, which can be inappropriate.
  3082. @item During reset, do you need to write to certain memory locations
  3083. to set up system clocks or
  3084. to reconfigure the SDRAM?
  3085. How about configuring the watchdog timer, or other peripherals,
  3086. to stop running while you hold the core stopped for debugging?
  3087. @end itemize
  3088. All of the above items can be addressed by target event handlers.
  3089. These are set up by @command{$target_name configure -event} or
  3090. @command{target create ... -event}.
  3091. The programmer's model matches the @code{-command} option used in Tcl/Tk
  3092. buttons and events. The two examples below act the same, but one creates
  3093. and invokes a small procedure while the other inlines it.
  3094. @example
  3095. proc my_attach_proc @{ @} @{
  3096. echo "Reset..."
  3097. reset halt
  3098. @}
  3099. mychip.cpu configure -event gdb-attach my_attach_proc
  3100. mychip.cpu configure -event gdb-attach @{
  3101. echo "Reset..."
  3102. reset halt
  3103. @}
  3104. @end example
  3105. The following target events are defined:
  3106. @itemize @bullet
  3107. @item @b{debug-halted}
  3108. @* The target has halted for debug reasons (i.e.: breakpoint)
  3109. @item @b{debug-resumed}
  3110. @* The target has resumed (i.e.: gdb said run)
  3111. @item @b{early-halted}
  3112. @* Occurs early in the halt process
  3113. @ignore
  3114. @item @b{examine-end}
  3115. @* Currently not used (goal: when JTAG examine completes)
  3116. @item @b{examine-start}
  3117. @* Currently not used (goal: when JTAG examine starts)
  3118. @end ignore
  3119. @item @b{gdb-attach}
  3120. @* When GDB connects
  3121. @item @b{gdb-detach}
  3122. @* When GDB disconnects
  3123. @item @b{gdb-end}
  3124. @* When the target has halted and GDB is not doing anything (see early halt)
  3125. @item @b{gdb-flash-erase-start}
  3126. @* Before the GDB flash process tries to erase the flash
  3127. @item @b{gdb-flash-erase-end}
  3128. @* After the GDB flash process has finished erasing the flash
  3129. @item @b{gdb-flash-write-start}
  3130. @* Before GDB writes to the flash
  3131. @item @b{gdb-flash-write-end}
  3132. @* After GDB writes to the flash
  3133. @item @b{gdb-start}
  3134. @* Before the target steps, gdb is trying to start/resume the target
  3135. @item @b{halted}
  3136. @* The target has halted
  3137. @ignore
  3138. @item @b{old-gdb_program_config}
  3139. @* DO NOT USE THIS: Used internally
  3140. @item @b{old-pre_resume}
  3141. @* DO NOT USE THIS: Used internally
  3142. @end ignore
  3143. @item @b{reset-assert-pre}
  3144. @* Issued as part of @command{reset} processing
  3145. after @command{reset_init} was triggered
  3146. but before either SRST alone is re-asserted on the scan chain,
  3147. or @code{reset-assert} is triggered.
  3148. @item @b{reset-assert}
  3149. @* Issued as part of @command{reset} processing
  3150. after @command{reset-assert-pre} was triggered.
  3151. When such a handler is present, cores which support this event will use
  3152. it instead of asserting SRST.
  3153. This support is essential for debugging with JTAG interfaces which
  3154. don't include an SRST line (JTAG doesn't require SRST), and for
  3155. selective reset on scan chains that have multiple targets.
  3156. @item @b{reset-assert-post}
  3157. @* Issued as part of @command{reset} processing
  3158. after @code{reset-assert} has been triggered.
  3159. or the target asserted SRST on the entire scan chain.
  3160. @item @b{reset-deassert-pre}
  3161. @* Issued as part of @command{reset} processing
  3162. after @code{reset-assert-post} has been triggered.
  3163. @item @b{reset-deassert-post}
  3164. @* Issued as part of @command{reset} processing
  3165. after @code{reset-deassert-pre} has been triggered
  3166. and (if the target is using it) after SRST has been
  3167. released on the scan chain.
  3168. @item @b{reset-end}
  3169. @* Issued as the final step in @command{reset} processing.
  3170. @ignore
  3171. @item @b{reset-halt-post}
  3172. @* Currently not used
  3173. @item @b{reset-halt-pre}
  3174. @* Currently not used
  3175. @end ignore
  3176. @item @b{reset-init}
  3177. @* Used by @b{reset init} command for board-specific initialization.
  3178. This event fires after @emph{reset-deassert-post}.
  3179. This is where you would configure PLLs and clocking, set up DRAM so
  3180. you can download programs that don't fit in on-chip SRAM, set up pin
  3181. multiplexing, and so on.
  3182. (You may be able to switch to a fast JTAG clock rate here, after
  3183. the target clocks are fully set up.)
  3184. @item @b{reset-start}
  3185. @* Issued as part of @command{reset} processing
  3186. before @command{reset_init} is called.
  3187. This is the most robust place to use @command{jtag_rclk}
  3188. or @command{jtag_khz} to switch to a low JTAG clock rate,
  3189. when reset disables PLLs needed to use a fast clock.
  3190. @ignore
  3191. @item @b{reset-wait-pos}
  3192. @* Currently not used
  3193. @item @b{reset-wait-pre}
  3194. @* Currently not used
  3195. @end ignore
  3196. @item @b{resume-start}
  3197. @* Before any target is resumed
  3198. @item @b{resume-end}
  3199. @* After all targets have resumed
  3200. @item @b{resume-ok}
  3201. @* Success
  3202. @item @b{resumed}
  3203. @* Target has resumed
  3204. @end itemize
  3205. @node Flash Commands
  3206. @chapter Flash Commands
  3207. OpenOCD has different commands for NOR and NAND flash;
  3208. the ``flash'' command works with NOR flash, while
  3209. the ``nand'' command works with NAND flash.
  3210. This partially reflects different hardware technologies:
  3211. NOR flash usually supports direct CPU instruction and data bus access,
  3212. while data from a NAND flash must be copied to memory before it can be
  3213. used. (SPI flash must also be copied to memory before use.)
  3214. However, the documentation also uses ``flash'' as a generic term;
  3215. for example, ``Put flash configuration in board-specific files''.
  3216. Flash Steps:
  3217. @enumerate
  3218. @item Configure via the command @command{flash bank}
  3219. @* Do this in a board-specific configuration file,
  3220. passing parameters as needed by the driver.
  3221. @item Operate on the flash via @command{flash subcommand}
  3222. @* Often commands to manipulate the flash are typed by a human, or run
  3223. via a script in some automated way. Common tasks include writing a
  3224. boot loader, operating system, or other data.
  3225. @item GDB Flashing
  3226. @* Flashing via GDB requires the flash be configured via ``flash
  3227. bank'', and the GDB flash features be enabled.
  3228. @xref{GDB Configuration}.
  3229. @end enumerate
  3230. Many CPUs have the ablity to ``boot'' from the first flash bank.
  3231. This means that misprogramming that bank can ``brick'' a system,
  3232. so that it can't boot.
  3233. JTAG tools, like OpenOCD, are often then used to ``de-brick'' the
  3234. board by (re)installing working boot firmware.
  3235. @anchor{NOR Configuration}
  3236. @section Flash Configuration Commands
  3237. @cindex flash configuration
  3238. @deffn {Config Command} {flash bank} name driver base size chip_width bus_width target [driver_options]
  3239. Configures a flash bank which provides persistent storage
  3240. for addresses from @math{base} to @math{base + size - 1}.
  3241. These banks will often be visible to GDB through the target's memory map.
  3242. In some cases, configuring a flash bank will activate extra commands;
  3243. see the driver-specific documentation.
  3244. @itemize @bullet
  3245. @item @var{name} ... may be used to reference the flash bank
  3246. in other flash commands. A number is also available.
  3247. @item @var{driver} ... identifies the controller driver
  3248. associated with the flash bank being declared.
  3249. This is usually @code{cfi} for external flash, or else
  3250. the name of a microcontroller with embedded flash memory.
  3251. @xref{Flash Driver List}.
  3252. @item @var{base} ... Base address of the flash chip.
  3253. @item @var{size} ... Size of the chip, in bytes.
  3254. For some drivers, this value is detected from the hardware.
  3255. @item @var{chip_width} ... Width of the flash chip, in bytes;
  3256. ignored for most microcontroller drivers.
  3257. @item @var{bus_width} ... Width of the data bus used to access the
  3258. chip, in bytes; ignored for most microcontroller drivers.
  3259. @item @var{target} ... Names the target used to issue
  3260. commands to the flash controller.
  3261. @comment Actually, it's currently a controller-specific parameter...
  3262. @item @var{driver_options} ... drivers may support, or require,
  3263. additional parameters. See the driver-specific documentation
  3264. for more information.
  3265. @end itemize
  3266. @quotation Note
  3267. This command is not available after OpenOCD initialization has completed.
  3268. Use it in board specific configuration files, not interactively.
  3269. @end quotation
  3270. @end deffn
  3271. @comment the REAL name for this command is "ocd_flash_banks"
  3272. @comment less confusing would be: "flash list" (like "nand list")
  3273. @deffn Command {flash banks}
  3274. Prints a one-line summary of each device that was
  3275. declared using @command{flash bank}, numbered from zero.
  3276. Note that this is the @emph{plural} form;
  3277. the @emph{singular} form is a very different command.
  3278. @end deffn
  3279. @deffn Command {flash list}
  3280. Retrieves a list of associative arrays for each device that was
  3281. declared using @command{flash bank}, numbered from zero.
  3282. This returned list can be manipulated easily from within scripts.
  3283. @end deffn
  3284. @deffn Command {flash probe} num
  3285. Identify the flash, or validate the parameters of the configured flash. Operation
  3286. depends on the flash type.
  3287. The @var{num} parameter is a value shown by @command{flash banks}.
  3288. Most flash commands will implicitly @emph{autoprobe} the bank;
  3289. flash drivers can distinguish between probing and autoprobing,
  3290. but most don't bother.
  3291. @end deffn
  3292. @section Erasing, Reading, Writing to Flash
  3293. @cindex flash erasing
  3294. @cindex flash reading
  3295. @cindex flash writing
  3296. @cindex flash programming
  3297. One feature distinguishing NOR flash from NAND or serial flash technologies
  3298. is that for read access, it acts exactly like any other addressible memory.
  3299. This means you can use normal memory read commands like @command{mdw} or
  3300. @command{dump_image} with it, with no special @command{flash} subcommands.
  3301. @xref{Memory access}, and @ref{Image access}.
  3302. Write access works differently. Flash memory normally needs to be erased
  3303. before it's written. Erasing a sector turns all of its bits to ones, and
  3304. writing can turn ones into zeroes. This is why there are special commands
  3305. for interactive erasing and writing, and why GDB needs to know which parts
  3306. of the address space hold NOR flash memory.
  3307. @quotation Note
  3308. Most of these erase and write commands leverage the fact that NOR flash
  3309. chips consume target address space. They implicitly refer to the current
  3310. JTAG target, and map from an address in that target's address space
  3311. back to a flash bank.
  3312. @comment In May 2009, those mappings may fail if any bank associated
  3313. @comment with that target doesn't succesfuly autoprobe ... bug worth fixing?
  3314. A few commands use abstract addressing based on bank and sector numbers,
  3315. and don't depend on searching the current target and its address space.
  3316. Avoid confusing the two command models.
  3317. @end quotation
  3318. Some flash chips implement software protection against accidental writes,
  3319. since such buggy writes could in some cases ``brick'' a system.
  3320. For such systems, erasing and writing may require sector protection to be
  3321. disabled first.
  3322. Examples include CFI flash such as ``Intel Advanced Bootblock flash'',
  3323. and AT91SAM7 on-chip flash.
  3324. @xref{flash protect}.
  3325. @anchor{flash erase_sector}
  3326. @deffn Command {flash erase_sector} num first last
  3327. Erase sectors in bank @var{num}, starting at sector @var{first}
  3328. up to and including @var{last}.
  3329. Sector numbering starts at 0.
  3330. Providing a @var{last} sector of @option{last}
  3331. specifies "to the end of the flash bank".
  3332. The @var{num} parameter is a value shown by @command{flash banks}.
  3333. @end deffn
  3334. @deffn Command {flash erase_address} [@option{pad}] address length
  3335. Erase sectors starting at @var{address} for @var{length} bytes.
  3336. Unless @option{pad} is specified, @math{address} must begin a
  3337. flash sector, and @math{address + length - 1} must end a sector.
  3338. Specifying @option{pad} erases extra data at the beginning and/or
  3339. end of the specified region, as needed to erase only full sectors.
  3340. The flash bank to use is inferred from the @var{address}, and
  3341. the specified length must stay within that bank.
  3342. As a special case, when @var{length} is zero and @var{address} is
  3343. the start of the bank, the whole flash is erased.
  3344. @end deffn
  3345. @deffn Command {flash fillw} address word length
  3346. @deffnx Command {flash fillh} address halfword length
  3347. @deffnx Command {flash fillb} address byte length
  3348. Fills flash memory with the specified @var{word} (32 bits),
  3349. @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
  3350. starting at @var{address} and continuing
  3351. for @var{length} units (word/halfword/byte).
  3352. No erasure is done before writing; when needed, that must be done
  3353. before issuing this command.
  3354. Writes are done in blocks of up to 1024 bytes, and each write is
  3355. verified by reading back the data and comparing it to what was written.
  3356. The flash bank to use is inferred from the @var{address} of
  3357. each block, and the specified length must stay within that bank.
  3358. @end deffn
  3359. @comment no current checks for errors if fill blocks touch multiple banks!
  3360. @anchor{flash write_bank}
  3361. @deffn Command {flash write_bank} num filename offset
  3362. Write the binary @file{filename} to flash bank @var{num},
  3363. starting at @var{offset} bytes from the beginning of the bank.
  3364. The @var{num} parameter is a value shown by @command{flash banks}.
  3365. @end deffn
  3366. @anchor{flash write_image}
  3367. @deffn Command {flash write_image} [erase] [unlock] filename [offset] [type]
  3368. Write the image @file{filename} to the current target's flash bank(s).
  3369. A relocation @var{offset} may be specified, in which case it is added
  3370. to the base address for each section in the image.
  3371. The file [@var{type}] can be specified
  3372. explicitly as @option{bin} (binary), @option{ihex} (Intel hex),
  3373. @option{elf} (ELF file), @option{s19} (Motorola s19).
  3374. @option{mem}, or @option{builder}.
  3375. The relevant flash sectors will be erased prior to programming
  3376. if the @option{erase} parameter is given. If @option{unlock} is
  3377. provided, then the flash banks are unlocked before erase and
  3378. program. The flash bank to use is inferred from the address of
  3379. each image section.
  3380. @quotation Warning
  3381. Be careful using the @option{erase} flag when the flash is holding
  3382. data you want to preserve.
  3383. Portions of the flash outside those described in the image's
  3384. sections might be erased with no notice.
  3385. @itemize
  3386. @item
  3387. When a section of the image being written does not fill out all the
  3388. sectors it uses, the unwritten parts of those sectors are necessarily
  3389. also erased, because sectors can't be partially erased.
  3390. @item
  3391. Data stored in sector "holes" between image sections are also affected.
  3392. For example, "@command{flash write_image erase ...}" of an image with
  3393. one byte at the beginning of a flash bank and one byte at the end
  3394. erases the entire bank -- not just the two sectors being written.
  3395. @end itemize
  3396. Also, when flash protection is important, you must re-apply it after
  3397. it has been removed by the @option{unlock} flag.
  3398. @end quotation
  3399. @end deffn
  3400. @section Other Flash commands
  3401. @cindex flash protection
  3402. @deffn Command {flash erase_check} num
  3403. Check erase state of sectors in flash bank @var{num},
  3404. and display that status.
  3405. The @var{num} parameter is a value shown by @command{flash banks}.
  3406. @end deffn
  3407. @deffn Command {flash info} num
  3408. Print info about flash bank @var{num}
  3409. The @var{num} parameter is a value shown by @command{flash banks}.
  3410. The information includes per-sector protect status, which may be
  3411. incorrect (outdated) unless you first issue a
  3412. @command{flash protect_check num} command.
  3413. @end deffn
  3414. @anchor{flash protect}
  3415. @deffn Command {flash protect} num first last (@option{on}|@option{off})
  3416. Enable (@option{on}) or disable (@option{off}) protection of flash sectors
  3417. in flash bank @var{num}, starting at sector @var{first}
  3418. and continuing up to and including @var{last}.
  3419. Providing a @var{last} sector of @option{last}
  3420. specifies "to the end of the flash bank".
  3421. The @var{num} parameter is a value shown by @command{flash banks}.
  3422. @end deffn
  3423. @deffn Command {flash protect_check} num
  3424. Check protection state of sectors in flash bank @var{num}.
  3425. The @var{num} parameter is a value shown by @command{flash banks}.
  3426. @comment @option{flash erase_sector} using the same syntax.
  3427. This updates the protection information displayed by @option{flash info}.
  3428. (Code execution may have invalidated any state records kept by OpenOCD.)
  3429. @end deffn
  3430. @anchor{Flash Driver List}
  3431. @section Flash Driver List
  3432. As noted above, the @command{flash bank} command requires a driver name,
  3433. and allows driver-specific options and behaviors.
  3434. Some drivers also activate driver-specific commands.
  3435. @subsection External Flash
  3436. @deffn {Flash Driver} cfi
  3437. @cindex Common Flash Interface
  3438. @cindex CFI
  3439. The ``Common Flash Interface'' (CFI) is the main standard for
  3440. external NOR flash chips, each of which connects to a
  3441. specific external chip select on the CPU.
  3442. Frequently the first such chip is used to boot the system.
  3443. Your board's @code{reset-init} handler might need to
  3444. configure additional chip selects using other commands (like: @command{mww} to
  3445. configure a bus and its timings), or
  3446. perhaps configure a GPIO pin that controls the ``write protect'' pin
  3447. on the flash chip.
  3448. The CFI driver can use a target-specific working area to significantly
  3449. speed up operation.
  3450. The CFI driver can accept the following optional parameters, in any order:
  3451. @itemize
  3452. @item @var{jedec_probe} ... is used to detect certain non-CFI flash ROMs,
  3453. like AM29LV010 and similar types.
  3454. @item @var{x16_as_x8} ... when a 16-bit flash is hooked up to an 8-bit bus.
  3455. @end itemize
  3456. To configure two adjacent banks of 16 MBytes each, both sixteen bits (two bytes)
  3457. wide on a sixteen bit bus:
  3458. @example
  3459. flash bank cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
  3460. flash bank cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
  3461. @end example
  3462. To configure one bank of 32 MBytes
  3463. built from two sixteen bit (two byte) wide parts wired in parallel
  3464. to create a thirty-two bit (four byte) bus with doubled throughput:
  3465. @example
  3466. flash bank cfi 0x00000000 0x02000000 2 4 $_TARGETNAME
  3467. @end example
  3468. @c "cfi part_id" disabled
  3469. @end deffn
  3470. @subsection Internal Flash (Microcontrollers)
  3471. @deffn {Flash Driver} aduc702x
  3472. The ADUC702x analog microcontrollers from Analog Devices
  3473. include internal flash and use ARM7TDMI cores.
  3474. The aduc702x flash driver works with models ADUC7019 through ADUC7028.
  3475. The setup command only requires the @var{target} argument
  3476. since all devices in this family have the same memory layout.
  3477. @example
  3478. flash bank aduc702x 0 0 0 0 $_TARGETNAME
  3479. @end example
  3480. @end deffn
  3481. @deffn {Flash Driver} at91sam3
  3482. @cindex at91sam3
  3483. All members of the AT91SAM3 microcontroller family from
  3484. Atmel include internal flash and use ARM's Cortex-M3 core. The driver
  3485. currently (6/22/09) recognizes the AT91SAM3U[1/2/4][C/E] chips. Note
  3486. that the driver was orginaly developed and tested using the
  3487. AT91SAM3U4E, using a SAM3U-EK eval board. Support for other chips in
  3488. the family was cribbed from the data sheet. @emph{Note to future
  3489. readers/updaters: Please remove this worrysome comment after other
  3490. chips are confirmed.}
  3491. The AT91SAM3U4[E/C] (256K) chips have two flash banks; most other chips
  3492. have one flash bank. In all cases the flash banks are at
  3493. the following fixed locations:
  3494. @example
  3495. # Flash bank 0 - all chips
  3496. flash bank at91sam3 0x00080000 0 1 1 $_TARGETNAME
  3497. # Flash bank 1 - only 256K chips
  3498. flash bank at91sam3 0x00100000 0 1 1 $_TARGETNAME
  3499. @end example
  3500. Internally, the AT91SAM3 flash memory is organized as follows.
  3501. Unlike the AT91SAM7 chips, these are not used as parameters
  3502. to the @command{flash bank} command:
  3503. @itemize
  3504. @item @emph{N-Banks:} 256K chips have 2 banks, others have 1 bank.
  3505. @item @emph{Bank Size:} 128K/64K Per flash bank
  3506. @item @emph{Sectors:} 16 or 8 per bank
  3507. @item @emph{SectorSize:} 8K Per Sector
  3508. @item @emph{PageSize:} 256 bytes per page. Note that OpenOCD operates on 'sector' sizes, not page sizes.
  3509. @end itemize
  3510. The AT91SAM3 driver adds some additional commands:
  3511. @deffn Command {at91sam3 gpnvm}
  3512. @deffnx Command {at91sam3 gpnvm clear} number
  3513. @deffnx Command {at91sam3 gpnvm set} number
  3514. @deffnx Command {at91sam3 gpnvm show} [@option{all}|number]
  3515. With no parameters, @command{show} or @command{show all},
  3516. shows the status of all GPNVM bits.
  3517. With @command{show} @var{number}, displays that bit.
  3518. With @command{set} @var{number} or @command{clear} @var{number},
  3519. modifies that GPNVM bit.
  3520. @end deffn
  3521. @deffn Command {at91sam3 info}
  3522. This command attempts to display information about the AT91SAM3
  3523. chip. @emph{First} it read the @code{CHIPID_CIDR} [address 0x400e0740, see
  3524. Section 28.2.1, page 505 of the AT91SAM3U 29/may/2009 datasheet,
  3525. document id: doc6430A] and decodes the values. @emph{Second} it reads the
  3526. various clock configuration registers and attempts to display how it
  3527. believes the chip is configured. By default, the SLOWCLK is assumed to
  3528. be 32768 Hz, see the command @command{at91sam3 slowclk}.
  3529. @end deffn
  3530. @deffn Command {at91sam3 slowclk} [value]
  3531. This command shows/sets the slow clock frequency used in the
  3532. @command{at91sam3 info} command calculations above.
  3533. @end deffn
  3534. @end deffn
  3535. @deffn {Flash Driver} at91sam7
  3536. All members of the AT91SAM7 microcontroller family from Atmel include
  3537. internal flash and use ARM7TDMI cores. The driver automatically
  3538. recognizes a number of these chips using the chip identification
  3539. register, and autoconfigures itself.
  3540. @example
  3541. flash bank at91sam7 0 0 0 0 $_TARGETNAME
  3542. @end example
  3543. For chips which are not recognized by the controller driver, you must
  3544. provide additional parameters in the following order:
  3545. @itemize
  3546. @item @var{chip_model} ... label used with @command{flash info}
  3547. @item @var{banks}
  3548. @item @var{sectors_per_bank}
  3549. @item @var{pages_per_sector}
  3550. @item @var{pages_size}
  3551. @item @var{num_nvm_bits}
  3552. @item @var{freq_khz} ... required if an external clock is provided,
  3553. optional (but recommended) when the oscillator frequency is known
  3554. @end itemize
  3555. It is recommended that you provide zeroes for all of those values
  3556. except the clock frequency, so that everything except that frequency
  3557. will be autoconfigured.
  3558. Knowing the frequency helps ensure correct timings for flash access.
  3559. The flash controller handles erases automatically on a page (128/256 byte)
  3560. basis, so explicit erase commands are not necessary for flash programming.
  3561. However, there is an ``EraseAll`` command that can erase an entire flash
  3562. plane (of up to 256KB), and it will be used automatically when you issue
  3563. @command{flash erase_sector} or @command{flash erase_address} commands.
  3564. @deffn Command {at91sam7 gpnvm} bitnum (@option{set}|@option{clear})
  3565. Set or clear a ``General Purpose Non-Volatile Memory'' (GPNVM)
  3566. bit for the processor. Each processor has a number of such bits,
  3567. used for controlling features such as brownout detection (so they
  3568. are not truly general purpose).
  3569. @quotation Note
  3570. This assumes that the first flash bank (number 0) is associated with
  3571. the appropriate at91sam7 target.
  3572. @end quotation
  3573. @end deffn
  3574. @end deffn
  3575. @deffn {Flash Driver} avr
  3576. The AVR 8-bit microcontrollers from Atmel integrate flash memory.
  3577. @emph{The current implementation is incomplete.}
  3578. @comment - defines mass_erase ... pointless given flash_erase_address
  3579. @end deffn
  3580. @deffn {Flash Driver} ecosflash
  3581. @emph{No idea what this is...}
  3582. The @var{ecosflash} driver defines one mandatory parameter,
  3583. the name of a modules of target code which is downloaded
  3584. and executed.
  3585. @end deffn
  3586. @deffn {Flash Driver} lpc2000
  3587. Most members of the LPC1700 and LPC2000 microcontroller families from NXP
  3588. include internal flash and use Cortex-M3 (LPC1700) or ARM7TDMI (LPC2000) cores.
  3589. @quotation Note
  3590. There are LPC2000 devices which are not supported by the @var{lpc2000}
  3591. driver:
  3592. The LPC2888 is supported by the @var{lpc288x} driver.
  3593. The LPC29xx family is supported by the @var{lpc2900} driver.
  3594. @end quotation
  3595. The @var{lpc2000} driver defines two mandatory and one optional parameters,
  3596. which must appear in the following order:
  3597. @itemize
  3598. @item @var{variant} ... required, may be
  3599. @option{lpc2000_v1} (older LPC21xx and LPC22xx)
  3600. @option{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx)
  3601. or @option{lpc1700} (LPC175x and LPC176x)
  3602. @item @var{clock_kHz} ... the frequency, in kiloHertz,
  3603. at which the core is running
  3604. @item @option{calc_checksum} ... optional (but you probably want to provide this!),
  3605. telling the driver to calculate a valid checksum for the exception vector table.
  3606. @quotation Note
  3607. If you don't provide @option{calc_checksum} when you're writing the vector
  3608. table, the boot ROM will almost certainly ignore your flash image.
  3609. However, if you do provide it,
  3610. with most tool chains @command{verify_image} will fail.
  3611. @end quotation
  3612. @end itemize
  3613. LPC flashes don't require the chip and bus width to be specified.
  3614. @example
  3615. flash bank lpc2000 0x0 0x7d000 0 0 $_TARGETNAME \
  3616. lpc2000_v2 14765 calc_checksum
  3617. @end example
  3618. @deffn {Command} {lpc2000 part_id} bank
  3619. Displays the four byte part identifier associated with
  3620. the specified flash @var{bank}.
  3621. @end deffn
  3622. @end deffn
  3623. @deffn {Flash Driver} lpc288x
  3624. The LPC2888 microcontroller from NXP needs slightly different flash
  3625. support from its lpc2000 siblings.
  3626. The @var{lpc288x} driver defines one mandatory parameter,
  3627. the programming clock rate in Hz.
  3628. LPC flashes don't require the chip and bus width to be specified.
  3629. @example
  3630. flash bank lpc288x 0 0 0 0 $_TARGETNAME 12000000
  3631. @end example
  3632. @end deffn
  3633. @deffn {Flash Driver} lpc2900
  3634. This driver supports the LPC29xx ARM968E based microcontroller family
  3635. from NXP.
  3636. The predefined parameters @var{base}, @var{size}, @var{chip_width} and
  3637. @var{bus_width} of the @code{flash bank} command are ignored. Flash size and
  3638. sector layout are auto-configured by the driver.
  3639. The driver has one additional mandatory parameter: The CPU clock rate
  3640. (in kHz) at the time the flash operations will take place. Most of the time this
  3641. will not be the crystal frequency, but a higher PLL frequency. The
  3642. @code{reset-init} event handler in the board script is usually the place where
  3643. you start the PLL.
  3644. The driver rejects flashless devices (currently the LPC2930).
  3645. The EEPROM in LPC2900 devices is not mapped directly into the address space.
  3646. It must be handled much more like NAND flash memory, and will therefore be
  3647. handled by a separate @code{lpc2900_eeprom} driver (not yet available).
  3648. Sector protection in terms of the LPC2900 is handled transparently. Every time a
  3649. sector needs to be erased or programmed, it is automatically unprotected.
  3650. What is shown as protection status in the @code{flash info} command, is
  3651. actually the LPC2900 @emph{sector security}. This is a mechanism to prevent a
  3652. sector from ever being erased or programmed again. As this is an irreversible
  3653. mechanism, it is handled by a special command (@code{lpc2900 secure_sector}),
  3654. and not by the standard @code{flash protect} command.
  3655. Example for a 125 MHz clock frequency:
  3656. @example
  3657. flash bank lpc2900 0 0 0 0 $_TARGETNAME 125000
  3658. @end example
  3659. Some @code{lpc2900}-specific commands are defined. In the following command list,
  3660. the @var{bank} parameter is the bank number as obtained by the
  3661. @code{flash banks} command.
  3662. @deffn Command {lpc2900 signature} bank
  3663. Calculates a 128-bit hash value, the @emph{signature}, from the whole flash
  3664. content. This is a hardware feature of the flash block, hence the calculation is
  3665. very fast. You may use this to verify the content of a programmed device against
  3666. a known signature.
  3667. Example:
  3668. @example
  3669. lpc2900 signature 0
  3670. signature: 0x5f40cdc8:0xc64e592e:0x10490f89:0x32a0f317
  3671. @end example
  3672. @end deffn
  3673. @deffn Command {lpc2900 read_custom} bank filename
  3674. Reads the 912 bytes of customer information from the flash index sector, and
  3675. saves it to a file in binary format.
  3676. Example:
  3677. @example
  3678. lpc2900 read_custom 0 /path_to/customer_info.bin
  3679. @end example
  3680. @end deffn
  3681. The index sector of the flash is a @emph{write-only} sector. It cannot be
  3682. erased! In order to guard against unintentional write access, all following
  3683. commands need to be preceeded by a successful call to the @code{password}
  3684. command:
  3685. @deffn Command {lpc2900 password} bank password
  3686. You need to use this command right before each of the following commands:
  3687. @code{lpc2900 write_custom}, @code{lpc2900 secure_sector},
  3688. @code{lpc2900 secure_jtag}.
  3689. The password string is fixed to "I_know_what_I_am_doing".
  3690. Example:
  3691. @example
  3692. lpc2900 password 0 I_know_what_I_am_doing
  3693. Potentially dangerous operation allowed in next command!
  3694. @end example
  3695. @end deffn
  3696. @deffn Command {lpc2900 write_custom} bank filename type
  3697. Writes the content of the file into the customer info space of the flash index
  3698. sector. The filetype can be specified with the @var{type} field. Possible values
  3699. for @var{type} are: @var{bin} (binary), @var{ihex} (Intel hex format),
  3700. @var{elf} (ELF binary) or @var{s19} (Motorola S-records). The file must
  3701. contain a single section, and the contained data length must be exactly
  3702. 912 bytes.
  3703. @quotation Attention
  3704. This cannot be reverted! Be careful!
  3705. @end quotation
  3706. Example:
  3707. @example
  3708. lpc2900 write_custom 0 /path_to/customer_info.bin bin
  3709. @end example
  3710. @end deffn
  3711. @deffn Command {lpc2900 secure_sector} bank first last
  3712. Secures the sector range from @var{first} to @var{last} (including) against
  3713. further program and erase operations. The sector security will be effective
  3714. after the next power cycle.
  3715. @quotation Attention
  3716. This cannot be reverted! Be careful!
  3717. @end quotation
  3718. Secured sectors appear as @emph{protected} in the @code{flash info} command.
  3719. Example:
  3720. @example
  3721. lpc2900 secure_sector 0 1 1
  3722. flash info 0
  3723. #0 : lpc2900 at 0x20000000, size 0x000c0000, (...)
  3724. # 0: 0x00000000 (0x2000 8kB) not protected
  3725. # 1: 0x00002000 (0x2000 8kB) protected
  3726. # 2: 0x00004000 (0x2000 8kB) not protected
  3727. @end example
  3728. @end deffn
  3729. @deffn Command {lpc2900 secure_jtag} bank
  3730. Irreversibly disable the JTAG port. The new JTAG security setting will be
  3731. effective after the next power cycle.
  3732. @quotation Attention
  3733. This cannot be reverted! Be careful!
  3734. @end quotation
  3735. Examples:
  3736. @example
  3737. lpc2900 secure_jtag 0
  3738. @end example
  3739. @end deffn
  3740. @end deffn
  3741. @deffn {Flash Driver} ocl
  3742. @emph{No idea what this is, other than using some arm7/arm9 core.}
  3743. @example
  3744. flash bank ocl 0 0 0 0 $_TARGETNAME
  3745. @end example
  3746. @end deffn
  3747. @deffn {Flash Driver} pic32mx
  3748. The PIC32MX microcontrollers are based on the MIPS 4K cores,
  3749. and integrate flash memory.
  3750. @emph{The current implementation is incomplete.}
  3751. @example
  3752. flash bank pix32mx 0 0 0 0 $_TARGETNAME
  3753. @end example
  3754. @comment numerous *disabled* commands are defined:
  3755. @comment - chip_erase ... pointless given flash_erase_address
  3756. @comment - lock, unlock ... pointless given protect on/off (yes?)
  3757. @comment - pgm_word ... shouldn't bank be deduced from address??
  3758. Some pic32mx-specific commands are defined:
  3759. @deffn Command {pic32mx pgm_word} address value bank
  3760. Programs the specified 32-bit @var{value} at the given @var{address}
  3761. in the specified chip @var{bank}.
  3762. @end deffn
  3763. @end deffn
  3764. @deffn {Flash Driver} stellaris
  3765. All members of the Stellaris LM3Sxxx microcontroller family from
  3766. Texas Instruments
  3767. include internal flash and use ARM Cortex M3 cores.
  3768. The driver automatically recognizes a number of these chips using
  3769. the chip identification register, and autoconfigures itself.
  3770. @footnote{Currently there is a @command{stellaris mass_erase} command.
  3771. That seems pointless since the same effect can be had using the
  3772. standard @command{flash erase_address} command.}
  3773. @example
  3774. flash bank stellaris 0 0 0 0 $_TARGETNAME
  3775. @end example
  3776. @end deffn
  3777. @deffn {Flash Driver} stm32x
  3778. All members of the STM32 microcontroller family from ST Microelectronics
  3779. include internal flash and use ARM Cortex M3 cores.
  3780. The driver automatically recognizes a number of these chips using
  3781. the chip identification register, and autoconfigures itself.
  3782. @example
  3783. flash bank stm32x 0 0 0 0 $_TARGETNAME
  3784. @end example
  3785. Some stm32x-specific commands
  3786. @footnote{Currently there is a @command{stm32x mass_erase} command.
  3787. That seems pointless since the same effect can be had using the
  3788. standard @command{flash erase_address} command.}
  3789. are defined:
  3790. @deffn Command {stm32x lock} num
  3791. Locks the entire stm32 device.
  3792. The @var{num} parameter is a value shown by @command{flash banks}.
  3793. @end deffn
  3794. @deffn Command {stm32x unlock} num
  3795. Unlocks the entire stm32 device.
  3796. The @var{num} parameter is a value shown by @command{flash banks}.
  3797. @end deffn
  3798. @deffn Command {stm32x options_read} num
  3799. Read and display the stm32 option bytes written by
  3800. the @command{stm32x options_write} command.
  3801. The @var{num} parameter is a value shown by @command{flash banks}.
  3802. @end deffn
  3803. @deffn Command {stm32x options_write} num (@option{SWWDG}|@option{HWWDG}) (@option{RSTSTNDBY}|@option{NORSTSTNDBY}) (@option{RSTSTOP}|@option{NORSTSTOP})
  3804. Writes the stm32 option byte with the specified values.
  3805. The @var{num} parameter is a value shown by @command{flash banks}.
  3806. @end deffn
  3807. @end deffn
  3808. @deffn {Flash Driver} str7x
  3809. All members of the STR7 microcontroller family from ST Microelectronics
  3810. include internal flash and use ARM7TDMI cores.
  3811. The @var{str7x} driver defines one mandatory parameter, @var{variant},
  3812. which is either @code{STR71x}, @code{STR73x} or @code{STR75x}.
  3813. @example
  3814. flash bank str7x 0x40000000 0x00040000 0 0 $_TARGETNAME STR71x
  3815. @end example
  3816. @deffn Command {str7x disable_jtag} bank
  3817. Activate the Debug/Readout protection mechanism
  3818. for the specified flash bank.
  3819. @end deffn
  3820. @end deffn
  3821. @deffn {Flash Driver} str9x
  3822. Most members of the STR9 microcontroller family from ST Microelectronics
  3823. include internal flash and use ARM966E cores.
  3824. The str9 needs the flash controller to be configured using
  3825. the @command{str9x flash_config} command prior to Flash programming.
  3826. @example
  3827. flash bank str9x 0x40000000 0x00040000 0 0 $_TARGETNAME
  3828. str9x flash_config 0 4 2 0 0x80000
  3829. @end example
  3830. @deffn Command {str9x flash_config} num bbsr nbbsr bbadr nbbadr
  3831. Configures the str9 flash controller.
  3832. The @var{num} parameter is a value shown by @command{flash banks}.
  3833. @itemize @bullet
  3834. @item @var{bbsr} - Boot Bank Size register
  3835. @item @var{nbbsr} - Non Boot Bank Size register
  3836. @item @var{bbadr} - Boot Bank Start Address register
  3837. @item @var{nbbadr} - Boot Bank Start Address register
  3838. @end itemize
  3839. @end deffn
  3840. @end deffn
  3841. @deffn {Flash Driver} tms470
  3842. Most members of the TMS470 microcontroller family from Texas Instruments
  3843. include internal flash and use ARM7TDMI cores.
  3844. This driver doesn't require the chip and bus width to be specified.
  3845. Some tms470-specific commands are defined:
  3846. @deffn Command {tms470 flash_keyset} key0 key1 key2 key3
  3847. Saves programming keys in a register, to enable flash erase and write commands.
  3848. @end deffn
  3849. @deffn Command {tms470 osc_mhz} clock_mhz
  3850. Reports the clock speed, which is used to calculate timings.
  3851. @end deffn
  3852. @deffn Command {tms470 plldis} (0|1)
  3853. Disables (@var{1}) or enables (@var{0}) use of the PLL to speed up
  3854. the flash clock.
  3855. @end deffn
  3856. @end deffn
  3857. @subsection str9xpec driver
  3858. @cindex str9xpec
  3859. Here is some background info to help
  3860. you better understand how this driver works. OpenOCD has two flash drivers for
  3861. the str9:
  3862. @enumerate
  3863. @item
  3864. Standard driver @option{str9x} programmed via the str9 core. Normally used for
  3865. flash programming as it is faster than the @option{str9xpec} driver.
  3866. @item
  3867. Direct programming @option{str9xpec} using the flash controller. This is an
  3868. ISC compilant (IEEE 1532) tap connected in series with the str9 core. The str9
  3869. core does not need to be running to program using this flash driver. Typical use
  3870. for this driver is locking/unlocking the target and programming the option bytes.
  3871. @end enumerate
  3872. Before we run any commands using the @option{str9xpec} driver we must first disable
  3873. the str9 core. This example assumes the @option{str9xpec} driver has been
  3874. configured for flash bank 0.
  3875. @example
  3876. # assert srst, we do not want core running
  3877. # while accessing str9xpec flash driver
  3878. jtag_reset 0 1
  3879. # turn off target polling
  3880. poll off
  3881. # disable str9 core
  3882. str9xpec enable_turbo 0
  3883. # read option bytes
  3884. str9xpec options_read 0
  3885. # re-enable str9 core
  3886. str9xpec disable_turbo 0
  3887. poll on
  3888. reset halt
  3889. @end example
  3890. The above example will read the str9 option bytes.
  3891. When performing a unlock remember that you will not be able to halt the str9 - it
  3892. has been locked. Halting the core is not required for the @option{str9xpec} driver
  3893. as mentioned above, just issue the commands above manually or from a telnet prompt.
  3894. @deffn {Flash Driver} str9xpec
  3895. Only use this driver for locking/unlocking the device or configuring the option bytes.
  3896. Use the standard str9 driver for programming.
  3897. Before using the flash commands the turbo mode must be enabled using the
  3898. @command{str9xpec enable_turbo} command.
  3899. Several str9xpec-specific commands are defined:
  3900. @deffn Command {str9xpec disable_turbo} num
  3901. Restore the str9 into JTAG chain.
  3902. @end deffn
  3903. @deffn Command {str9xpec enable_turbo} num
  3904. Enable turbo mode, will simply remove the str9 from the chain and talk
  3905. directly to the embedded flash controller.
  3906. @end deffn
  3907. @deffn Command {str9xpec lock} num
  3908. Lock str9 device. The str9 will only respond to an unlock command that will
  3909. erase the device.
  3910. @end deffn
  3911. @deffn Command {str9xpec part_id} num
  3912. Prints the part identifier for bank @var{num}.
  3913. @end deffn
  3914. @deffn Command {str9xpec options_cmap} num (@option{bank0}|@option{bank1})
  3915. Configure str9 boot bank.
  3916. @end deffn
  3917. @deffn Command {str9xpec options_lvdsel} num (@option{vdd}|@option{vdd_vddq})
  3918. Configure str9 lvd source.
  3919. @end deffn
  3920. @deffn Command {str9xpec options_lvdthd} num (@option{2.4v}|@option{2.7v})
  3921. Configure str9 lvd threshold.
  3922. @end deffn
  3923. @deffn Command {str9xpec options_lvdwarn} bank (@option{vdd}|@option{vdd_vddq})
  3924. Configure str9 lvd reset warning source.
  3925. @end deffn
  3926. @deffn Command {str9xpec options_read} num
  3927. Read str9 option bytes.
  3928. @end deffn
  3929. @deffn Command {str9xpec options_write} num
  3930. Write str9 option bytes.
  3931. @end deffn
  3932. @deffn Command {str9xpec unlock} num
  3933. unlock str9 device.
  3934. @end deffn
  3935. @end deffn
  3936. @section mFlash
  3937. @subsection mFlash Configuration
  3938. @cindex mFlash Configuration
  3939. @deffn {Config Command} {mflash bank} soc base RST_pin target
  3940. Configures a mflash for @var{soc} host bank at
  3941. address @var{base}.
  3942. The pin number format depends on the host GPIO naming convention.
  3943. Currently, the mflash driver supports s3c2440 and pxa270.
  3944. Example for s3c2440 mflash where @var{RST pin} is GPIO B1:
  3945. @example
  3946. mflash bank s3c2440 0x10000000 1b 0
  3947. @end example
  3948. Example for pxa270 mflash where @var{RST pin} is GPIO 43:
  3949. @example
  3950. mflash bank pxa270 0x08000000 43 0
  3951. @end example
  3952. @end deffn
  3953. @subsection mFlash commands
  3954. @cindex mFlash commands
  3955. @deffn Command {mflash config pll} frequency
  3956. Configure mflash PLL.
  3957. The @var{frequency} is the mflash input frequency, in Hz.
  3958. Issuing this command will erase mflash's whole internal nand and write new pll.
  3959. After this command, mflash needs power-on-reset for normal operation.
  3960. If pll was newly configured, storage and boot(optional) info also need to be update.
  3961. @end deffn
  3962. @deffn Command {mflash config boot}
  3963. Configure bootable option.
  3964. If bootable option is set, mflash offer the first 8 sectors
  3965. (4kB) for boot.
  3966. @end deffn
  3967. @deffn Command {mflash config storage}
  3968. Configure storage information.
  3969. For the normal storage operation, this information must be
  3970. written.
  3971. @end deffn
  3972. @deffn Command {mflash dump} num filename offset size
  3973. Dump @var{size} bytes, starting at @var{offset} bytes from the
  3974. beginning of the bank @var{num}, to the file named @var{filename}.
  3975. @end deffn
  3976. @deffn Command {mflash probe}
  3977. Probe mflash.
  3978. @end deffn
  3979. @deffn Command {mflash write} num filename offset
  3980. Write the binary file @var{filename} to mflash bank @var{num}, starting at
  3981. @var{offset} bytes from the beginning of the bank.
  3982. @end deffn
  3983. @node NAND Flash Commands
  3984. @chapter NAND Flash Commands
  3985. @cindex NAND
  3986. Compared to NOR or SPI flash, NAND devices are inexpensive
  3987. and high density. Today's NAND chips, and multi-chip modules,
  3988. commonly hold multiple GigaBytes of data.
  3989. NAND chips consist of a number of ``erase blocks'' of a given
  3990. size (such as 128 KBytes), each of which is divided into a
  3991. number of pages (of perhaps 512 or 2048 bytes each). Each
  3992. page of a NAND flash has an ``out of band'' (OOB) area to hold
  3993. Error Correcting Code (ECC) and other metadata, usually 16 bytes
  3994. of OOB for every 512 bytes of page data.
  3995. One key characteristic of NAND flash is that its error rate
  3996. is higher than that of NOR flash. In normal operation, that
  3997. ECC is used to correct and detect errors. However, NAND
  3998. blocks can also wear out and become unusable; those blocks
  3999. are then marked "bad". NAND chips are even shipped from the
  4000. manufacturer with a few bad blocks. The highest density chips
  4001. use a technology (MLC) that wears out more quickly, so ECC
  4002. support is increasingly important as a way to detect blocks
  4003. that have begun to fail, and help to preserve data integrity
  4004. with techniques such as wear leveling.
  4005. Software is used to manage the ECC. Some controllers don't
  4006. support ECC directly; in those cases, software ECC is used.
  4007. Other controllers speed up the ECC calculations with hardware.
  4008. Single-bit error correction hardware is routine. Controllers
  4009. geared for newer MLC chips may correct 4 or more errors for
  4010. every 512 bytes of data.
  4011. You will need to make sure that any data you write using
  4012. OpenOCD includes the apppropriate kind of ECC. For example,
  4013. that may mean passing the @code{oob_softecc} flag when
  4014. writing NAND data, or ensuring that the correct hardware
  4015. ECC mode is used.
  4016. The basic steps for using NAND devices include:
  4017. @enumerate
  4018. @item Declare via the command @command{nand device}
  4019. @* Do this in a board-specific configuration file,
  4020. passing parameters as needed by the controller.
  4021. @item Configure each device using @command{nand probe}.
  4022. @* Do this only after the associated target is set up,
  4023. such as in its reset-init script or in procures defined
  4024. to access that device.
  4025. @item Operate on the flash via @command{nand subcommand}
  4026. @* Often commands to manipulate the flash are typed by a human, or run
  4027. via a script in some automated way. Common task include writing a
  4028. boot loader, operating system, or other data needed to initialize or
  4029. de-brick a board.
  4030. @end enumerate
  4031. @b{NOTE:} At the time this text was written, the largest NAND
  4032. flash fully supported by OpenOCD is 2 GiBytes (16 GiBits).
  4033. This is because the variables used to hold offsets and lengths
  4034. are only 32 bits wide.
  4035. (Larger chips may work in some cases, unless an offset or length
  4036. is larger than 0xffffffff, the largest 32-bit unsigned integer.)
  4037. Some larger devices will work, since they are actually multi-chip
  4038. modules with two smaller chips and individual chipselect lines.
  4039. @anchor{NAND Configuration}
  4040. @section NAND Configuration Commands
  4041. @cindex NAND configuration
  4042. NAND chips must be declared in configuration scripts,
  4043. plus some additional configuration that's done after
  4044. OpenOCD has initialized.
  4045. @deffn {Config Command} {nand device} name driver target [configparams...]
  4046. Declares a NAND device, which can be read and written to
  4047. after it has been configured through @command{nand probe}.
  4048. In OpenOCD, devices are single chips; this is unlike some
  4049. operating systems, which may manage multiple chips as if
  4050. they were a single (larger) device.
  4051. In some cases, configuring a device will activate extra
  4052. commands; see the controller-specific documentation.
  4053. @b{NOTE:} This command is not available after OpenOCD
  4054. initialization has completed. Use it in board specific
  4055. configuration files, not interactively.
  4056. @itemize @bullet
  4057. @item @var{name} ... may be used to reference the NAND bank
  4058. in most other NAND commands. A number is also available.
  4059. @item @var{driver} ... identifies the NAND controller driver
  4060. associated with the NAND device being declared.
  4061. @xref{NAND Driver List}.
  4062. @item @var{target} ... names the target used when issuing
  4063. commands to the NAND controller.
  4064. @comment Actually, it's currently a controller-specific parameter...
  4065. @item @var{configparams} ... controllers may support, or require,
  4066. additional parameters. See the controller-specific documentation
  4067. for more information.
  4068. @end itemize
  4069. @end deffn
  4070. @deffn Command {nand list}
  4071. Prints a summary of each device declared
  4072. using @command{nand device}, numbered from zero.
  4073. Note that un-probed devices show no details.
  4074. @example
  4075. > nand list
  4076. #0: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
  4077. blocksize: 131072, blocks: 8192
  4078. #1: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
  4079. blocksize: 131072, blocks: 8192
  4080. >
  4081. @end example
  4082. @end deffn
  4083. @deffn Command {nand probe} num
  4084. Probes the specified device to determine key characteristics
  4085. like its page and block sizes, and how many blocks it has.
  4086. The @var{num} parameter is the value shown by @command{nand list}.
  4087. You must (successfully) probe a device before you can use
  4088. it with most other NAND commands.
  4089. @end deffn
  4090. @section Erasing, Reading, Writing to NAND Flash
  4091. @deffn Command {nand dump} num filename offset length [oob_option]
  4092. @cindex NAND reading
  4093. Reads binary data from the NAND device and writes it to the file,
  4094. starting at the specified offset.
  4095. The @var{num} parameter is the value shown by @command{nand list}.
  4096. Use a complete path name for @var{filename}, so you don't depend
  4097. on the directory used to start the OpenOCD server.
  4098. The @var{offset} and @var{length} must be exact multiples of the
  4099. device's page size. They describe a data region; the OOB data
  4100. associated with each such page may also be accessed.
  4101. @b{NOTE:} At the time this text was written, no error correction
  4102. was done on the data that's read, unless raw access was disabled
  4103. and the underlying NAND controller driver had a @code{read_page}
  4104. method which handled that error correction.
  4105. By default, only page data is saved to the specified file.
  4106. Use an @var{oob_option} parameter to save OOB data:
  4107. @itemize @bullet
  4108. @item no oob_* parameter
  4109. @*Output file holds only page data; OOB is discarded.
  4110. @item @code{oob_raw}
  4111. @*Output file interleaves page data and OOB data;
  4112. the file will be longer than "length" by the size of the
  4113. spare areas associated with each data page.
  4114. Note that this kind of "raw" access is different from
  4115. what's implied by @command{nand raw_access}, which just
  4116. controls whether a hardware-aware access method is used.
  4117. @item @code{oob_only}
  4118. @*Output file has only raw OOB data, and will
  4119. be smaller than "length" since it will contain only the
  4120. spare areas associated with each data page.
  4121. @end itemize
  4122. @end deffn
  4123. @deffn Command {nand erase} num [offset length]
  4124. @cindex NAND erasing
  4125. @cindex NAND programming
  4126. Erases blocks on the specified NAND device, starting at the
  4127. specified @var{offset} and continuing for @var{length} bytes.
  4128. Both of those values must be exact multiples of the device's
  4129. block size, and the region they specify must fit entirely in the chip.
  4130. If those parameters are not specified,
  4131. the whole NAND chip will be erased.
  4132. The @var{num} parameter is the value shown by @command{nand list}.
  4133. @b{NOTE:} This command will try to erase bad blocks, when told
  4134. to do so, which will probably invalidate the manufacturer's bad
  4135. block marker.
  4136. For the remainder of the current server session, @command{nand info}
  4137. will still report that the block ``is'' bad.
  4138. @end deffn
  4139. @deffn Command {nand write} num filename offset [option...]
  4140. @cindex NAND writing
  4141. @cindex NAND programming
  4142. Writes binary data from the file into the specified NAND device,
  4143. starting at the specified offset. Those pages should already
  4144. have been erased; you can't change zero bits to one bits.
  4145. The @var{num} parameter is the value shown by @command{nand list}.
  4146. Use a complete path name for @var{filename}, so you don't depend
  4147. on the directory used to start the OpenOCD server.
  4148. The @var{offset} must be an exact multiple of the device's page size.
  4149. All data in the file will be written, assuming it doesn't run
  4150. past the end of the device.
  4151. Only full pages are written, and any extra space in the last
  4152. page will be filled with 0xff bytes. (That includes OOB data,
  4153. if that's being written.)
  4154. @b{NOTE:} At the time this text was written, bad blocks are
  4155. ignored. That is, this routine will not skip bad blocks,
  4156. but will instead try to write them. This can cause problems.
  4157. Provide at most one @var{option} parameter. With some
  4158. NAND drivers, the meanings of these parameters may change
  4159. if @command{nand raw_access} was used to disable hardware ECC.
  4160. @itemize @bullet
  4161. @item no oob_* parameter
  4162. @*File has only page data, which is written.
  4163. If raw acccess is in use, the OOB area will not be written.
  4164. Otherwise, if the underlying NAND controller driver has
  4165. a @code{write_page} routine, that routine may write the OOB
  4166. with hardware-computed ECC data.
  4167. @item @code{oob_only}
  4168. @*File has only raw OOB data, which is written to the OOB area.
  4169. Each page's data area stays untouched. @i{This can be a dangerous
  4170. option}, since it can invalidate the ECC data.
  4171. You may need to force raw access to use this mode.
  4172. @item @code{oob_raw}
  4173. @*File interleaves data and OOB data, both of which are written
  4174. If raw access is enabled, the data is written first, then the
  4175. un-altered OOB.
  4176. Otherwise, if the underlying NAND controller driver has
  4177. a @code{write_page} routine, that routine may modify the OOB
  4178. before it's written, to include hardware-computed ECC data.
  4179. @item @code{oob_softecc}
  4180. @*File has only page data, which is written.
  4181. The OOB area is filled with 0xff, except for a standard 1-bit
  4182. software ECC code stored in conventional locations.
  4183. You might need to force raw access to use this mode, to prevent
  4184. the underlying driver from applying hardware ECC.
  4185. @item @code{oob_softecc_kw}
  4186. @*File has only page data, which is written.
  4187. The OOB area is filled with 0xff, except for a 4-bit software ECC
  4188. specific to the boot ROM in Marvell Kirkwood SoCs.
  4189. You might need to force raw access to use this mode, to prevent
  4190. the underlying driver from applying hardware ECC.
  4191. @end itemize
  4192. @end deffn
  4193. @deffn Command {nand verify} num filename offset [option...]
  4194. @cindex NAND verification
  4195. @cindex NAND programming
  4196. Verify the binary data in the file has been programmed to the
  4197. specified NAND device, starting at the specified offset.
  4198. The @var{num} parameter is the value shown by @command{nand list}.
  4199. Use a complete path name for @var{filename}, so you don't depend
  4200. on the directory used to start the OpenOCD server.
  4201. The @var{offset} must be an exact multiple of the device's page size.
  4202. All data in the file will be read and compared to the contents of the
  4203. flash, assuming it doesn't run past the end of the device.
  4204. As with @command{nand write}, only full pages are verified, so any extra
  4205. space in the last page will be filled with 0xff bytes.
  4206. The same @var{options} accepted by @command{nand write},
  4207. and the file will be processed similarly to produce the buffers that
  4208. can be compared against the contents produced from @command{nand dump}.
  4209. @b{NOTE:} This will not work when the underlying NAND controller
  4210. driver's @code{write_page} routine must update the OOB with a
  4211. hardward-computed ECC before the data is written. This limitation may
  4212. be removed in a future release.
  4213. @end deffn
  4214. @section Other NAND commands
  4215. @cindex NAND other commands
  4216. @deffn Command {nand check_bad_blocks} [offset length]
  4217. Checks for manufacturer bad block markers on the specified NAND
  4218. device. If no parameters are provided, checks the whole
  4219. device; otherwise, starts at the specified @var{offset} and
  4220. continues for @var{length} bytes.
  4221. Both of those values must be exact multiples of the device's
  4222. block size, and the region they specify must fit entirely in the chip.
  4223. The @var{num} parameter is the value shown by @command{nand list}.
  4224. @b{NOTE:} Before using this command you should force raw access
  4225. with @command{nand raw_access enable} to ensure that the underlying
  4226. driver will not try to apply hardware ECC.
  4227. @end deffn
  4228. @deffn Command {nand info} num
  4229. The @var{num} parameter is the value shown by @command{nand list}.
  4230. This prints the one-line summary from "nand list", plus for
  4231. devices which have been probed this also prints any known
  4232. status for each block.
  4233. @end deffn
  4234. @deffn Command {nand raw_access} num (@option{enable}|@option{disable})
  4235. Sets or clears an flag affecting how page I/O is done.
  4236. The @var{num} parameter is the value shown by @command{nand list}.
  4237. This flag is cleared (disabled) by default, but changing that
  4238. value won't affect all NAND devices. The key factor is whether
  4239. the underlying driver provides @code{read_page} or @code{write_page}
  4240. methods. If it doesn't provide those methods, the setting of
  4241. this flag is irrelevant; all access is effectively ``raw''.
  4242. When those methods exist, they are normally used when reading
  4243. data (@command{nand dump} or reading bad block markers) or
  4244. writing it (@command{nand write}). However, enabling
  4245. raw access (setting the flag) prevents use of those methods,
  4246. bypassing hardware ECC logic.
  4247. @i{This can be a dangerous option}, since writing blocks
  4248. with the wrong ECC data can cause them to be marked as bad.
  4249. @end deffn
  4250. @anchor{NAND Driver List}
  4251. @section NAND Driver List
  4252. As noted above, the @command{nand device} command allows
  4253. driver-specific options and behaviors.
  4254. Some controllers also activate controller-specific commands.
  4255. @deffn {NAND Driver} at91sam9
  4256. This driver handles the NAND controllers found on AT91SAM9 family chips from
  4257. Atmel. It takes two extra parameters: address of the NAND chip;
  4258. address of the ECC controller.
  4259. @example
  4260. nand device $NANDFLASH at91sam9 $CHIPNAME 0x40000000 0xfffffe800
  4261. @end example
  4262. AT91SAM9 chips support single-bit ECC hardware. The @code{write_page} and
  4263. @code{read_page} methods are used to utilize the ECC hardware unless they are
  4264. disabled by using the @command{nand raw_access} command. There are four
  4265. additional commands that are needed to fully configure the AT91SAM9 NAND
  4266. controller. Two are optional; most boards use the same wiring for ALE/CLE:
  4267. @deffn Command {at91sam9 cle} num addr_line
  4268. Configure the address line used for latching commands. The @var{num}
  4269. parameter is the value shown by @command{nand list}.
  4270. @end deffn
  4271. @deffn Command {at91sam9 ale} num addr_line
  4272. Configure the address line used for latching addresses. The @var{num}
  4273. parameter is the value shown by @command{nand list}.
  4274. @end deffn
  4275. For the next two commands, it is assumed that the pins have already been
  4276. properly configured for input or output.
  4277. @deffn Command {at91sam9 rdy_busy} num pio_base_addr pin
  4278. Configure the RDY/nBUSY input from the NAND device. The @var{num}
  4279. parameter is the value shown by @command{nand list}. @var{pio_base_addr}
  4280. is the base address of the PIO controller and @var{pin} is the pin number.
  4281. @end deffn
  4282. @deffn Command {at91sam9 ce} num pio_base_addr pin
  4283. Configure the chip enable input to the NAND device. The @var{num}
  4284. parameter is the value shown by @command{nand list}. @var{pio_base_addr}
  4285. is the base address of the PIO controller and @var{pin} is the pin number.
  4286. @end deffn
  4287. @end deffn
  4288. @deffn {NAND Driver} davinci
  4289. This driver handles the NAND controllers found on DaVinci family
  4290. chips from Texas Instruments.
  4291. It takes three extra parameters:
  4292. address of the NAND chip;
  4293. hardware ECC mode to use (@option{hwecc1},
  4294. @option{hwecc4}, @option{hwecc4_infix});
  4295. address of the AEMIF controller on this processor.
  4296. @example
  4297. nand device davinci dm355.arm 0x02000000 hwecc4 0x01e10000
  4298. @end example
  4299. All DaVinci processors support the single-bit ECC hardware,
  4300. and newer ones also support the four-bit ECC hardware.
  4301. The @code{write_page} and @code{read_page} methods are used
  4302. to implement those ECC modes, unless they are disabled using
  4303. the @command{nand raw_access} command.
  4304. @end deffn
  4305. @deffn {NAND Driver} lpc3180
  4306. These controllers require an extra @command{nand device}
  4307. parameter: the clock rate used by the controller.
  4308. @deffn Command {lpc3180 select} num [mlc|slc]
  4309. Configures use of the MLC or SLC controller mode.
  4310. MLC implies use of hardware ECC.
  4311. The @var{num} parameter is the value shown by @command{nand list}.
  4312. @end deffn
  4313. At this writing, this driver includes @code{write_page}
  4314. and @code{read_page} methods. Using @command{nand raw_access}
  4315. to disable those methods will prevent use of hardware ECC
  4316. in the MLC controller mode, but won't change SLC behavior.
  4317. @end deffn
  4318. @comment current lpc3180 code won't issue 5-byte address cycles
  4319. @deffn {NAND Driver} orion
  4320. These controllers require an extra @command{nand device}
  4321. parameter: the address of the controller.
  4322. @example
  4323. nand device orion 0xd8000000
  4324. @end example
  4325. These controllers don't define any specialized commands.
  4326. At this writing, their drivers don't include @code{write_page}
  4327. or @code{read_page} methods, so @command{nand raw_access} won't
  4328. change any behavior.
  4329. @end deffn
  4330. @deffn {NAND Driver} s3c2410
  4331. @deffnx {NAND Driver} s3c2412
  4332. @deffnx {NAND Driver} s3c2440
  4333. @deffnx {NAND Driver} s3c2443
  4334. @deffnx {NAND Driver} s3c6400
  4335. These S3C family controllers don't have any special
  4336. @command{nand device} options, and don't define any
  4337. specialized commands.
  4338. At this writing, their drivers don't include @code{write_page}
  4339. or @code{read_page} methods, so @command{nand raw_access} won't
  4340. change any behavior.
  4341. @end deffn
  4342. @node PLD/FPGA Commands
  4343. @chapter PLD/FPGA Commands
  4344. @cindex PLD
  4345. @cindex FPGA
  4346. Programmable Logic Devices (PLDs) and the more flexible
  4347. Field Programmable Gate Arrays (FPGAs) are both types of programmable hardware.
  4348. OpenOCD can support programming them.
  4349. Although PLDs are generally restrictive (cells are less functional, and
  4350. there are no special purpose cells for memory or computational tasks),
  4351. they share the same OpenOCD infrastructure.
  4352. Accordingly, both are called PLDs here.
  4353. @section PLD/FPGA Configuration and Commands
  4354. As it does for JTAG TAPs, debug targets, and flash chips (both NOR and NAND),
  4355. OpenOCD maintains a list of PLDs available for use in various commands.
  4356. Also, each such PLD requires a driver.
  4357. They are referenced by the number shown by the @command{pld devices} command,
  4358. and new PLDs are defined by @command{pld device driver_name}.
  4359. @deffn {Config Command} {pld device} driver_name tap_name [driver_options]
  4360. Defines a new PLD device, supported by driver @var{driver_name},
  4361. using the TAP named @var{tap_name}.
  4362. The driver may make use of any @var{driver_options} to configure its
  4363. behavior.
  4364. @end deffn
  4365. @deffn {Command} {pld devices}
  4366. Lists the PLDs and their numbers.
  4367. @end deffn
  4368. @deffn {Command} {pld load} num filename
  4369. Loads the file @file{filename} into the PLD identified by @var{num}.
  4370. The file format must be inferred by the driver.
  4371. @end deffn
  4372. @section PLD/FPGA Drivers, Options, and Commands
  4373. Drivers may support PLD-specific options to the @command{pld device}
  4374. definition command, and may also define commands usable only with
  4375. that particular type of PLD.
  4376. @deffn {FPGA Driver} virtex2
  4377. Virtex-II is a family of FPGAs sold by Xilinx.
  4378. It supports the IEEE 1532 standard for In-System Configuration (ISC).
  4379. No driver-specific PLD definition options are used,
  4380. and one driver-specific command is defined.
  4381. @deffn {Command} {virtex2 read_stat} num
  4382. Reads and displays the Virtex-II status register (STAT)
  4383. for FPGA @var{num}.
  4384. @end deffn
  4385. @end deffn
  4386. @node General Commands
  4387. @chapter General Commands
  4388. @cindex commands
  4389. The commands documented in this chapter here are common commands that
  4390. you, as a human, may want to type and see the output of. Configuration type
  4391. commands are documented elsewhere.
  4392. Intent:
  4393. @itemize @bullet
  4394. @item @b{Source Of Commands}
  4395. @* OpenOCD commands can occur in a configuration script (discussed
  4396. elsewhere) or typed manually by a human or supplied programatically,
  4397. or via one of several TCP/IP Ports.
  4398. @item @b{From the human}
  4399. @* A human should interact with the telnet interface (default port: 4444)
  4400. or via GDB (default port 3333).
  4401. To issue commands from within a GDB session, use the @option{monitor}
  4402. command, e.g. use @option{monitor poll} to issue the @option{poll}
  4403. command. All output is relayed through the GDB session.
  4404. @item @b{Machine Interface}
  4405. The Tcl interface's intent is to be a machine interface. The default Tcl
  4406. port is 5555.
  4407. @end itemize
  4408. @section Daemon Commands
  4409. @deffn {Command} exit
  4410. Exits the current telnet session.
  4411. @end deffn
  4412. @deffn {Command} help [string]
  4413. With no parameters, prints help text for all commands.
  4414. Otherwise, prints each helptext containing @var{string}.
  4415. Not every command provides helptext.
  4416. Configuration commands, and commands valid at any time, are
  4417. explicitly noted in parenthesis.
  4418. In most cases, no such restriction is listed; this indicates commands
  4419. which are only available after the configuration stage has completed.
  4420. @end deffn
  4421. @deffn Command sleep msec [@option{busy}]
  4422. Wait for at least @var{msec} milliseconds before resuming.
  4423. If @option{busy} is passed, busy-wait instead of sleeping.
  4424. (This option is strongly discouraged.)
  4425. Useful in connection with script files
  4426. (@command{script} command and @command{target_name} configuration).
  4427. @end deffn
  4428. @deffn Command shutdown
  4429. Close the OpenOCD daemon, disconnecting all clients (GDB, telnet, other).
  4430. @end deffn
  4431. @anchor{debug_level}
  4432. @deffn Command debug_level [n]
  4433. @cindex message level
  4434. Display debug level.
  4435. If @var{n} (from 0..3) is provided, then set it to that level.
  4436. This affects the kind of messages sent to the server log.
  4437. Level 0 is error messages only;
  4438. level 1 adds warnings;
  4439. level 2 adds informational messages;
  4440. and level 3 adds debugging messages.
  4441. The default is level 2, but that can be overridden on
  4442. the command line along with the location of that log
  4443. file (which is normally the server's standard output).
  4444. @xref{Running}.
  4445. @end deffn
  4446. @deffn Command fast (@option{enable}|@option{disable})
  4447. Default disabled.
  4448. Set default behaviour of OpenOCD to be "fast and dangerous".
  4449. At this writing, this only affects the defaults for two ARM7/ARM9 parameters:
  4450. fast memory access, and DCC downloads. Those parameters may still be
  4451. individually overridden.
  4452. The target specific "dangerous" optimisation tweaking options may come and go
  4453. as more robust and user friendly ways are found to ensure maximum throughput
  4454. and robustness with a minimum of configuration.
  4455. Typically the "fast enable" is specified first on the command line:
  4456. @example
  4457. openocd -c "fast enable" -c "interface dummy" -f target/str710.cfg
  4458. @end example
  4459. @end deffn
  4460. @deffn Command echo message
  4461. Logs a message at "user" priority.
  4462. Output @var{message} to stdout.
  4463. @example
  4464. echo "Downloading kernel -- please wait"
  4465. @end example
  4466. @end deffn
  4467. @deffn Command log_output [filename]
  4468. Redirect logging to @var{filename};
  4469. the initial log output channel is stderr.
  4470. @end deffn
  4471. @anchor{Target State handling}
  4472. @section Target State handling
  4473. @cindex reset
  4474. @cindex halt
  4475. @cindex target initialization
  4476. In this section ``target'' refers to a CPU configured as
  4477. shown earlier (@pxref{CPU Configuration}).
  4478. These commands, like many, implicitly refer to
  4479. a current target which is used to perform the
  4480. various operations. The current target may be changed
  4481. by using @command{targets} command with the name of the
  4482. target which should become current.
  4483. @deffn Command reg [(number|name) [value]]
  4484. Access a single register by @var{number} or by its @var{name}.
  4485. The target must generally be halted before access to CPU core
  4486. registers is allowed. Depending on the hardware, some other
  4487. registers may be accessible while the target is running.
  4488. @emph{With no arguments}:
  4489. list all available registers for the current target,
  4490. showing number, name, size, value, and cache status.
  4491. For valid entries, a value is shown; valid entries
  4492. which are also dirty (and will be written back later)
  4493. are flagged as such.
  4494. @emph{With number/name}: display that register's value.
  4495. @emph{With both number/name and value}: set register's value.
  4496. Writes may be held in a writeback cache internal to OpenOCD,
  4497. so that setting the value marks the register as dirty instead
  4498. of immediately flushing that value. Resuming CPU execution
  4499. (including by single stepping) or otherwise activating the
  4500. relevant module will flush such values.
  4501. Cores may have surprisingly many registers in their
  4502. Debug and trace infrastructure:
  4503. @example
  4504. > reg
  4505. ===== ARM registers
  4506. (0) r0 (/32): 0x0000D3C2 (dirty)
  4507. (1) r1 (/32): 0xFD61F31C
  4508. (2) r2 (/32)
  4509. ...
  4510. (164) ETM_contextid_comparator_mask (/32)
  4511. >
  4512. @end example
  4513. @end deffn
  4514. @deffn Command halt [ms]
  4515. @deffnx Command wait_halt [ms]
  4516. The @command{halt} command first sends a halt request to the target,
  4517. which @command{wait_halt} doesn't.
  4518. Otherwise these behave the same: wait up to @var{ms} milliseconds,
  4519. or 5 seconds if there is no parameter, for the target to halt
  4520. (and enter debug mode).
  4521. Using 0 as the @var{ms} parameter prevents OpenOCD from waiting.
  4522. @quotation Warning
  4523. On ARM cores, software using the @emph{wait for interrupt} operation
  4524. often blocks the JTAG access needed by a @command{halt} command.
  4525. This is because that operation also puts the core into a low
  4526. power mode by gating the core clock;
  4527. but the core clock is needed to detect JTAG clock transitions.
  4528. One partial workaround uses adaptive clocking: when the core is
  4529. interrupted the operation completes, then JTAG clocks are accepted
  4530. at least until the interrupt handler completes.
  4531. However, this workaround is often unusable since the processor, board,
  4532. and JTAG adapter must all support adaptive JTAG clocking.
  4533. Also, it can't work until an interrupt is issued.
  4534. A more complete workaround is to not use that operation while you
  4535. work with a JTAG debugger.
  4536. Tasking environments generaly have idle loops where the body is the
  4537. @emph{wait for interrupt} operation.
  4538. (On older cores, it is a coprocessor action;
  4539. newer cores have a @option{wfi} instruction.)
  4540. Such loops can just remove that operation, at the cost of higher
  4541. power consumption (because the CPU is needlessly clocked).
  4542. @end quotation
  4543. @end deffn
  4544. @deffn Command resume [address]
  4545. Resume the target at its current code position,
  4546. or the optional @var{address} if it is provided.
  4547. OpenOCD will wait 5 seconds for the target to resume.
  4548. @end deffn
  4549. @deffn Command step [address]
  4550. Single-step the target at its current code position,
  4551. or the optional @var{address} if it is provided.
  4552. @end deffn
  4553. @anchor{Reset Command}
  4554. @deffn Command reset
  4555. @deffnx Command {reset run}
  4556. @deffnx Command {reset halt}
  4557. @deffnx Command {reset init}
  4558. Perform as hard a reset as possible, using SRST if possible.
  4559. @emph{All defined targets will be reset, and target
  4560. events will fire during the reset sequence.}
  4561. The optional parameter specifies what should
  4562. happen after the reset.
  4563. If there is no parameter, a @command{reset run} is executed.
  4564. The other options will not work on all systems.
  4565. @xref{Reset Configuration}.
  4566. @itemize @minus
  4567. @item @b{run} Let the target run
  4568. @item @b{halt} Immediately halt the target
  4569. @item @b{init} Immediately halt the target, and execute the reset-init script
  4570. @end itemize
  4571. @end deffn
  4572. @deffn Command soft_reset_halt
  4573. Requesting target halt and executing a soft reset. This is often used
  4574. when a target cannot be reset and halted. The target, after reset is
  4575. released begins to execute code. OpenOCD attempts to stop the CPU and
  4576. then sets the program counter back to the reset vector. Unfortunately
  4577. the code that was executed may have left the hardware in an unknown
  4578. state.
  4579. @end deffn
  4580. @section I/O Utilities
  4581. These commands are available when
  4582. OpenOCD is built with @option{--enable-ioutil}.
  4583. They are mainly useful on embedded targets,
  4584. notably the ZY1000.
  4585. Hosts with operating systems have complementary tools.
  4586. @emph{Note:} there are several more such commands.
  4587. @deffn Command append_file filename [string]*
  4588. Appends the @var{string} parameters to
  4589. the text file @file{filename}.
  4590. Each string except the last one is followed by one space.
  4591. The last string is followed by a newline.
  4592. @end deffn
  4593. @deffn Command cat filename
  4594. Reads and displays the text file @file{filename}.
  4595. @end deffn
  4596. @deffn Command cp src_filename dest_filename
  4597. Copies contents from the file @file{src_filename}
  4598. into @file{dest_filename}.
  4599. @end deffn
  4600. @deffn Command ip
  4601. @emph{No description provided.}
  4602. @end deffn
  4603. @deffn Command ls
  4604. @emph{No description provided.}
  4605. @end deffn
  4606. @deffn Command mac
  4607. @emph{No description provided.}
  4608. @end deffn
  4609. @deffn Command meminfo
  4610. Display available RAM memory on OpenOCD host.
  4611. Used in OpenOCD regression testing scripts.
  4612. @end deffn
  4613. @deffn Command peek
  4614. @emph{No description provided.}
  4615. @end deffn
  4616. @deffn Command poke
  4617. @emph{No description provided.}
  4618. @end deffn
  4619. @deffn Command rm filename
  4620. @c "rm" has both normal and Jim-level versions??
  4621. Unlinks the file @file{filename}.
  4622. @end deffn
  4623. @deffn Command trunc filename
  4624. Removes all data in the file @file{filename}.
  4625. @end deffn
  4626. @anchor{Memory access}
  4627. @section Memory access commands
  4628. @cindex memory access
  4629. These commands allow accesses of a specific size to the memory
  4630. system. Often these are used to configure the current target in some
  4631. special way. For example - one may need to write certain values to the
  4632. SDRAM controller to enable SDRAM.
  4633. @enumerate
  4634. @item Use the @command{targets} (plural) command
  4635. to change the current target.
  4636. @item In system level scripts these commands are deprecated.
  4637. Please use their TARGET object siblings to avoid making assumptions
  4638. about what TAP is the current target, or about MMU configuration.
  4639. @end enumerate
  4640. @deffn Command mdw [phys] addr [count]
  4641. @deffnx Command mdh [phys] addr [count]
  4642. @deffnx Command mdb [phys] addr [count]
  4643. Display contents of address @var{addr}, as
  4644. 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
  4645. or 8-bit bytes (@command{mdb}).
  4646. When the current target has an MMU which is present and active,
  4647. @var{addr} is interpreted as a virtual address.
  4648. Otherwise, or if the optional @var{phys} flag is specified,
  4649. @var{addr} is interpreted as a physical address.
  4650. If @var{count} is specified, displays that many units.
  4651. (If you want to manipulate the data instead of displaying it,
  4652. see the @code{mem2array} primitives.)
  4653. @end deffn
  4654. @deffn Command mww [phys] addr word
  4655. @deffnx Command mwh [phys] addr halfword
  4656. @deffnx Command mwb [phys] addr byte
  4657. Writes the specified @var{word} (32 bits),
  4658. @var{halfword} (16 bits), or @var{byte} (8-bit) value,
  4659. at the specified address @var{addr}.
  4660. When the current target has an MMU which is present and active,
  4661. @var{addr} is interpreted as a virtual address.
  4662. Otherwise, or if the optional @var{phys} flag is specified,
  4663. @var{addr} is interpreted as a physical address.
  4664. @end deffn
  4665. @anchor{Image access}
  4666. @section Image loading commands
  4667. @cindex image loading
  4668. @cindex image dumping
  4669. @anchor{dump_image}
  4670. @deffn Command {dump_image} filename address size
  4671. Dump @var{size} bytes of target memory starting at @var{address} to the
  4672. binary file named @var{filename}.
  4673. @end deffn
  4674. @deffn Command {fast_load}
  4675. Loads an image stored in memory by @command{fast_load_image} to the
  4676. current target. Must be preceeded by fast_load_image.
  4677. @end deffn
  4678. @deffn Command {fast_load_image} filename address [@option{bin}|@option{ihex}|@option{elf}]
  4679. Normally you should be using @command{load_image} or GDB load. However, for
  4680. testing purposes or when I/O overhead is significant(OpenOCD running on an embedded
  4681. host), storing the image in memory and uploading the image to the target
  4682. can be a way to upload e.g. multiple debug sessions when the binary does not change.
  4683. Arguments are the same as @command{load_image}, but the image is stored in OpenOCD host
  4684. memory, i.e. does not affect target. This approach is also useful when profiling
  4685. target programming performance as I/O and target programming can easily be profiled
  4686. separately.
  4687. @end deffn
  4688. @anchor{load_image}
  4689. @deffn Command {load_image} filename address [@option{bin}|@option{ihex}|@option{elf}]
  4690. Load image from file @var{filename} to target memory at @var{address}.
  4691. The file format may optionally be specified
  4692. (@option{bin}, @option{ihex}, or @option{elf})
  4693. @end deffn
  4694. @deffn Command {test_image} filename [address [@option{bin}|@option{ihex}|@option{elf}]]
  4695. Displays image section sizes and addresses
  4696. as if @var{filename} were loaded into target memory
  4697. starting at @var{address} (defaults to zero).
  4698. The file format may optionally be specified
  4699. (@option{bin}, @option{ihex}, or @option{elf})
  4700. @end deffn
  4701. @deffn Command {verify_image} filename address [@option{bin}|@option{ihex}|@option{elf}]
  4702. Verify @var{filename} against target memory starting at @var{address}.
  4703. The file format may optionally be specified
  4704. (@option{bin}, @option{ihex}, or @option{elf})
  4705. This will first attempt a comparison using a CRC checksum, if this fails it will try a binary compare.
  4706. @end deffn
  4707. @section Breakpoint and Watchpoint commands
  4708. @cindex breakpoint
  4709. @cindex watchpoint
  4710. CPUs often make debug modules accessible through JTAG, with
  4711. hardware support for a handful of code breakpoints and data
  4712. watchpoints.
  4713. In addition, CPUs almost always support software breakpoints.
  4714. @deffn Command {bp} [address len [@option{hw}]]
  4715. With no parameters, lists all active breakpoints.
  4716. Else sets a breakpoint on code execution starting
  4717. at @var{address} for @var{length} bytes.
  4718. This is a software breakpoint, unless @option{hw} is specified
  4719. in which case it will be a hardware breakpoint.
  4720. (@xref{arm9 vector_catch}, or @pxref{xscale vector_catch},
  4721. for similar mechanisms that do not consume hardware breakpoints.)
  4722. @end deffn
  4723. @deffn Command {rbp} address
  4724. Remove the breakpoint at @var{address}.
  4725. @end deffn
  4726. @deffn Command {rwp} address
  4727. Remove data watchpoint on @var{address}
  4728. @end deffn
  4729. @deffn Command {wp} [address len [(@option{r}|@option{w}|@option{a}) [value [mask]]]]
  4730. With no parameters, lists all active watchpoints.
  4731. Else sets a data watchpoint on data from @var{address} for @var{length} bytes.
  4732. The watch point is an "access" watchpoint unless
  4733. the @option{r} or @option{w} parameter is provided,
  4734. defining it as respectively a read or write watchpoint.
  4735. If a @var{value} is provided, that value is used when determining if
  4736. the watchpoint should trigger. The value may be first be masked
  4737. using @var{mask} to mark ``don't care'' fields.
  4738. @end deffn
  4739. @section Misc Commands
  4740. @cindex profiling
  4741. @deffn Command {profile} seconds filename
  4742. Profiling samples the CPU's program counter as quickly as possible,
  4743. which is useful for non-intrusive stochastic profiling.
  4744. Saves up to 10000 sampines in @file{filename} using ``gmon.out'' format.
  4745. @end deffn
  4746. @deffn Command {version}
  4747. Displays a string identifying the version of this OpenOCD server.
  4748. @end deffn
  4749. @deffn Command {virt2phys} virtual_address
  4750. Requests the current target to map the specified @var{virtual_address}
  4751. to its corresponding physical address, and displays the result.
  4752. @end deffn
  4753. @node Architecture and Core Commands
  4754. @chapter Architecture and Core Commands
  4755. @cindex Architecture Specific Commands
  4756. @cindex Core Specific Commands
  4757. Most CPUs have specialized JTAG operations to support debugging.
  4758. OpenOCD packages most such operations in its standard command framework.
  4759. Some of those operations don't fit well in that framework, so they are
  4760. exposed here as architecture or implementation (core) specific commands.
  4761. @anchor{ARM Hardware Tracing}
  4762. @section ARM Hardware Tracing
  4763. @cindex tracing
  4764. @cindex ETM
  4765. @cindex ETB
  4766. CPUs based on ARM cores may include standard tracing interfaces,
  4767. based on an ``Embedded Trace Module'' (ETM) which sends voluminous
  4768. address and data bus trace records to a ``Trace Port''.
  4769. @itemize
  4770. @item
  4771. Development-oriented boards will sometimes provide a high speed
  4772. trace connector for collecting that data, when the particular CPU
  4773. supports such an interface.
  4774. (The standard connector is a 38-pin Mictor, with both JTAG
  4775. and trace port support.)
  4776. Those trace connectors are supported by higher end JTAG adapters
  4777. and some logic analyzer modules; frequently those modules can
  4778. buffer several megabytes of trace data.
  4779. Configuring an ETM coupled to such an external trace port belongs
  4780. in the board-specific configuration file.
  4781. @item
  4782. If the CPU doesn't provide an external interface, it probably
  4783. has an ``Embedded Trace Buffer'' (ETB) on the chip, which is a
  4784. dedicated SRAM. 4KBytes is one common ETB size.
  4785. Configuring an ETM coupled only to an ETB belongs in the CPU-specific
  4786. (target) configuration file, since it works the same on all boards.
  4787. @end itemize
  4788. ETM support in OpenOCD doesn't seem to be widely used yet.
  4789. @quotation Issues
  4790. ETM support may be buggy, and at least some @command{etm config}
  4791. parameters should be detected by asking the ETM for them.
  4792. ETM trigger events could also implement a kind of complex
  4793. hardware breakpoint, much more powerful than the simple
  4794. watchpoint hardware exported by EmbeddedICE modules.
  4795. @emph{Such breakpoints can be triggered even when using the
  4796. dummy trace port driver}.
  4797. It seems like a GDB hookup should be possible,
  4798. as well as tracing only during specific states
  4799. (perhaps @emph{handling IRQ 23} or @emph{calls foo()}).
  4800. There should be GUI tools to manipulate saved trace data and help
  4801. analyse it in conjunction with the source code.
  4802. It's unclear how much of a common interface is shared
  4803. with the current XScale trace support, or should be
  4804. shared with eventual Nexus-style trace module support.
  4805. At this writing (November 2009) only ARM7, ARM9, and ARM11 support
  4806. for ETM modules is available. The code should be able to
  4807. work with some newer cores; but not all of them support
  4808. this original style of JTAG access.
  4809. @end quotation
  4810. @subsection ETM Configuration
  4811. ETM setup is coupled with the trace port driver configuration.
  4812. @deffn {Config Command} {etm config} target width mode clocking driver
  4813. Declares the ETM associated with @var{target}, and associates it
  4814. with a given trace port @var{driver}. @xref{Trace Port Drivers}.
  4815. Several of the parameters must reflect the trace port capabilities,
  4816. which are a function of silicon capabilties (exposed later
  4817. using @command{etm info}) and of what hardware is connected to
  4818. that port (such as an external pod, or ETB).
  4819. The @var{width} must be either 4, 8, or 16,
  4820. except with ETMv3.0 and newer modules which may also
  4821. support 1, 2, 24, 32, 48, and 64 bit widths.
  4822. (With those versions, @command{etm info} also shows whether
  4823. the selected port width and mode are supported.)
  4824. The @var{mode} must be @option{normal}, @option{multiplexed},
  4825. or @option{demultiplexed}.
  4826. The @var{clocking} must be @option{half} or @option{full}.
  4827. @quotation Warning
  4828. With ETMv3.0 and newer, the bits set with the @var{mode} and
  4829. @var{clocking} parameters both control the mode.
  4830. This modified mode does not map to the values supported by
  4831. previous ETM modules, so this syntax is subject to change.
  4832. @end quotation
  4833. @quotation Note
  4834. You can see the ETM registers using the @command{reg} command.
  4835. Not all possible registers are present in every ETM.
  4836. Most of the registers are write-only, and are used to configure
  4837. what CPU activities are traced.
  4838. @end quotation
  4839. @end deffn
  4840. @deffn Command {etm info}
  4841. Displays information about the current target's ETM.
  4842. This includes resource counts from the @code{ETM_CONFIG} register,
  4843. as well as silicon capabilities (except on rather old modules).
  4844. from the @code{ETM_SYS_CONFIG} register.
  4845. @end deffn
  4846. @deffn Command {etm status}
  4847. Displays status of the current target's ETM and trace port driver:
  4848. is the ETM idle, or is it collecting data?
  4849. Did trace data overflow?
  4850. Was it triggered?
  4851. @end deffn
  4852. @deffn Command {etm tracemode} [type context_id_bits cycle_accurate branch_output]
  4853. Displays what data that ETM will collect.
  4854. If arguments are provided, first configures that data.
  4855. When the configuration changes, tracing is stopped
  4856. and any buffered trace data is invalidated.
  4857. @itemize
  4858. @item @var{type} ... describing how data accesses are traced,
  4859. when they pass any ViewData filtering that that was set up.
  4860. The value is one of
  4861. @option{none} (save nothing),
  4862. @option{data} (save data),
  4863. @option{address} (save addresses),
  4864. @option{all} (save data and addresses)
  4865. @item @var{context_id_bits} ... 0, 8, 16, or 32
  4866. @item @var{cycle_accurate} ... @option{enable} or @option{disable}
  4867. cycle-accurate instruction tracing.
  4868. Before ETMv3, enabling this causes much extra data to be recorded.
  4869. @item @var{branch_output} ... @option{enable} or @option{disable}.
  4870. Disable this unless you need to try reconstructing the instruction
  4871. trace stream without an image of the code.
  4872. @end itemize
  4873. @end deffn
  4874. @deffn Command {etm trigger_debug} (@option{enable}|@option{disable})
  4875. Displays whether ETM triggering debug entry (like a breakpoint) is
  4876. enabled or disabled, after optionally modifying that configuration.
  4877. The default behaviour is @option{disable}.
  4878. Any change takes effect after the next @command{etm start}.
  4879. By using script commands to configure ETM registers, you can make the
  4880. processor enter debug state automatically when certain conditions,
  4881. more complex than supported by the breakpoint hardware, happen.
  4882. @end deffn
  4883. @subsection ETM Trace Operation
  4884. After setting up the ETM, you can use it to collect data.
  4885. That data can be exported to files for later analysis.
  4886. It can also be parsed with OpenOCD, for basic sanity checking.
  4887. To configure what is being traced, you will need to write
  4888. various trace registers using @command{reg ETM_*} commands.
  4889. For the definitions of these registers, read ARM publication
  4890. @emph{IHI 0014, ``Embedded Trace Macrocell, Architecture Specification''}.
  4891. Be aware that most of the relevant registers are write-only,
  4892. and that ETM resources are limited. There are only a handful
  4893. of address comparators, data comparators, counters, and so on.
  4894. Examples of scenarios you might arrange to trace include:
  4895. @itemize
  4896. @item Code flow within a function, @emph{excluding} subroutines
  4897. it calls. Use address range comparators to enable tracing
  4898. for instruction access within that function's body.
  4899. @item Code flow within a function, @emph{including} subroutines
  4900. it calls. Use the sequencer and address comparators to activate
  4901. tracing on an ``entered function'' state, then deactivate it by
  4902. exiting that state when the function's exit code is invoked.
  4903. @item Code flow starting at the fifth invocation of a function,
  4904. combining one of the above models with a counter.
  4905. @item CPU data accesses to the registers for a particular device,
  4906. using address range comparators and the ViewData logic.
  4907. @item Such data accesses only during IRQ handling, combining the above
  4908. model with sequencer triggers which on entry and exit to the IRQ handler.
  4909. @item @emph{... more}
  4910. @end itemize
  4911. At this writing, September 2009, there are no Tcl utility
  4912. procedures to help set up any common tracing scenarios.
  4913. @deffn Command {etm analyze}
  4914. Reads trace data into memory, if it wasn't already present.
  4915. Decodes and prints the data that was collected.
  4916. @end deffn
  4917. @deffn Command {etm dump} filename
  4918. Stores the captured trace data in @file{filename}.
  4919. @end deffn
  4920. @deffn Command {etm image} filename [base_address] [type]
  4921. Opens an image file.
  4922. @end deffn
  4923. @deffn Command {etm load} filename
  4924. Loads captured trace data from @file{filename}.
  4925. @end deffn
  4926. @deffn Command {etm start}
  4927. Starts trace data collection.
  4928. @end deffn
  4929. @deffn Command {etm stop}
  4930. Stops trace data collection.
  4931. @end deffn
  4932. @anchor{Trace Port Drivers}
  4933. @subsection Trace Port Drivers
  4934. To use an ETM trace port it must be associated with a driver.
  4935. @deffn {Trace Port Driver} dummy
  4936. Use the @option{dummy} driver if you are configuring an ETM that's
  4937. not connected to anything (on-chip ETB or off-chip trace connector).
  4938. @emph{This driver lets OpenOCD talk to the ETM, but it does not expose
  4939. any trace data collection.}
  4940. @deffn {Config Command} {etm_dummy config} target
  4941. Associates the ETM for @var{target} with a dummy driver.
  4942. @end deffn
  4943. @end deffn
  4944. @deffn {Trace Port Driver} etb
  4945. Use the @option{etb} driver if you are configuring an ETM
  4946. to use on-chip ETB memory.
  4947. @deffn {Config Command} {etb config} target etb_tap
  4948. Associates the ETM for @var{target} with the ETB at @var{etb_tap}.
  4949. You can see the ETB registers using the @command{reg} command.
  4950. @end deffn
  4951. @deffn Command {etb trigger_percent} [percent]
  4952. This displays, or optionally changes, ETB behavior after the
  4953. ETM's configured @emph{trigger} event fires.
  4954. It controls how much more trace data is saved after the (single)
  4955. trace trigger becomes active.
  4956. @itemize
  4957. @item The default corresponds to @emph{trace around} usage,
  4958. recording 50 percent data before the event and the rest
  4959. afterwards.
  4960. @item The minimum value of @var{percent} is 2 percent,
  4961. recording almost exclusively data before the trigger.
  4962. Such extreme @emph{trace before} usage can help figure out
  4963. what caused that event to happen.
  4964. @item The maximum value of @var{percent} is 100 percent,
  4965. recording data almost exclusively after the event.
  4966. This extreme @emph{trace after} usage might help sort out
  4967. how the event caused trouble.
  4968. @end itemize
  4969. @c REVISIT allow "break" too -- enter debug mode.
  4970. @end deffn
  4971. @end deffn
  4972. @deffn {Trace Port Driver} oocd_trace
  4973. This driver isn't available unless OpenOCD was explicitly configured
  4974. with the @option{--enable-oocd_trace} option. You probably don't want
  4975. to configure it unless you've built the appropriate prototype hardware;
  4976. it's @emph{proof-of-concept} software.
  4977. Use the @option{oocd_trace} driver if you are configuring an ETM that's
  4978. connected to an off-chip trace connector.
  4979. @deffn {Config Command} {oocd_trace config} target tty
  4980. Associates the ETM for @var{target} with a trace driver which
  4981. collects data through the serial port @var{tty}.
  4982. @end deffn
  4983. @deffn Command {oocd_trace resync}
  4984. Re-synchronizes with the capture clock.
  4985. @end deffn
  4986. @deffn Command {oocd_trace status}
  4987. Reports whether the capture clock is locked or not.
  4988. @end deffn
  4989. @end deffn
  4990. @section Generic ARM
  4991. @cindex ARM
  4992. These commands should be available on all ARM processors.
  4993. They are available in addition to other core-specific
  4994. commands that may be available.
  4995. @deffn Command {arm core_state} [@option{arm}|@option{thumb}]
  4996. Displays the core_state, optionally changing it to process
  4997. either @option{arm} or @option{thumb} instructions.
  4998. The target may later be resumed in the currently set core_state.
  4999. (Processors may also support the Jazelle state, but
  5000. that is not currently supported in OpenOCD.)
  5001. @end deffn
  5002. @deffn Command {arm disassemble} address [count [@option{thumb}]]
  5003. @cindex disassemble
  5004. Disassembles @var{count} instructions starting at @var{address}.
  5005. If @var{count} is not specified, a single instruction is disassembled.
  5006. If @option{thumb} is specified, or the low bit of the address is set,
  5007. Thumb2 (mixed 16/32-bit) instructions are used;
  5008. else ARM (32-bit) instructions are used.
  5009. (Processors may also support the Jazelle state, but
  5010. those instructions are not currently understood by OpenOCD.)
  5011. Note that all Thumb instructions are Thumb2 instructions,
  5012. so older processors (without Thumb2 support) will still
  5013. see correct disassembly of Thumb code.
  5014. Also, ThumbEE opcodes are the same as Thumb2,
  5015. with a handful of exceptions.
  5016. ThumbEE disassembly currently has no explicit support.
  5017. @end deffn
  5018. @deffn Command {arm mcr} pX op1 CRn CRm op2 value
  5019. Write @var{value} to a coprocessor @var{pX} register
  5020. passing parameters @var{CRn},
  5021. @var{CRm}, opcodes @var{opc1} and @var{opc2},
  5022. and using the MCR instruction.
  5023. (Parameter sequence matches the ARM instruction, but omits
  5024. an ARM register.)
  5025. @end deffn
  5026. @deffn Command {arm mrc} pX coproc op1 CRn CRm op2
  5027. Read a coprocessor @var{pX} register passing parameters @var{CRn},
  5028. @var{CRm}, opcodes @var{opc1} and @var{opc2},
  5029. and the MRC instruction.
  5030. Returns the result so it can be manipulated by Jim scripts.
  5031. (Parameter sequence matches the ARM instruction, but omits
  5032. an ARM register.)
  5033. @end deffn
  5034. @deffn Command {arm reg}
  5035. Display a table of all banked core registers, fetching the current value from every
  5036. core mode if necessary.
  5037. @end deffn
  5038. @section ARMv4 and ARMv5 Architecture
  5039. @cindex ARMv4
  5040. @cindex ARMv5
  5041. The ARMv4 and ARMv5 architectures are widely used in embedded systems,
  5042. and introduced core parts of the instruction set in use today.
  5043. That includes the Thumb instruction set, introduced in the ARMv4T
  5044. variant.
  5045. @subsection ARM7 and ARM9 specific commands
  5046. @cindex ARM7
  5047. @cindex ARM9
  5048. These commands are specific to ARM7 and ARM9 cores, like ARM7TDMI, ARM720T,
  5049. ARM9TDMI, ARM920T or ARM926EJ-S.
  5050. They are available in addition to the ARM commands,
  5051. and any other core-specific commands that may be available.
  5052. @deffn Command {arm7_9 dbgrq} [@option{enable}|@option{disable}]
  5053. Displays the value of the flag controlling use of the
  5054. the EmbeddedIce DBGRQ signal to force entry into debug mode,
  5055. instead of breakpoints.
  5056. If a boolean parameter is provided, first assigns that flag.
  5057. This should be
  5058. safe for all but ARM7TDMI-S cores (like NXP LPC).
  5059. This feature is enabled by default on most ARM9 cores,
  5060. including ARM9TDMI, ARM920T, and ARM926EJ-S.
  5061. @end deffn
  5062. @deffn Command {arm7_9 dcc_downloads} [@option{enable}|@option{disable}]
  5063. @cindex DCC
  5064. Displays the value of the flag controlling use of the debug communications
  5065. channel (DCC) to write larger (>128 byte) amounts of memory.
  5066. If a boolean parameter is provided, first assigns that flag.
  5067. DCC downloads offer a huge speed increase, but might be
  5068. unsafe, especially with targets running at very low speeds. This command was introduced
  5069. with OpenOCD rev. 60, and requires a few bytes of working area.
  5070. @end deffn
  5071. @anchor{arm7_9 fast_memory_access}
  5072. @deffn Command {arm7_9 fast_memory_access} [@option{enable}|@option{disable}]
  5073. Displays the value of the flag controlling use of memory writes and reads
  5074. that don't check completion of the operation.
  5075. If a boolean parameter is provided, first assigns that flag.
  5076. This provides a huge speed increase, especially with USB JTAG
  5077. cables (FT2232), but might be unsafe if used with targets running at very low
  5078. speeds, like the 32kHz startup clock of an AT91RM9200.
  5079. @end deffn
  5080. @deffn Command {arm7_9 semihosting} [@option{enable}|@option{disable}]
  5081. @cindex ARM semihosting
  5082. Display status of semihosting, after optionally changing that status.
  5083. Semihosting allows for code executing on an ARM target to use the
  5084. I/O facilities on the host computer i.e. the system where OpenOCD
  5085. is running. The target application must be linked against a library
  5086. implementing the ARM semihosting convention that forwards operation
  5087. requests by using a special SVC instruction that is trapped at the
  5088. Supervisor Call vector by OpenOCD.
  5089. @end deffn
  5090. @subsection ARM720T specific commands
  5091. @cindex ARM720T
  5092. These commands are available to ARM720T based CPUs,
  5093. which are implementations of the ARMv4T architecture
  5094. based on the ARM7TDMI-S integer core.
  5095. They are available in addition to the ARM and ARM7/ARM9 commands.
  5096. @deffn Command {arm720t cp15} opcode [value]
  5097. @emph{DEPRECATED -- avoid using this.
  5098. Use the @command{arm mrc} or @command{arm mcr} commands instead.}
  5099. Display cp15 register returned by the ARM instruction @var{opcode};
  5100. else if a @var{value} is provided, that value is written to that register.
  5101. The @var{opcode} should be the value of either an MRC or MCR instruction.
  5102. @end deffn
  5103. @subsection ARM9 specific commands
  5104. @cindex ARM9
  5105. ARM9-family cores are built around ARM9TDMI or ARM9E (including ARM9EJS)
  5106. integer processors.
  5107. Such cores include the ARM920T, ARM926EJ-S, and ARM966.
  5108. @c 9-june-2009: tried this on arm920t, it didn't work.
  5109. @c no-params always lists nothing caught, and that's how it acts.
  5110. @c 23-oct-2009: doesn't work _consistently_ ... as if the ICE
  5111. @c versions have different rules about when they commit writes.
  5112. @anchor{arm9 vector_catch}
  5113. @deffn Command {arm9 vector_catch} [@option{all}|@option{none}|list]
  5114. @cindex vector_catch
  5115. Vector Catch hardware provides a sort of dedicated breakpoint
  5116. for hardware events such as reset, interrupt, and abort.
  5117. You can use this to conserve normal breakpoint resources,
  5118. so long as you're not concerned with code that branches directly
  5119. to those hardware vectors.
  5120. This always finishes by listing the current configuration.
  5121. If parameters are provided, it first reconfigures the
  5122. vector catch hardware to intercept
  5123. @option{all} of the hardware vectors,
  5124. @option{none} of them,
  5125. or a list with one or more of the following:
  5126. @option{reset} @option{undef} @option{swi} @option{pabt} @option{dabt}
  5127. @option{irq} @option{fiq}.
  5128. @end deffn
  5129. @subsection ARM920T specific commands
  5130. @cindex ARM920T
  5131. These commands are available to ARM920T based CPUs,
  5132. which are implementations of the ARMv4T architecture
  5133. built using the ARM9TDMI integer core.
  5134. They are available in addition to the ARM, ARM7/ARM9,
  5135. and ARM9 commands.
  5136. @deffn Command {arm920t cache_info}
  5137. Print information about the caches found. This allows to see whether your target
  5138. is an ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
  5139. @end deffn
  5140. @deffn Command {arm920t cp15} regnum [value]
  5141. Display cp15 register @var{regnum};
  5142. else if a @var{value} is provided, that value is written to that register.
  5143. This uses "physical access" and the register number is as
  5144. shown in bits 38..33 of table 9-9 in the ARM920T TRM.
  5145. (Not all registers can be written.)
  5146. @end deffn
  5147. @deffn Command {arm920t cp15i} opcode [value [address]]
  5148. @emph{DEPRECATED -- avoid using this.
  5149. Use the @command{arm mrc} or @command{arm mcr} commands instead.}
  5150. Interpreted access using ARM instruction @var{opcode}, which should
  5151. be the value of either an MRC or MCR instruction
  5152. (as shown tables 9-11, 9-12, and 9-13 in the ARM920T TRM).
  5153. If no @var{value} is provided, the result is displayed.
  5154. Else if that value is written using the specified @var{address},
  5155. or using zero if no other address is provided.
  5156. @end deffn
  5157. @deffn Command {arm920t read_cache} filename
  5158. Dump the content of ICache and DCache to a file named @file{filename}.
  5159. @end deffn
  5160. @deffn Command {arm920t read_mmu} filename
  5161. Dump the content of the ITLB and DTLB to a file named @file{filename}.
  5162. @end deffn
  5163. @subsection ARM926ej-s specific commands
  5164. @cindex ARM926ej-s
  5165. These commands are available to ARM926ej-s based CPUs,
  5166. which are implementations of the ARMv5TEJ architecture
  5167. based on the ARM9EJ-S integer core.
  5168. They are available in addition to the ARM, ARM7/ARM9,
  5169. and ARM9 commands.
  5170. The Feroceon cores also support these commands, although
  5171. they are not built from ARM926ej-s designs.
  5172. @deffn Command {arm926ejs cache_info}
  5173. Print information about the caches found.
  5174. @end deffn
  5175. @subsection ARM966E specific commands
  5176. @cindex ARM966E
  5177. These commands are available to ARM966 based CPUs,
  5178. which are implementations of the ARMv5TE architecture.
  5179. They are available in addition to the ARM, ARM7/ARM9,
  5180. and ARM9 commands.
  5181. @deffn Command {arm966e cp15} regnum [value]
  5182. Display cp15 register @var{regnum};
  5183. else if a @var{value} is provided, that value is written to that register.
  5184. The six bit @var{regnum} values are bits 37..32 from table 7-2 of the
  5185. ARM966E-S TRM.
  5186. There is no current control over bits 31..30 from that table,
  5187. as required for BIST support.
  5188. @end deffn
  5189. @subsection XScale specific commands
  5190. @cindex XScale
  5191. Some notes about the debug implementation on the XScale CPUs:
  5192. The XScale CPU provides a special debug-only mini-instruction cache
  5193. (mini-IC) in which exception vectors and target-resident debug handler
  5194. code are placed by OpenOCD. In order to get access to the CPU, OpenOCD
  5195. must point vector 0 (the reset vector) to the entry of the debug
  5196. handler. However, this means that the complete first cacheline in the
  5197. mini-IC is marked valid, which makes the CPU fetch all exception
  5198. handlers from the mini-IC, ignoring the code in RAM.
  5199. OpenOCD currently does not sync the mini-IC entries with the RAM
  5200. contents (which would fail anyway while the target is running), so
  5201. the user must provide appropriate values using the @code{xscale
  5202. vector_table} command.
  5203. It is recommended to place a pc-relative indirect branch in the vector
  5204. table, and put the branch destination somewhere in memory. Doing so
  5205. makes sure the code in the vector table stays constant regardless of
  5206. code layout in memory:
  5207. @example
  5208. _vectors:
  5209. ldr pc,[pc,#0x100-8]
  5210. ldr pc,[pc,#0x100-8]
  5211. ldr pc,[pc,#0x100-8]
  5212. ldr pc,[pc,#0x100-8]
  5213. ldr pc,[pc,#0x100-8]
  5214. ldr pc,[pc,#0x100-8]
  5215. ldr pc,[pc,#0x100-8]
  5216. ldr pc,[pc,#0x100-8]
  5217. .org 0x100
  5218. .long real_reset_vector
  5219. .long real_ui_handler
  5220. .long real_swi_handler
  5221. .long real_pf_abort
  5222. .long real_data_abort
  5223. .long 0 /* unused */
  5224. .long real_irq_handler
  5225. .long real_fiq_handler
  5226. @end example
  5227. The debug handler must be placed somewhere in the address space using
  5228. the @code{xscale debug_handler} command. The allowed locations for the
  5229. debug handler are either (0x800 - 0x1fef800) or (0xfe000800 -
  5230. 0xfffff800). The default value is 0xfe000800.
  5231. These commands are available to XScale based CPUs,
  5232. which are implementations of the ARMv5TE architecture.
  5233. @deffn Command {xscale analyze_trace}
  5234. Displays the contents of the trace buffer.
  5235. @end deffn
  5236. @deffn Command {xscale cache_clean_address} address
  5237. Changes the address used when cleaning the data cache.
  5238. @end deffn
  5239. @deffn Command {xscale cache_info}
  5240. Displays information about the CPU caches.
  5241. @end deffn
  5242. @deffn Command {xscale cp15} regnum [value]
  5243. Display cp15 register @var{regnum};
  5244. else if a @var{value} is provided, that value is written to that register.
  5245. @end deffn
  5246. @deffn Command {xscale debug_handler} target address
  5247. Changes the address used for the specified target's debug handler.
  5248. @end deffn
  5249. @deffn Command {xscale dcache} [@option{enable}|@option{disable}]
  5250. Enables or disable the CPU's data cache.
  5251. @end deffn
  5252. @deffn Command {xscale dump_trace} filename
  5253. Dumps the raw contents of the trace buffer to @file{filename}.
  5254. @end deffn
  5255. @deffn Command {xscale icache} [@option{enable}|@option{disable}]
  5256. Enables or disable the CPU's instruction cache.
  5257. @end deffn
  5258. @deffn Command {xscale mmu} [@option{enable}|@option{disable}]
  5259. Enables or disable the CPU's memory management unit.
  5260. @end deffn
  5261. @deffn Command {xscale trace_buffer} [@option{enable}|@option{disable} [@option{fill} [n] | @option{wrap}]]
  5262. Displays the trace buffer status, after optionally
  5263. enabling or disabling the trace buffer
  5264. and modifying how it is emptied.
  5265. @end deffn
  5266. @deffn Command {xscale trace_image} filename [offset [type]]
  5267. Opens a trace image from @file{filename}, optionally rebasing
  5268. its segment addresses by @var{offset}.
  5269. The image @var{type} may be one of
  5270. @option{bin} (binary), @option{ihex} (Intel hex),
  5271. @option{elf} (ELF file), @option{s19} (Motorola s19),
  5272. @option{mem}, or @option{builder}.
  5273. @end deffn
  5274. @anchor{xscale vector_catch}
  5275. @deffn Command {xscale vector_catch} [mask]
  5276. @cindex vector_catch
  5277. Display a bitmask showing the hardware vectors to catch.
  5278. If the optional parameter is provided, first set the bitmask to that value.
  5279. The mask bits correspond with bit 16..23 in the DCSR:
  5280. @example
  5281. 0x01 Trap Reset
  5282. 0x02 Trap Undefined Instructions
  5283. 0x04 Trap Software Interrupt
  5284. 0x08 Trap Prefetch Abort
  5285. 0x10 Trap Data Abort
  5286. 0x20 reserved
  5287. 0x40 Trap IRQ
  5288. 0x80 Trap FIQ
  5289. @end example
  5290. @end deffn
  5291. @anchor{xscale vector_table}
  5292. @deffn Command {xscale vector_table} [(@option{low}|@option{high}) index value]
  5293. @cindex vector_table
  5294. Set an entry in the mini-IC vector table. There are two tables: one for
  5295. low vectors (at 0x00000000), and one for high vectors (0xFFFF0000), each
  5296. holding the 8 exception vectors. @var{index} can be 1-7, because vector 0
  5297. points to the debug handler entry and can not be overwritten.
  5298. @var{value} holds the 32-bit opcode that is placed in the mini-IC.
  5299. Without arguments, the current settings are displayed.
  5300. @end deffn
  5301. @section ARMv6 Architecture
  5302. @cindex ARMv6
  5303. @subsection ARM11 specific commands
  5304. @cindex ARM11
  5305. @deffn Command {arm11 memwrite burst} [@option{enable}|@option{disable}]
  5306. Displays the value of the memwrite burst-enable flag,
  5307. which is enabled by default.
  5308. If a boolean parameter is provided, first assigns that flag.
  5309. Burst writes are only used for memory writes larger than 1 word.
  5310. They improve performance by assuming that the CPU has read each data
  5311. word over JTAG and completed its write before the next word arrives,
  5312. instead of polling for a status flag to verify that completion.
  5313. This is usually safe, because JTAG runs much slower than the CPU.
  5314. @end deffn
  5315. @deffn Command {arm11 memwrite error_fatal} [@option{enable}|@option{disable}]
  5316. Displays the value of the memwrite error_fatal flag,
  5317. which is enabled by default.
  5318. If a boolean parameter is provided, first assigns that flag.
  5319. When set, certain memory write errors cause earlier transfer termination.
  5320. @end deffn
  5321. @deffn Command {arm11 step_irq_enable} [@option{enable}|@option{disable}]
  5322. Displays the value of the flag controlling whether
  5323. IRQs are enabled during single stepping;
  5324. they are disabled by default.
  5325. If a boolean parameter is provided, first assigns that.
  5326. @end deffn
  5327. @deffn Command {arm11 vcr} [value]
  5328. @cindex vector_catch
  5329. Displays the value of the @emph{Vector Catch Register (VCR)},
  5330. coprocessor 14 register 7.
  5331. If @var{value} is defined, first assigns that.
  5332. Vector Catch hardware provides dedicated breakpoints
  5333. for certain hardware events.
  5334. The specific bit values are core-specific (as in fact is using
  5335. coprocessor 14 register 7 itself) but all current ARM11
  5336. cores @emph{except the ARM1176} use the same six bits.
  5337. @end deffn
  5338. @section ARMv7 Architecture
  5339. @cindex ARMv7
  5340. @subsection ARMv7 Debug Access Port (DAP) specific commands
  5341. @cindex Debug Access Port
  5342. @cindex DAP
  5343. These commands are specific to ARM architecture v7 Debug Access Port (DAP),
  5344. included on Cortex-M3 and Cortex-A8 systems.
  5345. They are available in addition to other core-specific commands that may be available.
  5346. @deffn Command {dap apid} [num]
  5347. Displays ID register from AP @var{num},
  5348. defaulting to the currently selected AP.
  5349. @end deffn
  5350. @deffn Command {dap apsel} [num]
  5351. Select AP @var{num}, defaulting to 0.
  5352. @end deffn
  5353. @deffn Command {dap baseaddr} [num]
  5354. Displays debug base address from MEM-AP @var{num},
  5355. defaulting to the currently selected AP.
  5356. @end deffn
  5357. @deffn Command {dap info} [num]
  5358. Displays the ROM table for MEM-AP @var{num},
  5359. defaulting to the currently selected AP.
  5360. @end deffn
  5361. @deffn Command {dap memaccess} [value]
  5362. Displays the number of extra tck cycles in the JTAG idle to use for MEM-AP
  5363. memory bus access [0-255], giving additional time to respond to reads.
  5364. If @var{value} is defined, first assigns that.
  5365. @end deffn
  5366. @subsection Cortex-M3 specific commands
  5367. @cindex Cortex-M3
  5368. @deffn Command {cortex_m3 disassemble} address [count]
  5369. @cindex disassemble
  5370. Disassembles @var{count} Thumb2 instructions starting at @var{address}.
  5371. If @var{count} is not specified, a single instruction is disassembled.
  5372. @end deffn
  5373. @deffn Command {cortex_m3 maskisr} (@option{on}|@option{off})
  5374. Control masking (disabling) interrupts during target step/resume.
  5375. @end deffn
  5376. @deffn Command {cortex_m3 vector_catch} [@option{all}|@option{none}|list]
  5377. @cindex vector_catch
  5378. Vector Catch hardware provides dedicated breakpoints
  5379. for certain hardware events.
  5380. Parameters request interception of
  5381. @option{all} of these hardware event vectors,
  5382. @option{none} of them,
  5383. or one or more of the following:
  5384. @option{hard_err} for a HardFault exception;
  5385. @option{mm_err} for a MemManage exception;
  5386. @option{bus_err} for a BusFault exception;
  5387. @option{irq_err},
  5388. @option{state_err},
  5389. @option{chk_err}, or
  5390. @option{nocp_err} for various UsageFault exceptions; or
  5391. @option{reset}.
  5392. If NVIC setup code does not enable them,
  5393. MemManage, BusFault, and UsageFault exceptions
  5394. are mapped to HardFault.
  5395. UsageFault checks for
  5396. divide-by-zero and unaligned access
  5397. must also be explicitly enabled.
  5398. This finishes by listing the current vector catch configuration.
  5399. @end deffn
  5400. @anchor{Software Debug Messages and Tracing}
  5401. @section Software Debug Messages and Tracing
  5402. @cindex Linux-ARM DCC support
  5403. @cindex tracing
  5404. @cindex libdcc
  5405. @cindex DCC
  5406. OpenOCD can process certain requests from target software, when
  5407. the target uses appropriate libraries.
  5408. The most powerful mechanism is semihosting, but there is also
  5409. a lighter weight mechanism using only the DCC channel.
  5410. Currently @command{target_request debugmsgs}
  5411. is supported only for @option{arm7_9} and @option{cortex_m3} cores.
  5412. These messages are received as part of target polling, so
  5413. you need to have @command{poll on} active to receive them.
  5414. They are intrusive in that they will affect program execution
  5415. times. If that is a problem, @pxref{ARM Hardware Tracing}.
  5416. See @file{libdcc} in the contrib dir for more details.
  5417. In addition to sending strings, characters, and
  5418. arrays of various size integers from the target,
  5419. @file{libdcc} also exports a software trace point mechanism.
  5420. The target being debugged may
  5421. issue trace messages which include a 24-bit @dfn{trace point} number.
  5422. Trace point support includes two distinct mechanisms,
  5423. each supported by a command:
  5424. @itemize
  5425. @item @emph{History} ... A circular buffer of trace points
  5426. can be set up, and then displayed at any time.
  5427. This tracks where code has been, which can be invaluable in
  5428. finding out how some fault was triggered.
  5429. The buffer may overflow, since it collects records continuously.
  5430. It may be useful to use some of the 24 bits to represent a
  5431. particular event, and other bits to hold data.
  5432. @item @emph{Counting} ... An array of counters can be set up,
  5433. and then displayed at any time.
  5434. This can help establish code coverage and identify hot spots.
  5435. The array of counters is directly indexed by the trace point
  5436. number, so trace points with higher numbers are not counted.
  5437. @end itemize
  5438. Linux-ARM kernels have a ``Kernel low-level debugging
  5439. via EmbeddedICE DCC channel'' option (CONFIG_DEBUG_ICEDCC,
  5440. depends on CONFIG_DEBUG_LL) which uses this mechanism to
  5441. deliver messages before a serial console can be activated.
  5442. This is not the same format used by @file{libdcc}.
  5443. Other software, such as the U-Boot boot loader, sometimes
  5444. does the same thing.
  5445. @deffn Command {target_request debugmsgs} [@option{enable}|@option{disable}|@option{charmsg}]
  5446. Displays current handling of target DCC message requests.
  5447. These messages may be sent to the debugger while the target is running.
  5448. The optional @option{enable} and @option{charmsg} parameters
  5449. both enable the messages, while @option{disable} disables them.
  5450. With @option{charmsg} the DCC words each contain one character,
  5451. as used by Linux with CONFIG_DEBUG_ICEDCC;
  5452. otherwise the libdcc format is used.
  5453. @end deffn
  5454. @deffn Command {trace history} [@option{clear}|count]
  5455. With no parameter, displays all the trace points that have triggered
  5456. in the order they triggered.
  5457. With the parameter @option{clear}, erases all current trace history records.
  5458. With a @var{count} parameter, allocates space for that many
  5459. history records.
  5460. @end deffn
  5461. @deffn Command {trace point} [@option{clear}|identifier]
  5462. With no parameter, displays all trace point identifiers and how many times
  5463. they have been triggered.
  5464. With the parameter @option{clear}, erases all current trace point counters.
  5465. With a numeric @var{identifier} parameter, creates a new a trace point counter
  5466. and associates it with that identifier.
  5467. @emph{Important:} The identifier and the trace point number
  5468. are not related except by this command.
  5469. These trace point numbers always start at zero (from server startup,
  5470. or after @command{trace point clear}) and count up from there.
  5471. @end deffn
  5472. @node JTAG Commands
  5473. @chapter JTAG Commands
  5474. @cindex JTAG Commands
  5475. Most general purpose JTAG commands have been presented earlier.
  5476. (@xref{JTAG Speed}, @ref{Reset Configuration}, and @ref{TAP Declaration}.)
  5477. Lower level JTAG commands, as presented here,
  5478. may be needed to work with targets which require special
  5479. attention during operations such as reset or initialization.
  5480. To use these commands you will need to understand some
  5481. of the basics of JTAG, including:
  5482. @itemize @bullet
  5483. @item A JTAG scan chain consists of a sequence of individual TAP
  5484. devices such as a CPUs.
  5485. @item Control operations involve moving each TAP through the same
  5486. standard state machine (in parallel)
  5487. using their shared TMS and clock signals.
  5488. @item Data transfer involves shifting data through the chain of
  5489. instruction or data registers of each TAP, writing new register values
  5490. while the reading previous ones.
  5491. @item Data register sizes are a function of the instruction active in
  5492. a given TAP, while instruction register sizes are fixed for each TAP.
  5493. All TAPs support a BYPASS instruction with a single bit data register.
  5494. @item The way OpenOCD differentiates between TAP devices is by
  5495. shifting different instructions into (and out of) their instruction
  5496. registers.
  5497. @end itemize
  5498. @section Low Level JTAG Commands
  5499. These commands are used by developers who need to access
  5500. JTAG instruction or data registers, possibly controlling
  5501. the order of TAP state transitions.
  5502. If you're not debugging OpenOCD internals, or bringing up a
  5503. new JTAG adapter or a new type of TAP device (like a CPU or
  5504. JTAG router), you probably won't need to use these commands.
  5505. @deffn Command {drscan} tap [numbits value]+ [@option{-endstate} tap_state]
  5506. Loads the data register of @var{tap} with a series of bit fields
  5507. that specify the entire register.
  5508. Each field is @var{numbits} bits long with
  5509. a numeric @var{value} (hexadecimal encouraged).
  5510. The return value holds the original value of each
  5511. of those fields.
  5512. For example, a 38 bit number might be specified as one
  5513. field of 32 bits then one of 6 bits.
  5514. @emph{For portability, never pass fields which are more
  5515. than 32 bits long. Many OpenOCD implementations do not
  5516. support 64-bit (or larger) integer values.}
  5517. All TAPs other than @var{tap} must be in BYPASS mode.
  5518. The single bit in their data registers does not matter.
  5519. When @var{tap_state} is specified, the JTAG state machine is left
  5520. in that state.
  5521. For example @sc{drpause} might be specified, so that more
  5522. instructions can be issued before re-entering the @sc{run/idle} state.
  5523. If the end state is not specified, the @sc{run/idle} state is entered.
  5524. @quotation Warning
  5525. OpenOCD does not record information about data register lengths,
  5526. so @emph{it is important that you get the bit field lengths right}.
  5527. Remember that different JTAG instructions refer to different
  5528. data registers, which may have different lengths.
  5529. Moreover, those lengths may not be fixed;
  5530. the SCAN_N instruction can change the length of
  5531. the register accessed by the INTEST instruction
  5532. (by connecting a different scan chain).
  5533. @end quotation
  5534. @end deffn
  5535. @deffn Command {flush_count}
  5536. Returns the number of times the JTAG queue has been flushed.
  5537. This may be used for performance tuning.
  5538. For example, flushing a queue over USB involves a
  5539. minimum latency, often several milliseconds, which does
  5540. not change with the amount of data which is written.
  5541. You may be able to identify performance problems by finding
  5542. tasks which waste bandwidth by flushing small transfers too often,
  5543. instead of batching them into larger operations.
  5544. @end deffn
  5545. @deffn Command {irscan} [tap instruction]+ [@option{-endstate} tap_state]
  5546. For each @var{tap} listed, loads the instruction register
  5547. with its associated numeric @var{instruction}.
  5548. (The number of bits in that instruction may be displayed
  5549. using the @command{scan_chain} command.)
  5550. For other TAPs, a BYPASS instruction is loaded.
  5551. When @var{tap_state} is specified, the JTAG state machine is left
  5552. in that state.
  5553. For example @sc{irpause} might be specified, so the data register
  5554. can be loaded before re-entering the @sc{run/idle} state.
  5555. If the end state is not specified, the @sc{run/idle} state is entered.
  5556. @quotation Note
  5557. OpenOCD currently supports only a single field for instruction
  5558. register values, unlike data register values.
  5559. For TAPs where the instruction register length is more than 32 bits,
  5560. portable scripts currently must issue only BYPASS instructions.
  5561. @end quotation
  5562. @end deffn
  5563. @deffn Command {jtag_reset} trst srst
  5564. Set values of reset signals.
  5565. The @var{trst} and @var{srst} parameter values may be
  5566. @option{0}, indicating that reset is inactive (pulled or driven high),
  5567. or @option{1}, indicating it is active (pulled or driven low).
  5568. The @command{reset_config} command should already have been used
  5569. to configure how the board and JTAG adapter treat these two
  5570. signals, and to say if either signal is even present.
  5571. @xref{Reset Configuration}.
  5572. Note that TRST is specially handled.
  5573. It actually signifies JTAG's @sc{reset} state.
  5574. So if the board doesn't support the optional TRST signal,
  5575. or it doesn't support it along with the specified SRST value,
  5576. JTAG reset is triggered with TMS and TCK signals
  5577. instead of the TRST signal.
  5578. And no matter how that JTAG reset is triggered, once
  5579. the scan chain enters @sc{reset} with TRST inactive,
  5580. TAP @code{post-reset} events are delivered to all TAPs
  5581. with handlers for that event.
  5582. @end deffn
  5583. @deffn Command {pathmove} start_state [next_state ...]
  5584. Start by moving to @var{start_state}, which
  5585. must be one of the @emph{stable} states.
  5586. Unless it is the only state given, this will often be the
  5587. current state, so that no TCK transitions are needed.
  5588. Then, in a series of single state transitions
  5589. (conforming to the JTAG state machine) shift to
  5590. each @var{next_state} in sequence, one per TCK cycle.
  5591. The final state must also be stable.
  5592. @end deffn
  5593. @deffn Command {runtest} @var{num_cycles}
  5594. Move to the @sc{run/idle} state, and execute at least
  5595. @var{num_cycles} of the JTAG clock (TCK).
  5596. Instructions often need some time
  5597. to execute before they take effect.
  5598. @end deffn
  5599. @c tms_sequence (short|long)
  5600. @c ... temporary, debug-only, other than USBprog bug workaround...
  5601. @deffn Command {verify_ircapture} (@option{enable}|@option{disable})
  5602. Verify values captured during @sc{ircapture} and returned
  5603. during IR scans. Default is enabled, but this can be
  5604. overridden by @command{verify_jtag}.
  5605. This flag is ignored when validating JTAG chain configuration.
  5606. @end deffn
  5607. @deffn Command {verify_jtag} (@option{enable}|@option{disable})
  5608. Enables verification of DR and IR scans, to help detect
  5609. programming errors. For IR scans, @command{verify_ircapture}
  5610. must also be enabled.
  5611. Default is enabled.
  5612. @end deffn
  5613. @section TAP state names
  5614. @cindex TAP state names
  5615. The @var{tap_state} names used by OpenOCD in the @command{drscan},
  5616. @command{irscan}, and @command{pathmove} commands are the same
  5617. as those used in SVF boundary scan documents, except that
  5618. SVF uses @sc{idle} instead of @sc{run/idle}.
  5619. @itemize @bullet
  5620. @item @b{RESET} ... @emph{stable} (with TMS high);
  5621. acts as if TRST were pulsed
  5622. @item @b{RUN/IDLE} ... @emph{stable}; don't assume this always means IDLE
  5623. @item @b{DRSELECT}
  5624. @item @b{DRCAPTURE}
  5625. @item @b{DRSHIFT} ... @emph{stable}; TDI/TDO shifting
  5626. through the data register
  5627. @item @b{DREXIT1}
  5628. @item @b{DRPAUSE} ... @emph{stable}; data register ready
  5629. for update or more shifting
  5630. @item @b{DREXIT2}
  5631. @item @b{DRUPDATE}
  5632. @item @b{IRSELECT}
  5633. @item @b{IRCAPTURE}
  5634. @item @b{IRSHIFT} ... @emph{stable}; TDI/TDO shifting
  5635. through the instruction register
  5636. @item @b{IREXIT1}
  5637. @item @b{IRPAUSE} ... @emph{stable}; instruction register ready
  5638. for update or more shifting
  5639. @item @b{IREXIT2}
  5640. @item @b{IRUPDATE}
  5641. @end itemize
  5642. Note that only six of those states are fully ``stable'' in the
  5643. face of TMS fixed (low except for @sc{reset})
  5644. and a free-running JTAG clock. For all the
  5645. others, the next TCK transition changes to a new state.
  5646. @itemize @bullet
  5647. @item From @sc{drshift} and @sc{irshift}, clock transitions will
  5648. produce side effects by changing register contents. The values
  5649. to be latched in upcoming @sc{drupdate} or @sc{irupdate} states
  5650. may not be as expected.
  5651. @item @sc{run/idle}, @sc{drpause}, and @sc{irpause} are reasonable
  5652. choices after @command{drscan} or @command{irscan} commands,
  5653. since they are free of JTAG side effects.
  5654. @item @sc{run/idle} may have side effects that appear at non-JTAG
  5655. levels, such as advancing the ARM9E-S instruction pipeline.
  5656. Consult the documentation for the TAP(s) you are working with.
  5657. @end itemize
  5658. @node Boundary Scan Commands
  5659. @chapter Boundary Scan Commands
  5660. One of the original purposes of JTAG was to support
  5661. boundary scan based hardware testing.
  5662. Although its primary focus is to support On-Chip Debugging,
  5663. OpenOCD also includes some boundary scan commands.
  5664. @section SVF: Serial Vector Format
  5665. @cindex Serial Vector Format
  5666. @cindex SVF
  5667. The Serial Vector Format, better known as @dfn{SVF}, is a
  5668. way to represent JTAG test patterns in text files.
  5669. OpenOCD supports running such test files.
  5670. @deffn Command {svf} filename [@option{quiet}]
  5671. This issues a JTAG reset (Test-Logic-Reset) and then
  5672. runs the SVF script from @file{filename}.
  5673. Unless the @option{quiet} option is specified,
  5674. each command is logged before it is executed.
  5675. @end deffn
  5676. @section XSVF: Xilinx Serial Vector Format
  5677. @cindex Xilinx Serial Vector Format
  5678. @cindex XSVF
  5679. The Xilinx Serial Vector Format, better known as @dfn{XSVF}, is a
  5680. binary representation of SVF which is optimized for use with
  5681. Xilinx devices.
  5682. OpenOCD supports running such test files.
  5683. @quotation Important
  5684. Not all XSVF commands are supported.
  5685. @end quotation
  5686. @deffn Command {xsvf} (tapname|@option{plain}) filename [@option{virt2}] [@option{quiet}]
  5687. This issues a JTAG reset (Test-Logic-Reset) and then
  5688. runs the XSVF script from @file{filename}.
  5689. When a @var{tapname} is specified, the commands are directed at
  5690. that TAP.
  5691. When @option{virt2} is specified, the @sc{xruntest} command counts
  5692. are interpreted as TCK cycles instead of microseconds.
  5693. Unless the @option{quiet} option is specified,
  5694. messages are logged for comments and some retries.
  5695. @end deffn
  5696. The OpenOCD sources also include two utility scripts
  5697. for working with XSVF; they are not currently installed
  5698. after building the software.
  5699. You may find them useful:
  5700. @itemize
  5701. @item @emph{svf2xsvf} ... converts SVF files into the extended XSVF
  5702. syntax understood by the @command{xsvf} command; see notes below.
  5703. @item @emph{xsvfdump} ... converts XSVF files into a text output format;
  5704. understands the OpenOCD extensions.
  5705. @end itemize
  5706. The input format accepts a handful of non-standard extensions.
  5707. These include three opcodes corresponding to SVF extensions
  5708. from Lattice Semiconductor (LCOUNT, LDELAY, LDSR), and
  5709. two opcodes supporting a more accurate translation of SVF
  5711. If @emph{xsvfdump} shows a file is using those opcodes, it
  5712. probably will not be usable with other XSVF tools.
  5713. @node TFTP
  5714. @chapter TFTP
  5715. @cindex TFTP
  5716. If OpenOCD runs on an embedded host(as ZY1000 does), then TFTP can
  5717. be used to access files on PCs (either the developer's PC or some other PC).
  5718. The way this works on the ZY1000 is to prefix a filename by
  5719. "/tftp/ip/" and append the TFTP path on the TFTP
  5720. server (tftpd). For example,
  5721. @example
  5722. load_image /tftp/\temp\abc.elf
  5723. @end example
  5724. will load c:\temp\abc.elf from the developer pc ( into memory as
  5725. if the file was hosted on the embedded host.
  5726. In order to achieve decent performance, you must choose a TFTP server
  5727. that supports a packet size bigger than the default packet size (512 bytes). There
  5728. are numerous TFTP servers out there (free and commercial) and you will have to do
  5729. a bit of googling to find something that fits your requirements.
  5730. @node GDB and OpenOCD
  5731. @chapter GDB and OpenOCD
  5732. @cindex GDB
  5733. OpenOCD complies with the remote gdbserver protocol, and as such can be used
  5734. to debug remote targets.
  5735. Setting up GDB to work with OpenOCD can involve several components:
  5736. @itemize
  5737. @item The OpenOCD server support for GDB may need to be configured.
  5738. @xref{GDB Configuration}.
  5739. @item GDB's support for OpenOCD may need configuration,
  5740. as shown in this chapter.
  5741. @item If you have a GUI environment like Eclipse,
  5742. that also will probably need to be configured.
  5743. @end itemize
  5744. Of course, the version of GDB you use will need to be one which has
  5745. been built to know about the target CPU you're using. It's probably
  5746. part of the tool chain you're using. For example, if you are doing
  5747. cross-development for ARM on an x86 PC, instead of using the native
  5748. x86 @command{gdb} command you might use @command{arm-none-eabi-gdb}
  5749. if that's the tool chain used to compile your code.
  5750. @anchor{Connecting to GDB}
  5751. @section Connecting to GDB
  5752. @cindex Connecting to GDB
  5753. Use GDB 6.7 or newer with OpenOCD if you run into trouble. For
  5754. instance GDB 6.3 has a known bug that produces bogus memory access
  5755. errors, which has since been fixed; see
  5756. @url{}
  5757. OpenOCD can communicate with GDB in two ways:
  5758. @enumerate
  5759. @item
  5760. A socket (TCP/IP) connection is typically started as follows:
  5761. @example
  5762. target remote localhost:3333
  5763. @end example
  5764. This would cause GDB to connect to the gdbserver on the local pc using port 3333.
  5765. @item
  5766. A pipe connection is typically started as follows:
  5767. @example
  5768. target remote | openocd --pipe
  5769. @end example
  5770. This would cause GDB to run OpenOCD and communicate using pipes (stdin/stdout).
  5771. Using this method has the advantage of GDB starting/stopping OpenOCD for the debug
  5772. session.
  5773. @end enumerate
  5774. To list the available OpenOCD commands type @command{monitor help} on the
  5775. GDB command line.
  5776. @section Sample GDB session startup
  5777. With the remote protocol, GDB sessions start a little differently
  5778. than they do when you're debugging locally.
  5779. Here's an examples showing how to start a debug session with a
  5780. small ARM program.
  5781. In this case the program was linked to be loaded into SRAM on a Cortex-M3.
  5782. Most programs would be written into flash (address 0) and run from there.
  5783. @example
  5784. $ arm-none-eabi-gdb example.elf
  5785. (gdb) target remote localhost:3333
  5786. Remote debugging using localhost:3333
  5787. ...
  5788. (gdb) monitor reset halt
  5789. ...
  5790. (gdb) load
  5791. Loading section .vectors, size 0x100 lma 0x20000000
  5792. Loading section .text, size 0x5a0 lma 0x20000100
  5793. Loading section .data, size 0x18 lma 0x200006a0
  5794. Start address 0x2000061c, load size 1720
  5795. Transfer rate: 22 KB/sec, 573 bytes/write.
  5796. (gdb) continue
  5797. Continuing.
  5798. ...
  5799. @end example
  5800. You could then interrupt the GDB session to make the program break,
  5801. type @command{where} to show the stack, @command{list} to show the
  5802. code around the program counter, @command{step} through code,
  5803. set breakpoints or watchpoints, and so on.
  5804. @section Configuring GDB for OpenOCD
  5805. OpenOCD supports the gdb @option{qSupported} packet, this enables information
  5806. to be sent by the GDB remote server (i.e. OpenOCD) to GDB. Typical information includes
  5807. packet size and the device's memory map.
  5808. You do not need to configure the packet size by hand,
  5809. and the relevant parts of the memory map should be automatically
  5810. set up when you declare (NOR) flash banks.
  5811. However, there are other things which GDB can't currently query.
  5812. You may need to set those up by hand.
  5813. As OpenOCD starts up, you will often see a line reporting
  5814. something like:
  5815. @example
  5816. Info : lm3s.cpu: hardware has 6 breakpoints, 4 watchpoints
  5817. @end example
  5818. You can pass that information to GDB with these commands:
  5819. @example
  5820. set remote hardware-breakpoint-limit 6
  5821. set remote hardware-watchpoint-limit 4
  5822. @end example
  5823. With that particular hardware (Cortex-M3) the hardware breakpoints
  5824. only work for code running from flash memory. Most other ARM systems
  5825. do not have such restrictions.
  5826. Another example of useful GDB configuration came from a user who
  5827. found that single stepping his Cortex-M3 didn't work well with IRQs
  5828. and an RTOS until he told GDB to disable the IRQs while stepping:
  5829. @example
  5830. define hook-step
  5831. mon cortex_m3 maskisr on
  5832. end
  5833. define hookpost-step
  5834. mon cortex_m3 maskisr off
  5835. end
  5836. @end example
  5837. Rather than typing such commands interactively, you may prefer to
  5838. save them in a file and have GDB execute them as it starts, perhaps
  5839. using a @file{.gdbinit} in your project directory or starting GDB
  5840. using @command{gdb -x filename}.
  5841. @section Programming using GDB
  5842. @cindex Programming using GDB
  5843. By default the target memory map is sent to GDB. This can be disabled by
  5844. the following OpenOCD configuration option:
  5845. @example
  5846. gdb_memory_map disable
  5847. @end example
  5848. For this to function correctly a valid flash configuration must also be set
  5849. in OpenOCD. For faster performance you should also configure a valid
  5850. working area.
  5851. Informing GDB of the memory map of the target will enable GDB to protect any
  5852. flash areas of the target and use hardware breakpoints by default. This means
  5853. that the OpenOCD option @command{gdb_breakpoint_override} is not required when
  5854. using a memory map. @xref{gdb_breakpoint_override}.
  5855. To view the configured memory map in GDB, use the GDB command @option{info mem}
  5856. All other unassigned addresses within GDB are treated as RAM.
  5857. GDB 6.8 and higher set any memory area not in the memory map as inaccessible.
  5858. This can be changed to the old behaviour by using the following GDB command
  5859. @example
  5860. set mem inaccessible-by-default off
  5861. @end example
  5862. If @command{gdb_flash_program enable} is also used, GDB will be able to
  5863. program any flash memory using the vFlash interface.
  5864. GDB will look at the target memory map when a load command is given, if any
  5865. areas to be programmed lie within the target flash area the vFlash packets
  5866. will be used.
  5867. If the target needs configuring before GDB programming, an event
  5868. script can be executed:
  5869. @example
  5870. $_TARGETNAME configure -event EVENTNAME BODY
  5871. @end example
  5872. To verify any flash programming the GDB command @option{compare-sections}
  5873. can be used.
  5874. @node Tcl Scripting API
  5875. @chapter Tcl Scripting API
  5876. @cindex Tcl Scripting API
  5877. @cindex Tcl scripts
  5878. @section API rules
  5879. The commands are stateless. E.g. the telnet command line has a concept
  5880. of currently active target, the Tcl API proc's take this sort of state
  5881. information as an argument to each proc.
  5882. There are three main types of return values: single value, name value
  5883. pair list and lists.
  5884. Name value pair. The proc 'foo' below returns a name/value pair
  5885. list.
  5886. @verbatim
  5887. > set foo(me) Duane
  5888. > set foo(you) Oyvind
  5889. > set foo(mouse) Micky
  5890. > set foo(duck) Donald
  5891. If one does this:
  5892. > set foo
  5893. The result is:
  5894. me Duane you Oyvind mouse Micky duck Donald
  5895. Thus, to get the names of the associative array is easy:
  5896. foreach { name value } [set foo] {
  5897. puts "Name: $name, Value: $value"
  5898. }
  5899. @end verbatim
  5900. Lists returned must be relatively small. Otherwise a range
  5901. should be passed in to the proc in question.
  5902. @section Internal low-level Commands
  5903. By low-level, the intent is a human would not directly use these commands.
  5904. Low-level commands are (should be) prefixed with "ocd_", e.g.
  5905. @command{ocd_flash_banks}
  5906. is the low level API upon which @command{flash banks} is implemented.
  5907. @itemize @bullet
  5908. @item @b{ocd_mem2array} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
  5909. Read memory and return as a Tcl array for script processing
  5910. @item @b{ocd_array2mem} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
  5911. Convert a Tcl array to memory locations and write the values
  5912. @item @b{ocd_flash_banks} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}> <@var{target}> [@option{driver options} ...]
  5913. Return information about the flash banks
  5914. @end itemize
  5915. OpenOCD commands can consist of two words, e.g. "flash banks". The
  5916. @file{startup.tcl} "unknown" proc will translate this into a Tcl proc
  5917. called "flash_banks".
  5918. @section OpenOCD specific Global Variables
  5919. Real Tcl has ::tcl_platform(), and platform::identify, and many other
  5920. variables. JimTCL, as implemented in OpenOCD creates $ocd_HOSTOS which
  5921. holds one of the following values:
  5922. @itemize @bullet
  5923. @item @b{cygwin} Running under Cygwin
  5924. @item @b{darwin} Darwin (Mac-OS) is the underlying operating sytem.
  5925. @item @b{freebsd} Running under FreeBSD
  5926. @item @b{linux} Linux is the underlying operating sytem
  5927. @item @b{mingw32} Running under MingW32
  5928. @item @b{winxx} Built using Microsoft Visual Studio
  5929. @item @b{other} Unknown, none of the above.
  5930. @end itemize
  5931. Note: 'winxx' was choosen because today (March-2009) no distinction is made between Win32 and Win64.
  5932. @quotation Note
  5933. We should add support for a variable like Tcl variable
  5934. @code{tcl_platform(platform)}, it should be called
  5935. @code{jim_platform} (because it
  5936. is jim, not real tcl).
  5937. @end quotation
  5938. @node FAQ
  5939. @chapter FAQ
  5940. @cindex faq
  5941. @enumerate
  5942. @anchor{FAQ RTCK}
  5943. @item @b{RTCK, also known as: Adaptive Clocking - What is it?}
  5944. @cindex RTCK
  5945. @cindex adaptive clocking
  5946. @*
  5947. In digital circuit design it is often refered to as ``clock
  5948. synchronisation'' the JTAG interface uses one clock (TCK or TCLK)
  5949. operating at some speed, your CPU target is operating at another.
  5950. The two clocks are not synchronised, they are ``asynchronous''
  5951. In order for the two to work together they must be synchronised
  5952. well enough to work; JTAG can't go ten times faster than the CPU,
  5953. for example. There are 2 basic options:
  5954. @enumerate
  5955. @item
  5956. Use a special "adaptive clocking" circuit to change the JTAG
  5957. clock rate to match what the CPU currently supports.
  5958. @item
  5959. The JTAG clock must be fixed at some speed that's enough slower than
  5960. the CPU clock that all TMS and TDI transitions can be detected.
  5961. @end enumerate
  5962. @b{Does this really matter?} For some chips and some situations, this
  5963. is a non-issue, like a 500MHz ARM926 with a 5 MHz JTAG link;
  5964. the CPU has no difficulty keeping up with JTAG.
  5965. Startup sequences are often problematic though, as are other
  5966. situations where the CPU clock rate changes (perhaps to save
  5967. power).
  5968. For example, Atmel AT91SAM chips start operation from reset with
  5969. a 32kHz system clock. Boot firmware may activate the main oscillator
  5970. and PLL before switching to a faster clock (perhaps that 500 MHz
  5971. ARM926 scenario).
  5972. If you're using JTAG to debug that startup sequence, you must slow
  5973. the JTAG clock to sometimes 1 to 4kHz. After startup completes,
  5974. JTAG can use a faster clock.
  5975. Consider also debugging a 500MHz ARM926 hand held battery powered
  5976. device that enters a low power ``deep sleep'' mode, at 32kHz CPU
  5977. clock, between keystrokes unless it has work to do. When would
  5978. that 5 MHz JTAG clock be usable?
  5979. @b{Solution #1 - A special circuit}
  5980. In order to make use of this,
  5981. both your CPU and your JTAG dongle must support the RTCK
  5982. feature. Not all dongles support this - keep reading!
  5983. The RTCK ("Return TCK") signal in some ARM chips is used to help with
  5984. this problem. ARM has a good description of the problem described at
  5985. this link: @url{} [checked
  5986. 28/nov/2008]. Link title: ``How does the JTAG synchronisation logic
  5987. work? / how does adaptive clocking work?''.
  5988. The nice thing about adaptive clocking is that ``battery powered hand
  5989. held device example'' - the adaptiveness works perfectly all the
  5990. time. One can set a break point or halt the system in the deep power
  5991. down code, slow step out until the system speeds up.
  5992. Note that adaptive clocking may also need to work at the board level,
  5993. when a board-level scan chain has multiple chips.
  5994. Parallel clock voting schemes are good way to implement this,
  5995. both within and between chips, and can easily be implemented
  5996. with a CPLD.
  5997. It's not difficult to have logic fan a module's input TCK signal out
  5998. to each TAP in the scan chain, and then wait until each TAP's RTCK comes
  5999. back with the right polarity before changing the output RTCK signal.
  6000. Texas Instruments makes some clock voting logic available
  6001. for free (with no support) in VHDL form; see
  6002. @url{}
  6003. @b{Solution #2 - Always works - but may be slower}
  6004. Often this is a perfectly acceptable solution.
  6005. In most simple terms: Often the JTAG clock must be 1/10 to 1/12 of
  6006. the target clock speed. But what that ``magic division'' is varies
  6007. depending on the chips on your board.
  6008. @b{ARM rule of thumb} Most ARM based systems require an 6:1 division;
  6009. ARM11 cores use an 8:1 division.
  6010. @b{Xilinx rule of thumb} is 1/12 the clock speed.
  6011. Note: Many FTDI2232C based JTAG dongles are limited to 6MHz.
  6012. You can still debug the 'low power' situations - you just need to
  6013. either use a fixed and very slow JTAG clock rate ... or else
  6014. manually adjust the clock speed at every step. (Adjusting is painful
  6015. and tedious, and is not always practical.)
  6016. It is however easy to ``code your way around it'' - i.e.: Cheat a little,
  6017. have a special debug mode in your application that does a ``high power
  6018. sleep''. If you are careful - 98% of your problems can be debugged
  6019. this way.
  6020. Note that on ARM you may need to avoid using the @emph{wait for interrupt}
  6021. operation in your idle loops even if you don't otherwise change the CPU
  6022. clock rate.
  6023. That operation gates the CPU clock, and thus the JTAG clock; which
  6024. prevents JTAG access. One consequence is not being able to @command{halt}
  6025. cores which are executing that @emph{wait for interrupt} operation.
  6026. To set the JTAG frequency use the command:
  6027. @example
  6028. # Example: 1.234MHz
  6029. jtag_khz 1234
  6030. @end example
  6031. @item @b{Win32 Pathnames} Why don't backslashes work in Windows paths?
  6032. OpenOCD uses Tcl and a backslash is an escape char. Use @{ and @}
  6033. around Windows filenames.
  6034. @example
  6035. > echo \a
  6036. > echo @{\a@}
  6037. \a
  6038. > echo "\a"
  6039. >
  6040. @end example
  6041. @item @b{Missing: cygwin1.dll} OpenOCD complains about a missing cygwin1.dll.
  6042. Make sure you have Cygwin installed, or at least a version of OpenOCD that
  6043. claims to come with all the necessary DLLs. When using Cygwin, try launching
  6044. OpenOCD from the Cygwin shell.
  6045. @item @b{Breakpoint Issue} I'm trying to set a breakpoint using GDB (or a frontend like Insight or
  6046. Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213
  6047. arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".
  6048. GDB issues software breakpoints when a normal breakpoint is requested, or to implement
  6049. source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720T or ARM920T,
  6050. software breakpoints consume one of the two available hardware breakpoints.
  6051. @item @b{LPC2000 Flash} When erasing or writing LPC2000 on-chip flash, the operation fails at random.
  6052. Make sure the core frequency specified in the @option{flash lpc2000} line matches the
  6053. clock at the time you're programming the flash. If you've specified the crystal's
  6054. frequency, make sure the PLL is disabled. If you've specified the full core speed
  6055. (e.g. 60MHz), make sure the PLL is enabled.
  6056. @item @b{Amontec Chameleon} When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
  6057. I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed
  6058. out while waiting for end of scan, rtck was disabled".
  6059. Make sure your PC's parallel port operates in EPP mode. You might have to try several
  6060. settings in your PC BIOS (ECP, EPP, and different versions of those).
  6061. @item @b{Data Aborts} When debugging with OpenOCD and GDB (plain GDB, Insight, or Eclipse),
  6062. I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():
  6063. memory read caused data abort".
  6064. The errors are non-fatal, and are the result of GDB trying to trace stack frames
  6065. beyond the last valid frame. It might be possible to prevent this by setting up
  6066. a proper "initial" stack frame, if you happen to know what exactly has to
  6067. be done, feel free to add this here.
  6068. @b{Simple:} In your startup code - push 8 registers of zeros onto the
  6069. stack before calling main(). What GDB is doing is ``climbing'' the run
  6070. time stack by reading various values on the stack using the standard
  6071. call frame for the target. GDB keeps going - until one of 2 things
  6072. happen @b{#1} an invalid frame is found, or @b{#2} some huge number of
  6073. stackframes have been processed. By pushing zeros on the stack, GDB
  6074. gracefully stops.
  6075. @b{Debugging Interrupt Service Routines} - In your ISR before you call
  6076. your C code, do the same - artifically push some zeros onto the stack,
  6077. remember to pop them off when the ISR is done.
  6078. @b{Also note:} If you have a multi-threaded operating system, they
  6079. often do not @b{in the intrest of saving memory} waste these few
  6080. bytes. Painful...
  6081. @item @b{JTAG Reset Config} I get the following message in the OpenOCD console (or log file):
  6082. "Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".
  6083. This warning doesn't indicate any serious problem, as long as you don't want to
  6084. debug your core right out of reset. Your .cfg file specified @option{jtag_reset
  6085. trst_and_srst srst_pulls_trst} to tell OpenOCD that either your board,
  6086. your debugger or your target uC (e.g. LPC2000) can't assert the two reset signals
  6087. independently. With this setup, it's not possible to halt the core right out of
  6088. reset, everything else should work fine.
  6089. @item @b{USB Power} When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto
  6090. toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be
  6091. unstable. When single-stepping over large blocks of code, GDB and OpenOCD
  6092. quit with an error message. Is there a stability issue with OpenOCD?
  6093. No, this is not a stability issue concerning OpenOCD. Most users have solved
  6094. this issue by simply using a self-powered USB hub, which they connect their
  6095. Amontec JTAGkey to. Apparently, some computers do not provide a USB power
  6096. supply stable enough for the Amontec JTAGkey to be operated.
  6097. @b{Laptops running on battery have this problem too...}
  6098. @item @b{USB Power} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the
  6099. following error messages: "Error: ft2232.c:201 ft2232_read(): FT_Read returned:
  6100. 4" and "Error: ft2232.c:365 ft2232_send_and_recv(): couldn't read from FT2232".
  6101. What does that mean and what might be the reason for this?
  6102. First of all, the reason might be the USB power supply. Try using a self-powered
  6103. hub instead of a direct connection to your computer. Secondly, the error code 4
  6104. corresponds to an FT_IO_ERROR, which means that the driver for the FTDI USB
  6105. chip ran into some sort of error - this points us to a USB problem.
  6106. @item @b{GDB Disconnects} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following
  6107. error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054".
  6108. What does that mean and what might be the reason for this?
  6109. Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB)
  6110. has closed the connection to OpenOCD. This might be a GDB issue.
  6111. @item @b{LPC2000 Flash} In the configuration file in the section where flash device configurations
  6112. are described, there is a parameter for specifying the clock frequency
  6113. for LPC2000 internal flash devices (e.g. @option{flash bank lpc2000
  6114. 0x0 0x40000 0 0 0 lpc2000_v1 14746 calc_checksum}), which must be
  6115. specified in kilohertz. However, I do have a quartz crystal of a
  6116. frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz,
  6117. i.e. 14,745.600 kHz). Is it possible to specify real numbers for the
  6118. clock frequency?
  6119. No. The clock frequency specified here must be given as an integral number.
  6120. However, this clock frequency is used by the In-Application-Programming (IAP)
  6121. routines of the LPC2000 family only, which seems to be very tolerant concerning
  6122. the given clock frequency, so a slight difference between the specified clock
  6123. frequency and the actual clock frequency will not cause any trouble.
  6124. @item @b{Command Order} Do I have to keep a specific order for the commands in the configuration file?
  6125. Well, yes and no. Commands can be given in arbitrary order, yet the
  6126. devices listed for the JTAG scan chain must be given in the right
  6127. order (jtag newdevice), with the device closest to the TDO-Pin being
  6128. listed first. In general, whenever objects of the same type exist
  6129. which require an index number, then these objects must be given in the
  6130. right order (jtag newtap, targets and flash banks - a target
  6131. references a jtag newtap and a flash bank references a target).
  6132. You can use the ``scan_chain'' command to verify and display the tap order.
  6133. Also, some commands can't execute until after @command{init} has been
  6134. processed. Such commands include @command{nand probe} and everything
  6135. else that needs to write to controller registers, perhaps for setting
  6136. up DRAM and loading it with code.
  6137. @anchor{FAQ TAP Order}
  6138. @item @b{JTAG TAP Order} Do I have to declare the TAPS in some
  6139. particular order?
  6140. Yes; whenever you have more than one, you must declare them in
  6141. the same order used by the hardware.
  6142. Many newer devices have multiple JTAG TAPs. For example: ST
  6143. Microsystems STM32 chips have two TAPs, a ``boundary scan TAP'' and
  6144. ``Cortex-M3'' TAP. Example: The STM32 reference manual, Document ID:
  6145. RM0008, Section 26.5, Figure 259, page 651/681, the ``TDI'' pin is
  6146. connected to the boundary scan TAP, which then connects to the
  6147. Cortex-M3 TAP, which then connects to the TDO pin.
  6148. Thus, the proper order for the STM32 chip is: (1) The Cortex-M3, then
  6149. (2) The boundary scan TAP. If your board includes an additional JTAG
  6150. chip in the scan chain (for example a Xilinx CPLD or FPGA) you could
  6151. place it before or after the STM32 chip in the chain. For example:
  6152. @itemize @bullet
  6153. @item OpenOCD_TDI(output) -> STM32 TDI Pin (BS Input)
  6154. @item STM32 BS TDO (output) -> STM32 Cortex-M3 TDI (input)
  6155. @item STM32 Cortex-M3 TDO (output) -> SM32 TDO Pin
  6156. @item STM32 TDO Pin (output) -> Xilinx TDI Pin (input)
  6157. @item Xilinx TDO Pin -> OpenOCD TDO (input)
  6158. @end itemize
  6159. The ``jtag device'' commands would thus be in the order shown below. Note:
  6160. @itemize @bullet
  6161. @item jtag newtap Xilinx tap -irlen ...
  6162. @item jtag newtap stm32 cpu -irlen ...
  6163. @item jtag newtap stm32 bs -irlen ...
  6164. @item # Create the debug target and say where it is
  6165. @item target create stm32.cpu -chain-position stm32.cpu ...
  6166. @end itemize
  6167. @item @b{SYSCOMP} Sometimes my debugging session terminates with an error. When I look into the
  6168. log file, I can see these error messages: Error: arm7_9_common.c:561
  6169. arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP
  6170. TODO.
  6171. @end enumerate
  6172. @node Tcl Crash Course
  6173. @chapter Tcl Crash Course
  6174. @cindex Tcl
  6175. Not everyone knows Tcl - this is not intended to be a replacement for
  6176. learning Tcl, the intent of this chapter is to give you some idea of
  6177. how the Tcl scripts work.
  6178. This chapter is written with two audiences in mind. (1) OpenOCD users
  6179. who need to understand a bit more of how JIM-Tcl works so they can do
  6180. something useful, and (2) those that want to add a new command to
  6181. OpenOCD.
  6182. @section Tcl Rule #1
  6183. There is a famous joke, it goes like this:
  6184. @enumerate
  6185. @item Rule #1: The wife is always correct
  6186. @item Rule #2: If you think otherwise, See Rule #1
  6187. @end enumerate
  6188. The Tcl equal is this:
  6189. @enumerate
  6190. @item Rule #1: Everything is a string
  6191. @item Rule #2: If you think otherwise, See Rule #1
  6192. @end enumerate
  6193. As in the famous joke, the consequences of Rule #1 are profound. Once
  6194. you understand Rule #1, you will understand Tcl.
  6195. @section Tcl Rule #1b
  6196. There is a second pair of rules.
  6197. @enumerate
  6198. @item Rule #1: Control flow does not exist. Only commands
  6199. @* For example: the classic FOR loop or IF statement is not a control
  6200. flow item, they are commands, there is no such thing as control flow
  6201. in Tcl.
  6202. @item Rule #2: If you think otherwise, See Rule #1
  6203. @* Actually what happens is this: There are commands that by
  6204. convention, act like control flow key words in other languages. One of
  6205. those commands is the word ``for'', another command is ``if''.
  6206. @end enumerate
  6207. @section Per Rule #1 - All Results are strings
  6208. Every Tcl command results in a string. The word ``result'' is used
  6209. deliberatly. No result is just an empty string. Remember: @i{Rule #1 -
  6210. Everything is a string}
  6211. @section Tcl Quoting Operators
  6212. In life of a Tcl script, there are two important periods of time, the
  6213. difference is subtle.
  6214. @enumerate
  6215. @item Parse Time
  6216. @item Evaluation Time
  6217. @end enumerate
  6218. The two key items here are how ``quoted things'' work in Tcl. Tcl has
  6219. three primary quoting constructs, the [square-brackets] the
  6220. @{curly-braces@} and ``double-quotes''
  6221. By now you should know $VARIABLES always start with a $DOLLAR
  6222. sign. BTW: To set a variable, you actually use the command ``set'', as
  6223. in ``set VARNAME VALUE'' much like the ancient BASIC langauge ``let x
  6224. = 1'' statement, but without the equal sign.
  6225. @itemize @bullet
  6226. @item @b{[square-brackets]}
  6227. @* @b{[square-brackets]} are command substitutions. It operates much
  6228. like Unix Shell `back-ticks`. The result of a [square-bracket]
  6229. operation is exactly 1 string. @i{Remember Rule #1 - Everything is a
  6230. string}. These two statements are roughly identical:
  6231. @example
  6232. # bash example
  6233. X=`date`
  6234. echo "The Date is: $X"
  6235. # Tcl example
  6236. set X [date]
  6237. puts "The Date is: $X"
  6238. @end example
  6239. @item @b{``double-quoted-things''}
  6240. @* @b{``double-quoted-things''} are just simply quoted
  6241. text. $VARIABLES and [square-brackets] are expanded in place - the
  6242. result however is exactly 1 string. @i{Remember Rule #1 - Everything
  6243. is a string}
  6244. @example
  6245. set x "Dinner"
  6246. puts "It is now \"[date]\", $x is in 1 hour"
  6247. @end example
  6248. @item @b{@{Curly-Braces@}}
  6249. @*@b{@{Curly-Braces@}} are magic: $VARIABLES and [square-brackets] are
  6250. parsed, but are NOT expanded or executed. @{Curly-Braces@} are like
  6251. 'single-quote' operators in BASH shell scripts, with the added
  6252. feature: @{curly-braces@} can be nested, single quotes can not. @{@{@{this is
  6253. nested 3 times@}@}@} NOTE: [date] is a bad example;
  6254. at this writing, Jim/OpenOCD does not have a date command.
  6255. @end itemize
  6256. @section Consequences of Rule 1/2/3/4
  6257. The consequences of Rule 1 are profound.
  6258. @subsection Tokenisation & Execution.
  6259. Of course, whitespace, blank lines and #comment lines are handled in
  6260. the normal way.
  6261. As a script is parsed, each (multi) line in the script file is
  6262. tokenised and according to the quoting rules. After tokenisation, that
  6263. line is immedatly executed.
  6264. Multi line statements end with one or more ``still-open''
  6265. @{curly-braces@} which - eventually - closes a few lines later.
  6266. @subsection Command Execution
  6267. Remember earlier: There are no ``control flow''
  6268. statements in Tcl. Instead there are COMMANDS that simply act like
  6269. control flow operators.
  6270. Commands are executed like this:
  6271. @enumerate
  6272. @item Parse the next line into (argc) and (argv[]).
  6273. @item Look up (argv[0]) in a table and call its function.
  6274. @item Repeat until End Of File.
  6275. @end enumerate
  6276. It sort of works like this:
  6277. @example
  6278. for(;;)@{
  6279. ReadAndParse( &argc, &argv );
  6280. cmdPtr = LookupCommand( argv[0] );
  6281. (*cmdPtr->Execute)( argc, argv );
  6282. @}
  6283. @end example
  6284. When the command ``proc'' is parsed (which creates a procedure
  6285. function) it gets 3 parameters on the command line. @b{1} the name of
  6286. the proc (function), @b{2} the list of parameters, and @b{3} the body
  6287. of the function. Not the choice of words: LIST and BODY. The PROC
  6288. command stores these items in a table somewhere so it can be found by
  6289. ``LookupCommand()''
  6290. @subsection The FOR command
  6291. The most interesting command to look at is the FOR command. In Tcl,
  6292. the FOR command is normally implemented in C. Remember, FOR is a
  6293. command just like any other command.
  6294. When the ascii text containing the FOR command is parsed, the parser
  6295. produces 5 parameter strings, @i{(If in doubt: Refer to Rule #1)} they
  6296. are:
  6297. @enumerate 0
  6298. @item The ascii text 'for'
  6299. @item The start text
  6300. @item The test expression
  6301. @item The next text
  6302. @item The body text
  6303. @end enumerate
  6304. Sort of reminds you of ``main( int argc, char **argv )'' does it not?
  6305. Remember @i{Rule #1 - Everything is a string.} The key point is this:
  6306. Often many of those parameters are in @{curly-braces@} - thus the
  6307. variables inside are not expanded or replaced until later.
  6308. Remember that every Tcl command looks like the classic ``main( argc,
  6309. argv )'' function in C. In JimTCL - they actually look like this:
  6310. @example
  6311. int
  6312. MyCommand( Jim_Interp *interp,
  6313. int *argc,
  6314. Jim_Obj * const *argvs );
  6315. @end example
  6316. Real Tcl is nearly identical. Although the newer versions have
  6317. introduced a byte-code parser and intepreter, but at the core, it
  6318. still operates in the same basic way.
  6319. @subsection FOR command implementation
  6320. To understand Tcl it is perhaps most helpful to see the FOR
  6321. command. Remember, it is a COMMAND not a control flow structure.
  6322. In Tcl there are two underlying C helper functions.
  6323. Remember Rule #1 - You are a string.
  6324. The @b{first} helper parses and executes commands found in an ascii
  6325. string. Commands can be seperated by semicolons, or newlines. While
  6326. parsing, variables are expanded via the quoting rules.
  6327. The @b{second} helper evaluates an ascii string as a numerical
  6328. expression and returns a value.
  6329. Here is an example of how the @b{FOR} command could be
  6330. implemented. The pseudo code below does not show error handling.
  6331. @example
  6332. void Execute_AsciiString( void *interp, const char *string );
  6333. int Evaluate_AsciiExpression( void *interp, const char *string );
  6334. int
  6335. MyForCommand( void *interp,
  6336. int argc,
  6337. char **argv )
  6338. @{
  6339. if( argc != 5 )@{
  6340. SetResult( interp, "WRONG number of parameters");
  6341. return ERROR;
  6342. @}
  6343. // argv[0] = the ascii string just like C
  6344. // Execute the start statement.
  6345. Execute_AsciiString( interp, argv[1] );
  6346. // Top of loop test
  6347. for(;;)@{
  6348. i = Evaluate_AsciiExpression(interp, argv[2]);
  6349. if( i == 0 )
  6350. break;
  6351. // Execute the body
  6352. Execute_AsciiString( interp, argv[3] );
  6353. // Execute the LOOP part
  6354. Execute_AsciiString( interp, argv[4] );
  6355. @}
  6356. // Return no error
  6357. SetResult( interp, "" );
  6358. return SUCCESS;
  6359. @}
  6360. @end example
  6361. Every other command IF, WHILE, FORMAT, PUTS, EXPR, everything works
  6362. in the same basic way.
  6363. @section OpenOCD Tcl Usage
  6364. @subsection source and find commands
  6365. @b{Where:} In many configuration files
  6366. @* Example: @b{ source [find FILENAME] }
  6367. @*Remember the parsing rules
  6368. @enumerate
  6369. @item The FIND command is in square brackets.
  6370. @* The FIND command is executed with the parameter FILENAME. It should
  6371. find the full path to the named file. The RESULT is a string, which is
  6372. substituted on the orginal command line.
  6373. @item The command source is executed with the resulting filename.
  6374. @* SOURCE reads a file and executes as a script.
  6375. @end enumerate
  6376. @subsection format command
  6377. @b{Where:} Generally occurs in numerous places.
  6378. @* Tcl has no command like @b{printf()}, instead it has @b{format}, which is really more like
  6379. @b{sprintf()}.
  6380. @b{Example}
  6381. @example
  6382. set x 6
  6383. set y 7
  6384. puts [format "The answer: %d" [expr $x * $y]]
  6385. @end example
  6386. @enumerate
  6387. @item The SET command creates 2 variables, X and Y.
  6388. @item The double [nested] EXPR command performs math
  6389. @* The EXPR command produces numerical result as a string.
  6390. @* Refer to Rule #1
  6391. @item The format command is executed, producing a single string
  6392. @* Refer to Rule #1.
  6393. @item The PUTS command outputs the text.
  6394. @end enumerate
  6395. @subsection Body or Inlined Text
  6396. @b{Where:} Various TARGET scripts.
  6397. @example
  6398. #1 Good
  6399. proc someproc @{@} @{
  6400. ... multiple lines of stuff ...
  6401. @}
  6402. $_TARGETNAME configure -event FOO someproc
  6403. #2 Good - no variables
  6404. $_TARGETNAME confgure -event foo "this ; that;"
  6405. #3 Good Curly Braces
  6406. $_TARGETNAME configure -event FOO @{
  6407. puts "Time: [date]"
  6408. @}
  6410. $_TARGETNAME configure -event foo "puts \"Time: [date]\""
  6411. @end example
  6412. @enumerate
  6413. @item The $_TARGETNAME is an OpenOCD variable convention.
  6414. @*@b{$_TARGETNAME} represents the last target created, the value changes
  6415. each time a new target is created. Remember the parsing rules. When
  6416. the ascii text is parsed, the @b{$_TARGETNAME} becomes a simple string,
  6417. the name of the target which happens to be a TARGET (object)
  6418. command.
  6419. @item The 2nd parameter to the @option{-event} parameter is a TCBODY
  6420. @*There are 4 examples:
  6421. @enumerate
  6422. @item The TCLBODY is a simple string that happens to be a proc name
  6423. @item The TCLBODY is several simple commands seperated by semicolons
  6424. @item The TCLBODY is a multi-line @{curly-brace@} quoted string
  6425. @item The TCLBODY is a string with variables that get expanded.
  6426. @end enumerate
  6427. In the end, when the target event FOO occurs the TCLBODY is
  6428. evaluated. Method @b{#1} and @b{#2} are functionally identical. For
  6429. Method @b{#3} and @b{#4} it is more interesting. What is the TCLBODY?
  6430. Remember the parsing rules. In case #3, @{curly-braces@} mean the
  6431. $VARS and [square-brackets] are expanded later, when the EVENT occurs,
  6432. and the text is evaluated. In case #4, they are replaced before the
  6433. ``Target Object Command'' is executed. This occurs at the same time
  6434. $_TARGETNAME is replaced. In case #4 the date will never
  6435. change. @{BTW: [date] is a bad example; at this writing,
  6436. Jim/OpenOCD does not have a date command@}
  6437. @end enumerate
  6438. @subsection Global Variables
  6439. @b{Where:} You might discover this when writing your own procs @* In
  6440. simple terms: Inside a PROC, if you need to access a global variable
  6441. you must say so. See also ``upvar''. Example:
  6442. @example
  6443. proc myproc @{ @} @{
  6444. set y 0 #Local variable Y
  6445. global x #Global variable X
  6446. puts [format "X=%d, Y=%d" $x $y]
  6447. @}
  6448. @end example
  6449. @section Other Tcl Hacks
  6450. @b{Dynamic variable creation}
  6451. @example
  6452. # Dynamically create a bunch of variables.
  6453. for @{ set x 0 @} @{ $x < 32 @} @{ set x [expr $x + 1]@} @{
  6454. # Create var name
  6455. set vn [format "BIT%d" $x]
  6456. # Make it a global
  6457. global $vn
  6458. # Set it.
  6459. set $vn [expr (1 << $x)]
  6460. @}
  6461. @end example
  6462. @b{Dynamic proc/command creation}
  6463. @example
  6464. # One "X" function - 5 uart functions.
  6465. foreach who @{A B C D E@}
  6466. proc [format "show_uart%c" $who] @{ @} "show_UARTx $who"
  6467. @}
  6468. @end example
  6469. @include fdl.texi
  6470. @node OpenOCD Concept Index
  6471. @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
  6472. @comment case issue with ``Index.html'' and ``index.html''
  6473. @comment Occurs when creating ``--html --no-split'' output
  6474. @comment This fix is based on:
  6475. @unnumbered OpenOCD Concept Index
  6476. @printindex cp
  6477. @node Command and Driver Index
  6478. @unnumbered Command and Driver Index
  6479. @printindex fn
  6480. @bye