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  1. /***************************************************************************
  2. * Copyright (C) 2006 by Magnus Lundin *
  3. * lundin@mlu.mine.nu *
  4. * *
  5. * Copyright (C) 2008 by Spencer Oliver *
  6. * spen@spen-soft.co.uk *
  7. * *
  8. * This program is free software; you can redistribute it and/or modify *
  9. * it under the terms of the GNU General Public License as published by *
  10. * the Free Software Foundation; either version 2 of the License, or *
  11. * (at your option) any later version. *
  12. * *
  13. * This program is distributed in the hope that it will be useful, *
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  16. * GNU General Public License for more details. *
  17. * *
  18. * You should have received a copy of the GNU General Public License *
  19. * along with this program; if not, write to the *
  20. * Free Software Foundation, Inc., *
  21. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
  22. ***************************************************************************/
  23. #ifndef ARM_ADI_V5_H
  24. #define ARM_ADI_V5_H
  25. /**
  26. * @file
  27. * This defines formats and data structures used to talk to ADIv5 entities.
  28. * Those include a DAP, different types of Debug Port (DP), and memory mapped
  29. * resources accessed through a MEM-AP.
  30. */
  31. #include "arm_jtag.h"
  32. /* FIXME remove these JTAG-specific decls when mem_ap_read_buf_u32()
  33. * is no longer JTAG-specific
  34. */
  35. #define JTAG_DP_DPACC 0xA
  36. #define JTAG_DP_APACC 0xB
  37. /* three-bit ACK values for SWD access (sent LSB first) */
  38. #define SWD_ACK_OK 0x4
  39. #define SWD_ACK_WAIT 0x2
  40. #define SWD_ACK_FAULT 0x1
  41. #define DPAP_WRITE 0
  42. #define DPAP_READ 1
  43. /* A[3:0] for DP registers; A[1:0] are always zero.
  44. * - JTAG accesses all of these via JTAG_DP_DPACC, except for
  45. * IDCODE (JTAG_DP_IDCODE) and ABORT (JTAG_DP_ABORT).
  46. * - SWD accesses these directly, sometimes needing SELECT.CTRLSEL
  47. */
  48. #define DP_IDCODE 0 /* SWD: read */
  49. #define DP_ABORT 0 /* SWD: write */
  50. #define DP_CTRL_STAT 0x4 /* r/w */
  51. #define DP_WCR 0x4 /* SWD: r/w (mux CTRLSEL) */
  52. #define DP_RESEND 0x8 /* SWD: read */
  53. #define DP_SELECT 0x8 /* JTAG: r/w; SWD: write */
  54. #define DP_RDBUFF 0xC /* read-only */
  55. #define WCR_TO_TRN(wcr) (1 + (3 & ((wcr)) >> 8)) /* 1..4 clocks */
  56. #define WCR_TO_PRESCALE(wcr) (7 & ((wcr))) /* impl defined */
  57. /* Fields of the DP's AP ABORT register */
  58. #define DAPABORT (1 << 0)
  59. #define STKCMPCLR (1 << 1) /* SWD-only */
  60. #define STKERRCLR (1 << 2) /* SWD-only */
  61. #define WDERRCLR (1 << 3) /* SWD-only */
  62. #define ORUNERRCLR (1 << 4) /* SWD-only */
  63. /* Fields of the DP's CTRL/STAT register */
  64. #define CORUNDETECT (1 << 0)
  65. #define SSTICKYORUN (1 << 1)
  66. /* 3:2 - transaction mode (e.g. pushed compare) */
  67. #define SSTICKYCMP (1 << 4)
  68. #define SSTICKYERR (1 << 5)
  69. #define READOK (1 << 6) /* SWD-only */
  70. #define WDATAERR (1 << 7) /* SWD-only */
  71. /* 11:8 - mask lanes for pushed compare or verify ops */
  72. /* 21:12 - transaction counter */
  73. #define CDBGRSTREQ (1 << 26)
  74. #define CDBGRSTACK (1 << 27)
  75. #define CDBGPWRUPREQ (1 << 28)
  76. #define CDBGPWRUPACK (1 << 29)
  77. #define CSYSPWRUPREQ (1 << 30)
  78. #define CSYSPWRUPACK (1 << 31)
  79. /* MEM-AP register addresses */
  80. /* TODO: rename as MEM_AP_REG_* */
  81. #define AP_REG_CSW 0x00
  82. #define AP_REG_TAR 0x04
  83. #define AP_REG_DRW 0x0C
  84. #define AP_REG_BD0 0x10
  85. #define AP_REG_BD1 0x14
  86. #define AP_REG_BD2 0x18
  87. #define AP_REG_BD3 0x1C
  88. #define AP_REG_CFG 0xF4 /* big endian? */
  89. #define AP_REG_BASE 0xF8
  90. /* Generic AP register address */
  91. #define AP_REG_IDR 0xFC
  92. /* Fields of the MEM-AP's CSW register */
  93. #define CSW_8BIT 0
  94. #define CSW_16BIT 1
  95. #define CSW_32BIT 2
  96. #define CSW_ADDRINC_MASK (3 << 4)
  97. #define CSW_ADDRINC_OFF 0
  98. #define CSW_ADDRINC_SINGLE (1 << 4)
  99. #define CSW_ADDRINC_PACKED (2 << 4)
  100. #define CSW_DEVICE_EN (1 << 6)
  101. #define CSW_TRIN_PROG (1 << 7)
  102. #define CSW_SPIDEN (1 << 23)
  103. /* 30:24 - implementation-defined! */
  104. #define CSW_HPROT (1 << 25) /* ? */
  105. #define CSW_MASTER_DEBUG (1 << 29) /* ? */
  106. #define CSW_SPROT (1 << 30)
  107. #define CSW_DBGSWENABLE (1 << 31)
  108. /**
  109. * This represents an ARM Debug Interface (v5) Debug Access Port (DAP).
  110. * A DAP has two types of component: one Debug Port (DP), which is a
  111. * transport agent; and at least one Access Port (AP), controlling
  112. * resource access. Most common is a MEM-AP, for memory access.
  113. *
  114. * There are two basic DP transports: JTAG, and ARM's low pin-count SWD.
  115. * Accordingly, this interface is responsible for hiding the transport
  116. * differences so upper layer code can largely ignore them.
  117. *
  118. * When the chip is implemented with JTAG-DP or SW-DP, the transport is
  119. * fixed as JTAG or SWD, respectively. Chips incorporating SWJ-DP permit
  120. * a choice made at board design time (by only using the SWD pins), or
  121. * as part of setting up a debug session (if all the dual-role JTAG/SWD
  122. * signals are available).
  123. */
  124. struct adiv5_dap {
  125. const struct dap_ops *ops;
  126. struct arm_jtag *jtag_info;
  127. /* Control config */
  128. uint32_t dp_ctrl_stat;
  129. uint32_t apcsw[256];
  130. uint32_t apsel;
  131. /**
  132. * Cache for DP_SELECT bits identifying the current AP. A DAP may
  133. * connect to multiple APs, such as one MEM-AP for general access,
  134. * another reserved for accessing debug modules, and a JTAG-DP.
  135. * "-1" indicates no cached value.
  136. */
  137. uint32_t ap_current;
  138. /**
  139. * Cache for DP_SELECT bits identifying the current four-word AP
  140. * register bank. This caches AP register addresss bits 7:4; JTAG
  141. * and SWD access primitves pass address bits 3:2; bits 1:0 are zero.
  142. * "-1" indicates no cached value.
  143. */
  144. uint32_t ap_bank_value;
  145. /**
  146. * Cache for (MEM-AP) AP_REG_CSW register value. This is written to
  147. * configure an access mode, such as autoincrementing AP_REG_TAR during
  148. * word access. "-1" indicates no cached value.
  149. */
  150. uint32_t ap_csw_value;
  151. /**
  152. * Cache for (MEM-AP) AP_REG_TAR register value This is written to
  153. * configure the address being read or written
  154. * "-1" indicates no cached value.
  155. */
  156. uint32_t ap_tar_value;
  157. /* information about current pending SWjDP-AHBAP transaction */
  158. uint8_t ack;
  159. /**
  160. * Configures how many extra tck clocks are added after starting a
  161. * MEM-AP access before we try to read its status (and/or result).
  162. */
  163. uint32_t memaccess_tck;
  164. /* Size of TAR autoincrement block, ARM ADI Specification requires at least 10 bits */
  165. uint32_t tar_autoincr_block;
  166. };
  167. /**
  168. * Transport-neutral representation of queued DAP transactions, supporting
  169. * both JTAG and SWD transports. All submitted transactions are logically
  170. * queued, until the queue is executed by run(). Some implementations might
  171. * execute transactions as soon as they're submitted, but no status is made
  172. * availablue until run().
  173. */
  174. struct dap_ops {
  175. /** If the DAP transport isn't SWD, it must be JTAG. Upper level
  176. * code may need to care about the difference in some cases.
  177. */
  178. bool is_swd;
  179. /** Reads the DAP's IDCODe register. */
  180. int (*queue_idcode_read)(struct adiv5_dap *dap,
  181. uint8_t *ack, uint32_t *data);
  182. /** DP register read. */
  183. int (*queue_dp_read)(struct adiv5_dap *dap, unsigned reg,
  184. uint32_t *data);
  185. /** DP register write. */
  186. int (*queue_dp_write)(struct adiv5_dap *dap, unsigned reg,
  187. uint32_t data);
  188. /** AP register read. */
  189. int (*queue_ap_read)(struct adiv5_dap *dap, unsigned reg,
  190. uint32_t *data);
  191. /** AP register write. */
  192. int (*queue_ap_write)(struct adiv5_dap *dap, unsigned reg,
  193. uint32_t data);
  194. /** AP read block. */
  195. int (*queue_ap_read_block)(struct adiv5_dap *dap, unsigned reg,
  196. uint32_t blocksize, uint8_t *buffer);
  197. /** AP operation abort. */
  198. int (*queue_ap_abort)(struct adiv5_dap *dap, uint8_t *ack);
  199. /** Executes all queued DAP operations. */
  200. int (*run)(struct adiv5_dap *dap);
  201. };
  202. /*
  203. * Access Port types
  204. */
  205. enum ap_type {
  206. AP_TYPE_AHB_AP = 0x01, /* AHB Memory-AP */
  207. AP_TYPE_APB_AP = 0x02, /* APB Memory-AP */
  208. AP_TYPE_JTAG_AP = 0x10 /* JTAG-AP - JTAG master for controlling other JTAG devices */
  209. };
  210. /**
  211. * Queue an IDCODE register read. This is primarily useful for SWD
  212. * transports, where it is required as part of link initialization.
  213. * (For JTAG, this register is read as part of scan chain setup.)
  214. *
  215. * @param dap The DAP used for reading.
  216. * @param ack Pointer to where transaction status will be stored.
  217. * @param data Pointer saying where to store the IDCODE value.
  218. *
  219. * @return ERROR_OK for success, else a fault code.
  220. */
  221. static inline int dap_queue_idcode_read(struct adiv5_dap *dap,
  222. uint8_t *ack, uint32_t *data)
  223. {
  224. assert(dap->ops != NULL);
  225. return dap->ops->queue_idcode_read(dap, ack, data);
  226. }
  227. /**
  228. * Queue a DP register read.
  229. * Note that not all DP registers are readable; also, that JTAG and SWD
  230. * have slight differences in DP register support.
  231. *
  232. * @param dap The DAP used for reading.
  233. * @param reg The two-bit number of the DP register being read.
  234. * @param data Pointer saying where to store the register's value
  235. * (in host endianness).
  236. *
  237. * @return ERROR_OK for success, else a fault code.
  238. */
  239. static inline int dap_queue_dp_read(struct adiv5_dap *dap,
  240. unsigned reg, uint32_t *data)
  241. {
  242. assert(dap->ops != NULL);
  243. return dap->ops->queue_dp_read(dap, reg, data);
  244. }
  245. /**
  246. * Queue a DP register write.
  247. * Note that not all DP registers are writable; also, that JTAG and SWD
  248. * have slight differences in DP register support.
  249. *
  250. * @param dap The DAP used for writing.
  251. * @param reg The two-bit number of the DP register being written.
  252. * @param data Value being written (host endianness)
  253. *
  254. * @return ERROR_OK for success, else a fault code.
  255. */
  256. static inline int dap_queue_dp_write(struct adiv5_dap *dap,
  257. unsigned reg, uint32_t data)
  258. {
  259. assert(dap->ops != NULL);
  260. return dap->ops->queue_dp_write(dap, reg, data);
  261. }
  262. /**
  263. * Queue an AP register read.
  264. *
  265. * @param dap The DAP used for reading.
  266. * @param reg The number of the AP register being read.
  267. * @param data Pointer saying where to store the register's value
  268. * (in host endianness).
  269. *
  270. * @return ERROR_OK for success, else a fault code.
  271. */
  272. static inline int dap_queue_ap_read(struct adiv5_dap *dap,
  273. unsigned reg, uint32_t *data)
  274. {
  275. assert(dap->ops != NULL);
  276. return dap->ops->queue_ap_read(dap, reg, data);
  277. }
  278. /**
  279. * Queue an AP register write.
  280. *
  281. * @param dap The DAP used for writing.
  282. * @param reg The number of the AP register being written.
  283. * @param data Value being written (host endianness)
  284. *
  285. * @return ERROR_OK for success, else a fault code.
  286. */
  287. static inline int dap_queue_ap_write(struct adiv5_dap *dap,
  288. unsigned reg, uint32_t data)
  289. {
  290. assert(dap->ops != NULL);
  291. return dap->ops->queue_ap_write(dap, reg, data);
  292. }
  293. /**
  294. * Queue an AP block read.
  295. *
  296. * @param dap The DAP used for reading.
  297. * @param reg The number of the AP register being read.
  298. * @param blocksize The number of the AP register being read.
  299. * @param buffer Pointer saying where to store the data
  300. * (in host endianness).
  301. *
  302. * @return ERROR_OK for success, else a fault code.
  303. */
  304. static inline int dap_queue_ap_read_block(struct adiv5_dap *dap,
  305. unsigned reg, unsigned blocksize, uint8_t *buffer)
  306. {
  307. assert(dap->ops != NULL);
  308. return dap->ops->queue_ap_read_block(dap, reg, blocksize, buffer);
  309. }
  310. /**
  311. * Queue an AP abort operation. The current AP transaction is aborted,
  312. * including any update of the transaction counter. The AP is left in
  313. * an unknown state (so it must be re-initialized). For use only after
  314. * the AP has reported WAIT status for an extended period.
  315. *
  316. * @param dap The DAP used for writing.
  317. * @param ack Pointer to where transaction status will be stored.
  318. *
  319. * @return ERROR_OK for success, else a fault code.
  320. */
  321. static inline int dap_queue_ap_abort(struct adiv5_dap *dap, uint8_t *ack)
  322. {
  323. assert(dap->ops != NULL);
  324. return dap->ops->queue_ap_abort(dap, ack);
  325. }
  326. /**
  327. * Perform all queued DAP operations, and clear any errors posted in the
  328. * CTRL_STAT register when they are done. Note that if more than one AP
  329. * operation will be queued, one of the first operations in the queue
  330. * should probably enable CORUNDETECT in the CTRL/STAT register.
  331. *
  332. * @param dap The DAP used.
  333. *
  334. * @return ERROR_OK for success, else a fault code.
  335. */
  336. static inline int dap_run(struct adiv5_dap *dap)
  337. {
  338. assert(dap->ops != NULL);
  339. return dap->ops->run(dap);
  340. }
  341. /** Accessor for currently selected DAP-AP number (0..255) */
  342. static inline uint8_t dap_ap_get_select(struct adiv5_dap *swjdp)
  343. {
  344. return (uint8_t)(swjdp->ap_current >> 24);
  345. }
  346. /* AP selection applies to future AP transactions */
  347. void dap_ap_select(struct adiv5_dap *dap, uint8_t ap);
  348. /* Queued AP transactions */
  349. int dap_setup_accessport(struct adiv5_dap *swjdp,
  350. uint32_t csw, uint32_t tar);
  351. /* Queued MEM-AP memory mapped single word transfers */
  352. int mem_ap_read_u32(struct adiv5_dap *swjdp, uint32_t address, uint32_t *value);
  353. int mem_ap_write_u32(struct adiv5_dap *swjdp, uint32_t address, uint32_t value);
  354. /* Synchronous MEM-AP memory mapped single word transfers */
  355. int mem_ap_read_atomic_u32(struct adiv5_dap *swjdp,
  356. uint32_t address, uint32_t *value);
  357. int mem_ap_write_atomic_u32(struct adiv5_dap *swjdp,
  358. uint32_t address, uint32_t value);
  359. /* MEM-AP memory mapped bus block transfers */
  360. int mem_ap_read_buf_u8(struct adiv5_dap *swjdp,
  361. uint8_t *buffer, int count, uint32_t address);
  362. int mem_ap_read_buf_u16(struct adiv5_dap *swjdp,
  363. uint8_t *buffer, int count, uint32_t address);
  364. int mem_ap_read_buf_u32(struct adiv5_dap *swjdp,
  365. uint8_t *buffer, int count, uint32_t address, bool addr_incr);
  366. int mem_ap_write_buf_u8(struct adiv5_dap *swjdp,
  367. const uint8_t *buffer, int count, uint32_t address);
  368. int mem_ap_write_buf_u16(struct adiv5_dap *swjdp,
  369. const uint8_t *buffer, int count, uint32_t address);
  370. int mem_ap_write_buf_u32(struct adiv5_dap *swjdp,
  371. const uint8_t *buffer, int count, uint32_t address, bool addr_incr);
  372. /* Queued MEM-AP memory mapped single word transfers with selection of ap */
  373. int mem_ap_sel_read_u32(struct adiv5_dap *swjdp, uint8_t ap,
  374. uint32_t address, uint32_t *value);
  375. int mem_ap_sel_write_u32(struct adiv5_dap *swjdp, uint8_t ap,
  376. uint32_t address, uint32_t value);
  377. /* Synchronous MEM-AP memory mapped single word transfers with selection of ap */
  378. int mem_ap_sel_read_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
  379. uint32_t address, uint32_t *value);
  380. int mem_ap_sel_write_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
  381. uint32_t address, uint32_t value);
  382. /* Non incrementing buffer functions for accessing fifos */
  383. int mem_ap_sel_read_buf_u32_noincr(struct adiv5_dap *swjdp, uint8_t ap,
  384. uint8_t *buffer, int count, uint32_t address);
  385. int mem_ap_sel_write_buf_u32_noincr(struct adiv5_dap *swjdp, uint8_t ap,
  386. const uint8_t *buffer, int count, uint32_t address);
  387. /* MEM-AP memory mapped bus block transfers with selection of ap */
  388. int mem_ap_sel_read_buf_u8(struct adiv5_dap *swjdp, uint8_t ap,
  389. uint8_t *buffer, int count, uint32_t address);
  390. int mem_ap_sel_read_buf_u16(struct adiv5_dap *swjdp, uint8_t ap,
  391. uint8_t *buffer, int count, uint32_t address);
  392. int mem_ap_sel_read_buf_u32(struct adiv5_dap *swjdp, uint8_t ap,
  393. uint8_t *buffer, int count, uint32_t address);
  394. int mem_ap_sel_write_buf_u8(struct adiv5_dap *swjdp, uint8_t ap,
  395. const uint8_t *buffer, int count, uint32_t address);
  396. int mem_ap_sel_write_buf_u16(struct adiv5_dap *swjdp, uint8_t ap,
  397. const uint8_t *buffer, int count, uint32_t address);
  398. int mem_ap_sel_write_buf_u32(struct adiv5_dap *swjdp, uint8_t ap,
  399. const uint8_t *buffer, int count, uint32_t address);
  400. /* Initialisation of the debug system, power domains and registers */
  401. int ahbap_debugport_init(struct adiv5_dap *swjdp);
  402. /* Probe the AP for ROM Table location */
  403. int dap_get_debugbase(struct adiv5_dap *dap, int ap,
  404. uint32_t *dbgbase, uint32_t *apid);
  405. /* Probe Access Ports to find a particular type */
  406. int dap_find_ap(struct adiv5_dap *dap,
  407. enum ap_type type_to_find,
  408. uint8_t *ap_num_out);
  409. /* Lookup CoreSight component */
  410. int dap_lookup_cs_component(struct adiv5_dap *dap, int ap,
  411. uint32_t dbgbase, uint8_t type, uint32_t *addr);
  412. struct target;
  413. /* Put debug link into SWD mode */
  414. int dap_to_swd(struct target *target);
  415. /* Put debug link into JTAG mode */
  416. int dap_to_jtag(struct target *target);
  417. extern const struct command_registration dap_command_handlers[];
  418. #endif