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  1. #
  2. # For each named Cortex-M3 vector_catch flag VECTOR ...
  3. # bus_err state_err
  4. # chk_err nocp_err
  5. # mm_err reset
  6. #
  7. # BUT NYET hard_err, int_err (their test cases don't yet work) ...
  8. #
  9. # Do the following:
  10. #
  11. # - Test #1: verify that OpenOCD ignores exceptions by default
  12. # + l_VECTOR (loads testcase to RAM)
  13. # + fault triggers loop-to-self exception "handler"
  14. # + "halt"
  15. # + observe fault "handling" -- loop-to-self from load_and_run (below)
  16. #
  17. # - Test #2: verify that "vector_catch" makes OpenOCD stops ignoring them
  18. # + cortex_m3 vector_catch none
  19. # + cortex_m3 vector_catch VECTOR
  20. # + l_VECTOR (loads testcase to RAM)
  21. # + fault triggers vector catch hardware
  22. # + observe OpenOCD entering debug state with no assistance
  23. #
  24. # NOTE "reset" includes the NVIC, so that test case gets its reset vector
  25. # from the flash, not from the vector table set up here. Which means that
  26. # for that vector_catch option, the Test #1 (above) "observe" step won't
  27. # use the SRAM address.
  28. #
  29. # we can fully automate test #2
  30. proc vector_test {tag} {
  31. halt
  32. # REVISIT -- annoying, we'd like to scrap vector_catch output
  33. cortex_m3 vector_catch none
  34. cortex_m3 vector_catch $tag
  35. eval "l_$tag"
  36. }
  37. #
  38. # Load and start one vector_catch test case.
  39. #
  40. # name -- tag for the vector_catch flag being tested
  41. # halfwords -- array of instructions (some wide, some narrow)
  42. # n_instr -- how many instructions are in $halfwords
  43. #
  44. proc load_and_run { name halfwords n_instr } {
  45. reset halt
  46. # Load code at beginning of SRAM.
  47. echo "# code to trigger $name vector"
  48. set addr 0x20000000
  49. # ocd_array2mem should be faster, though we'd need to
  50. # compute the resulting $addr ourselves
  51. foreach opcode $halfwords {
  52. mwh $addr $opcode
  53. incr addr 2
  54. }
  55. # create default loop-to-self at $addr ... it serves as
  56. # (a) "main loop" on error
  57. # (b) handler for all exceptions that get triggered
  58. mwh $addr 0xe7fe
  59. # disassemble, as sanity check and what's-happening trace
  60. arm disassemble 0x20000000 [expr 1 + $n_instr ]
  61. # Assume that block of code is at most 16 halfwords long.
  62. # Create a basic table of loop-to-self exception handlers.
  63. mww 0x20000020 $addr 16
  64. # Store its address in VTOR
  65. mww 0xe000ed08 0x20000020
  66. # Use SHCSR to ensure nothing escalates to a HardFault
  67. mww 0xe000ed24 0x00070000
  68. # now start, trigering the $name vector catch logic
  69. resume 0x20000000
  70. }
  71. #proc l_hard_err {} {
  72. # IMPLEMENT ME
  73. # FORCED -- escalate something to HardFault
  74. #}
  75. #proc l_int_err {} {
  76. # IMPLEMENT ME
  77. # STKERR -- exception stack BusFault
  78. #}
  79. # BusFault, escalates to HardFault
  80. proc l_bus_err {} {
  81. # PRECISERR -- assume less than 512 MBytes of SRAM
  82. load_and_run bus_err {
  83. 0xf06f 0x4040
  84. 0x7800
  85. } 2
  86. }
  87. # UsageFault, escalates to HardFault
  88. proc l_state_err {} {
  89. # UNDEFINSTR -- issue architecturally undefined instruction
  90. load_and_run state_err {
  91. 0xde00
  92. } 1
  93. }
  94. # UsageFault, escalates to HardFault
  95. proc l_chk_err {} {
  96. # UNALIGNED -- LDM through unaligned pointer
  97. load_and_run chk_err {
  98. 0xf04f 0x0001
  99. 0xe890 0x0006
  100. } 2
  101. }
  102. # UsageFault, escalates to HardFault
  103. proc l_nocp_err {} {
  104. # NOCP -- issue cp14 DCC instruction
  105. load_and_run nocp_err {
  106. 0xee10 0x0e15
  107. } 1
  108. }
  109. # MemManage, escalates to HardFault
  110. proc l_mm_err {} {
  111. # IACCVIOL -- instruction fetch from an XN region
  112. load_and_run mm_err {
  113. 0xf04f 0x4060
  114. 0x4687
  115. } 2
  116. }
  117. proc l_reset {} {
  118. # issue SYSRESETREQ via AIRCR
  119. load_and_run reset {
  120. 0xf04f 0x0104
  121. 0xf2c0 0x51fa
  122. 0xf44f 0x406d
  123. 0xf100 0x000c
  124. 0xf2ce 0x0000
  125. 0x6001
  126. } 6
  127. }