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  1. /***************************************************************************
  2. * Copyright (C) 2005 by Dominic Rath *
  3. * Dominic.Rath@gmx.de *
  4. * *
  5. * Copyright (C) 2008 by Spencer Oliver *
  6. * spen@spen-soft.co.uk *
  7. * *
  8. * Copyright (C) 2011 Øyvind Harboe *
  9. * oyvind.harboe@zylin.com *
  10. * *
  11. * This program is free software; you can redistribute it and/or modify *
  12. * it under the terms of the GNU General Public License as published by *
  13. * the Free Software Foundation; either version 2 of the License, or *
  14. * (at your option) any later version. *
  15. * *
  16. * This program is distributed in the hope that it will be useful, *
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  19. * GNU General Public License for more details. *
  20. * *
  21. * You should have received a copy of the GNU General Public License *
  22. * along with this program; if not, write to the *
  23. * Free Software Foundation, Inc., *
  24. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
  25. ***************************************************************************/
  26. #ifdef HAVE_CONFIG_H
  27. #include "config.h"
  28. #endif
  29. #include "imp.h"
  30. #include <helper/binarybuffer.h>
  31. #include <target/algorithm.h>
  32. #include <target/armv7m.h>
  33. /* Regarding performance:
  34. *
  35. * Short story - it might be best to leave the performance at
  36. * current levels.
  37. *
  38. * You may see a jump in speed if you change to using
  39. * 32bit words for the block programming.
  40. *
  41. * Its a shame you cannot use the double word as its
  42. * even faster - but you require external VPP for that mode.
  43. *
  44. * Having said all that 16bit writes give us the widest vdd
  45. * operating range, so may be worth adding a note to that effect.
  46. *
  47. */
  48. /* Danger!!!! The STM32F1xxxx and STM32F2xxxx series actually have
  49. * quite different flash controllers.
  50. *
  51. * What's more scary is that the names of the registers and their
  52. * addresses are the same, but the actual bits and what they do are
  53. * can be very different.
  54. *
  55. * To reduce testing complexity and dangers of regressions,
  56. * a seperate file is used for stm32fx2222.
  57. *
  58. * 1mByte part with 4 x 16, 1 x 64, 7 x 128kBytes sectors
  59. *
  60. * What's the protection page size???
  61. *
  62. * Tested with STM3220F-EVAL board.
  63. *
  64. * STM32F21xx series for reference.
  65. *
  66. * RM0033
  67. * http://www.st.com/internet/mcu/product/250192.jsp
  68. *
  69. * PM0059
  70. * www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/PROGRAMMING_MANUAL/CD00233952.pdf
  71. *
  72. * STM32F1xxx series - notice that this code was copy, pasted and knocked
  73. * into a stm32f2xxx driver, so in case something has been converted or
  74. * bugs haven't been fixed, here are the original manuals:
  75. *
  76. * RM0008 - Reference manual
  77. *
  78. * RM0042, the Flash programming manual for low-, medium- high-density and
  79. * connectivity line STM32F10xxx devices
  80. *
  81. * PM0068, the Flash programming manual for XL-density STM32F10xxx devices.
  82. *
  83. */
  84. // Erase time can be as high as 1000ms, 10x this and it's toast...
  85. #define FLASH_ERASE_TIMEOUT 10000
  86. #define FLASH_WRITE_TIMEOUT 5
  87. #define STM32_FLASH_BASE 0x40023c00
  88. #define STM32_FLASH_ACR 0x40023c00
  89. #define STM32_FLASH_KEYR 0x40023c04
  90. #define STM32_FLASH_OPTKEYR 0x40023c08
  91. #define STM32_FLASH_SR 0x40023c0C
  92. #define STM32_FLASH_CR 0x40023c10
  93. #define STM32_FLASH_OPTCR 0x40023c14
  94. #define STM32_FLASH_OBR 0x40023c1C
  95. /* option byte location */
  96. #define STM32_OB_RDP 0x1FFFF800
  97. #define STM32_OB_USER 0x1FFFF802
  98. #define STM32_OB_DATA0 0x1FFFF804
  99. #define STM32_OB_DATA1 0x1FFFF806
  100. #define STM32_OB_WRP0 0x1FFFF808
  101. #define STM32_OB_WRP1 0x1FFFF80A
  102. #define STM32_OB_WRP2 0x1FFFF80C
  103. #define STM32_OB_WRP3 0x1FFFF80E
  104. /* FLASH_CR register bits */
  105. #define FLASH_PG (1 << 0)
  106. #define FLASH_SER (1 << 1)
  107. #define FLASH_MER (1 << 2)
  108. #define FLASH_STRT (1 << 16)
  109. #define FLASH_PSIZE_8 (0 << 8)
  110. #define FLASH_PSIZE_16 (1 << 8)
  111. #define FLASH_PSIZE_32 (2 << 8)
  112. #define FLASH_PSIZE_64 (3 << 8)
  113. #define FLASH_SNB(a) ((a) << 3)
  114. #define FLASH_LOCK (1 << 31)
  115. /* FLASH_SR register bits */
  116. #define FLASH_BSY (1 << 16)
  117. #define FLASH_PGSERR (1 << 7) // Programming sequence error
  118. #define FLASH_PGPERR (1 << 6) // Programming parallelism error
  119. #define FLASH_PGAERR (1 << 5) // Programming alignment error
  120. #define FLASH_WRPERR (1 << 4) // Write protection error
  121. #define FLASH_OPERR (1 << 1) // Operation error
  122. #define FLASH_ERROR (FLASH_PGSERR | FLASH_PGPERR | FLASH_PGAERR| FLASH_WRPERR| FLASH_OPERR)
  123. /* STM32_FLASH_OBR bit definitions (reading) */
  124. #define OPT_ERROR 0
  125. #define OPT_READOUT 1
  126. #define OPT_RDWDGSW 2
  127. #define OPT_RDRSTSTOP 3
  128. #define OPT_RDRSTSTDBY 4
  129. #define OPT_BFB2 5 /* dual flash bank only */
  130. /* register unlock keys */
  131. #define KEY1 0x45670123
  132. #define KEY2 0xCDEF89AB
  133. struct stm32x_flash_bank
  134. {
  135. struct working_area *write_algorithm;
  136. int probed;
  137. };
  138. /* flash bank stm32x <base> <size> 0 0 <target#>
  139. */
  140. FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
  141. {
  142. struct stm32x_flash_bank *stm32x_info;
  143. if (CMD_ARGC < 6)
  144. {
  145. LOG_WARNING("incomplete flash_bank stm32x configuration");
  146. return ERROR_FLASH_BANK_INVALID;
  147. }
  148. stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
  149. bank->driver_priv = stm32x_info;
  150. stm32x_info->write_algorithm = NULL;
  151. stm32x_info->probed = 0;
  152. return ERROR_OK;
  153. }
  154. static inline int stm32x_get_flash_reg(struct flash_bank *bank, uint32_t reg)
  155. {
  156. return reg;
  157. }
  158. static inline int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
  159. {
  160. struct target *target = bank->target;
  161. return target_read_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), status);
  162. }
  163. static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
  164. {
  165. struct target *target = bank->target;
  166. uint32_t status;
  167. int retval = ERROR_OK;
  168. /* wait for busy to clear */
  169. for (;;)
  170. {
  171. retval = stm32x_get_flash_status(bank, &status);
  172. if (retval != ERROR_OK)
  173. return retval;
  174. LOG_DEBUG("status: 0x%" PRIx32 "", status);
  175. if ((status & FLASH_BSY) == 0)
  176. break;
  177. if (timeout-- <= 0)
  178. {
  179. LOG_ERROR("timed out waiting for flash");
  180. return ERROR_FAIL;
  181. }
  182. alive_sleep(1);
  183. }
  184. if (status & FLASH_WRPERR)
  185. {
  186. LOG_ERROR("stm32x device protected");
  187. retval = ERROR_FAIL;
  188. }
  189. /* Clear but report errors */
  190. if (status & FLASH_ERROR)
  191. {
  192. /* If this operation fails, we ignore it and report the original
  193. * retval
  194. */
  195. target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR),
  196. status & FLASH_ERROR);
  197. }
  198. return retval;
  199. }
  200. static int stm32x_unlock_reg(struct target *target)
  201. {
  202. /* unlock flash registers */
  203. int retval = target_write_u32(target, STM32_FLASH_KEYR, KEY1);
  204. if (retval != ERROR_OK)
  205. return retval;
  206. retval = target_write_u32(target, STM32_FLASH_KEYR, KEY2);
  207. if (retval != ERROR_OK)
  208. return retval;
  209. return ERROR_OK;
  210. }
  211. static int stm32x_protect_check(struct flash_bank *bank)
  212. {
  213. return ERROR_OK;
  214. }
  215. static int stm32x_erase(struct flash_bank *bank, int first, int last)
  216. {
  217. struct target *target = bank->target;
  218. int i;
  219. if (bank->target->state != TARGET_HALTED)
  220. {
  221. LOG_ERROR("Target not halted");
  222. return ERROR_TARGET_NOT_HALTED;
  223. }
  224. int retval;
  225. retval = stm32x_unlock_reg(target);
  226. if (retval != ERROR_OK)
  227. return retval;
  228. /*
  229. Sector Erase
  230. To erase a sector, follow the procedure below:
  231. 1. Check that no Flash memory operation is ongoing by checking the BSY bit in the
  232. FLASH_SR register
  233. 2. Set the SER bit and select the sector (out of the 12 sectors in the main memory block)
  234. you wish to erase (SNB) in the FLASH_CR register
  235. 3. Set the STRT bit in the FLASH_CR register
  236. 4. Wait for the BSY bit to be cleared
  237. */
  238. for (i = first; i <= last; i++)
  239. {
  240. retval = target_write_u32(target,
  241. stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_SER | FLASH_SNB(i) | FLASH_STRT);
  242. if (retval != ERROR_OK)
  243. return retval;
  244. retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
  245. if (retval != ERROR_OK)
  246. return retval;
  247. bank->sectors[i].is_erased = 1;
  248. }
  249. retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
  250. if (retval != ERROR_OK)
  251. return retval;
  252. return ERROR_OK;
  253. }
  254. static int stm32x_protect(struct flash_bank *bank, int set, int first, int last)
  255. {
  256. return ERROR_OK;
  257. }
  258. static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer,
  259. uint32_t offset, uint32_t count)
  260. {
  261. struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
  262. struct target *target = bank->target;
  263. uint32_t buffer_size = 16384;
  264. struct working_area *source;
  265. uint32_t address = bank->base + offset;
  266. struct reg_param reg_params[5];
  267. struct armv7m_algorithm armv7m_info;
  268. int retval = ERROR_OK;
  269. /* see contib/loaders/flash/stm32x.s for src */
  270. static const uint16_t stm32x_flash_write_code_16[] = {
  271. // 00000000 <write>:
  272. 0x4b07, // ldr r3, [pc, #28] (20 <STM32_PROG16>)
  273. 0x6123, // str r3, [r4, #16]
  274. 0xf830, 0x3b02, //ldrh.w r3, [r0], #2
  275. 0xf821, 0x3b02, //strh.w r3, [r1], #2
  276. //0000000c <busy>:
  277. 0x68e3, //ldr r3, [r4, #12]
  278. 0xf413, 0x3f80, // tst.w r3, #65536 ; 0x10000
  279. 0xd0fb, //beq.n c <busy>
  280. 0xf013, 0x0ff0, //tst.w r3, #240 ; 0xf0
  281. 0xd101, //bne.n 1e <exit>
  282. 0x3a01, //subs r2, #1
  283. 0xd1f0, //bne.n 0 <write>
  284. //0000001e <exit>:
  285. 0xbe00, // bkpt 0x0000
  286. //00000020 <STM32_PROG16>:
  287. 0x0101, 0x0000, // .word 0x00000101
  288. };
  289. // Flip endian
  290. uint8_t stm32x_flash_write_code[sizeof(stm32x_flash_write_code_16)*2];
  291. for (unsigned i = 0; i < sizeof(stm32x_flash_write_code_16) / 2; i++)
  292. {
  293. stm32x_flash_write_code[i*2 + 0] = stm32x_flash_write_code_16[i] & 0xff;
  294. stm32x_flash_write_code[i*2 + 1] = (stm32x_flash_write_code_16[i] >> 8) & 0xff;
  295. }
  296. if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
  297. &stm32x_info->write_algorithm) != ERROR_OK)
  298. {
  299. LOG_WARNING("no working area available, can't do block memory writes");
  300. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  301. };
  302. if ((retval = target_write_buffer(target, stm32x_info->write_algorithm->address,
  303. sizeof(stm32x_flash_write_code),
  304. (uint8_t*)stm32x_flash_write_code)) != ERROR_OK)
  305. return retval;
  306. /* memory buffer */
  307. while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK)
  308. {
  309. buffer_size /= 2;
  310. if (buffer_size <= 256)
  311. {
  312. /* if we already allocated the writing code, but failed to get a
  313. * buffer, free the algorithm */
  314. if (stm32x_info->write_algorithm)
  315. target_free_working_area(target, stm32x_info->write_algorithm);
  316. LOG_WARNING("no large enough working area available, can't do block memory writes");
  317. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  318. }
  319. };
  320. armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
  321. armv7m_info.core_mode = ARMV7M_MODE_ANY;
  322. init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
  323. init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
  324. init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
  325. init_reg_param(&reg_params[3], "r3", 32, PARAM_IN_OUT);
  326. init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT);
  327. while (count > 0)
  328. {
  329. uint32_t thisrun_count = (count > (buffer_size / 2)) ?
  330. (buffer_size / 2) : count;
  331. if ((retval = target_write_buffer(target, source->address,
  332. thisrun_count * 2, buffer)) != ERROR_OK)
  333. break;
  334. buf_set_u32(reg_params[0].value, 0, 32, source->address);
  335. buf_set_u32(reg_params[1].value, 0, 32, address);
  336. buf_set_u32(reg_params[2].value, 0, 32, thisrun_count);
  337. // R3 is a return value only
  338. buf_set_u32(reg_params[4].value, 0, 32, STM32_FLASH_BASE);
  339. if ((retval = target_run_algorithm(target, 0, NULL,
  340. sizeof(reg_params) / sizeof(*reg_params),
  341. reg_params,
  342. stm32x_info->write_algorithm->address,
  343. 0,
  344. 10000, &armv7m_info)) != ERROR_OK)
  345. {
  346. LOG_ERROR("error executing stm32x flash write algorithm");
  347. break;
  348. }
  349. uint32_t error = buf_get_u32(reg_params[3].value, 0, 32) & FLASH_ERROR;
  350. if (error & FLASH_WRPERR)
  351. {
  352. LOG_ERROR("flash memory write protected");
  353. }
  354. if (error != 0)
  355. {
  356. LOG_ERROR("flash write failed = %08x", error);
  357. /* Clear but report errors */
  358. target_write_u32(target, STM32_FLASH_SR, error);
  359. retval = ERROR_FAIL;
  360. break;
  361. }
  362. buffer += thisrun_count * 2;
  363. address += thisrun_count * 2;
  364. count -= thisrun_count;
  365. }
  366. target_free_working_area(target, source);
  367. target_free_working_area(target, stm32x_info->write_algorithm);
  368. destroy_reg_param(&reg_params[0]);
  369. destroy_reg_param(&reg_params[1]);
  370. destroy_reg_param(&reg_params[2]);
  371. destroy_reg_param(&reg_params[3]);
  372. destroy_reg_param(&reg_params[4]);
  373. return retval;
  374. }
  375. static int stm32x_write(struct flash_bank *bank, uint8_t *buffer,
  376. uint32_t offset, uint32_t count)
  377. {
  378. struct target *target = bank->target;
  379. uint32_t words_remaining = (count / 2);
  380. uint32_t bytes_remaining = (count & 0x00000001);
  381. uint32_t address = bank->base + offset;
  382. uint32_t bytes_written = 0;
  383. int retval;
  384. if (bank->target->state != TARGET_HALTED)
  385. {
  386. LOG_ERROR("Target not halted");
  387. return ERROR_TARGET_NOT_HALTED;
  388. }
  389. if (offset & 0x1)
  390. {
  391. LOG_WARNING("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
  392. return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
  393. }
  394. retval = stm32x_unlock_reg(target);
  395. if (retval != ERROR_OK)
  396. return retval;
  397. /* multiple half words (2-byte) to be programmed? */
  398. if (words_remaining > 0)
  399. {
  400. /* try using a block write */
  401. if ((retval = stm32x_write_block(bank, buffer, offset, words_remaining)) != ERROR_OK)
  402. {
  403. if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
  404. {
  405. /* if block write failed (no sufficient working area),
  406. * we use normal (slow) single dword accesses */
  407. LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
  408. }
  409. }
  410. else
  411. {
  412. buffer += words_remaining * 2;
  413. address += words_remaining * 2;
  414. words_remaining = 0;
  415. }
  416. }
  417. if ((retval != ERROR_OK) && (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE))
  418. return retval;
  419. /*
  420. Standard programming
  421. The Flash memory programming sequence is as follows:
  422. 1. Check that no main Flash memory operation is ongoing by checking the BSY bit in the
  423. FLASH_SR register.
  424. 2. Set the PG bit in the FLASH_CR register
  425. 3. Perform the data write operation(s) to the desired memory address (inside main
  426. memory block or OTP area):
  427. – – Half-word access in case of x16 parallelism
  428. – Word access in case of x32 parallelism
  429. 4.
  430. Byte access in case of x8 parallelism
  431. Double word access in case of x64 parallelism
  432. Wait for the BSY bit to be cleared
  433. */
  434. while (words_remaining > 0)
  435. {
  436. uint16_t value;
  437. memcpy(&value, buffer + bytes_written, sizeof(uint16_t));
  438. retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR),
  439. FLASH_PG | FLASH_PSIZE_16);
  440. if (retval != ERROR_OK)
  441. return retval;
  442. retval = target_write_u16(target, address, value);
  443. if (retval != ERROR_OK)
  444. return retval;
  445. retval = stm32x_wait_status_busy(bank, FLASH_WRITE_TIMEOUT);
  446. if (retval != ERROR_OK)
  447. return retval;
  448. bytes_written += 2;
  449. words_remaining--;
  450. address += 2;
  451. }
  452. if (bytes_remaining)
  453. {
  454. retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR),
  455. FLASH_PG | FLASH_PSIZE_8);
  456. if (retval != ERROR_OK)
  457. return retval;
  458. retval = target_write_u8(target, address, buffer[bytes_written]);
  459. if (retval != ERROR_OK)
  460. return retval;
  461. retval = stm32x_wait_status_busy(bank, FLASH_WRITE_TIMEOUT);
  462. if (retval != ERROR_OK)
  463. return retval;
  464. }
  465. return target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
  466. }
  467. static void setup_sector(struct flash_bank *bank, int start, int num, int size)
  468. {
  469. for (int i = start; i < (start + num) ; i++)
  470. {
  471. bank->sectors[i].offset = bank->size;
  472. bank->sectors[i].size = size;
  473. bank->size += bank->sectors[i].size;
  474. }
  475. }
  476. static int stm32x_probe(struct flash_bank *bank)
  477. {
  478. struct target *target = bank->target;
  479. struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
  480. int i;
  481. uint16_t num_pages;
  482. uint32_t device_id;
  483. uint32_t base_address = 0x08000000;
  484. stm32x_info->probed = 0;
  485. /* read stm32 device id register */
  486. int retval = target_read_u32(target, 0xE0042000, &device_id);
  487. if (retval != ERROR_OK)
  488. return retval;
  489. LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
  490. /* get flash size from target. */
  491. retval = target_read_u16(target, 0x1FFFF7E0, &num_pages);
  492. if (retval != ERROR_OK)
  493. {
  494. LOG_WARNING("failed reading flash size, default to max target family");
  495. /* failed reading flash size, default to max target family */
  496. num_pages = 0xffff;
  497. }
  498. if ((device_id & 0x7ff) != 0x411)
  499. {
  500. LOG_WARNING("Cannot identify target as a STM32 family, try the other STM32 drivers.");
  501. return ERROR_FAIL;
  502. }
  503. /* sectors sizes vary, handle this in a different code path
  504. * than the rest.
  505. */
  506. // Uhhh.... what to use here?
  507. /* calculate numbers of pages*/
  508. num_pages = 4 + 1 + 7;
  509. if (bank->sectors)
  510. {
  511. free(bank->sectors);
  512. bank->sectors = NULL;
  513. }
  514. bank->base = base_address;
  515. bank->num_sectors = num_pages;
  516. bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
  517. bank->size = 0;
  518. setup_sector(bank, 0, 4, 16 * 1024);
  519. setup_sector(bank, 4, 1, 64 * 1024);
  520. setup_sector(bank, 4+1, 7, 128 * 1024);
  521. for (i = 0; i < num_pages; i++)
  522. {
  523. bank->sectors[i].is_erased = -1;
  524. bank->sectors[i].is_protected = 0;
  525. }
  526. LOG_INFO("flash size = %dkBytes", bank->size / 1024);
  527. stm32x_info->probed = 1;
  528. return ERROR_OK;
  529. }
  530. static int stm32x_auto_probe(struct flash_bank *bank)
  531. {
  532. struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
  533. if (stm32x_info->probed)
  534. return ERROR_OK;
  535. return stm32x_probe(bank);
  536. }
  537. static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
  538. {
  539. struct target *target = bank->target;
  540. uint32_t device_id;
  541. int printed;
  542. /* read stm32 device id register */
  543. int retval = target_read_u32(target, 0xE0042000, &device_id);
  544. if (retval != ERROR_OK)
  545. return retval;
  546. if ((device_id & 0x7ff) == 0x411)
  547. {
  548. printed = snprintf(buf, buf_size, "stm32x (1mByte part) - Rev: ");
  549. buf += printed;
  550. buf_size -= printed;
  551. switch (device_id >> 16)
  552. {
  553. case 0x1000:
  554. snprintf(buf, buf_size, "A");
  555. break;
  556. case 0x2000:
  557. snprintf(buf, buf_size, "B");
  558. break;
  559. case 0x1001:
  560. snprintf(buf, buf_size, "Z");
  561. break;
  562. default:
  563. snprintf(buf, buf_size, "unknown");
  564. break;
  565. }
  566. }
  567. else
  568. {
  569. snprintf(buf, buf_size, "Cannot identify target as a stm32x\n");
  570. return ERROR_FAIL;
  571. }
  572. return ERROR_OK;
  573. }
  574. static const struct command_registration stm32x_exec_command_handlers[] = {
  575. COMMAND_REGISTRATION_DONE
  576. };
  577. static const struct command_registration stm32x_command_handlers[] = {
  578. {
  579. .name = "stm32f2xxx",
  580. .mode = COMMAND_ANY,
  581. .help = "stm32f2xxx flash command group",
  582. .chain = stm32x_exec_command_handlers,
  583. },
  584. COMMAND_REGISTRATION_DONE
  585. };
  586. struct flash_driver stm32xf2xxx_flash = {
  587. .name = "stm32f2xxx",
  588. .commands = stm32x_command_handlers,
  589. .flash_bank_command = stm32x_flash_bank_command,
  590. .erase = stm32x_erase,
  591. .protect = stm32x_protect,
  592. .write = stm32x_write,
  593. .read = default_flash_read,
  594. .probe = stm32x_probe,
  595. .auto_probe = stm32x_auto_probe,
  596. .erase_check = default_flash_mem_blank_check,
  597. .protect_check = stm32x_protect_check,
  598. .info = get_stm32x_info,
  599. };