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  1. /***************************************************************************
  2. * Copyright (C) 2006, 2007 by Dominic Rath *
  3. * Dominic.Rath@gmx.de *
  4. * *
  5. * Copyright (C) 2007,2008 Øyvind Harboe *
  6. * oyvind.harboe@zylin.com *
  7. * *
  8. * Copyright (C) 2009 Michael Schwingen *
  9. * michael@schwingen.org *
  10. * *
  11. * This program is free software; you can redistribute it and/or modify *
  12. * it under the terms of the GNU General Public License as published by *
  13. * the Free Software Foundation; either version 2 of the License, or *
  14. * (at your option) any later version. *
  15. * *
  16. * This program is distributed in the hope that it will be useful, *
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  19. * GNU General Public License for more details. *
  20. * *
  21. * You should have received a copy of the GNU General Public License *
  22. * along with this program; if not, write to the *
  23. * Free Software Foundation, Inc., *
  24. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
  25. ***************************************************************************/
  26. #ifdef HAVE_CONFIG_H
  27. #include "config.h"
  28. #endif
  29. #include "xscale.h"
  30. #include "target_type.h"
  31. #include "arm7_9_common.h"
  32. #include "arm_simulator.h"
  33. #include "arm_disassembler.h"
  34. #include "time_support.h"
  35. #include "image.h"
  36. /*
  37. * Important XScale documents available as of October 2009 include:
  38. *
  39. * Intel XScale® Core Developer’s Manual, January 2004
  40. * Order Number: 273473-002
  41. * This has a chapter detailing debug facilities, and punts some
  42. * details to chip-specific microarchitecture documentats.
  43. *
  44. * Hot-Debug for Intel XScale® Core Debug White Paper, May 2005
  45. * Document Number: 273539-005
  46. * Less detailed than the developer's manual, but summarizes those
  47. * missing details (for most XScales) and gives LOTS of notes about
  48. * debugger/handler interaction issues. Presents a simpler reset
  49. * and load-handler sequence than the arch doc. (Note, OpenOCD
  50. * doesn't currently support "Hot-Debug" as defined there.)
  51. *
  52. * Chip-specific microarchitecture documents may also be useful.
  53. */
  54. /* forward declarations */
  55. static int xscale_resume(struct target_s *, int current,
  56. uint32_t address, int handle_breakpoints, int debug_execution);
  57. static int xscale_debug_entry(target_t *);
  58. static int xscale_restore_context(target_t *);
  59. static int xscale_get_reg(reg_t *reg);
  60. static int xscale_set_reg(reg_t *reg, uint8_t *buf);
  61. static int xscale_set_breakpoint(struct target_s *, breakpoint_t *);
  62. static int xscale_set_watchpoint(struct target_s *, watchpoint_t *);
  63. static int xscale_unset_breakpoint(struct target_s *, breakpoint_t *);
  64. static int xscale_read_trace(target_t *);
  65. static char *const xscale_reg_list[] =
  66. {
  67. "XSCALE_MAINID", /* 0 */
  68. "XSCALE_CACHETYPE",
  69. "XSCALE_CTRL",
  70. "XSCALE_AUXCTRL",
  71. "XSCALE_TTB",
  72. "XSCALE_DAC",
  73. "XSCALE_FSR",
  74. "XSCALE_FAR",
  75. "XSCALE_PID",
  76. "XSCALE_CPACCESS",
  77. "XSCALE_IBCR0", /* 10 */
  78. "XSCALE_IBCR1",
  79. "XSCALE_DBR0",
  80. "XSCALE_DBR1",
  81. "XSCALE_DBCON",
  82. "XSCALE_TBREG",
  83. "XSCALE_CHKPT0",
  84. "XSCALE_CHKPT1",
  85. "XSCALE_DCSR",
  86. "XSCALE_TX",
  87. "XSCALE_RX", /* 20 */
  88. "XSCALE_TXRXCTRL",
  89. };
  90. static const xscale_reg_t xscale_reg_arch_info[] =
  91. {
  92. {XSCALE_MAINID, NULL},
  93. {XSCALE_CACHETYPE, NULL},
  94. {XSCALE_CTRL, NULL},
  95. {XSCALE_AUXCTRL, NULL},
  96. {XSCALE_TTB, NULL},
  97. {XSCALE_DAC, NULL},
  98. {XSCALE_FSR, NULL},
  99. {XSCALE_FAR, NULL},
  100. {XSCALE_PID, NULL},
  101. {XSCALE_CPACCESS, NULL},
  102. {XSCALE_IBCR0, NULL},
  103. {XSCALE_IBCR1, NULL},
  104. {XSCALE_DBR0, NULL},
  105. {XSCALE_DBR1, NULL},
  106. {XSCALE_DBCON, NULL},
  107. {XSCALE_TBREG, NULL},
  108. {XSCALE_CHKPT0, NULL},
  109. {XSCALE_CHKPT1, NULL},
  110. {XSCALE_DCSR, NULL}, /* DCSR accessed via JTAG or SW */
  111. {-1, NULL}, /* TX accessed via JTAG */
  112. {-1, NULL}, /* RX accessed via JTAG */
  113. {-1, NULL}, /* TXRXCTRL implicit access via JTAG */
  114. };
  115. static int xscale_reg_arch_type = -1;
  116. /* convenience wrapper to access XScale specific registers */
  117. static int xscale_set_reg_u32(reg_t *reg, uint32_t value)
  118. {
  119. uint8_t buf[4];
  120. buf_set_u32(buf, 0, 32, value);
  121. return xscale_set_reg(reg, buf);
  122. }
  123. static int xscale_get_arch_pointers(target_t *target,
  124. armv4_5_common_t **armv4_5_p, xscale_common_t **xscale_p)
  125. {
  126. armv4_5_common_t *armv4_5 = target->arch_info;
  127. xscale_common_t *xscale = armv4_5->arch_info;
  128. if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
  129. {
  130. LOG_ERROR("target isn't an XScale target");
  131. return -1;
  132. }
  133. if (xscale->common_magic != XSCALE_COMMON_MAGIC)
  134. {
  135. LOG_ERROR("target isn't an XScale target");
  136. return -1;
  137. }
  138. *armv4_5_p = armv4_5;
  139. *xscale_p = xscale;
  140. return ERROR_OK;
  141. }
  142. static int xscale_jtag_set_instr(jtag_tap_t *tap, uint32_t new_instr)
  143. {
  144. if (tap == NULL)
  145. return ERROR_FAIL;
  146. if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr)
  147. {
  148. scan_field_t field;
  149. field.tap = tap;
  150. field.num_bits = tap->ir_length;
  151. field.out_value = calloc(CEIL(field.num_bits, 8), 1);
  152. buf_set_u32(field.out_value, 0, field.num_bits, new_instr);
  153. uint8_t tmp[4];
  154. field.in_value = tmp;
  155. jtag_add_ir_scan(1, &field, jtag_get_end_state());
  156. /* FIX!!!! isn't this check superfluous? verify_ircapture handles this? */
  157. jtag_check_value_mask(&field, tap->expected, tap->expected_mask);
  158. free(field.out_value);
  159. }
  160. return ERROR_OK;
  161. }
  162. static int xscale_read_dcsr(target_t *target)
  163. {
  164. armv4_5_common_t *armv4_5 = target->arch_info;
  165. xscale_common_t *xscale = armv4_5->arch_info;
  166. int retval;
  167. scan_field_t fields[3];
  168. uint8_t field0 = 0x0;
  169. uint8_t field0_check_value = 0x2;
  170. uint8_t field0_check_mask = 0x7;
  171. uint8_t field2 = 0x0;
  172. uint8_t field2_check_value = 0x0;
  173. uint8_t field2_check_mask = 0x1;
  174. jtag_set_end_state(TAP_DRPAUSE);
  175. xscale_jtag_set_instr(target->tap, XSCALE_SELDCSR);
  176. buf_set_u32(&field0, 1, 1, xscale->hold_rst);
  177. buf_set_u32(&field0, 2, 1, xscale->external_debug_break);
  178. fields[0].tap = target->tap;
  179. fields[0].num_bits = 3;
  180. fields[0].out_value = &field0;
  181. uint8_t tmp;
  182. fields[0].in_value = &tmp;
  183. fields[1].tap = target->tap;
  184. fields[1].num_bits = 32;
  185. fields[1].out_value = NULL;
  186. fields[1].in_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
  187. fields[2].tap = target->tap;
  188. fields[2].num_bits = 1;
  189. fields[2].out_value = &field2;
  190. uint8_t tmp2;
  191. fields[2].in_value = &tmp2;
  192. jtag_add_dr_scan(3, fields, jtag_get_end_state());
  193. jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask);
  194. jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask);
  195. if ((retval = jtag_execute_queue()) != ERROR_OK)
  196. {
  197. LOG_ERROR("JTAG error while reading DCSR");
  198. return retval;
  199. }
  200. xscale->reg_cache->reg_list[XSCALE_DCSR].dirty = 0;
  201. xscale->reg_cache->reg_list[XSCALE_DCSR].valid = 1;
  202. /* write the register with the value we just read
  203. * on this second pass, only the first bit of field0 is guaranteed to be 0)
  204. */
  205. field0_check_mask = 0x1;
  206. fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
  207. fields[1].in_value = NULL;
  208. jtag_set_end_state(TAP_IDLE);
  209. jtag_add_dr_scan(3, fields, jtag_get_end_state());
  210. /* DANGER!!! this must be here. It will make sure that the arguments
  211. * to jtag_set_check_value() does not go out of scope! */
  212. return jtag_execute_queue();
  213. }
  214. static void xscale_getbuf(jtag_callback_data_t arg)
  215. {
  216. uint8_t *in = (uint8_t *)arg;
  217. *((uint32_t *)in) = buf_get_u32(in, 0, 32);
  218. }
  219. static int xscale_receive(target_t *target, uint32_t *buffer, int num_words)
  220. {
  221. if (num_words == 0)
  222. return ERROR_INVALID_ARGUMENTS;
  223. int retval = ERROR_OK;
  224. tap_state_t path[3];
  225. scan_field_t fields[3];
  226. uint8_t *field0 = malloc(num_words * 1);
  227. uint8_t field0_check_value = 0x2;
  228. uint8_t field0_check_mask = 0x6;
  229. uint32_t *field1 = malloc(num_words * 4);
  230. uint8_t field2_check_value = 0x0;
  231. uint8_t field2_check_mask = 0x1;
  232. int words_done = 0;
  233. int words_scheduled = 0;
  234. int i;
  235. path[0] = TAP_DRSELECT;
  236. path[1] = TAP_DRCAPTURE;
  237. path[2] = TAP_DRSHIFT;
  238. fields[0].tap = target->tap;
  239. fields[0].num_bits = 3;
  240. fields[0].out_value = NULL;
  241. fields[0].in_value = NULL;
  242. fields[0].check_value = &field0_check_value;
  243. fields[0].check_mask = &field0_check_mask;
  244. fields[1].tap = target->tap;
  245. fields[1].num_bits = 32;
  246. fields[1].out_value = NULL;
  247. fields[1].check_value = NULL;
  248. fields[1].check_mask = NULL;
  249. fields[2].tap = target->tap;
  250. fields[2].num_bits = 1;
  251. fields[2].out_value = NULL;
  252. fields[2].in_value = NULL;
  253. fields[2].check_value = &field2_check_value;
  254. fields[2].check_mask = &field2_check_mask;
  255. jtag_set_end_state(TAP_IDLE);
  256. xscale_jtag_set_instr(target->tap, XSCALE_DBGTX);
  257. jtag_add_runtest(1, jtag_get_end_state()); /* ensures that we're in the TAP_IDLE state as the above could be a no-op */
  258. /* repeat until all words have been collected */
  259. int attempts = 0;
  260. while (words_done < num_words)
  261. {
  262. /* schedule reads */
  263. words_scheduled = 0;
  264. for (i = words_done; i < num_words; i++)
  265. {
  266. fields[0].in_value = &field0[i];
  267. jtag_add_pathmove(3, path);
  268. fields[1].in_value = (uint8_t *)(field1 + i);
  269. jtag_add_dr_scan_check(3, fields, jtag_set_end_state(TAP_IDLE));
  270. jtag_add_callback(xscale_getbuf, (jtag_callback_data_t)(field1 + i));
  271. words_scheduled++;
  272. }
  273. if ((retval = jtag_execute_queue()) != ERROR_OK)
  274. {
  275. LOG_ERROR("JTAG error while receiving data from debug handler");
  276. break;
  277. }
  278. /* examine results */
  279. for (i = words_done; i < num_words; i++)
  280. {
  281. if (!(field0[0] & 1))
  282. {
  283. /* move backwards if necessary */
  284. int j;
  285. for (j = i; j < num_words - 1; j++)
  286. {
  287. field0[j] = field0[j + 1];
  288. field1[j] = field1[j + 1];
  289. }
  290. words_scheduled--;
  291. }
  292. }
  293. if (words_scheduled == 0)
  294. {
  295. if (attempts++==1000)
  296. {
  297. LOG_ERROR("Failed to receiving data from debug handler after 1000 attempts");
  298. retval = ERROR_TARGET_TIMEOUT;
  299. break;
  300. }
  301. }
  302. words_done += words_scheduled;
  303. }
  304. for (i = 0; i < num_words; i++)
  305. *(buffer++) = buf_get_u32((uint8_t*)&field1[i], 0, 32);
  306. free(field1);
  307. return retval;
  308. }
  309. static int xscale_read_tx(target_t *target, int consume)
  310. {
  311. armv4_5_common_t *armv4_5 = target->arch_info;
  312. xscale_common_t *xscale = armv4_5->arch_info;
  313. tap_state_t path[3];
  314. tap_state_t noconsume_path[6];
  315. int retval;
  316. struct timeval timeout, now;
  317. scan_field_t fields[3];
  318. uint8_t field0_in = 0x0;
  319. uint8_t field0_check_value = 0x2;
  320. uint8_t field0_check_mask = 0x6;
  321. uint8_t field2_check_value = 0x0;
  322. uint8_t field2_check_mask = 0x1;
  323. jtag_set_end_state(TAP_IDLE);
  324. xscale_jtag_set_instr(target->tap, XSCALE_DBGTX);
  325. path[0] = TAP_DRSELECT;
  326. path[1] = TAP_DRCAPTURE;
  327. path[2] = TAP_DRSHIFT;
  328. noconsume_path[0] = TAP_DRSELECT;
  329. noconsume_path[1] = TAP_DRCAPTURE;
  330. noconsume_path[2] = TAP_DREXIT1;
  331. noconsume_path[3] = TAP_DRPAUSE;
  332. noconsume_path[4] = TAP_DREXIT2;
  333. noconsume_path[5] = TAP_DRSHIFT;
  334. fields[0].tap = target->tap;
  335. fields[0].num_bits = 3;
  336. fields[0].out_value = NULL;
  337. fields[0].in_value = &field0_in;
  338. fields[1].tap = target->tap;
  339. fields[1].num_bits = 32;
  340. fields[1].out_value = NULL;
  341. fields[1].in_value = xscale->reg_cache->reg_list[XSCALE_TX].value;
  342. fields[2].tap = target->tap;
  343. fields[2].num_bits = 1;
  344. fields[2].out_value = NULL;
  345. uint8_t tmp;
  346. fields[2].in_value = &tmp;
  347. gettimeofday(&timeout, NULL);
  348. timeval_add_time(&timeout, 1, 0);
  349. for (;;)
  350. {
  351. /* if we want to consume the register content (i.e. clear TX_READY),
  352. * we have to go straight from Capture-DR to Shift-DR
  353. * otherwise, we go from Capture-DR to Exit1-DR to Pause-DR
  354. */
  355. if (consume)
  356. jtag_add_pathmove(3, path);
  357. else
  358. {
  359. jtag_add_pathmove(sizeof(noconsume_path)/sizeof(*noconsume_path), noconsume_path);
  360. }
  361. jtag_add_dr_scan(3, fields, jtag_set_end_state(TAP_IDLE));
  362. jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask);
  363. jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask);
  364. if ((retval = jtag_execute_queue()) != ERROR_OK)
  365. {
  366. LOG_ERROR("JTAG error while reading TX");
  367. return ERROR_TARGET_TIMEOUT;
  368. }
  369. gettimeofday(&now, NULL);
  370. if ((now.tv_sec > timeout.tv_sec) || ((now.tv_sec == timeout.tv_sec)&& (now.tv_usec > timeout.tv_usec)))
  371. {
  372. LOG_ERROR("time out reading TX register");
  373. return ERROR_TARGET_TIMEOUT;
  374. }
  375. if (!((!(field0_in & 1)) && consume))
  376. {
  377. goto done;
  378. }
  379. if (debug_level >= 3)
  380. {
  381. LOG_DEBUG("waiting 100ms");
  382. alive_sleep(100); /* avoid flooding the logs */
  383. } else
  384. {
  385. keep_alive();
  386. }
  387. }
  388. done:
  389. if (!(field0_in & 1))
  390. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  391. return ERROR_OK;
  392. }
  393. static int xscale_write_rx(target_t *target)
  394. {
  395. armv4_5_common_t *armv4_5 = target->arch_info;
  396. xscale_common_t *xscale = armv4_5->arch_info;
  397. int retval;
  398. struct timeval timeout, now;
  399. scan_field_t fields[3];
  400. uint8_t field0_out = 0x0;
  401. uint8_t field0_in = 0x0;
  402. uint8_t field0_check_value = 0x2;
  403. uint8_t field0_check_mask = 0x6;
  404. uint8_t field2 = 0x0;
  405. uint8_t field2_check_value = 0x0;
  406. uint8_t field2_check_mask = 0x1;
  407. jtag_set_end_state(TAP_IDLE);
  408. xscale_jtag_set_instr(target->tap, XSCALE_DBGRX);
  409. fields[0].tap = target->tap;
  410. fields[0].num_bits = 3;
  411. fields[0].out_value = &field0_out;
  412. fields[0].in_value = &field0_in;
  413. fields[1].tap = target->tap;
  414. fields[1].num_bits = 32;
  415. fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_RX].value;
  416. fields[1].in_value = NULL;
  417. fields[2].tap = target->tap;
  418. fields[2].num_bits = 1;
  419. fields[2].out_value = &field2;
  420. uint8_t tmp;
  421. fields[2].in_value = &tmp;
  422. gettimeofday(&timeout, NULL);
  423. timeval_add_time(&timeout, 1, 0);
  424. /* poll until rx_read is low */
  425. LOG_DEBUG("polling RX");
  426. for (;;)
  427. {
  428. jtag_add_dr_scan(3, fields, jtag_set_end_state(TAP_IDLE));
  429. jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask);
  430. jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask);
  431. if ((retval = jtag_execute_queue()) != ERROR_OK)
  432. {
  433. LOG_ERROR("JTAG error while writing RX");
  434. return retval;
  435. }
  436. gettimeofday(&now, NULL);
  437. if ((now.tv_sec > timeout.tv_sec) || ((now.tv_sec == timeout.tv_sec)&& (now.tv_usec > timeout.tv_usec)))
  438. {
  439. LOG_ERROR("time out writing RX register");
  440. return ERROR_TARGET_TIMEOUT;
  441. }
  442. if (!(field0_in & 1))
  443. goto done;
  444. if (debug_level >= 3)
  445. {
  446. LOG_DEBUG("waiting 100ms");
  447. alive_sleep(100); /* avoid flooding the logs */
  448. } else
  449. {
  450. keep_alive();
  451. }
  452. }
  453. done:
  454. /* set rx_valid */
  455. field2 = 0x1;
  456. jtag_add_dr_scan(3, fields, jtag_set_end_state(TAP_IDLE));
  457. if ((retval = jtag_execute_queue()) != ERROR_OK)
  458. {
  459. LOG_ERROR("JTAG error while writing RX");
  460. return retval;
  461. }
  462. return ERROR_OK;
  463. }
  464. /* send count elements of size byte to the debug handler */
  465. static int xscale_send(target_t *target, uint8_t *buffer, int count, int size)
  466. {
  467. uint32_t t[3];
  468. int bits[3];
  469. int retval;
  470. int done_count = 0;
  471. jtag_set_end_state(TAP_IDLE);
  472. xscale_jtag_set_instr(target->tap, XSCALE_DBGRX);
  473. bits[0]=3;
  474. t[0]=0;
  475. bits[1]=32;
  476. t[2]=1;
  477. bits[2]=1;
  478. int endianness = target->endianness;
  479. while (done_count++ < count)
  480. {
  481. switch (size)
  482. {
  483. case 4:
  484. if (endianness == TARGET_LITTLE_ENDIAN)
  485. {
  486. t[1]=le_to_h_u32(buffer);
  487. } else
  488. {
  489. t[1]=be_to_h_u32(buffer);
  490. }
  491. break;
  492. case 2:
  493. if (endianness == TARGET_LITTLE_ENDIAN)
  494. {
  495. t[1]=le_to_h_u16(buffer);
  496. } else
  497. {
  498. t[1]=be_to_h_u16(buffer);
  499. }
  500. break;
  501. case 1:
  502. t[1]=buffer[0];
  503. break;
  504. default:
  505. LOG_ERROR("BUG: size neither 4, 2 nor 1");
  506. exit(-1);
  507. }
  508. jtag_add_dr_out(target->tap,
  509. 3,
  510. bits,
  511. t,
  512. jtag_set_end_state(TAP_IDLE));
  513. buffer += size;
  514. }
  515. if ((retval = jtag_execute_queue()) != ERROR_OK)
  516. {
  517. LOG_ERROR("JTAG error while sending data to debug handler");
  518. return retval;
  519. }
  520. return ERROR_OK;
  521. }
  522. static int xscale_send_u32(target_t *target, uint32_t value)
  523. {
  524. armv4_5_common_t *armv4_5 = target->arch_info;
  525. xscale_common_t *xscale = armv4_5->arch_info;
  526. buf_set_u32(xscale->reg_cache->reg_list[XSCALE_RX].value, 0, 32, value);
  527. return xscale_write_rx(target);
  528. }
  529. static int xscale_write_dcsr(target_t *target, int hold_rst, int ext_dbg_brk)
  530. {
  531. armv4_5_common_t *armv4_5 = target->arch_info;
  532. xscale_common_t *xscale = armv4_5->arch_info;
  533. int retval;
  534. scan_field_t fields[3];
  535. uint8_t field0 = 0x0;
  536. uint8_t field0_check_value = 0x2;
  537. uint8_t field0_check_mask = 0x7;
  538. uint8_t field2 = 0x0;
  539. uint8_t field2_check_value = 0x0;
  540. uint8_t field2_check_mask = 0x1;
  541. if (hold_rst != -1)
  542. xscale->hold_rst = hold_rst;
  543. if (ext_dbg_brk != -1)
  544. xscale->external_debug_break = ext_dbg_brk;
  545. jtag_set_end_state(TAP_IDLE);
  546. xscale_jtag_set_instr(target->tap, XSCALE_SELDCSR);
  547. buf_set_u32(&field0, 1, 1, xscale->hold_rst);
  548. buf_set_u32(&field0, 2, 1, xscale->external_debug_break);
  549. fields[0].tap = target->tap;
  550. fields[0].num_bits = 3;
  551. fields[0].out_value = &field0;
  552. uint8_t tmp;
  553. fields[0].in_value = &tmp;
  554. fields[1].tap = target->tap;
  555. fields[1].num_bits = 32;
  556. fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
  557. fields[1].in_value = NULL;
  558. fields[2].tap = target->tap;
  559. fields[2].num_bits = 1;
  560. fields[2].out_value = &field2;
  561. uint8_t tmp2;
  562. fields[2].in_value = &tmp2;
  563. jtag_add_dr_scan(3, fields, jtag_get_end_state());
  564. jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask);
  565. jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask);
  566. if ((retval = jtag_execute_queue()) != ERROR_OK)
  567. {
  568. LOG_ERROR("JTAG error while writing DCSR");
  569. return retval;
  570. }
  571. xscale->reg_cache->reg_list[XSCALE_DCSR].dirty = 0;
  572. xscale->reg_cache->reg_list[XSCALE_DCSR].valid = 1;
  573. return ERROR_OK;
  574. }
  575. /* parity of the number of bits 0 if even; 1 if odd. for 32 bit words */
  576. static unsigned int parity (unsigned int v)
  577. {
  578. // unsigned int ov = v;
  579. v ^= v >> 16;
  580. v ^= v >> 8;
  581. v ^= v >> 4;
  582. v &= 0xf;
  583. // LOG_DEBUG("parity of 0x%x is %i", ov, (0x6996 >> v) & 1);
  584. return (0x6996 >> v) & 1;
  585. }
  586. static int xscale_load_ic(target_t *target, uint32_t va, uint32_t buffer[8])
  587. {
  588. uint8_t packet[4];
  589. uint8_t cmd;
  590. int word;
  591. scan_field_t fields[2];
  592. LOG_DEBUG("loading miniIC at 0x%8.8" PRIx32 "", va);
  593. /* LDIC into IR */
  594. jtag_set_end_state(TAP_IDLE);
  595. xscale_jtag_set_instr(target->tap, XSCALE_LDIC);
  596. /* CMD is b011 to load a cacheline into the Mini ICache.
  597. * Loading into the main ICache is deprecated, and unused.
  598. * It's followed by three zero bits, and 27 address bits.
  599. */
  600. buf_set_u32(&cmd, 0, 6, 0x3);
  601. /* virtual address of desired cache line */
  602. buf_set_u32(packet, 0, 27, va >> 5);
  603. fields[0].tap = target->tap;
  604. fields[0].num_bits = 6;
  605. fields[0].out_value = &cmd;
  606. fields[0].in_value = NULL;
  607. fields[1].tap = target->tap;
  608. fields[1].num_bits = 27;
  609. fields[1].out_value = packet;
  610. fields[1].in_value = NULL;
  611. jtag_add_dr_scan(2, fields, jtag_get_end_state());
  612. /* rest of packet is a cacheline: 8 instructions, with parity */
  613. fields[0].num_bits = 32;
  614. fields[0].out_value = packet;
  615. fields[1].num_bits = 1;
  616. fields[1].out_value = &cmd;
  617. for (word = 0; word < 8; word++)
  618. {
  619. buf_set_u32(packet, 0, 32, buffer[word]);
  620. uint32_t value;
  621. memcpy(&value, packet, sizeof(uint32_t));
  622. cmd = parity(value);
  623. jtag_add_dr_scan(2, fields, jtag_get_end_state());
  624. }
  625. return jtag_execute_queue();
  626. }
  627. static int xscale_invalidate_ic_line(target_t *target, uint32_t va)
  628. {
  629. uint8_t packet[4];
  630. uint8_t cmd;
  631. scan_field_t fields[2];
  632. jtag_set_end_state(TAP_IDLE);
  633. xscale_jtag_set_instr(target->tap, XSCALE_LDIC);
  634. /* CMD for invalidate IC line b000, bits [6:4] b000 */
  635. buf_set_u32(&cmd, 0, 6, 0x0);
  636. /* virtual address of desired cache line */
  637. buf_set_u32(packet, 0, 27, va >> 5);
  638. fields[0].tap = target->tap;
  639. fields[0].num_bits = 6;
  640. fields[0].out_value = &cmd;
  641. fields[0].in_value = NULL;
  642. fields[1].tap = target->tap;
  643. fields[1].num_bits = 27;
  644. fields[1].out_value = packet;
  645. fields[1].in_value = NULL;
  646. jtag_add_dr_scan(2, fields, jtag_get_end_state());
  647. return ERROR_OK;
  648. }
  649. static int xscale_update_vectors(target_t *target)
  650. {
  651. armv4_5_common_t *armv4_5 = target->arch_info;
  652. xscale_common_t *xscale = armv4_5->arch_info;
  653. int i;
  654. int retval;
  655. uint32_t low_reset_branch, high_reset_branch;
  656. for (i = 1; i < 8; i++)
  657. {
  658. /* if there's a static vector specified for this exception, override */
  659. if (xscale->static_high_vectors_set & (1 << i))
  660. {
  661. xscale->high_vectors[i] = xscale->static_high_vectors[i];
  662. }
  663. else
  664. {
  665. retval = target_read_u32(target, 0xffff0000 + 4*i, &xscale->high_vectors[i]);
  666. if (retval == ERROR_TARGET_TIMEOUT)
  667. return retval;
  668. if (retval != ERROR_OK)
  669. {
  670. /* Some of these reads will fail as part of normal execution */
  671. xscale->high_vectors[i] = ARMV4_5_B(0xfffffe, 0);
  672. }
  673. }
  674. }
  675. for (i = 1; i < 8; i++)
  676. {
  677. if (xscale->static_low_vectors_set & (1 << i))
  678. {
  679. xscale->low_vectors[i] = xscale->static_low_vectors[i];
  680. }
  681. else
  682. {
  683. retval = target_read_u32(target, 0x0 + 4*i, &xscale->low_vectors[i]);
  684. if (retval == ERROR_TARGET_TIMEOUT)
  685. return retval;
  686. if (retval != ERROR_OK)
  687. {
  688. /* Some of these reads will fail as part of normal execution */
  689. xscale->low_vectors[i] = ARMV4_5_B(0xfffffe, 0);
  690. }
  691. }
  692. }
  693. /* calculate branches to debug handler */
  694. low_reset_branch = (xscale->handler_address + 0x20 - 0x0 - 0x8) >> 2;
  695. high_reset_branch = (xscale->handler_address + 0x20 - 0xffff0000 - 0x8) >> 2;
  696. xscale->low_vectors[0] = ARMV4_5_B((low_reset_branch & 0xffffff), 0);
  697. xscale->high_vectors[0] = ARMV4_5_B((high_reset_branch & 0xffffff), 0);
  698. /* invalidate and load exception vectors in mini i-cache */
  699. xscale_invalidate_ic_line(target, 0x0);
  700. xscale_invalidate_ic_line(target, 0xffff0000);
  701. xscale_load_ic(target, 0x0, xscale->low_vectors);
  702. xscale_load_ic(target, 0xffff0000, xscale->high_vectors);
  703. return ERROR_OK;
  704. }
  705. static int xscale_arch_state(struct target_s *target)
  706. {
  707. armv4_5_common_t *armv4_5 = target->arch_info;
  708. xscale_common_t *xscale = armv4_5->arch_info;
  709. static const char *state[] =
  710. {
  711. "disabled", "enabled"
  712. };
  713. static const char *arch_dbg_reason[] =
  714. {
  715. "", "\n(processor reset)", "\n(trace buffer full)"
  716. };
  717. if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
  718. {
  719. LOG_ERROR("BUG: called for a non-ARMv4/5 target");
  720. exit(-1);
  721. }
  722. LOG_USER("target halted in %s state due to %s, current mode: %s\n"
  723. "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
  724. "MMU: %s, D-Cache: %s, I-Cache: %s"
  725. "%s",
  726. armv4_5_state_strings[armv4_5->core_state],
  727. Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name ,
  728. armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
  729. buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
  730. buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
  731. state[xscale->armv4_5_mmu.mmu_enabled],
  732. state[xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
  733. state[xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled],
  734. arch_dbg_reason[xscale->arch_debug_reason]);
  735. return ERROR_OK;
  736. }
  737. static int xscale_poll(target_t *target)
  738. {
  739. int retval = ERROR_OK;
  740. armv4_5_common_t *armv4_5 = target->arch_info;
  741. xscale_common_t *xscale = armv4_5->arch_info;
  742. if ((target->state == TARGET_RUNNING) || (target->state == TARGET_DEBUG_RUNNING))
  743. {
  744. enum target_state previous_state = target->state;
  745. if ((retval = xscale_read_tx(target, 0)) == ERROR_OK)
  746. {
  747. /* there's data to read from the tx register, we entered debug state */
  748. xscale->handler_running = 1;
  749. target->state = TARGET_HALTED;
  750. /* process debug entry, fetching current mode regs */
  751. retval = xscale_debug_entry(target);
  752. }
  753. else if (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
  754. {
  755. LOG_USER("error while polling TX register, reset CPU");
  756. /* here we "lie" so GDB won't get stuck and a reset can be perfomed */
  757. target->state = TARGET_HALTED;
  758. }
  759. /* debug_entry could have overwritten target state (i.e. immediate resume)
  760. * don't signal event handlers in that case
  761. */
  762. if (target->state != TARGET_HALTED)
  763. return ERROR_OK;
  764. /* if target was running, signal that we halted
  765. * otherwise we reentered from debug execution */
  766. if (previous_state == TARGET_RUNNING)
  767. target_call_event_callbacks(target, TARGET_EVENT_HALTED);
  768. else
  769. target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
  770. }
  771. return retval;
  772. }
  773. static int xscale_debug_entry(target_t *target)
  774. {
  775. armv4_5_common_t *armv4_5 = target->arch_info;
  776. xscale_common_t *xscale = armv4_5->arch_info;
  777. uint32_t pc;
  778. uint32_t buffer[10];
  779. int i;
  780. int retval;
  781. uint32_t moe;
  782. /* clear external dbg break (will be written on next DCSR read) */
  783. xscale->external_debug_break = 0;
  784. if ((retval = xscale_read_dcsr(target)) != ERROR_OK)
  785. return retval;
  786. /* get r0, pc, r1 to r7 and cpsr */
  787. if ((retval = xscale_receive(target, buffer, 10)) != ERROR_OK)
  788. return retval;
  789. /* move r0 from buffer to register cache */
  790. buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, buffer[0]);
  791. armv4_5->core_cache->reg_list[0].dirty = 1;
  792. armv4_5->core_cache->reg_list[0].valid = 1;
  793. LOG_DEBUG("r0: 0x%8.8" PRIx32 "", buffer[0]);
  794. /* move pc from buffer to register cache */
  795. buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, buffer[1]);
  796. armv4_5->core_cache->reg_list[15].dirty = 1;
  797. armv4_5->core_cache->reg_list[15].valid = 1;
  798. LOG_DEBUG("pc: 0x%8.8" PRIx32 "", buffer[1]);
  799. /* move data from buffer to register cache */
  800. for (i = 1; i <= 7; i++)
  801. {
  802. buf_set_u32(armv4_5->core_cache->reg_list[i].value, 0, 32, buffer[1 + i]);
  803. armv4_5->core_cache->reg_list[i].dirty = 1;
  804. armv4_5->core_cache->reg_list[i].valid = 1;
  805. LOG_DEBUG("r%i: 0x%8.8" PRIx32 "", i, buffer[i + 1]);
  806. }
  807. buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, buffer[9]);
  808. armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
  809. armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
  810. LOG_DEBUG("cpsr: 0x%8.8" PRIx32 "", buffer[9]);
  811. armv4_5->core_mode = buffer[9] & 0x1f;
  812. if (armv4_5_mode_to_number(armv4_5->core_mode) == -1)
  813. {
  814. target->state = TARGET_UNKNOWN;
  815. LOG_ERROR("cpsr contains invalid mode value - communication failure");
  816. return ERROR_TARGET_FAILURE;
  817. }
  818. LOG_DEBUG("target entered debug state in %s mode", armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)]);
  819. if (buffer[9] & 0x20)
  820. armv4_5->core_state = ARMV4_5_STATE_THUMB;
  821. else
  822. armv4_5->core_state = ARMV4_5_STATE_ARM;
  823. if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
  824. return ERROR_FAIL;
  825. /* get banked registers, r8 to r14, and spsr if not in USR/SYS mode */
  826. if ((armv4_5->core_mode != ARMV4_5_MODE_USR) && (armv4_5->core_mode != ARMV4_5_MODE_SYS))
  827. {
  828. xscale_receive(target, buffer, 8);
  829. buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).value, 0, 32, buffer[7]);
  830. ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).dirty = 0;
  831. ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).valid = 1;
  832. }
  833. else
  834. {
  835. /* r8 to r14, but no spsr */
  836. xscale_receive(target, buffer, 7);
  837. }
  838. /* move data from buffer to register cache */
  839. for (i = 8; i <= 14; i++)
  840. {
  841. buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, buffer[i - 8]);
  842. ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 0;
  843. ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
  844. }
  845. /* examine debug reason */
  846. xscale_read_dcsr(target);
  847. moe = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 2, 3);
  848. /* stored PC (for calculating fixup) */
  849. pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
  850. switch (moe)
  851. {
  852. case 0x0: /* Processor reset */
  853. target->debug_reason = DBG_REASON_DBGRQ;
  854. xscale->arch_debug_reason = XSCALE_DBG_REASON_RESET;
  855. pc -= 4;
  856. break;
  857. case 0x1: /* Instruction breakpoint hit */
  858. target->debug_reason = DBG_REASON_BREAKPOINT;
  859. xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
  860. pc -= 4;
  861. break;
  862. case 0x2: /* Data breakpoint hit */
  863. target->debug_reason = DBG_REASON_WATCHPOINT;
  864. xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
  865. pc -= 4;
  866. break;
  867. case 0x3: /* BKPT instruction executed */
  868. target->debug_reason = DBG_REASON_BREAKPOINT;
  869. xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
  870. pc -= 4;
  871. break;
  872. case 0x4: /* Ext. debug event */
  873. target->debug_reason = DBG_REASON_DBGRQ;
  874. xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
  875. pc -= 4;
  876. break;
  877. case 0x5: /* Vector trap occured */
  878. target->debug_reason = DBG_REASON_BREAKPOINT;
  879. xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
  880. pc -= 4;
  881. break;
  882. case 0x6: /* Trace buffer full break */
  883. target->debug_reason = DBG_REASON_DBGRQ;
  884. xscale->arch_debug_reason = XSCALE_DBG_REASON_TB_FULL;
  885. pc -= 4;
  886. break;
  887. case 0x7: /* Reserved (may flag Hot-Debug support) */
  888. default:
  889. LOG_ERROR("Method of Entry is 'Reserved'");
  890. exit(-1);
  891. break;
  892. }
  893. /* apply PC fixup */
  894. buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, pc);
  895. /* on the first debug entry, identify cache type */
  896. if (xscale->armv4_5_mmu.armv4_5_cache.ctype == -1)
  897. {
  898. uint32_t cache_type_reg;
  899. /* read cp15 cache type register */
  900. xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CACHETYPE]);
  901. cache_type_reg = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CACHETYPE].value, 0, 32);
  902. armv4_5_identify_cache(cache_type_reg, &xscale->armv4_5_mmu.armv4_5_cache);
  903. }
  904. /* examine MMU and Cache settings */
  905. /* read cp15 control register */
  906. xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CTRL]);
  907. xscale->cp15_control_reg = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CTRL].value, 0, 32);
  908. xscale->armv4_5_mmu.mmu_enabled = (xscale->cp15_control_reg & 0x1U) ? 1 : 0;
  909. xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (xscale->cp15_control_reg & 0x4U) ? 1 : 0;
  910. xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled = (xscale->cp15_control_reg & 0x1000U) ? 1 : 0;
  911. /* tracing enabled, read collected trace data */
  912. if (xscale->trace.buffer_enabled)
  913. {
  914. xscale_read_trace(target);
  915. xscale->trace.buffer_fill--;
  916. /* resume if we're still collecting trace data */
  917. if ((xscale->arch_debug_reason == XSCALE_DBG_REASON_TB_FULL)
  918. && (xscale->trace.buffer_fill > 0))
  919. {
  920. xscale_resume(target, 1, 0x0, 1, 0);
  921. }
  922. else
  923. {
  924. xscale->trace.buffer_enabled = 0;
  925. }
  926. }
  927. return ERROR_OK;
  928. }
  929. static int xscale_halt(target_t *target)
  930. {
  931. armv4_5_common_t *armv4_5 = target->arch_info;
  932. xscale_common_t *xscale = armv4_5->arch_info;
  933. LOG_DEBUG("target->state: %s",
  934. target_state_name(target));
  935. if (target->state == TARGET_HALTED)
  936. {
  937. LOG_DEBUG("target was already halted");
  938. return ERROR_OK;
  939. }
  940. else if (target->state == TARGET_UNKNOWN)
  941. {
  942. /* this must not happen for a xscale target */
  943. LOG_ERROR("target was in unknown state when halt was requested");
  944. return ERROR_TARGET_INVALID;
  945. }
  946. else if (target->state == TARGET_RESET)
  947. {
  948. LOG_DEBUG("target->state == TARGET_RESET");
  949. }
  950. else
  951. {
  952. /* assert external dbg break */
  953. xscale->external_debug_break = 1;
  954. xscale_read_dcsr(target);
  955. target->debug_reason = DBG_REASON_DBGRQ;
  956. }
  957. return ERROR_OK;
  958. }
  959. static int xscale_enable_single_step(struct target_s *target, uint32_t next_pc)
  960. {
  961. armv4_5_common_t *armv4_5 = target->arch_info;
  962. xscale_common_t *xscale= armv4_5->arch_info;
  963. reg_t *ibcr0 = &xscale->reg_cache->reg_list[XSCALE_IBCR0];
  964. int retval;
  965. if (xscale->ibcr0_used)
  966. {
  967. breakpoint_t *ibcr0_bp = breakpoint_find(target, buf_get_u32(ibcr0->value, 0, 32) & 0xfffffffe);
  968. if (ibcr0_bp)
  969. {
  970. xscale_unset_breakpoint(target, ibcr0_bp);
  971. }
  972. else
  973. {
  974. LOG_ERROR("BUG: xscale->ibcr0_used is set, but no breakpoint with that address found");
  975. exit(-1);
  976. }
  977. }
  978. if ((retval = xscale_set_reg_u32(ibcr0, next_pc | 0x1)) != ERROR_OK)
  979. return retval;
  980. return ERROR_OK;
  981. }
  982. static int xscale_disable_single_step(struct target_s *target)
  983. {
  984. armv4_5_common_t *armv4_5 = target->arch_info;
  985. xscale_common_t *xscale= armv4_5->arch_info;
  986. reg_t *ibcr0 = &xscale->reg_cache->reg_list[XSCALE_IBCR0];
  987. int retval;
  988. if ((retval = xscale_set_reg_u32(ibcr0, 0x0)) != ERROR_OK)
  989. return retval;
  990. return ERROR_OK;
  991. }
  992. static void xscale_enable_watchpoints(struct target_s *target)
  993. {
  994. watchpoint_t *watchpoint = target->watchpoints;
  995. while (watchpoint)
  996. {
  997. if (watchpoint->set == 0)
  998. xscale_set_watchpoint(target, watchpoint);
  999. watchpoint = watchpoint->next;
  1000. }
  1001. }
  1002. static void xscale_enable_breakpoints(struct target_s *target)
  1003. {
  1004. breakpoint_t *breakpoint = target->breakpoints;
  1005. /* set any pending breakpoints */
  1006. while (breakpoint)
  1007. {
  1008. if (breakpoint->set == 0)
  1009. xscale_set_breakpoint(target, breakpoint);
  1010. breakpoint = breakpoint->next;
  1011. }
  1012. }
  1013. static int xscale_resume(struct target_s *target, int current,
  1014. uint32_t address, int handle_breakpoints, int debug_execution)
  1015. {
  1016. armv4_5_common_t *armv4_5 = target->arch_info;
  1017. xscale_common_t *xscale= armv4_5->arch_info;
  1018. breakpoint_t *breakpoint = target->breakpoints;
  1019. uint32_t current_pc;
  1020. int retval;
  1021. int i;
  1022. LOG_DEBUG("-");
  1023. if (target->state != TARGET_HALTED)
  1024. {
  1025. LOG_WARNING("target not halted");
  1026. return ERROR_TARGET_NOT_HALTED;
  1027. }
  1028. if (!debug_execution)
  1029. {
  1030. target_free_all_working_areas(target);
  1031. }
  1032. /* update vector tables */
  1033. if ((retval = xscale_update_vectors(target)) != ERROR_OK)
  1034. return retval;
  1035. /* current = 1: continue on current pc, otherwise continue at <address> */
  1036. if (!current)
  1037. buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
  1038. current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
  1039. /* if we're at the reset vector, we have to simulate the branch */
  1040. if (current_pc == 0x0)
  1041. {
  1042. arm_simulate_step(target, NULL);
  1043. current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
  1044. }
  1045. /* the front-end may request us not to handle breakpoints */
  1046. if (handle_breakpoints)
  1047. {
  1048. if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
  1049. {
  1050. uint32_t next_pc;
  1051. /* there's a breakpoint at the current PC, we have to step over it */
  1052. LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 "", breakpoint->address);
  1053. xscale_unset_breakpoint(target, breakpoint);
  1054. /* calculate PC of next instruction */
  1055. if ((retval = arm_simulate_step(target, &next_pc)) != ERROR_OK)
  1056. {
  1057. uint32_t current_opcode;
  1058. target_read_u32(target, current_pc, &current_opcode);
  1059. LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "", current_opcode);
  1060. }
  1061. LOG_DEBUG("enable single-step");
  1062. xscale_enable_single_step(target, next_pc);
  1063. /* restore banked registers */
  1064. xscale_restore_context(target);
  1065. /* send resume request (command 0x30 or 0x31)
  1066. * clean the trace buffer if it is to be enabled (0x62) */
  1067. if (xscale->trace.buffer_enabled)
  1068. {
  1069. xscale_send_u32(target, 0x62);
  1070. xscale_send_u32(target, 0x31);
  1071. }
  1072. else
  1073. xscale_send_u32(target, 0x30);
  1074. /* send CPSR */
  1075. xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
  1076. LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
  1077. for (i = 7; i >= 0; i--)
  1078. {
  1079. /* send register */
  1080. xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32));
  1081. LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32 "", i, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32));
  1082. }
  1083. /* send PC */
  1084. xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
  1085. LOG_DEBUG("writing PC with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
  1086. /* wait for and process debug entry */
  1087. xscale_debug_entry(target);
  1088. LOG_DEBUG("disable single-step");
  1089. xscale_disable_single_step(target);
  1090. LOG_DEBUG("set breakpoint at 0x%8.8" PRIx32 "", breakpoint->address);
  1091. xscale_set_breakpoint(target, breakpoint);
  1092. }
  1093. }
  1094. /* enable any pending breakpoints and watchpoints */
  1095. xscale_enable_breakpoints(target);
  1096. xscale_enable_watchpoints(target);
  1097. /* restore banked registers */
  1098. xscale_restore_context(target);
  1099. /* send resume request (command 0x30 or 0x31)
  1100. * clean the trace buffer if it is to be enabled (0x62) */
  1101. if (xscale->trace.buffer_enabled)
  1102. {
  1103. xscale_send_u32(target, 0x62);
  1104. xscale_send_u32(target, 0x31);
  1105. }
  1106. else
  1107. xscale_send_u32(target, 0x30);
  1108. /* send CPSR */
  1109. xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
  1110. LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
  1111. for (i = 7; i >= 0; i--)
  1112. {
  1113. /* send register */
  1114. xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32));
  1115. LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32 "", i, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32));
  1116. }
  1117. /* send PC */
  1118. xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
  1119. LOG_DEBUG("writing PC with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
  1120. target->debug_reason = DBG_REASON_NOTHALTED;
  1121. if (!debug_execution)
  1122. {
  1123. /* registers are now invalid */
  1124. armv4_5_invalidate_core_regs(target);
  1125. target->state = TARGET_RUNNING;
  1126. target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
  1127. }
  1128. else
  1129. {
  1130. target->state = TARGET_DEBUG_RUNNING;
  1131. target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
  1132. }
  1133. LOG_DEBUG("target resumed");
  1134. xscale->handler_running = 1;
  1135. return ERROR_OK;
  1136. }
  1137. static int xscale_step_inner(struct target_s *target, int current,
  1138. uint32_t address, int handle_breakpoints)
  1139. {
  1140. armv4_5_common_t *armv4_5 = target->arch_info;
  1141. xscale_common_t *xscale = armv4_5->arch_info;
  1142. uint32_t next_pc;
  1143. int retval;
  1144. int i;
  1145. target->debug_reason = DBG_REASON_SINGLESTEP;
  1146. /* calculate PC of next instruction */
  1147. if ((retval = arm_simulate_step(target, &next_pc)) != ERROR_OK)
  1148. {
  1149. uint32_t current_opcode, current_pc;
  1150. current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
  1151. target_read_u32(target, current_pc, &current_opcode);
  1152. LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "", current_opcode);
  1153. return retval;
  1154. }
  1155. LOG_DEBUG("enable single-step");
  1156. if ((retval = xscale_enable_single_step(target, next_pc)) != ERROR_OK)
  1157. return retval;
  1158. /* restore banked registers */
  1159. if ((retval = xscale_restore_context(target)) != ERROR_OK)
  1160. return retval;
  1161. /* send resume request (command 0x30 or 0x31)
  1162. * clean the trace buffer if it is to be enabled (0x62) */
  1163. if (xscale->trace.buffer_enabled)
  1164. {
  1165. if ((retval = xscale_send_u32(target, 0x62)) != ERROR_OK)
  1166. return retval;
  1167. if ((retval = xscale_send_u32(target, 0x31)) != ERROR_OK)
  1168. return retval;
  1169. }
  1170. else
  1171. if ((retval = xscale_send_u32(target, 0x30)) != ERROR_OK)
  1172. return retval;
  1173. /* send CPSR */
  1174. if ((retval = xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32))) != ERROR_OK)
  1175. return retval;
  1176. LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
  1177. for (i = 7; i >= 0; i--)
  1178. {
  1179. /* send register */
  1180. if ((retval = xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32))) != ERROR_OK)
  1181. return retval;
  1182. LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32 "", i, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32));
  1183. }
  1184. /* send PC */
  1185. if ((retval = xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))) != ERROR_OK)
  1186. return retval;
  1187. LOG_DEBUG("writing PC with value 0x%8.8" PRIx32, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
  1188. target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
  1189. /* registers are now invalid */
  1190. if ((retval = armv4_5_invalidate_core_regs(target)) != ERROR_OK)
  1191. return retval;
  1192. /* wait for and process debug entry */
  1193. if ((retval = xscale_debug_entry(target)) != ERROR_OK)
  1194. return retval;
  1195. LOG_DEBUG("disable single-step");
  1196. if ((retval = xscale_disable_single_step(target)) != ERROR_OK)
  1197. return retval;
  1198. target_call_event_callbacks(target, TARGET_EVENT_HALTED);
  1199. return ERROR_OK;
  1200. }
  1201. static int xscale_step(struct target_s *target, int current,
  1202. uint32_t address, int handle_breakpoints)
  1203. {
  1204. armv4_5_common_t *armv4_5 = target->arch_info;
  1205. breakpoint_t *breakpoint = target->breakpoints;
  1206. uint32_t current_pc;
  1207. int retval;
  1208. if (target->state != TARGET_HALTED)
  1209. {
  1210. LOG_WARNING("target not halted");
  1211. return ERROR_TARGET_NOT_HALTED;
  1212. }
  1213. /* current = 1: continue on current pc, otherwise continue at <address> */
  1214. if (!current)
  1215. buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
  1216. current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
  1217. /* if we're at the reset vector, we have to simulate the step */
  1218. if (current_pc == 0x0)
  1219. {
  1220. if ((retval = arm_simulate_step(target, NULL)) != ERROR_OK)
  1221. return retval;
  1222. current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
  1223. target->debug_reason = DBG_REASON_SINGLESTEP;
  1224. target_call_event_callbacks(target, TARGET_EVENT_HALTED);
  1225. return ERROR_OK;
  1226. }
  1227. /* the front-end may request us not to handle breakpoints */
  1228. if (handle_breakpoints)
  1229. if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
  1230. {
  1231. if ((retval = xscale_unset_breakpoint(target, breakpoint)) != ERROR_OK)
  1232. return retval;
  1233. }
  1234. retval = xscale_step_inner(target, current, address, handle_breakpoints);
  1235. if (breakpoint)
  1236. {
  1237. xscale_set_breakpoint(target, breakpoint);
  1238. }
  1239. LOG_DEBUG("target stepped");
  1240. return ERROR_OK;
  1241. }
  1242. static int xscale_assert_reset(target_t *target)
  1243. {
  1244. armv4_5_common_t *armv4_5 = target->arch_info;
  1245. xscale_common_t *xscale = armv4_5->arch_info;
  1246. LOG_DEBUG("target->state: %s",
  1247. target_state_name(target));
  1248. /* select DCSR instruction (set endstate to R-T-I to ensure we don't
  1249. * end up in T-L-R, which would reset JTAG
  1250. */
  1251. jtag_set_end_state(TAP_IDLE);
  1252. xscale_jtag_set_instr(target->tap, XSCALE_SELDCSR);
  1253. /* set Hold reset, Halt mode and Trap Reset */
  1254. buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 30, 1, 0x1);
  1255. buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 16, 1, 0x1);
  1256. xscale_write_dcsr(target, 1, 0);
  1257. /* select BYPASS, because having DCSR selected caused problems on the PXA27x */
  1258. xscale_jtag_set_instr(target->tap, 0x7f);
  1259. jtag_execute_queue();
  1260. /* assert reset */
  1261. jtag_add_reset(0, 1);
  1262. /* sleep 1ms, to be sure we fulfill any requirements */
  1263. jtag_add_sleep(1000);
  1264. jtag_execute_queue();
  1265. target->state = TARGET_RESET;
  1266. if (target->reset_halt)
  1267. {
  1268. int retval;
  1269. if ((retval = target_halt(target)) != ERROR_OK)
  1270. return retval;
  1271. }
  1272. return ERROR_OK;
  1273. }
  1274. static int xscale_deassert_reset(target_t *target)
  1275. {
  1276. armv4_5_common_t *armv4_5 = target->arch_info;
  1277. xscale_common_t *xscale = armv4_5->arch_info;
  1278. breakpoint_t *breakpoint = target->breakpoints;
  1279. LOG_DEBUG("-");
  1280. xscale->ibcr_available = 2;
  1281. xscale->ibcr0_used = 0;
  1282. xscale->ibcr1_used = 0;
  1283. xscale->dbr_available = 2;
  1284. xscale->dbr0_used = 0;
  1285. xscale->dbr1_used = 0;
  1286. /* mark all hardware breakpoints as unset */
  1287. while (breakpoint)
  1288. {
  1289. if (breakpoint->type == BKPT_HARD)
  1290. {
  1291. breakpoint->set = 0;
  1292. }
  1293. breakpoint = breakpoint->next;
  1294. }
  1295. if (!xscale->handler_installed)
  1296. {
  1297. uint32_t address;
  1298. unsigned buf_cnt;
  1299. const uint8_t *buffer = xscale_debug_handler;
  1300. int retval;
  1301. /* release SRST */
  1302. jtag_add_reset(0, 0);
  1303. /* wait 300ms; 150 and 100ms were not enough */
  1304. jtag_add_sleep(300*1000);
  1305. jtag_add_runtest(2030, jtag_set_end_state(TAP_IDLE));
  1306. jtag_execute_queue();
  1307. /* set Hold reset, Halt mode and Trap Reset */
  1308. buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 30, 1, 0x1);
  1309. buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 16, 1, 0x1);
  1310. xscale_write_dcsr(target, 1, 0);
  1311. /* Load the debug handler into the mini-icache. Since
  1312. * it's using halt mode (not monitor mode), it runs in
  1313. * "Special Debug State" for access to registers, memory,
  1314. * coprocessors, trace data, etc.
  1315. *
  1316. * REVISIT: *assumes* we've had a SRST+TRST reset so the
  1317. * mini-icache contents have been invalidated. Safest to
  1318. * force that, so writing new contents is reliable...
  1319. */
  1320. address = xscale->handler_address;
  1321. for (unsigned binary_size = xscale_debug_handler_size;
  1322. binary_size > 0;
  1323. binary_size -= buf_cnt, buffer += buf_cnt)
  1324. {
  1325. uint32_t cache_line[8];
  1326. unsigned i;
  1327. buf_cnt = binary_size;
  1328. if (buf_cnt > 32)
  1329. buf_cnt = 32;
  1330. for (i = 0; i < buf_cnt; i += 4)
  1331. {
  1332. /* convert LE buffer to host-endian uint32_t */
  1333. cache_line[i / 4] = le_to_h_u32(&buffer[i]);
  1334. }
  1335. for (; i < 32; i += 4)
  1336. {
  1337. cache_line[i / 4] = 0xe1a08008;
  1338. }
  1339. /* only load addresses other than the reset vectors */
  1340. if ((address % 0x400) != 0x0)
  1341. {
  1342. retval = xscale_load_ic(target, address,
  1343. cache_line);
  1344. if (retval != ERROR_OK)
  1345. return retval;
  1346. }
  1347. address += buf_cnt;
  1348. };
  1349. retval = xscale_load_ic(target, 0x0,
  1350. xscale->low_vectors);
  1351. if (retval != ERROR_OK)
  1352. return retval;
  1353. retval = xscale_load_ic(target, 0xffff0000,
  1354. xscale->high_vectors);
  1355. if (retval != ERROR_OK)
  1356. return retval;
  1357. jtag_add_runtest(30, jtag_set_end_state(TAP_IDLE));
  1358. jtag_add_sleep(100000);
  1359. /* set Hold reset, Halt mode and Trap Reset */
  1360. buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 30, 1, 0x1);
  1361. buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 16, 1, 0x1);
  1362. xscale_write_dcsr(target, 1, 0);
  1363. /* clear Hold reset to let the target run (should enter debug handler) */
  1364. xscale_write_dcsr(target, 0, 1);
  1365. target->state = TARGET_RUNNING;
  1366. if (!target->reset_halt)
  1367. {
  1368. jtag_add_sleep(10000);
  1369. /* we should have entered debug now */
  1370. xscale_debug_entry(target);
  1371. target->state = TARGET_HALTED;
  1372. /* resume the target */
  1373. xscale_resume(target, 1, 0x0, 1, 0);
  1374. }
  1375. }
  1376. else
  1377. {
  1378. jtag_add_reset(0, 0);
  1379. }
  1380. return ERROR_OK;
  1381. }
  1382. static int xscale_read_core_reg(struct target_s *target, int num,
  1383. enum armv4_5_mode mode)
  1384. {
  1385. LOG_ERROR("not implemented");
  1386. return ERROR_OK;
  1387. }
  1388. static int xscale_write_core_reg(struct target_s *target, int num,
  1389. enum armv4_5_mode mode, uint32_t value)
  1390. {
  1391. LOG_ERROR("not implemented");
  1392. return ERROR_OK;
  1393. }
  1394. static int xscale_full_context(target_t *target)
  1395. {
  1396. armv4_5_common_t *armv4_5 = target->arch_info;
  1397. uint32_t *buffer;
  1398. int i, j;
  1399. LOG_DEBUG("-");
  1400. if (target->state != TARGET_HALTED)
  1401. {
  1402. LOG_WARNING("target not halted");
  1403. return ERROR_TARGET_NOT_HALTED;
  1404. }
  1405. buffer = malloc(4 * 8);
  1406. /* iterate through processor modes (FIQ, IRQ, SVC, ABT, UND and SYS)
  1407. * we can't enter User mode on an XScale (unpredictable),
  1408. * but User shares registers with SYS
  1409. */
  1410. for (i = 1; i < 7; i++)
  1411. {
  1412. int valid = 1;
  1413. /* check if there are invalid registers in the current mode
  1414. */
  1415. for (j = 0; j <= 16; j++)
  1416. {
  1417. if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
  1418. valid = 0;
  1419. }
  1420. if (!valid)
  1421. {
  1422. uint32_t tmp_cpsr;
  1423. /* request banked registers */
  1424. xscale_send_u32(target, 0x0);
  1425. tmp_cpsr = 0x0;
  1426. tmp_cpsr |= armv4_5_number_to_mode(i);
  1427. tmp_cpsr |= 0xc0; /* I/F bits */
  1428. /* send CPSR for desired mode */
  1429. xscale_send_u32(target, tmp_cpsr);
  1430. /* get banked registers, r8 to r14, and spsr if not in USR/SYS mode */
  1431. if ((armv4_5_number_to_mode(i) != ARMV4_5_MODE_USR) && (armv4_5_number_to_mode(i) != ARMV4_5_MODE_SYS))
  1432. {
  1433. xscale_receive(target, buffer, 8);
  1434. buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).value, 0, 32, buffer[7]);
  1435. ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).dirty = 0;
  1436. ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid = 1;
  1437. }
  1438. else
  1439. {
  1440. xscale_receive(target, buffer, 7);
  1441. }
  1442. /* move data from buffer to register cache */
  1443. for (j = 8; j <= 14; j++)
  1444. {
  1445. buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).value, 0, 32, buffer[j - 8]);
  1446. ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).dirty = 0;
  1447. ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid = 1;
  1448. }
  1449. }
  1450. }
  1451. free(buffer);
  1452. return ERROR_OK;
  1453. }
  1454. static int xscale_restore_context(target_t *target)
  1455. {
  1456. armv4_5_common_t *armv4_5 = target->arch_info;
  1457. int i, j;
  1458. if (target->state != TARGET_HALTED)
  1459. {
  1460. LOG_WARNING("target not halted");
  1461. return ERROR_TARGET_NOT_HALTED;
  1462. }
  1463. /* iterate through processor modes (FIQ, IRQ, SVC, ABT, UND and SYS)
  1464. * we can't enter User mode on an XScale (unpredictable),
  1465. * but User shares registers with SYS
  1466. */
  1467. for (i = 1; i < 7; i++)
  1468. {
  1469. int dirty = 0;
  1470. /* check if there are invalid registers in the current mode
  1471. */
  1472. for (j = 8; j <= 14; j++)
  1473. {
  1474. if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).dirty == 1)
  1475. dirty = 1;
  1476. }
  1477. /* if not USR/SYS, check if the SPSR needs to be written */
  1478. if ((armv4_5_number_to_mode(i) != ARMV4_5_MODE_USR) && (armv4_5_number_to_mode(i) != ARMV4_5_MODE_SYS))
  1479. {
  1480. if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).dirty == 1)
  1481. dirty = 1;
  1482. }
  1483. if (dirty)
  1484. {
  1485. uint32_t tmp_cpsr;
  1486. /* send banked registers */
  1487. xscale_send_u32(target, 0x1);
  1488. tmp_cpsr = 0x0;
  1489. tmp_cpsr |= armv4_5_number_to_mode(i);
  1490. tmp_cpsr |= 0xc0; /* I/F bits */
  1491. /* send CPSR for desired mode */
  1492. xscale_send_u32(target, tmp_cpsr);
  1493. /* send banked registers, r8 to r14, and spsr if not in USR/SYS mode */
  1494. for (j = 8; j <= 14; j++)
  1495. {
  1496. xscale_send_u32(target, buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, j).value, 0, 32));
  1497. ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).dirty = 0;
  1498. }
  1499. if ((armv4_5_number_to_mode(i) != ARMV4_5_MODE_USR) && (armv4_5_number_to_mode(i) != ARMV4_5_MODE_SYS))
  1500. {
  1501. xscale_send_u32(target, buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).value, 0, 32));
  1502. ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).dirty = 0;
  1503. }
  1504. }
  1505. }
  1506. return ERROR_OK;
  1507. }
  1508. static int xscale_read_memory(struct target_s *target, uint32_t address,
  1509. uint32_t size, uint32_t count, uint8_t *buffer)
  1510. {
  1511. armv4_5_common_t *armv4_5 = target->arch_info;
  1512. xscale_common_t *xscale = armv4_5->arch_info;
  1513. uint32_t *buf32;
  1514. uint32_t i;
  1515. int retval;
  1516. LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32, address, size, count);
  1517. if (target->state != TARGET_HALTED)
  1518. {
  1519. LOG_WARNING("target not halted");
  1520. return ERROR_TARGET_NOT_HALTED;
  1521. }
  1522. /* sanitize arguments */
  1523. if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
  1524. return ERROR_INVALID_ARGUMENTS;
  1525. if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
  1526. return ERROR_TARGET_UNALIGNED_ACCESS;
  1527. /* send memory read request (command 0x1n, n: access size) */
  1528. if ((retval = xscale_send_u32(target, 0x10 | size)) != ERROR_OK)
  1529. return retval;
  1530. /* send base address for read request */
  1531. if ((retval = xscale_send_u32(target, address)) != ERROR_OK)
  1532. return retval;
  1533. /* send number of requested data words */
  1534. if ((retval = xscale_send_u32(target, count)) != ERROR_OK)
  1535. return retval;
  1536. /* receive data from target (count times 32-bit words in host endianness) */
  1537. buf32 = malloc(4 * count);
  1538. if ((retval = xscale_receive(target, buf32, count)) != ERROR_OK)
  1539. return retval;
  1540. /* extract data from host-endian buffer into byte stream */
  1541. for (i = 0; i < count; i++)
  1542. {
  1543. switch (size)
  1544. {
  1545. case 4:
  1546. target_buffer_set_u32(target, buffer, buf32[i]);
  1547. buffer += 4;
  1548. break;
  1549. case 2:
  1550. target_buffer_set_u16(target, buffer, buf32[i] & 0xffff);
  1551. buffer += 2;
  1552. break;
  1553. case 1:
  1554. *buffer++ = buf32[i] & 0xff;
  1555. break;
  1556. default:
  1557. LOG_ERROR("should never get here");
  1558. exit(-1);
  1559. }
  1560. }
  1561. free(buf32);
  1562. /* examine DCSR, to see if Sticky Abort (SA) got set */
  1563. if ((retval = xscale_read_dcsr(target)) != ERROR_OK)
  1564. return retval;
  1565. if (buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 5, 1) == 1)
  1566. {
  1567. /* clear SA bit */
  1568. if ((retval = xscale_send_u32(target, 0x60)) != ERROR_OK)
  1569. return retval;
  1570. return ERROR_TARGET_DATA_ABORT;
  1571. }
  1572. return ERROR_OK;
  1573. }
  1574. static int xscale_write_memory(struct target_s *target, uint32_t address,
  1575. uint32_t size, uint32_t count, uint8_t *buffer)
  1576. {
  1577. armv4_5_common_t *armv4_5 = target->arch_info;
  1578. xscale_common_t *xscale = armv4_5->arch_info;
  1579. int retval;
  1580. LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32, address, size, count);
  1581. if (target->state != TARGET_HALTED)
  1582. {
  1583. LOG_WARNING("target not halted");
  1584. return ERROR_TARGET_NOT_HALTED;
  1585. }
  1586. /* sanitize arguments */
  1587. if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
  1588. return ERROR_INVALID_ARGUMENTS;
  1589. if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
  1590. return ERROR_TARGET_UNALIGNED_ACCESS;
  1591. /* send memory write request (command 0x2n, n: access size) */
  1592. if ((retval = xscale_send_u32(target, 0x20 | size)) != ERROR_OK)
  1593. return retval;
  1594. /* send base address for read request */
  1595. if ((retval = xscale_send_u32(target, address)) != ERROR_OK)
  1596. return retval;
  1597. /* send number of requested data words to be written*/
  1598. if ((retval = xscale_send_u32(target, count)) != ERROR_OK)
  1599. return retval;
  1600. /* extract data from host-endian buffer into byte stream */
  1601. #if 0
  1602. for (i = 0; i < count; i++)
  1603. {
  1604. switch (size)
  1605. {
  1606. case 4:
  1607. value = target_buffer_get_u32(target, buffer);
  1608. xscale_send_u32(target, value);
  1609. buffer += 4;
  1610. break;
  1611. case 2:
  1612. value = target_buffer_get_u16(target, buffer);
  1613. xscale_send_u32(target, value);
  1614. buffer += 2;
  1615. break;
  1616. case 1:
  1617. value = *buffer;
  1618. xscale_send_u32(target, value);
  1619. buffer += 1;
  1620. break;
  1621. default:
  1622. LOG_ERROR("should never get here");
  1623. exit(-1);
  1624. }
  1625. }
  1626. #endif
  1627. if ((retval = xscale_send(target, buffer, count, size)) != ERROR_OK)
  1628. return retval;
  1629. /* examine DCSR, to see if Sticky Abort (SA) got set */
  1630. if ((retval = xscale_read_dcsr(target)) != ERROR_OK)
  1631. return retval;
  1632. if (buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 5, 1) == 1)
  1633. {
  1634. /* clear SA bit */
  1635. if ((retval = xscale_send_u32(target, 0x60)) != ERROR_OK)
  1636. return retval;
  1637. return ERROR_TARGET_DATA_ABORT;
  1638. }
  1639. return ERROR_OK;
  1640. }
  1641. static int xscale_bulk_write_memory(target_t *target, uint32_t address,
  1642. uint32_t count, uint8_t *buffer)
  1643. {
  1644. return xscale_write_memory(target, address, 4, count, buffer);
  1645. }
  1646. static uint32_t xscale_get_ttb(target_t *target)
  1647. {
  1648. armv4_5_common_t *armv4_5 = target->arch_info;
  1649. xscale_common_t *xscale = armv4_5->arch_info;
  1650. uint32_t ttb;
  1651. xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_TTB]);
  1652. ttb = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_TTB].value, 0, 32);
  1653. return ttb;
  1654. }
  1655. static void xscale_disable_mmu_caches(target_t *target, int mmu,
  1656. int d_u_cache, int i_cache)
  1657. {
  1658. armv4_5_common_t *armv4_5 = target->arch_info;
  1659. xscale_common_t *xscale = armv4_5->arch_info;
  1660. uint32_t cp15_control;
  1661. /* read cp15 control register */
  1662. xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CTRL]);
  1663. cp15_control = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CTRL].value, 0, 32);
  1664. if (mmu)
  1665. cp15_control &= ~0x1U;
  1666. if (d_u_cache)
  1667. {
  1668. /* clean DCache */
  1669. xscale_send_u32(target, 0x50);
  1670. xscale_send_u32(target, xscale->cache_clean_address);
  1671. /* invalidate DCache */
  1672. xscale_send_u32(target, 0x51);
  1673. cp15_control &= ~0x4U;
  1674. }
  1675. if (i_cache)
  1676. {
  1677. /* invalidate ICache */
  1678. xscale_send_u32(target, 0x52);
  1679. cp15_control &= ~0x1000U;
  1680. }
  1681. /* write new cp15 control register */
  1682. xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_CTRL], cp15_control);
  1683. /* execute cpwait to ensure outstanding operations complete */
  1684. xscale_send_u32(target, 0x53);
  1685. }
  1686. static void xscale_enable_mmu_caches(target_t *target, int mmu,
  1687. int d_u_cache, int i_cache)
  1688. {
  1689. armv4_5_common_t *armv4_5 = target->arch_info;
  1690. xscale_common_t *xscale = armv4_5->arch_info;
  1691. uint32_t cp15_control;
  1692. /* read cp15 control register */
  1693. xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CTRL]);
  1694. cp15_control = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CTRL].value, 0, 32);
  1695. if (mmu)
  1696. cp15_control |= 0x1U;
  1697. if (d_u_cache)
  1698. cp15_control |= 0x4U;
  1699. if (i_cache)
  1700. cp15_control |= 0x1000U;
  1701. /* write new cp15 control register */
  1702. xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_CTRL], cp15_control);
  1703. /* execute cpwait to ensure outstanding operations complete */
  1704. xscale_send_u32(target, 0x53);
  1705. }
  1706. static int xscale_set_breakpoint(struct target_s *target,
  1707. breakpoint_t *breakpoint)
  1708. {
  1709. int retval;
  1710. armv4_5_common_t *armv4_5 = target->arch_info;
  1711. xscale_common_t *xscale = armv4_5->arch_info;
  1712. if (target->state != TARGET_HALTED)
  1713. {
  1714. LOG_WARNING("target not halted");
  1715. return ERROR_TARGET_NOT_HALTED;
  1716. }
  1717. if (breakpoint->set)
  1718. {
  1719. LOG_WARNING("breakpoint already set");
  1720. return ERROR_OK;
  1721. }
  1722. if (breakpoint->type == BKPT_HARD)
  1723. {
  1724. uint32_t value = breakpoint->address | 1;
  1725. if (!xscale->ibcr0_used)
  1726. {
  1727. xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_IBCR0], value);
  1728. xscale->ibcr0_used = 1;
  1729. breakpoint->set = 1; /* breakpoint set on first breakpoint register */
  1730. }
  1731. else if (!xscale->ibcr1_used)
  1732. {
  1733. xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_IBCR1], value);
  1734. xscale->ibcr1_used = 1;
  1735. breakpoint->set = 2; /* breakpoint set on second breakpoint register */
  1736. }
  1737. else
  1738. {
  1739. LOG_ERROR("BUG: no hardware comparator available");
  1740. return ERROR_OK;
  1741. }
  1742. }
  1743. else if (breakpoint->type == BKPT_SOFT)
  1744. {
  1745. if (breakpoint->length == 4)
  1746. {
  1747. /* keep the original instruction in target endianness */
  1748. if ((retval = target_read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
  1749. {
  1750. return retval;
  1751. }
  1752. /* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */
  1753. if ((retval = target_write_u32(target, breakpoint->address, xscale->arm_bkpt)) != ERROR_OK)
  1754. {
  1755. return retval;
  1756. }
  1757. }
  1758. else
  1759. {
  1760. /* keep the original instruction in target endianness */
  1761. if ((retval = target_read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
  1762. {
  1763. return retval;
  1764. }
  1765. /* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */
  1766. if ((retval = target_write_u32(target, breakpoint->address, xscale->thumb_bkpt)) != ERROR_OK)
  1767. {
  1768. return retval;
  1769. }
  1770. }
  1771. breakpoint->set = 1;
  1772. }
  1773. return ERROR_OK;
  1774. }
  1775. static int xscale_add_breakpoint(struct target_s *target,
  1776. breakpoint_t *breakpoint)
  1777. {
  1778. armv4_5_common_t *armv4_5 = target->arch_info;
  1779. xscale_common_t *xscale = armv4_5->arch_info;
  1780. if (target->state != TARGET_HALTED)
  1781. {
  1782. LOG_WARNING("target not halted");
  1783. return ERROR_TARGET_NOT_HALTED;
  1784. }
  1785. if ((breakpoint->type == BKPT_HARD) && (xscale->ibcr_available < 1))
  1786. {
  1787. LOG_INFO("no breakpoint unit available for hardware breakpoint");
  1788. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  1789. }
  1790. if ((breakpoint->length != 2) && (breakpoint->length != 4))
  1791. {
  1792. LOG_INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
  1793. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  1794. }
  1795. if (breakpoint->type == BKPT_HARD)
  1796. {
  1797. xscale->ibcr_available--;
  1798. }
  1799. return ERROR_OK;
  1800. }
  1801. static int xscale_unset_breakpoint(struct target_s *target,
  1802. breakpoint_t *breakpoint)
  1803. {
  1804. int retval;
  1805. armv4_5_common_t *armv4_5 = target->arch_info;
  1806. xscale_common_t *xscale = armv4_5->arch_info;
  1807. if (target->state != TARGET_HALTED)
  1808. {
  1809. LOG_WARNING("target not halted");
  1810. return ERROR_TARGET_NOT_HALTED;
  1811. }
  1812. if (!breakpoint->set)
  1813. {
  1814. LOG_WARNING("breakpoint not set");
  1815. return ERROR_OK;
  1816. }
  1817. if (breakpoint->type == BKPT_HARD)
  1818. {
  1819. if (breakpoint->set == 1)
  1820. {
  1821. xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_IBCR0], 0x0);
  1822. xscale->ibcr0_used = 0;
  1823. }
  1824. else if (breakpoint->set == 2)
  1825. {
  1826. xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_IBCR1], 0x0);
  1827. xscale->ibcr1_used = 0;
  1828. }
  1829. breakpoint->set = 0;
  1830. }
  1831. else
  1832. {
  1833. /* restore original instruction (kept in target endianness) */
  1834. if (breakpoint->length == 4)
  1835. {
  1836. if ((retval = target_write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
  1837. {
  1838. return retval;
  1839. }
  1840. }
  1841. else
  1842. {
  1843. if ((retval = target_write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
  1844. {
  1845. return retval;
  1846. }
  1847. }
  1848. breakpoint->set = 0;
  1849. }
  1850. return ERROR_OK;
  1851. }
  1852. static int xscale_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
  1853. {
  1854. armv4_5_common_t *armv4_5 = target->arch_info;
  1855. xscale_common_t *xscale = armv4_5->arch_info;
  1856. if (target->state != TARGET_HALTED)
  1857. {
  1858. LOG_WARNING("target not halted");
  1859. return ERROR_TARGET_NOT_HALTED;
  1860. }
  1861. if (breakpoint->set)
  1862. {
  1863. xscale_unset_breakpoint(target, breakpoint);
  1864. }
  1865. if (breakpoint->type == BKPT_HARD)
  1866. xscale->ibcr_available++;
  1867. return ERROR_OK;
  1868. }
  1869. static int xscale_set_watchpoint(struct target_s *target,
  1870. watchpoint_t *watchpoint)
  1871. {
  1872. armv4_5_common_t *armv4_5 = target->arch_info;
  1873. xscale_common_t *xscale = armv4_5->arch_info;
  1874. uint8_t enable = 0;
  1875. reg_t *dbcon = &xscale->reg_cache->reg_list[XSCALE_DBCON];
  1876. uint32_t dbcon_value = buf_get_u32(dbcon->value, 0, 32);
  1877. if (target->state != TARGET_HALTED)
  1878. {
  1879. LOG_WARNING("target not halted");
  1880. return ERROR_TARGET_NOT_HALTED;
  1881. }
  1882. xscale_get_reg(dbcon);
  1883. switch (watchpoint->rw)
  1884. {
  1885. case WPT_READ:
  1886. enable = 0x3;
  1887. break;
  1888. case WPT_ACCESS:
  1889. enable = 0x2;
  1890. break;
  1891. case WPT_WRITE:
  1892. enable = 0x1;
  1893. break;
  1894. default:
  1895. LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");
  1896. }
  1897. if (!xscale->dbr0_used)
  1898. {
  1899. xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_DBR0], watchpoint->address);
  1900. dbcon_value |= enable;
  1901. xscale_set_reg_u32(dbcon, dbcon_value);
  1902. watchpoint->set = 1;
  1903. xscale->dbr0_used = 1;
  1904. }
  1905. else if (!xscale->dbr1_used)
  1906. {
  1907. xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_DBR1], watchpoint->address);
  1908. dbcon_value |= enable << 2;
  1909. xscale_set_reg_u32(dbcon, dbcon_value);
  1910. watchpoint->set = 2;
  1911. xscale->dbr1_used = 1;
  1912. }
  1913. else
  1914. {
  1915. LOG_ERROR("BUG: no hardware comparator available");
  1916. return ERROR_OK;
  1917. }
  1918. return ERROR_OK;
  1919. }
  1920. static int xscale_add_watchpoint(struct target_s *target,
  1921. watchpoint_t *watchpoint)
  1922. {
  1923. armv4_5_common_t *armv4_5 = target->arch_info;
  1924. xscale_common_t *xscale = armv4_5->arch_info;
  1925. if (target->state != TARGET_HALTED)
  1926. {
  1927. LOG_WARNING("target not halted");
  1928. return ERROR_TARGET_NOT_HALTED;
  1929. }
  1930. if (xscale->dbr_available < 1)
  1931. {
  1932. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  1933. }
  1934. if ((watchpoint->length != 1) && (watchpoint->length != 2) && (watchpoint->length != 4))
  1935. {
  1936. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  1937. }
  1938. xscale->dbr_available--;
  1939. return ERROR_OK;
  1940. }
  1941. static int xscale_unset_watchpoint(struct target_s *target,
  1942. watchpoint_t *watchpoint)
  1943. {
  1944. armv4_5_common_t *armv4_5 = target->arch_info;
  1945. xscale_common_t *xscale = armv4_5->arch_info;
  1946. reg_t *dbcon = &xscale->reg_cache->reg_list[XSCALE_DBCON];
  1947. uint32_t dbcon_value = buf_get_u32(dbcon->value, 0, 32);
  1948. if (target->state != TARGET_HALTED)
  1949. {
  1950. LOG_WARNING("target not halted");
  1951. return ERROR_TARGET_NOT_HALTED;
  1952. }
  1953. if (!watchpoint->set)
  1954. {
  1955. LOG_WARNING("breakpoint not set");
  1956. return ERROR_OK;
  1957. }
  1958. if (watchpoint->set == 1)
  1959. {
  1960. dbcon_value &= ~0x3;
  1961. xscale_set_reg_u32(dbcon, dbcon_value);
  1962. xscale->dbr0_used = 0;
  1963. }
  1964. else if (watchpoint->set == 2)
  1965. {
  1966. dbcon_value &= ~0xc;
  1967. xscale_set_reg_u32(dbcon, dbcon_value);
  1968. xscale->dbr1_used = 0;
  1969. }
  1970. watchpoint->set = 0;
  1971. return ERROR_OK;
  1972. }
  1973. static int xscale_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
  1974. {
  1975. armv4_5_common_t *armv4_5 = target->arch_info;
  1976. xscale_common_t *xscale = armv4_5->arch_info;
  1977. if (target->state != TARGET_HALTED)
  1978. {
  1979. LOG_WARNING("target not halted");
  1980. return ERROR_TARGET_NOT_HALTED;
  1981. }
  1982. if (watchpoint->set)
  1983. {
  1984. xscale_unset_watchpoint(target, watchpoint);
  1985. }
  1986. xscale->dbr_available++;
  1987. return ERROR_OK;
  1988. }
  1989. static int xscale_get_reg(reg_t *reg)
  1990. {
  1991. xscale_reg_t *arch_info = reg->arch_info;
  1992. target_t *target = arch_info->target;
  1993. armv4_5_common_t *armv4_5 = target->arch_info;
  1994. xscale_common_t *xscale = armv4_5->arch_info;
  1995. /* DCSR, TX and RX are accessible via JTAG */
  1996. if (strcmp(reg->name, "XSCALE_DCSR") == 0)
  1997. {
  1998. return xscale_read_dcsr(arch_info->target);
  1999. }
  2000. else if (strcmp(reg->name, "XSCALE_TX") == 0)
  2001. {
  2002. /* 1 = consume register content */
  2003. return xscale_read_tx(arch_info->target, 1);
  2004. }
  2005. else if (strcmp(reg->name, "XSCALE_RX") == 0)
  2006. {
  2007. /* can't read from RX register (host -> debug handler) */
  2008. return ERROR_OK;
  2009. }
  2010. else if (strcmp(reg->name, "XSCALE_TXRXCTRL") == 0)
  2011. {
  2012. /* can't (explicitly) read from TXRXCTRL register */
  2013. return ERROR_OK;
  2014. }
  2015. else /* Other DBG registers have to be transfered by the debug handler */
  2016. {
  2017. /* send CP read request (command 0x40) */
  2018. xscale_send_u32(target, 0x40);
  2019. /* send CP register number */
  2020. xscale_send_u32(target, arch_info->dbg_handler_number);
  2021. /* read register value */
  2022. xscale_read_tx(target, 1);
  2023. buf_cpy(xscale->reg_cache->reg_list[XSCALE_TX].value, reg->value, 32);
  2024. reg->dirty = 0;
  2025. reg->valid = 1;
  2026. }
  2027. return ERROR_OK;
  2028. }
  2029. static int xscale_set_reg(reg_t *reg, uint8_t* buf)
  2030. {
  2031. xscale_reg_t *arch_info = reg->arch_info;
  2032. target_t *target = arch_info->target;
  2033. armv4_5_common_t *armv4_5 = target->arch_info;
  2034. xscale_common_t *xscale = armv4_5->arch_info;
  2035. uint32_t value = buf_get_u32(buf, 0, 32);
  2036. /* DCSR, TX and RX are accessible via JTAG */
  2037. if (strcmp(reg->name, "XSCALE_DCSR") == 0)
  2038. {
  2039. buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 0, 32, value);
  2040. return xscale_write_dcsr(arch_info->target, -1, -1);
  2041. }
  2042. else if (strcmp(reg->name, "XSCALE_RX") == 0)
  2043. {
  2044. buf_set_u32(xscale->reg_cache->reg_list[XSCALE_RX].value, 0, 32, value);
  2045. return xscale_write_rx(arch_info->target);
  2046. }
  2047. else if (strcmp(reg->name, "XSCALE_TX") == 0)
  2048. {
  2049. /* can't write to TX register (debug-handler -> host) */
  2050. return ERROR_OK;
  2051. }
  2052. else if (strcmp(reg->name, "XSCALE_TXRXCTRL") == 0)
  2053. {
  2054. /* can't (explicitly) write to TXRXCTRL register */
  2055. return ERROR_OK;
  2056. }
  2057. else /* Other DBG registers have to be transfered by the debug handler */
  2058. {
  2059. /* send CP write request (command 0x41) */
  2060. xscale_send_u32(target, 0x41);
  2061. /* send CP register number */
  2062. xscale_send_u32(target, arch_info->dbg_handler_number);
  2063. /* send CP register value */
  2064. xscale_send_u32(target, value);
  2065. buf_set_u32(reg->value, 0, 32, value);
  2066. }
  2067. return ERROR_OK;
  2068. }
  2069. static int xscale_write_dcsr_sw(target_t *target, uint32_t value)
  2070. {
  2071. /* get pointers to arch-specific information */
  2072. armv4_5_common_t *armv4_5 = target->arch_info;
  2073. xscale_common_t *xscale = armv4_5->arch_info;
  2074. reg_t *dcsr = &xscale->reg_cache->reg_list[XSCALE_DCSR];
  2075. xscale_reg_t *dcsr_arch_info = dcsr->arch_info;
  2076. /* send CP write request (command 0x41) */
  2077. xscale_send_u32(target, 0x41);
  2078. /* send CP register number */
  2079. xscale_send_u32(target, dcsr_arch_info->dbg_handler_number);
  2080. /* send CP register value */
  2081. xscale_send_u32(target, value);
  2082. buf_set_u32(dcsr->value, 0, 32, value);
  2083. return ERROR_OK;
  2084. }
  2085. static int xscale_read_trace(target_t *target)
  2086. {
  2087. /* get pointers to arch-specific information */
  2088. armv4_5_common_t *armv4_5 = target->arch_info;
  2089. xscale_common_t *xscale = armv4_5->arch_info;
  2090. xscale_trace_data_t **trace_data_p;
  2091. /* 258 words from debug handler
  2092. * 256 trace buffer entries
  2093. * 2 checkpoint addresses
  2094. */
  2095. uint32_t trace_buffer[258];
  2096. int is_address[256];
  2097. int i, j;
  2098. if (target->state != TARGET_HALTED)
  2099. {
  2100. LOG_WARNING("target must be stopped to read trace data");
  2101. return ERROR_TARGET_NOT_HALTED;
  2102. }
  2103. /* send read trace buffer command (command 0x61) */
  2104. xscale_send_u32(target, 0x61);
  2105. /* receive trace buffer content */
  2106. xscale_receive(target, trace_buffer, 258);
  2107. /* parse buffer backwards to identify address entries */
  2108. for (i = 255; i >= 0; i--)
  2109. {
  2110. is_address[i] = 0;
  2111. if (((trace_buffer[i] & 0xf0) == 0x90) ||
  2112. ((trace_buffer[i] & 0xf0) == 0xd0))
  2113. {
  2114. if (i >= 3)
  2115. is_address[--i] = 1;
  2116. if (i >= 2)
  2117. is_address[--i] = 1;
  2118. if (i >= 1)
  2119. is_address[--i] = 1;
  2120. if (i >= 0)
  2121. is_address[--i] = 1;
  2122. }
  2123. }
  2124. /* search first non-zero entry */
  2125. for (j = 0; (j < 256) && (trace_buffer[j] == 0) && (!is_address[j]); j++)
  2126. ;
  2127. if (j == 256)
  2128. {
  2129. LOG_DEBUG("no trace data collected");
  2130. return ERROR_XSCALE_NO_TRACE_DATA;
  2131. }
  2132. for (trace_data_p = &xscale->trace.data; *trace_data_p; trace_data_p = &(*trace_data_p)->next)
  2133. ;
  2134. *trace_data_p = malloc(sizeof(xscale_trace_data_t));
  2135. (*trace_data_p)->next = NULL;
  2136. (*trace_data_p)->chkpt0 = trace_buffer[256];
  2137. (*trace_data_p)->chkpt1 = trace_buffer[257];
  2138. (*trace_data_p)->last_instruction = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
  2139. (*trace_data_p)->entries = malloc(sizeof(xscale_trace_entry_t) * (256 - j));
  2140. (*trace_data_p)->depth = 256 - j;
  2141. for (i = j; i < 256; i++)
  2142. {
  2143. (*trace_data_p)->entries[i - j].data = trace_buffer[i];
  2144. if (is_address[i])
  2145. (*trace_data_p)->entries[i - j].type = XSCALE_TRACE_ADDRESS;
  2146. else
  2147. (*trace_data_p)->entries[i - j].type = XSCALE_TRACE_MESSAGE;
  2148. }
  2149. return ERROR_OK;
  2150. }
  2151. static int xscale_read_instruction(target_t *target,
  2152. arm_instruction_t *instruction)
  2153. {
  2154. /* get pointers to arch-specific information */
  2155. armv4_5_common_t *armv4_5 = target->arch_info;
  2156. xscale_common_t *xscale = armv4_5->arch_info;
  2157. int i;
  2158. int section = -1;
  2159. uint32_t size_read;
  2160. uint32_t opcode;
  2161. int retval;
  2162. if (!xscale->trace.image)
  2163. return ERROR_TRACE_IMAGE_UNAVAILABLE;
  2164. /* search for the section the current instruction belongs to */
  2165. for (i = 0; i < xscale->trace.image->num_sections; i++)
  2166. {
  2167. if ((xscale->trace.image->sections[i].base_address <= xscale->trace.current_pc) &&
  2168. (xscale->trace.image->sections[i].base_address + xscale->trace.image->sections[i].size > xscale->trace.current_pc))
  2169. {
  2170. section = i;
  2171. break;
  2172. }
  2173. }
  2174. if (section == -1)
  2175. {
  2176. /* current instruction couldn't be found in the image */
  2177. return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
  2178. }
  2179. if (xscale->trace.core_state == ARMV4_5_STATE_ARM)
  2180. {
  2181. uint8_t buf[4];
  2182. if ((retval = image_read_section(xscale->trace.image, section,
  2183. xscale->trace.current_pc - xscale->trace.image->sections[section].base_address,
  2184. 4, buf, &size_read)) != ERROR_OK)
  2185. {
  2186. LOG_ERROR("error while reading instruction: %i", retval);
  2187. return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
  2188. }
  2189. opcode = target_buffer_get_u32(target, buf);
  2190. arm_evaluate_opcode(opcode, xscale->trace.current_pc, instruction);
  2191. }
  2192. else if (xscale->trace.core_state == ARMV4_5_STATE_THUMB)
  2193. {
  2194. uint8_t buf[2];
  2195. if ((retval = image_read_section(xscale->trace.image, section,
  2196. xscale->trace.current_pc - xscale->trace.image->sections[section].base_address,
  2197. 2, buf, &size_read)) != ERROR_OK)
  2198. {
  2199. LOG_ERROR("error while reading instruction: %i", retval);
  2200. return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
  2201. }
  2202. opcode = target_buffer_get_u16(target, buf);
  2203. thumb_evaluate_opcode(opcode, xscale->trace.current_pc, instruction);
  2204. }
  2205. else
  2206. {
  2207. LOG_ERROR("BUG: unknown core state encountered");
  2208. exit(-1);
  2209. }
  2210. return ERROR_OK;
  2211. }
  2212. static int xscale_branch_address(xscale_trace_data_t *trace_data,
  2213. int i, uint32_t *target)
  2214. {
  2215. /* if there are less than four entries prior to the indirect branch message
  2216. * we can't extract the address */
  2217. if (i < 4)
  2218. {
  2219. return -1;
  2220. }
  2221. *target = (trace_data->entries[i-1].data) | (trace_data->entries[i-2].data << 8) |
  2222. (trace_data->entries[i-3].data << 16) | (trace_data->entries[i-4].data << 24);
  2223. return 0;
  2224. }
  2225. static int xscale_analyze_trace(target_t *target, command_context_t *cmd_ctx)
  2226. {
  2227. /* get pointers to arch-specific information */
  2228. armv4_5_common_t *armv4_5 = target->arch_info;
  2229. xscale_common_t *xscale = armv4_5->arch_info;
  2230. int next_pc_ok = 0;
  2231. uint32_t next_pc = 0x0;
  2232. xscale_trace_data_t *trace_data = xscale->trace.data;
  2233. int retval;
  2234. while (trace_data)
  2235. {
  2236. int i, chkpt;
  2237. int rollover;
  2238. int branch;
  2239. int exception;
  2240. xscale->trace.core_state = ARMV4_5_STATE_ARM;
  2241. chkpt = 0;
  2242. rollover = 0;
  2243. for (i = 0; i < trace_data->depth; i++)
  2244. {
  2245. next_pc_ok = 0;
  2246. branch = 0;
  2247. exception = 0;
  2248. if (trace_data->entries[i].type == XSCALE_TRACE_ADDRESS)
  2249. continue;
  2250. switch ((trace_data->entries[i].data & 0xf0) >> 4)
  2251. {
  2252. case 0: /* Exceptions */
  2253. case 1:
  2254. case 2:
  2255. case 3:
  2256. case 4:
  2257. case 5:
  2258. case 6:
  2259. case 7:
  2260. exception = (trace_data->entries[i].data & 0x70) >> 4;
  2261. next_pc_ok = 1;
  2262. next_pc = (trace_data->entries[i].data & 0xf0) >> 2;
  2263. command_print(cmd_ctx, "--- exception %i ---", (trace_data->entries[i].data & 0xf0) >> 4);
  2264. break;
  2265. case 8: /* Direct Branch */
  2266. branch = 1;
  2267. break;
  2268. case 9: /* Indirect Branch */
  2269. branch = 1;
  2270. if (xscale_branch_address(trace_data, i, &next_pc) == 0)
  2271. {
  2272. next_pc_ok = 1;
  2273. }
  2274. break;
  2275. case 13: /* Checkpointed Indirect Branch */
  2276. if (xscale_branch_address(trace_data, i, &next_pc) == 0)
  2277. {
  2278. next_pc_ok = 1;
  2279. if (((chkpt == 0) && (next_pc != trace_data->chkpt0))
  2280. || ((chkpt == 1) && (next_pc != trace_data->chkpt1)))
  2281. LOG_WARNING("checkpointed indirect branch target address doesn't match checkpoint");
  2282. }
  2283. /* explicit fall-through */
  2284. case 12: /* Checkpointed Direct Branch */
  2285. branch = 1;
  2286. if (chkpt == 0)
  2287. {
  2288. next_pc_ok = 1;
  2289. next_pc = trace_data->chkpt0;
  2290. chkpt++;
  2291. }
  2292. else if (chkpt == 1)
  2293. {
  2294. next_pc_ok = 1;
  2295. next_pc = trace_data->chkpt0;
  2296. chkpt++;
  2297. }
  2298. else
  2299. {
  2300. LOG_WARNING("more than two checkpointed branches encountered");
  2301. }
  2302. break;
  2303. case 15: /* Roll-over */
  2304. rollover++;
  2305. continue;
  2306. default: /* Reserved */
  2307. command_print(cmd_ctx, "--- reserved trace message ---");
  2308. LOG_ERROR("BUG: trace message %i is reserved", (trace_data->entries[i].data & 0xf0) >> 4);
  2309. return ERROR_OK;
  2310. }
  2311. if (xscale->trace.pc_ok)
  2312. {
  2313. int executed = (trace_data->entries[i].data & 0xf) + rollover * 16;
  2314. arm_instruction_t instruction;
  2315. if ((exception == 6) || (exception == 7))
  2316. {
  2317. /* IRQ or FIQ exception, no instruction executed */
  2318. executed -= 1;
  2319. }
  2320. while (executed-- >= 0)
  2321. {
  2322. if ((retval = xscale_read_instruction(target, &instruction)) != ERROR_OK)
  2323. {
  2324. /* can't continue tracing with no image available */
  2325. if (retval == ERROR_TRACE_IMAGE_UNAVAILABLE)
  2326. {
  2327. return retval;
  2328. }
  2329. else if (retval == ERROR_TRACE_INSTRUCTION_UNAVAILABLE)
  2330. {
  2331. /* TODO: handle incomplete images */
  2332. }
  2333. }
  2334. /* a precise abort on a load to the PC is included in the incremental
  2335. * word count, other instructions causing data aborts are not included
  2336. */
  2337. if ((executed == 0) && (exception == 4)
  2338. && ((instruction.type >= ARM_LDR) && (instruction.type <= ARM_LDM)))
  2339. {
  2340. if ((instruction.type == ARM_LDM)
  2341. && ((instruction.info.load_store_multiple.register_list & 0x8000) == 0))
  2342. {
  2343. executed--;
  2344. }
  2345. else if (((instruction.type >= ARM_LDR) && (instruction.type <= ARM_LDRSH))
  2346. && (instruction.info.load_store.Rd != 15))
  2347. {
  2348. executed--;
  2349. }
  2350. }
  2351. /* only the last instruction executed
  2352. * (the one that caused the control flow change)
  2353. * could be a taken branch
  2354. */
  2355. if (((executed == -1) && (branch == 1)) &&
  2356. (((instruction.type == ARM_B) ||
  2357. (instruction.type == ARM_BL) ||
  2358. (instruction.type == ARM_BLX)) &&
  2359. (instruction.info.b_bl_bx_blx.target_address != 0xffffffff)))
  2360. {
  2361. xscale->trace.current_pc = instruction.info.b_bl_bx_blx.target_address;
  2362. }
  2363. else
  2364. {
  2365. xscale->trace.current_pc += (xscale->trace.core_state == ARMV4_5_STATE_ARM) ? 4 : 2;
  2366. }
  2367. command_print(cmd_ctx, "%s", instruction.text);
  2368. }
  2369. rollover = 0;
  2370. }
  2371. if (next_pc_ok)
  2372. {
  2373. xscale->trace.current_pc = next_pc;
  2374. xscale->trace.pc_ok = 1;
  2375. }
  2376. }
  2377. for (; xscale->trace.current_pc < trace_data->last_instruction; xscale->trace.current_pc += (xscale->trace.core_state == ARMV4_5_STATE_ARM) ? 4 : 2)
  2378. {
  2379. arm_instruction_t instruction;
  2380. if ((retval = xscale_read_instruction(target, &instruction)) != ERROR_OK)
  2381. {
  2382. /* can't continue tracing with no image available */
  2383. if (retval == ERROR_TRACE_IMAGE_UNAVAILABLE)
  2384. {
  2385. return retval;
  2386. }
  2387. else if (retval == ERROR_TRACE_INSTRUCTION_UNAVAILABLE)
  2388. {
  2389. /* TODO: handle incomplete images */
  2390. }
  2391. }
  2392. command_print(cmd_ctx, "%s", instruction.text);
  2393. }
  2394. trace_data = trace_data->next;
  2395. }
  2396. return ERROR_OK;
  2397. }
  2398. static void xscale_build_reg_cache(target_t *target)
  2399. {
  2400. /* get pointers to arch-specific information */
  2401. armv4_5_common_t *armv4_5 = target->arch_info;
  2402. xscale_common_t *xscale = armv4_5->arch_info;
  2403. reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
  2404. xscale_reg_t *arch_info = malloc(sizeof(xscale_reg_arch_info));
  2405. int i;
  2406. int num_regs = sizeof(xscale_reg_arch_info) / sizeof(xscale_reg_t);
  2407. (*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
  2408. armv4_5->core_cache = (*cache_p);
  2409. /* register a register arch-type for XScale dbg registers only once */
  2410. if (xscale_reg_arch_type == -1)
  2411. xscale_reg_arch_type = register_reg_arch_type(xscale_get_reg, xscale_set_reg);
  2412. (*cache_p)->next = malloc(sizeof(reg_cache_t));
  2413. cache_p = &(*cache_p)->next;
  2414. /* fill in values for the xscale reg cache */
  2415. (*cache_p)->name = "XScale registers";
  2416. (*cache_p)->next = NULL;
  2417. (*cache_p)->reg_list = malloc(num_regs * sizeof(reg_t));
  2418. (*cache_p)->num_regs = num_regs;
  2419. for (i = 0; i < num_regs; i++)
  2420. {
  2421. (*cache_p)->reg_list[i].name = xscale_reg_list[i];
  2422. (*cache_p)->reg_list[i].value = calloc(4, 1);
  2423. (*cache_p)->reg_list[i].dirty = 0;
  2424. (*cache_p)->reg_list[i].valid = 0;
  2425. (*cache_p)->reg_list[i].size = 32;
  2426. (*cache_p)->reg_list[i].bitfield_desc = NULL;
  2427. (*cache_p)->reg_list[i].num_bitfields = 0;
  2428. (*cache_p)->reg_list[i].arch_info = &arch_info[i];
  2429. (*cache_p)->reg_list[i].arch_type = xscale_reg_arch_type;
  2430. arch_info[i] = xscale_reg_arch_info[i];
  2431. arch_info[i].target = target;
  2432. }
  2433. xscale->reg_cache = (*cache_p);
  2434. }
  2435. static int xscale_init_target(struct command_context_s *cmd_ctx,
  2436. struct target_s *target)
  2437. {
  2438. xscale_build_reg_cache(target);
  2439. return ERROR_OK;
  2440. }
  2441. static int xscale_quit(void)
  2442. {
  2443. jtag_add_runtest(100, TAP_RESET);
  2444. return ERROR_OK;
  2445. }
  2446. static int xscale_init_arch_info(target_t *target,
  2447. xscale_common_t *xscale, jtag_tap_t *tap, const char *variant)
  2448. {
  2449. armv4_5_common_t *armv4_5;
  2450. uint32_t high_reset_branch, low_reset_branch;
  2451. int i;
  2452. armv4_5 = &xscale->armv4_5_common;
  2453. /* store architecture specfic data (none so far) */
  2454. xscale->arch_info = NULL;
  2455. xscale->common_magic = XSCALE_COMMON_MAGIC;
  2456. /* we don't really *need* variant info ... */
  2457. if (variant) {
  2458. int ir_length = 0;
  2459. if (strcmp(variant, "pxa250") == 0
  2460. || strcmp(variant, "pxa255") == 0
  2461. || strcmp(variant, "pxa26x") == 0)
  2462. ir_length = 5;
  2463. else if (strcmp(variant, "pxa27x") == 0
  2464. || strcmp(variant, "ixp42x") == 0
  2465. || strcmp(variant, "ixp45x") == 0
  2466. || strcmp(variant, "ixp46x") == 0)
  2467. ir_length = 7;
  2468. else
  2469. LOG_WARNING("%s: unrecognized variant %s",
  2470. tap->dotted_name, variant);
  2471. if (ir_length && ir_length != tap->ir_length) {
  2472. LOG_WARNING("%s: IR length for %s is %d; fixing",
  2473. tap->dotted_name, variant, ir_length);
  2474. tap->ir_length = ir_length;
  2475. }
  2476. }
  2477. /* the debug handler isn't installed (and thus not running) at this time */
  2478. xscale->handler_installed = 0;
  2479. xscale->handler_running = 0;
  2480. xscale->handler_address = 0xfe000800;
  2481. /* clear the vectors we keep locally for reference */
  2482. memset(xscale->low_vectors, 0, sizeof(xscale->low_vectors));
  2483. memset(xscale->high_vectors, 0, sizeof(xscale->high_vectors));
  2484. /* no user-specified vectors have been configured yet */
  2485. xscale->static_low_vectors_set = 0x0;
  2486. xscale->static_high_vectors_set = 0x0;
  2487. /* calculate branches to debug handler */
  2488. low_reset_branch = (xscale->handler_address + 0x20 - 0x0 - 0x8) >> 2;
  2489. high_reset_branch = (xscale->handler_address + 0x20 - 0xffff0000 - 0x8) >> 2;
  2490. xscale->low_vectors[0] = ARMV4_5_B((low_reset_branch & 0xffffff), 0);
  2491. xscale->high_vectors[0] = ARMV4_5_B((high_reset_branch & 0xffffff), 0);
  2492. for (i = 1; i <= 7; i++)
  2493. {
  2494. xscale->low_vectors[i] = ARMV4_5_B(0xfffffe, 0);
  2495. xscale->high_vectors[i] = ARMV4_5_B(0xfffffe, 0);
  2496. }
  2497. /* 64kB aligned region used for DCache cleaning */
  2498. xscale->cache_clean_address = 0xfffe0000;
  2499. xscale->hold_rst = 0;
  2500. xscale->external_debug_break = 0;
  2501. xscale->ibcr_available = 2;
  2502. xscale->ibcr0_used = 0;
  2503. xscale->ibcr1_used = 0;
  2504. xscale->dbr_available = 2;
  2505. xscale->dbr0_used = 0;
  2506. xscale->dbr1_used = 0;
  2507. xscale->arm_bkpt = ARMV5_BKPT(0x0);
  2508. xscale->thumb_bkpt = ARMV5_T_BKPT(0x0) & 0xffff;
  2509. xscale->vector_catch = 0x1;
  2510. xscale->trace.capture_status = TRACE_IDLE;
  2511. xscale->trace.data = NULL;
  2512. xscale->trace.image = NULL;
  2513. xscale->trace.buffer_enabled = 0;
  2514. xscale->trace.buffer_fill = 0;
  2515. /* prepare ARMv4/5 specific information */
  2516. armv4_5->arch_info = xscale;
  2517. armv4_5->read_core_reg = xscale_read_core_reg;
  2518. armv4_5->write_core_reg = xscale_write_core_reg;
  2519. armv4_5->full_context = xscale_full_context;
  2520. armv4_5_init_arch_info(target, armv4_5);
  2521. xscale->armv4_5_mmu.armv4_5_cache.ctype = -1;
  2522. xscale->armv4_5_mmu.get_ttb = xscale_get_ttb;
  2523. xscale->armv4_5_mmu.read_memory = xscale_read_memory;
  2524. xscale->armv4_5_mmu.write_memory = xscale_write_memory;
  2525. xscale->armv4_5_mmu.disable_mmu_caches = xscale_disable_mmu_caches;
  2526. xscale->armv4_5_mmu.enable_mmu_caches = xscale_enable_mmu_caches;
  2527. xscale->armv4_5_mmu.has_tiny_pages = 1;
  2528. xscale->armv4_5_mmu.mmu_enabled = 0;
  2529. return ERROR_OK;
  2530. }
  2531. static int xscale_target_create(struct target_s *target, Jim_Interp *interp)
  2532. {
  2533. xscale_common_t *xscale;
  2534. if (xscale_debug_handler_size > 0x800) {
  2535. LOG_ERROR("debug_handler.bin: larger than 2kb");
  2536. return ERROR_FAIL;
  2537. }
  2538. xscale = calloc(1, sizeof(*xscale));
  2539. if (!xscale)
  2540. return ERROR_FAIL;
  2541. return xscale_init_arch_info(target, xscale, target->tap,
  2542. target->variant);
  2543. }
  2544. static int
  2545. xscale_handle_debug_handler_command(struct command_context_s *cmd_ctx,
  2546. char *cmd, char **args, int argc)
  2547. {
  2548. target_t *target = NULL;
  2549. armv4_5_common_t *armv4_5;
  2550. xscale_common_t *xscale;
  2551. uint32_t handler_address;
  2552. if (argc < 2)
  2553. {
  2554. LOG_ERROR("'xscale debug_handler <target#> <address>' command takes two required operands");
  2555. return ERROR_OK;
  2556. }
  2557. if ((target = get_target(args[0])) == NULL)
  2558. {
  2559. LOG_ERROR("target '%s' not defined", args[0]);
  2560. return ERROR_FAIL;
  2561. }
  2562. if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK)
  2563. {
  2564. return ERROR_FAIL;
  2565. }
  2566. handler_address = strtoul(args[1], NULL, 0);
  2567. if (((handler_address >= 0x800) && (handler_address <= 0x1fef800)) ||
  2568. ((handler_address >= 0xfe000800) && (handler_address <= 0xfffff800)))
  2569. {
  2570. xscale->handler_address = handler_address;
  2571. }
  2572. else
  2573. {
  2574. LOG_ERROR("xscale debug_handler <address> must be between 0x800 and 0x1fef800 or between 0xfe000800 and 0xfffff800");
  2575. return ERROR_FAIL;
  2576. }
  2577. return ERROR_OK;
  2578. }
  2579. static int
  2580. xscale_handle_cache_clean_address_command(struct command_context_s *cmd_ctx,
  2581. char *cmd, char **args, int argc)
  2582. {
  2583. target_t *target = NULL;
  2584. armv4_5_common_t *armv4_5;
  2585. xscale_common_t *xscale;
  2586. uint32_t cache_clean_address;
  2587. if (argc < 2)
  2588. {
  2589. return ERROR_COMMAND_SYNTAX_ERROR;
  2590. }
  2591. target = get_target(args[0]);
  2592. if (target == NULL)
  2593. {
  2594. LOG_ERROR("target '%s' not defined", args[0]);
  2595. return ERROR_FAIL;
  2596. }
  2597. if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK)
  2598. {
  2599. return ERROR_FAIL;
  2600. }
  2601. cache_clean_address = strtoul(args[1], NULL, 0);
  2602. if (cache_clean_address & 0xffff)
  2603. {
  2604. LOG_ERROR("xscale cache_clean_address <address> must be 64kb aligned");
  2605. }
  2606. else
  2607. {
  2608. xscale->cache_clean_address = cache_clean_address;
  2609. }
  2610. return ERROR_OK;
  2611. }
  2612. static int
  2613. xscale_handle_cache_info_command(struct command_context_s *cmd_ctx,
  2614. char *cmd, char **args, int argc)
  2615. {
  2616. target_t *target = get_current_target(cmd_ctx);
  2617. armv4_5_common_t *armv4_5;
  2618. xscale_common_t *xscale;
  2619. if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK)
  2620. {
  2621. return ERROR_OK;
  2622. }
  2623. return armv4_5_handle_cache_info_command(cmd_ctx, &xscale->armv4_5_mmu.armv4_5_cache);
  2624. }
  2625. static int xscale_virt2phys(struct target_s *target,
  2626. uint32_t virtual, uint32_t *physical)
  2627. {
  2628. armv4_5_common_t *armv4_5;
  2629. xscale_common_t *xscale;
  2630. int retval;
  2631. int type;
  2632. uint32_t cb;
  2633. int domain;
  2634. uint32_t ap;
  2635. if ((retval = xscale_get_arch_pointers(target, &armv4_5, &xscale)) != ERROR_OK)
  2636. {
  2637. return retval;
  2638. }
  2639. uint32_t ret = armv4_5_mmu_translate_va(target, &xscale->armv4_5_mmu, virtual, &type, &cb, &domain, &ap);
  2640. if (type == -1)
  2641. {
  2642. return ret;
  2643. }
  2644. *physical = ret;
  2645. return ERROR_OK;
  2646. }
  2647. static int xscale_mmu(struct target_s *target, int *enabled)
  2648. {
  2649. armv4_5_common_t *armv4_5 = target->arch_info;
  2650. xscale_common_t *xscale = armv4_5->arch_info;
  2651. if (target->state != TARGET_HALTED)
  2652. {
  2653. LOG_ERROR("Target not halted");
  2654. return ERROR_TARGET_INVALID;
  2655. }
  2656. *enabled = xscale->armv4_5_mmu.mmu_enabled;
  2657. return ERROR_OK;
  2658. }
  2659. static int xscale_handle_mmu_command(command_context_t *cmd_ctx,
  2660. char *cmd, char **args, int argc)
  2661. {
  2662. target_t *target = get_current_target(cmd_ctx);
  2663. armv4_5_common_t *armv4_5;
  2664. xscale_common_t *xscale;
  2665. if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK)
  2666. {
  2667. return ERROR_OK;
  2668. }
  2669. if (target->state != TARGET_HALTED)
  2670. {
  2671. command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
  2672. return ERROR_OK;
  2673. }
  2674. if (argc >= 1)
  2675. {
  2676. if (strcmp("enable", args[0]) == 0)
  2677. {
  2678. xscale_enable_mmu_caches(target, 1, 0, 0);
  2679. xscale->armv4_5_mmu.mmu_enabled = 1;
  2680. }
  2681. else if (strcmp("disable", args[0]) == 0)
  2682. {
  2683. xscale_disable_mmu_caches(target, 1, 0, 0);
  2684. xscale->armv4_5_mmu.mmu_enabled = 0;
  2685. }
  2686. }
  2687. command_print(cmd_ctx, "mmu %s", (xscale->armv4_5_mmu.mmu_enabled) ? "enabled" : "disabled");
  2688. return ERROR_OK;
  2689. }
  2690. static int xscale_handle_idcache_command(command_context_t *cmd_ctx,
  2691. char *cmd, char **args, int argc)
  2692. {
  2693. target_t *target = get_current_target(cmd_ctx);
  2694. armv4_5_common_t *armv4_5;
  2695. xscale_common_t *xscale;
  2696. int icache = 0, dcache = 0;
  2697. if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK)
  2698. {
  2699. return ERROR_OK;
  2700. }
  2701. if (target->state != TARGET_HALTED)
  2702. {
  2703. command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
  2704. return ERROR_OK;
  2705. }
  2706. if (strcmp(cmd, "icache") == 0)
  2707. icache = 1;
  2708. else if (strcmp(cmd, "dcache") == 0)
  2709. dcache = 1;
  2710. if (argc >= 1)
  2711. {
  2712. if (strcmp("enable", args[0]) == 0)
  2713. {
  2714. xscale_enable_mmu_caches(target, 0, dcache, icache);
  2715. if (icache)
  2716. xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 1;
  2717. else if (dcache)
  2718. xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 1;
  2719. }
  2720. else if (strcmp("disable", args[0]) == 0)
  2721. {
  2722. xscale_disable_mmu_caches(target, 0, dcache, icache);
  2723. if (icache)
  2724. xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
  2725. else if (dcache)
  2726. xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
  2727. }
  2728. }
  2729. if (icache)
  2730. command_print(cmd_ctx, "icache %s", (xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled) ? "enabled" : "disabled");
  2731. if (dcache)
  2732. command_print(cmd_ctx, "dcache %s", (xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) ? "enabled" : "disabled");
  2733. return ERROR_OK;
  2734. }
  2735. static int xscale_handle_vector_catch_command(command_context_t *cmd_ctx,
  2736. char *cmd, char **args, int argc)
  2737. {
  2738. target_t *target = get_current_target(cmd_ctx);
  2739. armv4_5_common_t *armv4_5;
  2740. xscale_common_t *xscale;
  2741. if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK)
  2742. {
  2743. return ERROR_OK;
  2744. }
  2745. if (argc < 1)
  2746. {
  2747. command_print(cmd_ctx, "usage: xscale vector_catch [mask]");
  2748. }
  2749. else
  2750. {
  2751. xscale->vector_catch = strtoul(args[0], NULL, 0);
  2752. buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 16, 8, xscale->vector_catch);
  2753. xscale_write_dcsr(target, -1, -1);
  2754. }
  2755. command_print(cmd_ctx, "vector catch mask: 0x%2.2x", xscale->vector_catch);
  2756. return ERROR_OK;
  2757. }
  2758. static int xscale_handle_vector_table_command(command_context_t *cmd_ctx,
  2759. char *cmd, char **args, int argc)
  2760. {
  2761. target_t *target = get_current_target(cmd_ctx);
  2762. armv4_5_common_t *armv4_5;
  2763. xscale_common_t *xscale;
  2764. int err = 0;
  2765. if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK)
  2766. {
  2767. return ERROR_OK;
  2768. }
  2769. if (argc == 0) /* print current settings */
  2770. {
  2771. int idx;
  2772. command_print(cmd_ctx, "active user-set static vectors:");
  2773. for (idx = 1; idx < 8; idx++)
  2774. if (xscale->static_low_vectors_set & (1 << idx))
  2775. command_print(cmd_ctx, "low %d: 0x%" PRIx32, idx, xscale->static_low_vectors[idx]);
  2776. for (idx = 1; idx < 8; idx++)
  2777. if (xscale->static_high_vectors_set & (1 << idx))
  2778. command_print(cmd_ctx, "high %d: 0x%" PRIx32, idx, xscale->static_high_vectors[idx]);
  2779. return ERROR_OK;
  2780. }
  2781. if (argc != 3)
  2782. err = 1;
  2783. else
  2784. {
  2785. int idx;
  2786. uint32_t vec;
  2787. idx = strtoul(args[1], NULL, 0);
  2788. vec = strtoul(args[2], NULL, 0);
  2789. if (idx < 1 || idx >= 8)
  2790. err = 1;
  2791. if (!err && strcmp(args[0], "low") == 0)
  2792. {
  2793. xscale->static_low_vectors_set |= (1<<idx);
  2794. xscale->static_low_vectors[idx] = vec;
  2795. }
  2796. else if (!err && (strcmp(args[0], "high") == 0))
  2797. {
  2798. xscale->static_high_vectors_set |= (1<<idx);
  2799. xscale->static_high_vectors[idx] = vec;
  2800. }
  2801. else
  2802. err = 1;
  2803. }
  2804. if (err)
  2805. command_print(cmd_ctx, "usage: xscale vector_table <high|low> <index> <code>");
  2806. return ERROR_OK;
  2807. }
  2808. static int
  2809. xscale_handle_trace_buffer_command(struct command_context_s *cmd_ctx,
  2810. char *cmd, char **args, int argc)
  2811. {
  2812. target_t *target = get_current_target(cmd_ctx);
  2813. armv4_5_common_t *armv4_5;
  2814. xscale_common_t *xscale;
  2815. uint32_t dcsr_value;
  2816. if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK)
  2817. {
  2818. return ERROR_OK;
  2819. }
  2820. if (target->state != TARGET_HALTED)
  2821. {
  2822. command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
  2823. return ERROR_OK;
  2824. }
  2825. if ((argc >= 1) && (strcmp("enable", args[0]) == 0))
  2826. {
  2827. xscale_trace_data_t *td, *next_td;
  2828. xscale->trace.buffer_enabled = 1;
  2829. /* free old trace data */
  2830. td = xscale->trace.data;
  2831. while (td)
  2832. {
  2833. next_td = td->next;
  2834. if (td->entries)
  2835. free(td->entries);
  2836. free(td);
  2837. td = next_td;
  2838. }
  2839. xscale->trace.data = NULL;
  2840. }
  2841. else if ((argc >= 1) && (strcmp("disable", args[0]) == 0))
  2842. {
  2843. xscale->trace.buffer_enabled = 0;
  2844. }
  2845. if ((argc >= 2) && (strcmp("fill", args[1]) == 0))
  2846. {
  2847. if (argc >= 3)
  2848. xscale->trace.buffer_fill = strtoul(args[2], NULL, 0);
  2849. else
  2850. xscale->trace.buffer_fill = 1;
  2851. }
  2852. else if ((argc >= 2) && (strcmp("wrap", args[1]) == 0))
  2853. {
  2854. xscale->trace.buffer_fill = -1;
  2855. }
  2856. if (xscale->trace.buffer_enabled)
  2857. {
  2858. /* if we enable the trace buffer in fill-once
  2859. * mode we know the address of the first instruction */
  2860. xscale->trace.pc_ok = 1;
  2861. xscale->trace.current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
  2862. }
  2863. else
  2864. {
  2865. /* otherwise the address is unknown, and we have no known good PC */
  2866. xscale->trace.pc_ok = 0;
  2867. }
  2868. command_print(cmd_ctx, "trace buffer %s (%s)",
  2869. (xscale->trace.buffer_enabled) ? "enabled" : "disabled",
  2870. (xscale->trace.buffer_fill > 0) ? "fill" : "wrap");
  2871. dcsr_value = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 0, 32);
  2872. if (xscale->trace.buffer_fill >= 0)
  2873. xscale_write_dcsr_sw(target, (dcsr_value & 0xfffffffc) | 2);
  2874. else
  2875. xscale_write_dcsr_sw(target, dcsr_value & 0xfffffffc);
  2876. return ERROR_OK;
  2877. }
  2878. static int
  2879. xscale_handle_trace_image_command(struct command_context_s *cmd_ctx,
  2880. char *cmd, char **args, int argc)
  2881. {
  2882. target_t *target;
  2883. armv4_5_common_t *armv4_5;
  2884. xscale_common_t *xscale;
  2885. if (argc < 1)
  2886. {
  2887. command_print(cmd_ctx, "usage: xscale trace_image <file> [base address] [type]");
  2888. return ERROR_OK;
  2889. }
  2890. target = get_current_target(cmd_ctx);
  2891. if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK)
  2892. {
  2893. return ERROR_OK;
  2894. }
  2895. if (xscale->trace.image)
  2896. {
  2897. image_close(xscale->trace.image);
  2898. free(xscale->trace.image);
  2899. command_print(cmd_ctx, "previously loaded image found and closed");
  2900. }
  2901. xscale->trace.image = malloc(sizeof(image_t));
  2902. xscale->trace.image->base_address_set = 0;
  2903. xscale->trace.image->start_address_set = 0;
  2904. /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
  2905. if (argc >= 2)
  2906. {
  2907. xscale->trace.image->base_address_set = 1;
  2908. xscale->trace.image->base_address = strtoul(args[1], NULL, 0);
  2909. }
  2910. else
  2911. {
  2912. xscale->trace.image->base_address_set = 0;
  2913. }
  2914. if (image_open(xscale->trace.image, args[0], (argc >= 3) ? args[2] : NULL) != ERROR_OK)
  2915. {
  2916. free(xscale->trace.image);
  2917. xscale->trace.image = NULL;
  2918. return ERROR_OK;
  2919. }
  2920. return ERROR_OK;
  2921. }
  2922. static int xscale_handle_dump_trace_command(struct command_context_s *cmd_ctx,
  2923. char *cmd, char **args, int argc)
  2924. {
  2925. target_t *target = get_current_target(cmd_ctx);
  2926. armv4_5_common_t *armv4_5;
  2927. xscale_common_t *xscale;
  2928. xscale_trace_data_t *trace_data;
  2929. fileio_t file;
  2930. if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK)
  2931. {
  2932. return ERROR_OK;
  2933. }
  2934. if (target->state != TARGET_HALTED)
  2935. {
  2936. command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
  2937. return ERROR_OK;
  2938. }
  2939. if (argc < 1)
  2940. {
  2941. command_print(cmd_ctx, "usage: xscale dump_trace <file>");
  2942. return ERROR_OK;
  2943. }
  2944. trace_data = xscale->trace.data;
  2945. if (!trace_data)
  2946. {
  2947. command_print(cmd_ctx, "no trace data collected");
  2948. return ERROR_OK;
  2949. }
  2950. if (fileio_open(&file, args[0], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
  2951. {
  2952. return ERROR_OK;
  2953. }
  2954. while (trace_data)
  2955. {
  2956. int i;
  2957. fileio_write_u32(&file, trace_data->chkpt0);
  2958. fileio_write_u32(&file, trace_data->chkpt1);
  2959. fileio_write_u32(&file, trace_data->last_instruction);
  2960. fileio_write_u32(&file, trace_data->depth);
  2961. for (i = 0; i < trace_data->depth; i++)
  2962. fileio_write_u32(&file, trace_data->entries[i].data | ((trace_data->entries[i].type & 0xffff) << 16));
  2963. trace_data = trace_data->next;
  2964. }
  2965. fileio_close(&file);
  2966. return ERROR_OK;
  2967. }
  2968. static int
  2969. xscale_handle_analyze_trace_buffer_command(struct command_context_s *cmd_ctx,
  2970. char *cmd, char **args, int argc)
  2971. {
  2972. target_t *target = get_current_target(cmd_ctx);
  2973. armv4_5_common_t *armv4_5;
  2974. xscale_common_t *xscale;
  2975. if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK)
  2976. {
  2977. return ERROR_OK;
  2978. }
  2979. xscale_analyze_trace(target, cmd_ctx);
  2980. return ERROR_OK;
  2981. }
  2982. static int xscale_handle_cp15(command_context_t *cmd_ctx,
  2983. char *cmd, char **args, int argc)
  2984. {
  2985. target_t *target = get_current_target(cmd_ctx);
  2986. armv4_5_common_t *armv4_5;
  2987. xscale_common_t *xscale;
  2988. if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK)
  2989. {
  2990. return ERROR_OK;
  2991. }
  2992. if (target->state != TARGET_HALTED)
  2993. {
  2994. command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
  2995. return ERROR_OK;
  2996. }
  2997. uint32_t reg_no = 0;
  2998. reg_t *reg = NULL;
  2999. if (argc > 0)
  3000. {
  3001. reg_no = strtoul(args[0], NULL, 0);
  3002. /*translate from xscale cp15 register no to openocd register*/
  3003. switch (reg_no)
  3004. {
  3005. case 0:
  3006. reg_no = XSCALE_MAINID;
  3007. break;
  3008. case 1:
  3009. reg_no = XSCALE_CTRL;
  3010. break;
  3011. case 2:
  3012. reg_no = XSCALE_TTB;
  3013. break;
  3014. case 3:
  3015. reg_no = XSCALE_DAC;
  3016. break;
  3017. case 5:
  3018. reg_no = XSCALE_FSR;
  3019. break;
  3020. case 6:
  3021. reg_no = XSCALE_FAR;
  3022. break;
  3023. case 13:
  3024. reg_no = XSCALE_PID;
  3025. break;
  3026. case 15:
  3027. reg_no = XSCALE_CPACCESS;
  3028. break;
  3029. default:
  3030. command_print(cmd_ctx, "invalid register number");
  3031. return ERROR_INVALID_ARGUMENTS;
  3032. }
  3033. reg = &xscale->reg_cache->reg_list[reg_no];
  3034. }
  3035. if (argc == 1)
  3036. {
  3037. uint32_t value;
  3038. /* read cp15 control register */
  3039. xscale_get_reg(reg);
  3040. value = buf_get_u32(reg->value, 0, 32);
  3041. command_print(cmd_ctx, "%s (/%i): 0x%" PRIx32 "", reg->name, (int)(reg->size), value);
  3042. }
  3043. else if (argc == 2)
  3044. {
  3045. uint32_t value = strtoul(args[1], NULL, 0);
  3046. /* send CP write request (command 0x41) */
  3047. xscale_send_u32(target, 0x41);
  3048. /* send CP register number */
  3049. xscale_send_u32(target, reg_no);
  3050. /* send CP register value */
  3051. xscale_send_u32(target, value);
  3052. /* execute cpwait to ensure outstanding operations complete */
  3053. xscale_send_u32(target, 0x53);
  3054. }
  3055. else
  3056. {
  3057. command_print(cmd_ctx, "usage: cp15 [register]<, [value]>");
  3058. }
  3059. return ERROR_OK;
  3060. }
  3061. static int xscale_register_commands(struct command_context_s *cmd_ctx)
  3062. {
  3063. command_t *xscale_cmd;
  3064. xscale_cmd = register_command(cmd_ctx, NULL, "xscale", NULL, COMMAND_ANY, "xscale specific commands");
  3065. register_command(cmd_ctx, xscale_cmd, "debug_handler", xscale_handle_debug_handler_command, COMMAND_ANY, "'xscale debug_handler <target#> <address>' command takes two required operands");
  3066. register_command(cmd_ctx, xscale_cmd, "cache_clean_address", xscale_handle_cache_clean_address_command, COMMAND_ANY, NULL);
  3067. register_command(cmd_ctx, xscale_cmd, "cache_info", xscale_handle_cache_info_command, COMMAND_EXEC, NULL);
  3068. register_command(cmd_ctx, xscale_cmd, "mmu", xscale_handle_mmu_command, COMMAND_EXEC, "['enable'|'disable'] the MMU");
  3069. register_command(cmd_ctx, xscale_cmd, "icache", xscale_handle_idcache_command, COMMAND_EXEC, "['enable'|'disable'] the ICache");
  3070. register_command(cmd_ctx, xscale_cmd, "dcache", xscale_handle_idcache_command, COMMAND_EXEC, "['enable'|'disable'] the DCache");
  3071. register_command(cmd_ctx, xscale_cmd, "vector_catch", xscale_handle_vector_catch_command, COMMAND_EXEC, "<mask> of vectors that should be catched");
  3072. register_command(cmd_ctx, xscale_cmd, "vector_table", xscale_handle_vector_table_command, COMMAND_EXEC, "<high|low> <index> <code> set static code for exception handler entry");
  3073. register_command(cmd_ctx, xscale_cmd, "trace_buffer", xscale_handle_trace_buffer_command, COMMAND_EXEC, "<enable | disable> ['fill' [n]|'wrap']");
  3074. register_command(cmd_ctx, xscale_cmd, "dump_trace", xscale_handle_dump_trace_command, COMMAND_EXEC, "dump content of trace buffer to <file>");
  3075. register_command(cmd_ctx, xscale_cmd, "analyze_trace", xscale_handle_analyze_trace_buffer_command, COMMAND_EXEC, "analyze content of trace buffer");
  3076. register_command(cmd_ctx, xscale_cmd, "trace_image", xscale_handle_trace_image_command,
  3077. COMMAND_EXEC, "load image from <file> [base address]");
  3078. register_command(cmd_ctx, xscale_cmd, "cp15", xscale_handle_cp15, COMMAND_EXEC, "access coproc 15 <register> [value]");
  3079. armv4_5_register_commands(cmd_ctx);
  3080. return ERROR_OK;
  3081. }
  3082. target_type_t xscale_target =
  3083. {
  3084. .name = "xscale",
  3085. .poll = xscale_poll,
  3086. .arch_state = xscale_arch_state,
  3087. .target_request_data = NULL,
  3088. .halt = xscale_halt,
  3089. .resume = xscale_resume,
  3090. .step = xscale_step,
  3091. .assert_reset = xscale_assert_reset,
  3092. .deassert_reset = xscale_deassert_reset,
  3093. .soft_reset_halt = NULL,
  3094. .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
  3095. .read_memory = xscale_read_memory,
  3096. .write_memory = xscale_write_memory,
  3097. .bulk_write_memory = xscale_bulk_write_memory,
  3098. .checksum_memory = arm7_9_checksum_memory,
  3099. .blank_check_memory = arm7_9_blank_check_memory,
  3100. .run_algorithm = armv4_5_run_algorithm,
  3101. .add_breakpoint = xscale_add_breakpoint,
  3102. .remove_breakpoint = xscale_remove_breakpoint,
  3103. .add_watchpoint = xscale_add_watchpoint,
  3104. .remove_watchpoint = xscale_remove_watchpoint,
  3105. .register_commands = xscale_register_commands,
  3106. .target_create = xscale_target_create,
  3107. .init_target = xscale_init_target,
  3108. .quit = xscale_quit,
  3109. .virt2phys = xscale_virt2phys,
  3110. .mmu = xscale_mmu
  3111. };