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95 lines
2.7 KiB

  1. #
  2. # Support for General Plus GP326XXXA chips
  3. #
  4. if { [info exists CHIPNAME] } {
  5. set _CHIPNAME $CHIPNAME
  6. } else {
  7. set _CHIPNAME gp326xxxa
  8. }
  9. if { [info exists ENDIAN] } {
  10. set _ENDIAN $ENDIAN
  11. } else {
  12. set _ENDIAN little
  13. }
  14. if { [info exists CPUTAPID] } {
  15. set _CPUTAPID $CPUTAPID
  16. } else {
  17. set _CPUTAPID 0x4f1f0f0f
  18. }
  19. jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
  20. set _TARGETNAME $_CHIPNAME.cpu
  21. target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
  22. # Use internal SRAM as a work area
  23. $_TARGETNAME configure -work-area-phys 0xf8000000 -work-area-size 0x8000 -work-area-backup 0
  24. # The chip has both lines connected together
  25. reset_config trst_and_srst srst_pulls_trst
  26. # This delay is needed otherwise communication with the target would
  27. # be unreliable
  28. adapter_nsrst_delay 100
  29. # Set the adapter speed ridiculously low just in case we are
  30. # running off of a 32kHz clock
  31. adapter_khz 2
  32. proc gp32xxxa_halt_and_reset_control_registers {} {
  33. # System control registers
  34. set P_SYSTEM_CTRL_NEW 0xD0000008
  35. set P_SYSTEM_CTRL 0xD000000C
  36. set P_SYSTEM_CLK_EN0 0xD0000010
  37. set P_SYSTEM_CLK_EN1 0xD0000014
  38. set P_SYSTEM_RESET_FLAG 0xD0000018
  39. set P_SYSTEM_CLK_CTRL 0xD000001C
  40. set P_SYSTEM_LVR_CTRL 0xD0000020
  41. set P_SYSTEM_WATCHDOG_CTRL 0xD0000024
  42. set P_SYSTEM_PLLEN 0xD000005C
  43. # Since we can't use SRST without pulling TRST
  44. # we can't assume the state of the clock configuration
  45. # or watchdog settings. So reset them before porceeding
  46. # Set the adapter speed ridiculously low just in case we are
  47. # running off of a 32kHz clock
  48. adapter_khz 2
  49. # Disable any advanced features at this stage
  50. arm7_9 dcc_downloads disable
  51. arm7_9 fast_memory_access disable
  52. # Do a "soft reset"
  53. soft_reset_halt
  54. # Reset all system control registers to their default "after-reset" values
  55. mwh $P_SYSTEM_WATCHDOG_CTRL 0x0000
  56. mwh $P_SYSTEM_LVR_CTRL 0x0000
  57. mwh $P_SYSTEM_CTRL_NEW 0x0001
  58. mwh $P_SYSTEM_CTRL 0x0001
  59. # Clear all reset flags by writing 1's
  60. mwh $P_SYSTEM_RESET_FLAG 0x001C
  61. mwh $P_SYSTEM_CLK_CTRL 0x8000
  62. mwh $P_SYSTEM_CLK_EN0 0xFFFF
  63. mwh $P_SYSTEM_CLK_EN1 0xFFFF
  64. mwh $P_SYSTEM_PLLEN 0x0010
  65. # Unfortunately there's no register that would allow us to
  66. # know if PLL is locked. So just wait for 100ms in hopes that
  67. # it would be enough.
  68. sleep 100
  69. # Now that we know that we are running at 48Mhz
  70. # Increase JTAG speed and enable speed optimization features
  71. adapter_khz 5000
  72. arm7_9 dcc_downloads enable
  73. arm7_9 fast_memory_access enable
  74. }
  75. $_TARGETNAME configure -event reset-end { gp32xxxa_halt_and_reset_control_registers }