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  1. # script for stm32f0x family
  2. #
  3. # stm32 devices support SWD transports only.
  4. #
  5. source [find target/swj-dp.tcl]
  6. if { [info exists CHIPNAME] } {
  7. set _CHIPNAME $CHIPNAME
  8. } else {
  9. set _CHIPNAME stm32f0x
  10. }
  11. set _ENDIAN little
  12. # Work-area is a space in RAM used for flash programming
  13. # By default use 4kB
  14. if { [info exists WORKAREASIZE] } {
  15. set _WORKAREASIZE $WORKAREASIZE
  16. } else {
  17. set _WORKAREASIZE 0x1000
  18. }
  19. #jtag scan chain
  20. if { [info exists CPUTAPID] } {
  21. set _CPUTAPID $CPUTAPID
  22. } else {
  23. # See STM Document RM0091
  24. # Section 29.5.3
  25. set _CPUTAPID 0x0bb11477
  26. }
  27. swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
  28. set _TARGETNAME $_CHIPNAME.cpu
  29. target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
  30. $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
  31. # flash size will be probed
  32. set _FLASHNAME $_CHIPNAME.flash
  33. flash bank $_FLASHNAME stm32f1x 0x08000000 0 0 0 $_TARGETNAME
  34. # adapter speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
  35. adapter_khz 1000
  36. adapter_nsrst_delay 100
  37. reset_config srst_nogate
  38. if {![using_hla]} {
  39. # if srst is not fitted use SYSRESETREQ to
  40. # perform a soft reset
  41. cortex_m reset_config sysresetreq
  42. }