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  1. #
  2. # stm32l1 devices support both JTAG and SWD transports.
  3. #
  4. source [find target/swj-dp.tcl]
  5. source [find mem_helper.tcl]
  6. if { [info exists CHIPNAME] } {
  7. set _CHIPNAME $CHIPNAME
  8. } else {
  9. set _CHIPNAME stm32l1
  10. }
  11. set _ENDIAN little
  12. # Work-area is a space in RAM used for flash programming
  13. # By default use 10kB
  14. if { [info exists WORKAREASIZE] } {
  15. set _WORKAREASIZE $WORKAREASIZE
  16. } else {
  17. set _WORKAREASIZE 0x2800
  18. }
  19. # JTAG speed should be <= F_CPU/6.
  20. # F_CPU after reset is 2MHz, so use F_JTAG max = 333kHz
  21. adapter_khz 300
  22. adapter_nsrst_delay 100
  23. if {[using_jtag]} {
  24. jtag_ntrst_delay 100
  25. }
  26. #jtag scan chain
  27. if { [info exists CPUTAPID] } {
  28. set _CPUTAPID $CPUTAPID
  29. } else {
  30. if { [using_jtag] } {
  31. # See STM Document RM0038
  32. # Section 30.6.3 - corresponds to Cortex-M3 r2p0
  33. set _CPUTAPID 0x4ba00477
  34. } else {
  35. # SWD IDCODE (single drop, arm)
  36. set _CPUTAPID 0x2ba01477
  37. }
  38. }
  39. swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
  40. if { [info exists BSTAPID] } {
  41. # FIXME this never gets used to override defaults...
  42. set _BSTAPID $BSTAPID
  43. } else {
  44. # See STM Document RM0038 Section 30.6.1 Rev. 12
  45. # Low and medium density
  46. set _BSTAPID1 0x06416041
  47. # Cat.2 device (medium+ density)
  48. set _BSTAPID2 0x06429041
  49. # Cat.3 device (medium+ density)
  50. set _BSTAPID3 0x06427041
  51. # Cat.4 device, STM32L15/6xxD or Cat.3 device, some STM32L15/6xxC-A models
  52. set _BSTAPID4 0x06436041
  53. # Cat.5 device (high density), STM32L15/6xxE
  54. set _BSTAPID5 0x06437041
  55. }
  56. if {[using_jtag]} {
  57. swj_newdap $_CHIPNAME bs -irlen 5 \
  58. -expected-id $_BSTAPID1 -expected-id $_BSTAPID2 -expected-id $_BSTAPID3 \
  59. -expected-id $_BSTAPID4 -expected-id $_BSTAPID5
  60. }
  61. set _TARGETNAME $_CHIPNAME.cpu
  62. target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
  63. $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
  64. # flash size will be probed
  65. set _FLASHNAME $_CHIPNAME.flash
  66. flash bank $_FLASHNAME stm32lx 0x08000000 0 0 0 $_TARGETNAME
  67. reset_config srst_nogate
  68. if {![using_hla]} {
  69. # if srst is not fitted use SYSRESETREQ to
  70. # perform a soft reset
  71. cortex_m reset_config sysresetreq
  72. }
  73. proc stm32l_enable_HSI {} {
  74. # Enable HSI as clock source
  75. echo "STM32L: Enabling HSI"
  76. # Set HSION in RCC_CR
  77. mww 0x40023800 0x00000101
  78. # Set HSI as SYSCLK
  79. mww 0x40023808 0x00000001
  80. # Increase JTAG speed
  81. adapter_khz 2000
  82. }
  83. $_TARGETNAME configure -event reset-init {
  84. stm32l_enable_HSI
  85. }
  86. $_TARGETNAME configure -event reset-start {
  87. adapter_khz 300
  88. }
  89. $_TARGETNAME configure -event examine-end {
  90. # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
  91. mmw 0xE0042004 0x00000007 0
  92. # Stop watchdog counters during halt
  93. # DBGMCU_APB1_FZ = DBG_IWDG_STOP | DBG_WWDG_STOP
  94. mww 0xE0042008 0x00001800
  95. }
  96. $_TARGETNAME configure -event trace-config {
  97. # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
  98. # change this value accordingly to configure trace pins
  99. # assignment
  100. mmw 0xE0042004 0x00000020 0
  101. }