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  1. \input texinfo @c -*-texinfo-*-
  2. @c %**start of header
  3. @setfilename openocd.info
  4. @settitle Open On-Chip Debugger (openocd)
  5. @dircategory Development
  6. @direntry
  7. * OpenOCD: (openocd). Open On-Chip Debugger.
  8. @end direntry
  9. @c %**end of header
  10. @include version.texi
  11. @copying
  12. Copyright @copyright{} 2007-2008 Spen @email{spen@@spen-soft.co.uk}
  13. @quotation
  14. Permission is granted to copy, distribute and/or modify this document
  15. under the terms of the GNU Free Documentation License, Version 1.2 or
  16. any later version published by the Free Software Foundation; with no
  17. Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
  18. Texts. A copy of the license is included in the section entitled ``GNU
  19. Free Documentation License''.
  20. @end quotation
  21. @end copying
  22. @titlepage
  23. @title Open On-Chip Debugger (openocd)
  24. @subtitle Edition @value{EDITION} for openocd version @value{VERSION}
  25. @subtitle @value{UPDATED}
  26. @page
  27. @vskip 0pt plus 1filll
  28. @insertcopying
  29. @end titlepage
  30. @contents
  31. @node Top, About, , (dir)
  32. @top OpenOCD
  33. This manual documents edition @value{EDITION} of the Open On-Chip Debugger
  34. (openocd) version @value{VERSION}, @value{UPDATED}.
  35. @insertcopying
  36. @menu
  37. * About:: About Openocd.
  38. * Developers:: Openocd developers
  39. * Building:: Building Openocd
  40. * Running:: Running Openocd
  41. * Configuration:: Openocd Configuration.
  42. * Target library:: Target library
  43. * Commands:: Openocd Commands
  44. * Sample Scripts:: Sample Target Scripts
  45. * GDB and Openocd:: Using GDB and Openocd
  46. * Upgrading:: Deprecated/Removed Commands
  47. * FAQ:: Frequently Asked Questions
  48. * License:: GNU Free Documentation License
  49. * Index:: Main index.
  50. @end menu
  51. @node About
  52. @unnumbered About
  53. @cindex about
  54. The Open On-Chip Debugger (openocd) aims to provide debugging, in-system programming
  55. and boundary-scan testing for embedded target devices. The targets are interfaced
  56. using JTAG (IEEE 1149.1) compliant hardware, but this may be extended to other
  57. connection types in the future.
  58. Openocd currently supports Wiggler (clones), FTDI FT2232 based JTAG interfaces, the
  59. Amontec JTAG Accelerator, and the Gateworks GW1602. It allows ARM7 (ARM7TDMI and ARM720t),
  60. ARM9 (ARM920t, ARM922t, ARM926ej--s, ARM966e--s), XScale (PXA25x, IXP42x) and
  61. Cortex-M3 (Luminary Stellaris LM3 and ST STM32) based cores to be debugged.
  62. Flash writing is supported for external CFI compatible flashes (Intel and AMD/Spansion
  63. command set) and several internal flashes (LPC2000, AT91SAM7, STR7x, STR9x, LM3
  64. and STM32x). Preliminary support for using the LPC3180's NAND flash controller is included.
  65. @node Developers
  66. @chapter Developers
  67. @cindex developers
  68. Openocd has been created by Dominic Rath as part of a diploma thesis written at the
  69. University of Applied Sciences Augsburg (@uref{http://www.fh-augsburg.de}).
  70. Others interested in improving the state of free and open debug and testing technology
  71. are welcome to participate.
  72. Other developers have contributed support for additional targets and flashes as well
  73. as numerous bugfixes and enhancements. See the AUTHORS file for regular contributors.
  74. @node Building
  75. @chapter Building
  76. @cindex building openocd
  77. You can download the current SVN version with SVN client of your choice from the
  78. following repositories:
  79. (@uref{svn://svn.berlios.de/openocd/trunk})
  80. or
  81. (@uref{http://svn.berlios.de/svnroot/repos/openocd/trunk})
  82. Using the SVN command line client, you could use the following command to fetch the
  83. latest version (make sure there is no (non-svn) directory called "openocd" in the
  84. current directory):
  85. @smallexample
  86. svn checkout svn://svn.berlios.de/openocd/trunk openocd
  87. @end smallexample
  88. Building the OpenOCD requires a recent version of the GNU autotools.
  89. On my build system, I'm using autoconf 2.13 and automake 1.9. For building on Windows,
  90. you have to use Cygwin. Make sure that your @env{PATH} environment variable contains no
  91. other locations with Unix utils (like UnxUtils) - these can't handle the Cygwin
  92. paths, resulting in obscure dependency errors (This is an observation I've gathered
  93. from the logs of one user - correct me if I'm wrong).
  94. You further need the appropriate driver files, if you want to build support for
  95. a FTDI FT2232 based interface:
  96. @itemize @bullet
  97. @item @b{ftdi2232} libftdi (@uref{http://www.intra2net.com/opensource/ftdi/})
  98. @item @b{ftd2xx} libftd2xx (@uref{http://www.ftdichip.com/Drivers/D2XX.htm})
  99. @item When using the Amontec JTAGkey, you have to get the drivers from the Amontec
  100. homepage (@uref{www.amontec.com}), as the JTAGkey uses a non-standard VID/PID.
  101. @end itemize
  102. Please note that the ftdi2232 variant (using libftdi) isn't supported under Cygwin.
  103. You have to use the ftd2xx variant (using FTDI's D2XX) on Cygwin.
  104. In general, the D2XX driver provides superior performance (several times as fast),
  105. but has the draw-back of being binary-only - though that isn't as worse, as it isn't
  106. a kernel module, only a user space library.
  107. To build OpenOCD (on both Linux and Cygwin), use the following commands:
  108. @smallexample
  109. ./bootstrap
  110. @end smallexample
  111. Bootstrap generates the configure script, and prepares building on your system.
  112. @smallexample
  113. ./configure
  114. @end smallexample
  115. Configure generates the Makefiles used to build OpenOCD.
  116. @smallexample
  117. make
  118. @end smallexample
  119. Make builds the OpenOCD, and places the final executable in ./src/.
  120. The configure script takes several options, specifying which JTAG interfaces
  121. should be included:
  122. @itemize @bullet
  123. @item
  124. @option{--enable-parport}
  125. @item
  126. @option{--enable-parport_ppdev}
  127. @item
  128. @option{--enable-parport_giveio}
  129. @item
  130. @option{--enable-amtjtagaccel}
  131. @item
  132. @option{--enable-ft2232_ftd2xx}
  133. @footnote{Using the latest D2XX drivers from FTDI and following their installation
  134. instructions, I had to use @option{--enable-ft2232_libftd2xx} for the OpenOCD to
  135. build properly.}
  136. @item
  137. @option{--enable-ft2232_libftdi}
  138. @item
  139. @option{--with-ftd2xx=/path/to/d2xx/}
  140. @item
  141. @option{--enable-gw16012}
  142. @item
  143. @option{--enable-usbprog}
  144. @item
  145. @option{--enable-presto_libftdi}
  146. @item
  147. @option{--enable-presto_ftd2xx}
  148. @end itemize
  149. If you want to access the parallel port using the PPDEV interface you have to specify
  150. both the @option{--enable-parport} AND the @option{--enable-parport_ppdev} option since
  151. the @option{--enable-parport_ppdev} option actually is an option to the parport driver
  152. (see @uref{http://forum.sparkfun.com/viewtopic.php?t=3795} for more info).
  153. Cygwin users have to specify the location of the FTDI D2XX package. This should be an
  154. absolute path containing no spaces.
  155. Linux users should copy the various parts of the D2XX package to the appropriate
  156. locations, i.e. /usr/include, /usr/lib.
  157. @node Running
  158. @chapter Running
  159. @cindex running openocd
  160. @cindex --configfile
  161. @cindex --debug_level
  162. @cindex --logfile
  163. @cindex --search
  164. The OpenOCD runs as a daemon, waiting for connections from clients (Telnet or GDB).
  165. Run with @option{--help} or @option{-h} to view the available command line arguments.
  166. It reads its configuration by default from the file openocd.cfg located in the current
  167. working directory. This may be overwritten with the @option{-f <configfile>} command line
  168. switch. @option{-f} can be specified multiple times, in which case the config files
  169. are executed in order.
  170. Also it is possible to interleave commands w/config scripts using the @option{-c}.
  171. To enable debug output (when reporting problems or working on OpenOCD itself), use
  172. the @option{-d} command line switch. This sets the debug_level to "3", outputting
  173. the most information, including debug messages. The default setting is "2", outputting
  174. only informational messages, warnings and errors. You can also change this setting
  175. from within a telnet or gdb session (@option{debug_level <n>}).
  176. You can redirect all output from the daemon to a file using the @option{-l <logfile>} switch.
  177. Search paths for config/script files can be added to openocd by using
  178. the @option{-s <search>} switch. The current directory and the OpenOCD target library
  179. is in the search path by default.
  180. NB! OpenOCD will launch the GDB & telnet server even if it can not establish a connection
  181. with the target. In general, it is possible for the JTAG controller to be unresponsive until
  182. the target is set up correctly via e.g. GDB monitor commands in a GDB init script.
  183. @node Configuration
  184. @chapter Configuration
  185. @cindex configuration
  186. The Open On-Chip Debugger (OpenOCD) runs as a daemon, and reads it current configuration
  187. by default from the file openocd.cfg in the current directory. A different configuration
  188. file can be specified with the @option{-f <conf.file>} given at the openocd command line.
  189. The configuration file is used to specify on which ports the daemon listens for new
  190. connections, the JTAG interface used to connect to the target, the layout of the JTAG
  191. chain, the targets that should be debugged, and connected flashes.
  192. @section Daemon configuration
  193. @itemize @bullet
  194. @item @b{init} This command terminates the configuration stage and enters the normal
  195. command mode. This can be useful to add commands to the startup scripts and commands
  196. such as resetting the target, programming flash, etc. To reset the CPU upon startup,
  197. add "init" and "reset" at the end of the config script or at the end of the
  198. openocd command line using the -c option.
  199. @cindex init
  200. @item @b{telnet_port} <@var{number}>
  201. @cindex telnet_port
  202. Port on which to listen for incoming telnet connections
  203. @item @b{gdb_port} <@var{number}>
  204. @cindex gdb_port
  205. First port on which to listen for incoming GDB connections. The GDB port for the
  206. first target will be gdb_port, the second target will listen on gdb_port + 1, and so on.
  207. @item @b{gdb_detach} <@var{resume|reset|halt|nothing}>
  208. @cindex gdb_detach
  209. Configures what openocd will do when gdb detaches from the daeman.
  210. Default behaviour is <@var{resume}>
  211. @item @b{gdb_memory_map} <@var{enable|disable}>
  212. @cindex gdb_memory_map
  213. Set to <@var{enable}> so that openocd will send the memory configuration to gdb when
  214. requested. gdb will then know when to set hardware breakpoints, and program flash
  215. using the gdb load command. @option{gdb_flash_program enable} will also need enabling
  216. for flash programming to work.
  217. Default behaviour is <@var{disable}>
  218. @item @b{gdb_flash_program} <@var{enable|disable}>
  219. @cindex gdb_flash_program
  220. Set to <@var{enable}> so that openocd will program the flash memory when a
  221. vFlash packet is received.
  222. Default behaviour is <@var{disable}>
  223. @item @b{daemon_startup} <@var{mode}>
  224. @cindex daemon_startup
  225. @option{mode} can either @option{attach} or @option{reset}
  226. This is equivalent to adding "init" and "reset" to the end of the config script.
  227. It is availble as a command mainly for backwards compatibility.
  228. @end itemize
  229. @section JTAG interface configuration
  230. @itemize @bullet
  231. @item @b{interface} <@var{name}>
  232. @cindex interface
  233. Use the interface driver <@var{name}> to connect to the target. Currently supported
  234. interfaces are
  235. @itemize @minus
  236. @item @b{parport}
  237. PC parallel port bit-banging (Wigglers, PLD download cable, ...)
  238. @end itemize
  239. @itemize @minus
  240. @item @b{amt_jtagaccel}
  241. Amontec Chameleon in its JTAG Accelerator configuration connected to a PC's EPP
  242. mode parallel port
  243. @end itemize
  244. @itemize @minus
  245. @item @b{ft2232}
  246. FTDI FT2232 based devices using either the open-source libftdi or the binary only
  247. FTD2XX driver. The FTD2XX is superior in performance, but not available on every
  248. platform. The libftdi uses libusb, and should be portable to all systems that provide
  249. libusb.
  250. @end itemize
  251. @itemize @minus
  252. @item @b{ep93xx}
  253. Cirrus Logic EP93xx based single-board computer bit-banging (in development)
  254. @end itemize
  255. @itemize @minus
  256. @item @b{presto}
  257. ASIX PRESTO USB JTAG programmer.
  258. @end itemize
  259. @itemize @minus
  260. @item @b{usbprog}
  261. usbprog is a freely programmable USB adapter.
  262. @end itemize
  263. @itemize @minus
  264. @item @b{gw16012}
  265. Gateworks GW16012 JTAG programmer.
  266. @end itemize
  267. @end itemize
  268. @itemize @bullet
  269. @item @b{jtag_speed} <@var{reset speed}> <@var{post reset speed}>
  270. @cindex jtag_speed
  271. Limit the maximum speed of the JTAG interface. Usually, a value of zero means maximum
  272. speed. The actual effect of this option depends on the JTAG interface used. Reset
  273. speed is used during reset and post reset speed after reset. post reset speed
  274. is optional, in which case the reset speed is used.
  275. @itemize @minus
  276. @item wiggler: maximum speed / @var{number}
  277. @item ft2232: 6MHz / (@var{number}+1)
  278. @item amt jtagaccel: 8 / 2**@var{number}
  279. @end itemize
  280. Note: Make sure the jtag clock is no more than @math{1/6th × CPU-Clock}. This is
  281. especially true for synthesized cores (-S).
  282. @item @b{jtag_khz} <@var{reset speed kHz}> <@var{post reset speed kHz}>
  283. @cindex jtag_khz
  284. Same as jtag_speed, except that the speed is specified in maximum kHz. If
  285. the device can not support the rate asked for, or can not translate from
  286. kHz to jtag_speed, then an error is returned. 0 means RTCK. If RTCK
  287. is not supported, then an error is reported.
  288. @item @b{reset_config} <@var{signals}> [@var{combination}] [@var{trst_type}] [@var{srst_type}]
  289. @cindex reset_config
  290. The configuration of the reset signals available on the JTAG interface AND the target.
  291. If the JTAG interface provides SRST, but the target doesn't connect that signal properly,
  292. then OpenOCD can't use it. <@var{signals}> can be @option{none}, @option{trst_only},
  293. @option{srst_only} or @option{trst_and_srst}.
  294. [@var{combination}] is an optional value specifying broken reset signal implementations.
  295. @option{srst_pulls_trst} states that the testlogic is reset together with the reset of
  296. the system (e.g. Philips LPC2000, "broken" board layout), @option{trst_pulls_srst} says
  297. that the system is reset together with the test logic (only hypothetical, I haven't
  298. seen hardware with such a bug, and can be worked around).
  299. @option{combined} imples both @option{srst_pulls_trst} and @option{trst_pulls_srst}.
  300. The default behaviour if no option given is @option{separate}.
  301. The [@var{trst_type}] and [@var{srst_type}] parameters allow the driver type of the
  302. reset lines to be specified. Possible values are @option{trst_push_pull} (default)
  303. and @option{trst_open_drain} for the test reset signal, and @option{srst_open_drain}
  304. (default) and @option{srst_push_pull} for the system reset. These values only affect
  305. JTAG interfaces with support for different drivers, like the Amontec JTAGkey and JTAGAccelerator.
  306. @item @b{jtag_device} <@var{IR length}> <@var{IR capture}> <@var{IR mask}> <@var{IDCODE instruction}>
  307. @cindex jtag_device
  308. Describes the devices that form the JTAG daisy chain, with the first device being
  309. the one closest to TDO. The parameters are the length of the instruction register
  310. (4 for all ARM7/9s), the value captured during Capture-IR (0x1 for ARM7/9), and a mask
  311. of bits that should be validated when doing IR scans (all four bits (0xf) for ARM7/9).
  312. The IDCODE instruction will in future be used to query devices for their JTAG
  313. identification code. This line is the same for all ARM7 and ARM9 devices.
  314. Other devices, like CPLDs, require different parameters. An example configuration
  315. line for a Xilinx XC9500 CPLD would look like this:
  316. @smallexample
  317. jtag_device 8 0x01 0x0e3 0xfe
  318. @end smallexample
  319. The instruction register (IR) is 8 bits long, during Capture-IR 0x01 is loaded into
  320. the IR, but only bits 0-1 and 5-7 should be checked, the others (2-4) might vary.
  321. The IDCODE instruction is 0xfe.
  322. @item @b{jtag_nsrst_delay} <@var{ms}>
  323. @cindex jtag_nsrst_delay
  324. How long (in miliseconds) the OpenOCD should wait after deasserting nSRST before
  325. starting new JTAG operations.
  326. @item @b{jtag_ntrst_delay} <@var{ms}>
  327. @cindex jtag_ntrst_delay
  328. How long (in miliseconds) the OpenOCD should wait after deasserting nTRST before
  329. starting new JTAG operations.
  330. The jtag_n[st]rst_delay options are useful if reset circuitry (like a reset supervisor,
  331. or on-chip features) keep a reset line asserted for some time after the external reset
  332. got deasserted.
  333. @end itemize
  334. @section parport options
  335. @itemize @bullet
  336. @item @b{parport_port} <@var{number}>
  337. @cindex parport_port
  338. Either the address of the I/O port (default: 0x378 for LPT1) or the number of
  339. the @file{/dev/parport} device
  340. When using PPDEV to access the parallel port, use the number of the parallel port:
  341. @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
  342. you may encounter a problem.
  343. @item @b{parport_cable} <@var{name}>
  344. @cindex parport_cable
  345. The layout of the parallel port cable used to connect to the target.
  346. Currently supported cables are
  347. @itemize @minus
  348. @item @b{wiggler}
  349. @cindex wiggler
  350. Original Wiggler layout, also supported by several clones, such
  351. as the Olimex ARM-JTAG
  352. @item @b{old_amt_wiggler}
  353. @cindex old_amt_wiggler
  354. The Wiggler configuration that comes with Amontec's Chameleon Programmer. The new
  355. version available from the website uses the original Wiggler layout ('@var{wiggler}')
  356. @item @b{chameleon}
  357. @cindex chameleon
  358. Describes the connection of the Amontec Chameleon's CPLD when operated in
  359. configuration mode. This is only used to program the Chameleon itself, not
  360. a connected target.
  361. @item @b{dlc5}
  362. @cindex dlc5
  363. Xilinx Parallel cable III.
  364. @item @b{triton}
  365. @cindex triton
  366. The parallel port adapter found on the 'Karo Triton 1 Development Board'.
  367. This is also the layout used by the HollyGates design
  368. (see @uref{http://www.lartmaker.nl/projects/jtag/}).
  369. @item @b{flashlink}
  370. @cindex flashlink
  371. ST Parallel cable.
  372. @end itemize
  373. @item @b{parport_write_on_exit} <@var{on|off}>
  374. @cindex parport_write_on_exit
  375. This will configure the parallel driver to write a known value to the parallel
  376. interface on exiting openocd
  377. @end itemize
  378. @section amt_jtagaccel options
  379. @itemize @bullet
  380. @item @b{parport_port} <@var{number}>
  381. @cindex parport_port
  382. Either the address of the I/O port (default: 0x378 for LPT1) or the number of the
  383. @file{/dev/parport} device
  384. @end itemize
  385. @section ft2232 options
  386. @itemize @bullet
  387. @item @b{ft2232_device_desc} <@var{description}>
  388. @cindex ft2232_device_desc
  389. The USB device description of the FTDI FT2232 device. If not specified, the FTDI
  390. default value is used. This setting is only valid if compiled with FTD2XX support.
  391. @item @b{ft2232_layout} <@var{name}>
  392. @cindex ft2232_layout
  393. The layout of the FT2232 GPIO signals used to control output-enables and reset
  394. signals. Valid layouts are
  395. @itemize @minus
  396. @item @b{usbjtag}
  397. The "USBJTAG-1" layout described in the original OpenOCD diploma thesis
  398. @item @b{jtagkey}
  399. Amontec JTAGkey and JTAGkey-tiny
  400. @item @b{signalyzer}
  401. Signalyzer
  402. @item @b{olimex-jtag}
  403. Olimex ARM-USB-OCD
  404. @item @b{m5960}
  405. American Microsystems M5960
  406. @item @b{evb_lm3s811}
  407. Luminary Micro EVB_LM3S811 as a JTAG interface (not onboard processor), no TRST or
  408. SRST signals on external connector
  409. @item @b{comstick}
  410. Hitex STR9 comstick
  411. @item @b{stm32stick}
  412. Hitex STM32 Performance Stick
  413. @item @b{flyswatter}
  414. Tin Can Tools Flyswatter
  415. @item @b{turtelizer2}
  416. egnite Software turtelizer2
  417. @item @b{oocdlink}
  418. OOCDLink
  419. @end itemize
  420. @item @b{ft2232_vid_pid} <@var{vid}> <@var{pid}>
  421. The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
  422. default values are used. This command is not available on Windows.
  423. @item @b{ft2232_latency} <@var{ms}>
  424. On some systems using ft2232 based JTAG interfaces the FT_Read function call in
  425. ft2232_read() fails to return the expected number of bytes. This can be caused by
  426. USB communication delays and has proved hard to reproduce and debug. Setting the
  427. FT2232 latency timer to a larger value increases delays for short USB packages but it
  428. also reduces the risk of timeouts before receiving the expected number of bytes.
  429. The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
  430. @end itemize
  431. @section ep93xx options
  432. @cindex ep93xx options
  433. Currently, there are no options available for the ep93xx interface.
  434. @page
  435. @section Target configuration
  436. @itemize @bullet
  437. @item @b{target} <@var{type}> <@var{endianess}> <@var{reset_mode}> <@var{JTAG pos}>
  438. <@var{variant}>
  439. @cindex target
  440. Defines a target that should be debugged. Currently supported types are:
  441. @itemize @minus
  442. @item @b{arm7tdmi}
  443. @item @b{arm720t}
  444. @item @b{arm9tdmi}
  445. @item @b{arm920t}
  446. @item @b{arm922t}
  447. @item @b{arm926ejs}
  448. @item @b{arm966e}
  449. @item @b{cortex_m3}
  450. @item @b{feroceon}
  451. @item @b{xscale}
  452. @end itemize
  453. If you want to use a target board that is not on this list, see Adding a new
  454. target board
  455. Endianess may be @option{little} or @option{big}.
  456. The reset_mode specifies what should happen to the target when a reset occurs:
  457. @itemize @minus
  458. @item @b{reset_halt}
  459. @cindex reset_halt
  460. Immediately request a target halt after reset. This allows targets to be debugged
  461. from the very first instruction. This is only possible with targets and JTAG
  462. interfaces that correctly implement the reset signals.
  463. @item @b{reset_init}
  464. @cindex reset_init
  465. Similar to @option{reset_halt}, but executes the script file defined to handle the
  466. 'reset' event for the target. Like @option{reset_halt} this only works with
  467. correct reset implementations.
  468. @item @b{reset_run}
  469. @cindex reset_run
  470. Simply let the target run after a reset.
  471. @item @b{run_and_halt}
  472. @cindex run_and_halt
  473. Let the target run for some time (default: 1s), and then request halt.
  474. @item @b{run_and_init}
  475. @cindex run_and_init
  476. A combination of @option{reset_init} and @option{run_and_halt}. The target is allowed
  477. to run for some time, then halted, and the @option{reset} event script is executed.
  478. @end itemize
  479. On JTAG interfaces / targets where system reset and test-logic reset can't be driven
  480. completely independent (like the LPC2000 series), or where the JTAG interface is
  481. unavailable for some time during startup (like the STR7 series), you can't use
  482. @option{reset_halt} or @option{reset_init}.
  483. @item @b{target_script} <@var{target#}> <@var{event}> <@var{script_file}>
  484. @cindex target_script
  485. Event is either @option{reset}, @option{post_halt}, @option{pre_resume} or @option{gdb_program_config}
  486. TODO: describe exact semantic of events
  487. @item @b{run_and_halt_time} <@var{target#}> <@var{time_in_ms}>
  488. @cindex run_and_halt_time
  489. The amount of time the debugger should wait after releasing reset before it asserts
  490. a debug request. This is used by the @option{run_and_halt} and @option{run_and_init}
  491. reset modes.
  492. @item @b{working_area} <@var{target#}> <@var{address}> <@var{size}>
  493. <@var{backup}|@var{nobackup}>
  494. @cindex working_area
  495. Specifies a working area for the debugger to use. This may be used to speed-up
  496. downloads to target memory and flash operations, or to perform otherwise unavailable
  497. operations (some coprocessor operations on ARM7/9 systems, for example). The last
  498. parameter decides whether the memory should be preserved <@var{backup}>. If possible, use
  499. a working_area that doesn't need to be backed up, as that slows down operation.
  500. @end itemize
  501. @subsection arm7tdmi options
  502. @cindex arm7tdmi options
  503. target arm7tdmi <@var{endianess}> <@var{reset_mode}> <@var{jtag#}>
  504. The arm7tdmi target definition requires at least one additional argument, specifying
  505. the position of the target in the JTAG daisy-chain. The first JTAG device is number 0.
  506. The optional [@var{variant}] parameter has been removed in recent versions.
  507. The correct feature set is determined at runtime.
  508. @subsection arm720t options
  509. @cindex arm720t options
  510. ARM720t options are similar to ARM7TDMI options.
  511. @subsection arm9tdmi options
  512. @cindex arm9tdmi options
  513. ARM9TDMI options are similar to ARM7TDMI options. Supported variants are
  514. @option{arm920t}, @option{arm922t} and @option{arm940t}.
  515. This enables the hardware single-stepping support found on these cores.
  516. @subsection arm920t options
  517. @cindex arm920t options
  518. ARM920t options are similar to ARM9TDMI options.
  519. @subsection arm966e options
  520. @cindex arm966e options
  521. ARM966e options are similar to ARM9TDMI options.
  522. @subsection xscale options
  523. @cindex xscale options
  524. Supported variants are @option{ixp42x}, @option{ixp45x}, @option{ixp46x},
  525. @option{pxa250}, @option{pxa255}, @option{pxa26x}.
  526. @section Flash configuration
  527. @cindex Flash configuration
  528. @itemize @bullet
  529. @item @b{flash bank} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}>
  530. <@var{bus_width}> <@var{target#}> [@var{driver_options ...}]
  531. @cindex flash bank
  532. Configures a flash bank at <@var{base}> of <@var{size}> bytes and <@var{chip_width}>
  533. and <@var{bus_width}> bytes using the selected flash <driver>.
  534. @end itemize
  535. @subsection lpc2000 options
  536. @cindex lpc2000 options
  537. @b{flash bank lpc2000} <@var{base}> <@var{size}> 0 0 <@var{target#}> <@var{variant}>
  538. <@var{clock}> [@var{calc_checksum}]
  539. LPC flashes don't require the chip and bus width to be specified. Additional
  540. parameters are the <@var{variant}>, which may be @var{lpc2000_v1} (older LPC21xx and LPC22xx)
  541. or @var{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx), the number
  542. of the target this flash belongs to (first is 0), the frequency at which the core
  543. is currently running (in kHz - must be an integral number), and the optional keyword
  544. @var{calc_checksum}, telling the driver to calculate a valid checksum for the exception
  545. vector table.
  546. @subsection cfi options
  547. @cindex cfi options
  548. @b{flash bank cfi} <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}>
  549. <@var{target#}>
  550. CFI flashes require the number of the target they're connected to as an additional
  551. argument. The CFI driver makes use of a working area (specified for the target)
  552. to significantly speed up operation.
  553. @var{chip_width} and @var{bus_width} are specified in bytes.
  554. @subsection at91sam7 options
  555. @cindex at91sam7 options
  556. @b{flash bank at91sam7} 0 0 0 0 <@var{target#}>
  557. AT91SAM7 flashes only require the @var{target#}, all other values are looked up after
  558. reading the chip-id and type.
  559. @subsection str7 options
  560. @cindex str7 options
  561. @b{flash bank str7x} <@var{base}> <@var{size}> 0 0 <@var{target#}> <@var{variant}>
  562. variant can be either STR71x, STR73x or STR75x.
  563. @subsection str9 options
  564. @cindex str9 options
  565. @b{flash bank str9x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
  566. The str9 needs the flash controller to be configured prior to Flash programming, eg.
  567. @smallexample
  568. str9x flash_config 0 4 2 0 0x80000
  569. @end smallexample
  570. This will setup the BBSR, NBBSR, BBADR and NBBADR registers respectively.
  571. @subsection str9 options (str9xpec driver)
  572. @b{flash bank str9xpec} <@var{base}> <@var{size}> 0 0 <@var{target#}>
  573. Before using the flash commands the turbo mode will need enabling using str9xpec
  574. @option{enable_turbo} <@var{num>.}
  575. Only use this driver for locking/unlocking the device or configuring the option bytes.
  576. Use the standard str9 driver for programming.
  577. @subsection stellaris (LM3Sxxx) options
  578. @cindex stellaris (LM3Sxxx) options
  579. @b{flash bank stellaris} <@var{base}> <@var{size}> 0 0 <@var{target#}>
  580. stellaris flash plugin only require the @var{target#}.
  581. @subsection stm32x options
  582. @cindex stm32x options
  583. @b{flash bank stm32x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
  584. stm32x flash plugin only require the @var{target#}.
  585. @node Target library
  586. @chapter Target library
  587. @cindex Target library
  588. OpenOCD comes with a target configuration script library. These scripts can be
  589. used as-is or serve as a starting point.
  590. The target library is published together with the openocd executable and
  591. the path to the target library is in the OpenOCD script search path.
  592. Similarly there are example scripts for configuring the JTAG interface.
  593. The command line below uses the example parport configuration scripts
  594. that ships with OpenOCD, then configures the str710.cfg target and
  595. finally issues the init and reset command. The communication speed
  596. is set to 10kHz for reset and 8MHz for post reset.
  597. @smallexample
  598. openocd -f interface/parport.cfg -c "jtag_khz 10 8000" -f target/str710.cfg -c "init" -c "reset"
  599. @end smallexample
  600. To list the target scripts available:
  601. @smallexample
  602. $ ls /usr/local/lib/openocd/target
  603. arm7_fast.cfg lm3s6965.cfg pxa255.cfg stm32.cfg xba_revA3.cfg
  604. at91eb40a.cfg lpc2148.cfg pxa255_sst.cfg str710.cfg zy1000.cfg
  605. at91r40008.cfg lpc2294.cfg sam7s256.cfg str912.cfg
  606. at91sam9260.cfg nslu2.cfg sam7x256.cfg wi-9c.cfg
  607. @end smallexample
  608. @node Commands
  609. @chapter Commands
  610. @cindex commands
  611. The Open On-Chip Debugger (OpenOCD) allows user interaction through a telnet interface
  612. (default: port 4444) and a GDB server (default: port 3333). The command line interpreter
  613. is available from both the telnet interface and a GDB session. To issue commands to the
  614. interpreter from within a GDB session, use the @option{monitor} command, e.g. use
  615. @option{monitor poll} to issue the @option{poll} command. All output is relayed through the
  616. GDB session.
  617. @section Daemon
  618. @itemize @bullet
  619. @item @b{sleep} <@var{msec}>
  620. @cindex sleep
  621. Wait for n milliseconds before resuming. Useful in connection with script files
  622. (@var{script} command and @var{target_script} configuration).
  623. @item @b{shutdown}
  624. @cindex shutdown
  625. Close the OpenOCD daemon, disconnecting all clients (GDB, Telnet).
  626. @item @b{debug_level} [@var{n}]
  627. @cindex debug_level
  628. Display or adjust debug level to n<0-3>
  629. @item @b{fast} [@var{enable/disable}]
  630. @cindex fast
  631. Default disabled. Set default behaviour of OpenOCD to be "fast and dangerous". For instance ARM7/9 DCC memory
  632. downloads and fast memory access will work if the JTAG interface isn't too fast and
  633. the core doesn't run at a too low frequency. Note that this option only changes the default
  634. and that the indvidual options, like DCC memory downloads, can be enabled and disabled
  635. individually.
  636. The target specific "dangerous" optimisation tweaking options may come and go
  637. as more robust and user friendly ways are found to ensure maximum throughput
  638. and robustness with a minimum of configuration.
  639. Typically the "fast enable" is specified first on the command line:
  640. openocd -c "fast enable" -c "interface dummy" -f target/str710.cfg
  641. @item @b{log_output} <@var{file}>
  642. @cindex log_output
  643. Redirect logging to <file> (default: stderr)
  644. @item @b{script} <@var{file}>
  645. @cindex script
  646. Execute commands from <file>
  647. @end itemize
  648. @subsection Target state handling
  649. @itemize @bullet
  650. @item @b{poll} [@option{on}|@option{off}]
  651. @cindex poll
  652. Poll the target for its current state. If the target is in debug mode, architecture
  653. specific information about the current state are printed. An optional parameter
  654. allows continuous polling to be enabled and disabled.
  655. @item @b{halt} [@option{ms}]
  656. @cindex halt
  657. Send a halt request to the target and waits for it to halt for [@option{ms}].
  658. Default [@option{ms}] is 5 seconds if no arg given.
  659. Optional arg @option{ms} is a timeout in milliseconds. Using 0 as the [@option{ms}]
  660. will stop openocd from waiting.
  661. @item @b{wait_halt} [@option{ms}]
  662. @cindex wait_halt
  663. Wait for the target to enter debug mode. Optional [@option{ms}] is
  664. a timeout in milliseconds. Default [@option{ms}] is 5 seconds if no
  665. arg given.
  666. @item @b{resume} [@var{address}]
  667. @cindex resume
  668. Resume the target at its current code position, or at an optional address.
  669. Openocd will wait 5 seconds for the target to resume.
  670. @item @b{step} [@var{address}]
  671. @cindex step
  672. Single-step the target at its current code position, or at an optional address.
  673. @item @b{reset} [@option{run}|@option{halt}|@option{init}|@option{run_and_halt}
  674. |@option{run_and_init}]
  675. @cindex reset
  676. Do a hard-reset. The optional parameter specifies what should happen after the reset.
  677. This optional parameter overwrites the setting specified in the configuration file,
  678. making the new behaviour the default for the @option{reset} command.
  679. @itemize @minus
  680. @item @b{run}
  681. @cindex reset run
  682. Let the target run.
  683. @item @b{halt}
  684. @cindex reset halt
  685. Immediately halt the target (works only with certain configurations).
  686. @item @b{init}
  687. @cindex reset init
  688. Immediately halt the target, and execute the reset script (works only with certain
  689. configurations)
  690. @item @b{run_and_halt}
  691. @cindex reset run_and_halt
  692. Let the target run for a certain amount of time, then request a halt.
  693. @item @b{run_and_init}
  694. @cindex reset run_and_init
  695. Let the target run for a certain amount of time, then request a halt. Execute the
  696. reset script once the target entered debug mode.
  697. @end itemize
  698. @end itemize
  699. @subsection Memory access commands
  700. These commands allow accesses of a specific size to the memory system:
  701. @itemize @bullet
  702. @item @b{mdw} <@var{addr}> [@var{count}]
  703. @cindex mdw
  704. display memory words
  705. @item @b{mdh} <@var{addr}> [@var{count}]
  706. @cindex mdh
  707. display memory half-words
  708. @item @b{mdb} <@var{addr}> [@var{count}]
  709. @cindex mdb
  710. display memory bytes
  711. @item @b{mww} <@var{addr}> <@var{value}>
  712. @cindex mww
  713. write memory word
  714. @item @b{mwh} <@var{addr}> <@var{value}>
  715. @cindex mwh
  716. write memory half-word
  717. @item @b{mwb} <@var{addr}> <@var{value}>
  718. @cindex mwb
  719. write memory byte
  720. @item @b{load_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
  721. @cindex load_image
  722. Load image <@var{file}> to target memory at <@var{address}>
  723. @item @b{dump_image} <@var{file}> <@var{address}> <@var{size}>
  724. @cindex dump_image
  725. Dump <@var{size}> bytes of target memory starting at <@var{address}> to a
  726. (binary) <@var{file}>.
  727. @item @b{verify_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
  728. @cindex verify_image
  729. Verify <@var{file}> to target memory starting at <@var{address}>.
  730. This will first attempt using a crc checksum, if this fails it will try a binary compare.
  731. @end itemize
  732. @subsection Flash commands
  733. @cindex Flash commands
  734. @itemize @bullet
  735. @item @b{flash banks}
  736. @cindex flash banks
  737. List configured flash banks
  738. @item @b{flash info} <@var{num}>
  739. @cindex flash info
  740. Print info about flash bank <@option{num}>
  741. @item @b{flash probe} <@var{num}>
  742. @cindex flash probe
  743. Identify the flash, or validate the parameters of the configured flash. Operation
  744. depends on the flash type.
  745. @item @b{flash erase_check} <@var{num}>
  746. @cindex flash erase_check
  747. Check erase state of sectors in flash bank <@var{num}>. This is the only operation that
  748. updates the erase state information displayed by @option{flash info}. That means you have
  749. to issue an @option{erase_check} command after erasing or programming the device to get
  750. updated information.
  751. @item @b{flash protect_check} <@var{num}>
  752. @cindex flash protect_check
  753. Check protection state of sectors in flash bank <num>.
  754. @option{flash erase_sector} using the same syntax.
  755. @item @b{flash erase_sector} <@var{num}> <@var{first}> <@var{last}>
  756. @cindex flash erase_sector
  757. Erase sectors at bank <@var{num}>, starting at sector <@var{first}> up to and including
  758. <@var{last}>. Sector numbering starts at 0. Depending on the flash type, erasing might
  759. require the protection to be disabled first (e.g. Intel Advanced Bootblock flash using
  760. the CFI driver).
  761. @item @b{flash erase_address} <@var{address}> <@var{length}>
  762. @cindex flash erase_address
  763. Erase sectors starting at <@var{address}> for <@var{length}> number of bytes
  764. @item @b{flash write_bank} <@var{num}> <@var{file}> <@var{offset}>
  765. @cindex flash write_bank
  766. Write the binary <@var{file}> to flash bank <@var{num}>, starting at
  767. <@option{offset}> bytes from the beginning of the bank.
  768. @item @b{flash write_image} [@var{erase}] <@var{file}> [@var{offset}] [@var{type}]
  769. @cindex flash write_image
  770. Write the image <@var{file}> to the current target's flash bank(s). A relocation
  771. [@var{offset}] can be specified and the file [@var{type}] can be specified
  772. explicitly as @option{bin} (binary), @option{ihex} (Intel hex), @option{elf}
  773. (ELF file) or @option{s19} (Motorola s19). Flash memory will be erased prior to programming
  774. if the @option{erase} parameter is given.
  775. @item @b{flash protect} <@var{num}> <@var{first}> <@var{last}> <@option{on}|@option{off}>
  776. @cindex flash protect
  777. Enable (@var{on}) or disable (@var{off}) protection of flash sectors <@var{first}> to
  778. <@var{last}> of @option{flash bank} <@var{num}>.
  779. @end itemize
  780. @page
  781. @section Target Specific Commands
  782. @cindex Target Specific Commands
  783. @subsection AT91SAM7 specific commands
  784. @cindex AT91SAM7 specific commands
  785. The flash configuration is deduced from the chip identification register. The flash
  786. controller handles erases automatically on a page (128/265 byte) basis so erase is
  787. not necessary for flash programming. AT91SAM7 processors with less than 512K flash
  788. only have a single flash bank embedded on chip. AT91SAM7xx512 have two flash planes
  789. that can be erased separatly.Only an EraseAll command is supported by the controller
  790. for each flash plane and this is called with
  791. @itemize @bullet
  792. @item @b{flash erase} <@var{num}> @var{first_plane} @var{last_plane}
  793. bulk erase flash planes first_plane to last_plane.
  794. @item @b{at91sam7 gpnvm} <@var{num}> <@var{bit}> <@option{set}|@option{clear}>
  795. @cindex at91sam7 gpnvm
  796. set or clear a gpnvm bit for the processor
  797. @end itemize
  798. @subsection STR9 specific commands
  799. @cindex STR9 specific commands
  800. These are flash specific commands when using the str9xpec driver.
  801. @itemize @bullet
  802. @item @b{str9xpec enable_turbo} <@var{num}>
  803. @cindex str9xpec enable_turbo
  804. enable turbo mode, simply this will remove the str9 from the chain and talk
  805. directly to the embedded flash controller.
  806. @item @b{str9xpec disable_turbo} <@var{num}>
  807. @cindex str9xpec disable_turbo
  808. restore the str9 into jtag chain.
  809. @item @b{str9xpec lock} <@var{num}>
  810. @cindex str9xpec lock
  811. lock str9 device. The str9 will only respond to an unlock command that will
  812. erase the device.
  813. @item @b{str9xpec unlock} <@var{num}>
  814. @cindex str9xpec unlock
  815. unlock str9 device.
  816. @item @b{str9xpec options_read} <@var{num}>
  817. @cindex str9xpec options_read
  818. read str9 option bytes.
  819. @item @b{str9xpec options_write} <@var{num}>
  820. @cindex str9xpec options_write
  821. write str9 option bytes.
  822. @end itemize
  823. @subsection STR9 configuration
  824. @cindex STR9 configuration
  825. @itemize @bullet
  826. @item @b{str9x flash_config} <@var{bank}> <@var{BBSR}> <@var{NBBSR}>
  827. <@var{BBADR}> <@var{NBBADR}>
  828. @cindex str9x flash_config
  829. Configure str9 flash controller.
  830. @smallexample
  831. eg. str9x flash_config 0 4 2 0 0x80000
  832. This will setup
  833. BBSR - Boot Bank Size register
  834. NBBSR - Non Boot Bank Size register
  835. BBADR - Boot Bank Start Address register
  836. NBBADR - Boot Bank Start Address register
  837. @end smallexample
  838. @end itemize
  839. @subsection STR9 option byte configuration
  840. @cindex STR9 option byte configuration
  841. @itemize @bullet
  842. @item @b{str9xpec options_cmap} <@var{num}> <@option{bank0}|@option{bank1}>
  843. @cindex str9xpec options_cmap
  844. configure str9 boot bank.
  845. @item @b{str9xpec options_lvdthd} <@var{num}> <@option{2.4v}|@option{2.7v}>
  846. @cindex str9xpec options_lvdthd
  847. configure str9 lvd threshold.
  848. @item @b{str9xpec options_lvdsel} <@var{num}> <@option{vdd}|@option{vdd_vddq}>
  849. @cindex str9xpec options_lvdsel
  850. configure str9 lvd source.
  851. @item @b{str9xpec options_lvdwarn} <@var{bank}> <@option{vdd}|@option{vdd_vddq}>
  852. @cindex str9xpec options_lvdwarn
  853. configure str9 lvd reset warning source.
  854. @end itemize
  855. @subsection STM32x specific commands
  856. @cindex STM32x specific commands
  857. These are flash specific commands when using the stm32x driver.
  858. @itemize @bullet
  859. @item @b{stm32x lock} <@var{num}>
  860. @cindex stm32x lock
  861. lock stm32 device.
  862. @item @b{stm32x unlock} <@var{num}>
  863. @cindex stm32x unlock
  864. unlock stm32 device.
  865. @item @b{stm32x options_read} <@var{num}>
  866. @cindex stm32x options_read
  867. read stm32 option bytes.
  868. @item @b{stm32x options_write} <@var{num}> <@option{SWWDG}|@option{HWWDG}>
  869. <@option{RSTSTNDBY}|@option{NORSTSTNDBY}> <@option{RSTSTOP}|@option{NORSTSTOP}>
  870. @cindex stm32x options_write
  871. write stm32 option bytes.
  872. @item @b{stm32x mass_erase} <@var{num}>
  873. @cindex stm32x mass_erase
  874. mass erase flash memory.
  875. @end itemize
  876. @page
  877. @section Architecture Specific Commands
  878. @cindex Architecture Specific Commands
  879. @subsection ARMV4/5 specific commands
  880. @cindex ARMV4/5 specific commands
  881. These commands are specific to ARM architecture v4 and v5, like all ARM7/9 systems
  882. or Intel XScale (XScale isn't supported yet).
  883. @itemize @bullet
  884. @item @b{armv4_5 reg}
  885. @cindex armv4_5 reg
  886. Display a list of all banked core registers, fetching the current value from every
  887. core mode if necessary. OpenOCD versions before rev. 60 didn't fetch the current
  888. register value.
  889. @item @b{armv4_5 core_mode} [@var{arm}|@var{thumb}]
  890. @cindex armv4_5 core_mode
  891. Displays the core_mode, optionally changing it to either ARM or Thumb mode.
  892. The target is resumed in the currently set @option{core_mode}.
  893. @end itemize
  894. @subsection ARM7/9 specific commands
  895. @cindex ARM7/9 specific commands
  896. These commands are specific to ARM7 and ARM9 targets, like ARM7TDMI, ARM720t,
  897. ARM920t or ARM926EJ-S.
  898. @itemize @bullet
  899. @item @b{arm7_9 sw_bkpts} <@var{enable}|@var{disable}>
  900. @cindex arm7_9 sw_bkpts
  901. Enable/disable use of software breakpoints. On ARMv4 systems, this reserves
  902. one of the watchpoint registers to implement software breakpoints. Disabling
  903. SW Bkpts frees that register again.
  904. @item @b{arm7_9 force_hw_bkpts} <@var{enable}|@var{disable}>
  905. @cindex arm7_9 force_hw_bkpts
  906. When @option{force_hw_bkpts} is enabled, the @option{sw_bkpts} support is disabled, and all
  907. breakpoints are turned into hardware breakpoints.
  908. @item @b{arm7_9 dbgrq} <@var{enable}|@var{disable}>
  909. @cindex arm7_9 dbgrq
  910. Enable use of the DBGRQ bit to force entry into debug mode. This should be
  911. safe for all but ARM7TDMI--S cores (like Philips LPC).
  912. @item @b{arm7_9 fast_memory_access} <@var{enable}|@var{disable}>
  913. @cindex arm7_9 fast_memory_access
  914. Allow the OpenOCD to read and write memory without checking completion of
  915. the operation. This provides a huge speed increase, especially with USB JTAG
  916. cables (FT2232), but might be unsafe if used with targets running at a very low
  917. speed, like the 32kHz startup clock of an AT91RM9200.
  918. @item @b{arm7_9 dcc_downloads} <@var{enable}|@var{disable}>
  919. @cindex arm7_9 dcc_downloads
  920. Enable the use of the debug communications channel (DCC) to write larger (>128 byte)
  921. amounts of memory. DCC downloads offer a huge speed increase, but might be potentially
  922. unsafe, especially with targets running at a very low speed. This command was introduced
  923. with OpenOCD rev. 60.
  924. @end itemize
  925. @subsection ARM720T specific commands
  926. @cindex ARM720T specific commands
  927. @itemize @bullet
  928. @item @b{arm720t cp15} <@var{num}> [@var{value}]
  929. @cindex arm720t cp15
  930. display/modify cp15 register <@option{num}> [@option{value}].
  931. @item @b{arm720t md<bhw>_phys} <@var{addr}> [@var{count}]
  932. @cindex arm720t md<bhw>_phys
  933. Display memory at physical address addr.
  934. @item @b{arm720t mw<bhw>_phys} <@var{addr}> <@var{value}>
  935. @cindex arm720t mw<bhw>_phys
  936. Write memory at physical address addr.
  937. @item @b{arm720t virt2phys} <@var{va}>
  938. @cindex arm720t virt2phys
  939. Translate a virtual address to a physical address.
  940. @end itemize
  941. @subsection ARM9TDMI specific commands
  942. @cindex ARM9TDMI specific commands
  943. @itemize @bullet
  944. @item @b{arm9tdmi vector_catch} <@var{all}|@var{none}>
  945. @cindex arm9tdmi vector_catch
  946. Catch arm9 interrupt vectors, can be @option{all} @option{none} or any of the following:
  947. @option{reset} @option{undef} @option{swi} @option{pabt} @option{dabt} @option{reserved}
  948. @option{irq} @option{fiq}.
  949. Can also be used on other arm9 based cores, arm966, arm920t and arm926ejs.
  950. @end itemize
  951. @subsection ARM966E specific commands
  952. @cindex ARM966E specific commands
  953. @itemize @bullet
  954. @item @b{arm966e cp15} <@var{num}> [@var{value}]
  955. @cindex arm966e cp15
  956. display/modify cp15 register <@option{num}> [@option{value}].
  957. @end itemize
  958. @subsection ARM920T specific commands
  959. @cindex ARM920T specific commands
  960. @itemize @bullet
  961. @item @b{arm920t cp15} <@var{num}> [@var{value}]
  962. @cindex arm920t cp15
  963. display/modify cp15 register <@option{num}> [@option{value}].
  964. @item @b{arm920t cp15i} <@var{num}> [@var{value}] [@var{address}]
  965. @cindex arm920t cp15i
  966. display/modify cp15 (interpreted access) <@option{opcode}> [@option{value}] [@option{address}]
  967. @item @b{arm920t cache_info}
  968. @cindex arm920t cache_info
  969. Print information about the caches found. This allows you to see if your target
  970. is a ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
  971. @item @b{arm920t md<bhw>_phys} <@var{addr}> [@var{count}]
  972. @cindex arm920t md<bhw>_phys
  973. Display memory at physical address addr.
  974. @item @b{arm920t mw<bhw>_phys} <@var{addr}> <@var{value}>
  975. @cindex arm920t mw<bhw>_phys
  976. Write memory at physical address addr.
  977. @item @b{arm920t read_cache} <@var{filename}>
  978. @cindex arm920t read_cache
  979. Dump the content of ICache and DCache to a file.
  980. @item @b{arm920t read_mmu} <@var{filename}>
  981. @cindex arm920t read_mmu
  982. Dump the content of the ITLB and DTLB to a file.
  983. @item @b{arm920t virt2phys} <@var{va}>
  984. @cindex arm920t virt2phys
  985. Translate a virtual address to a physical address.
  986. @end itemize
  987. @subsection ARM926EJS specific commands
  988. @cindex ARM926EJS specific commands
  989. @itemize @bullet
  990. @item @b{arm926ejs cp15} <@var{num}> [@var{value}]
  991. @cindex arm926ejs cp15
  992. display/modify cp15 register <@option{num}> [@option{value}].
  993. @item @b{arm926ejs cache_info}
  994. @cindex arm926ejs cache_info
  995. Print information about the caches found.
  996. @item @b{arm926ejs md<bhw>_phys} <@var{addr}> [@var{count}]
  997. @cindex arm926ejs md<bhw>_phys
  998. Display memory at physical address addr.
  999. @item @b{arm926ejs mw<bhw>_phys} <@var{addr}> <@var{value}>
  1000. @cindex arm926ejs mw<bhw>_phys
  1001. Write memory at physical address addr.
  1002. @item @b{arm926ejs virt2phys} <@var{va}>
  1003. @cindex arm926ejs virt2phys
  1004. Translate a virtual address to a physical address.
  1005. @end itemize
  1006. @page
  1007. @section Debug commands
  1008. @cindex Debug commands
  1009. The following commands give direct access to the core, and are most likely
  1010. only useful while debugging the OpenOCD.
  1011. @itemize @bullet
  1012. @item @b{arm7_9 write_xpsr} <@var{32-bit value}> <@option{0=cpsr}, @option{1=spsr}>
  1013. @cindex arm7_9 write_xpsr
  1014. Immediately write either the current program status register (CPSR) or the saved
  1015. program status register (SPSR), without changing the register cache (as displayed
  1016. by the @option{reg} and @option{armv4_5 reg} commands).
  1017. @item @b{arm7_9 write_xpsr_im8} <@var{8-bit value}> <@var{rotate 4-bit}>
  1018. <@var{0=cpsr},@var{1=spsr}>
  1019. @cindex arm7_9 write_xpsr_im8
  1020. Write the 8-bit value rotated right by 2*rotate bits, using an immediate write
  1021. operation (similar to @option{write_xpsr}).
  1022. @item @b{arm7_9 write_core_reg} <@var{num}> <@var{mode}> <@var{value}>
  1023. @cindex arm7_9 write_core_reg
  1024. Write a core register, without changing the register cache (as displayed by the
  1025. @option{reg} and @option{armv4_5 reg} commands). The <@var{mode}> argument takes the
  1026. encoding of the [M4:M0] bits of the PSR.
  1027. @end itemize
  1028. @page
  1029. @section JTAG commands
  1030. @cindex JTAG commands
  1031. @itemize @bullet
  1032. @item @b{scan_chain}
  1033. @cindex scan_chain
  1034. Print current scan chain configuration.
  1035. @item @b{jtag_reset} <@var{trst}> <@var{srst}>
  1036. @cindex jtag_reset
  1037. Toggle reset lines.
  1038. @item @b{endstate} <@var{tap_state}>
  1039. @cindex endstate
  1040. Finish JTAG operations in <@var{tap_state}>.
  1041. @item @b{runtest} <@var{num_cycles}>
  1042. @cindex runtest
  1043. Move to Run-Test/Idle, and execute <@var{num_cycles}>
  1044. @item @b{statemove} [@var{tap_state}]
  1045. @cindex statemove
  1046. Move to current endstate or [@var{tap_state}]
  1047. @item @b{irscan} <@var{device}> <@var{instr}> [@var{dev2}] [@var{instr2}] ...
  1048. @cindex irscan
  1049. Execute IR scan <@var{device}> <@var{instr}> [@var{dev2}] [@var{instr2}] ...
  1050. @item @b{drscan} <@var{device}> [@var{dev2}] [@var{var2}] ...
  1051. @cindex drscan
  1052. Execute DR scan <@var{device}> [@var{dev2}] [@var{var2}] ...
  1053. @item @b{verify_ircapture} <@option{enable}|@option{disable}>
  1054. @cindex verify_ircapture
  1055. Verify value captured during Capture-IR. Default is enabled.
  1056. @item @b{var} <@var{name}> [@var{num_fields}|@var{del}] [@var{size1}] ...
  1057. @cindex var
  1058. Allocate, display or delete variable <@var{name}> [@var{num_fields}|@var{del}] [@var{size1}] ...
  1059. @item @b{field} <@var{var}> <@var{field}> [@var{value}|@var{flip}]
  1060. @cindex field
  1061. Display/modify variable field <@var{var}> <@var{field}> [@var{value}|@var{flip}].
  1062. @end itemize
  1063. @page
  1064. @section Target Requests
  1065. @cindex Target Requests
  1066. Openocd can handle certain target requests, currently debugmsg are only supported for arm7_9 and cortex_m3.
  1067. See libdcc in the contrib dir for more details.
  1068. @itemize @bullet
  1069. @item @b{target_request debugmsgs} <@var{enable}|@var{disable}>
  1070. @cindex target_request debugmsgs
  1071. Enable/disable target debugmsgs requests. debugmsgs enable messages to be sent to the debugger while the target is running.
  1072. @end itemize
  1073. @node Sample Scripts
  1074. @chapter Sample Scripts
  1075. @cindex scripts
  1076. This page shows how to use the target library.
  1077. The configuration script can be divided in the following section:
  1078. @itemize @bullet
  1079. @item daemon configuration
  1080. @item interface
  1081. @item jtag scan chain
  1082. @item target configuration
  1083. @item flash configuration
  1084. @end itemize
  1085. Detailed information about each section can be found at OpenOCD configuration.
  1086. @section AT91R40008 example
  1087. @cindex AT91R40008 example
  1088. To start OpenOCD with a target script for the AT91R40008 CPU and reset
  1089. the CPU upon startup of the OpenOCD daemon.
  1090. @smallexample
  1091. openocd -f interface/parport.cfg -f target/at91r40008.cfg -c init -c reset
  1092. @end smallexample
  1093. @node GDB and Openocd
  1094. @chapter GDB and Openocd
  1095. @cindex GDB and Openocd
  1096. Openocd complies with the remote gdbserver protocol, and as such can be used
  1097. to debug remote targets.
  1098. @section Connecting to gdb
  1099. @cindex Connecting to gdb
  1100. A connection is typically started as follows:
  1101. @smallexample
  1102. target remote localhost:3333
  1103. @end smallexample
  1104. This would cause gdb to connect to the gdbserver on the local pc using port 3333.
  1105. To see a list of available openocd commands type @option{monitor help} on the
  1106. gdb commandline.
  1107. Openocd supports the gdb @option{qSupported} packet, this enables information
  1108. to be sent by the gdb server (openocd) to gdb. Typical information includes
  1109. packet size and device memory map.
  1110. Previous versions of openocd required the following gdb options to increase
  1111. the packet size and speed up gdb communication.
  1112. @smallexample
  1113. set remote memory-write-packet-size 1024
  1114. set remote memory-write-packet-size fixed
  1115. set remote memory-read-packet-size 1024
  1116. set remote memory-read-packet-size fixed
  1117. @end smallexample
  1118. This is now handled in the @option{qSupported} PacketSize.
  1119. @section Programming using gdb
  1120. @cindex Programming using gdb
  1121. By default the target memory map is not sent to gdb, this can be enabled by
  1122. the following openocd config option:
  1123. @smallexample
  1124. gdb_memory_map enable
  1125. @end smallexample
  1126. For this to function correctly a valid flash config must also be configured
  1127. in openocd. For speed also configure a valid working area.
  1128. Informing gdb of the memory map of the target will enable gdb to protect any
  1129. flash area of the target and use hardware breakpoints by default. This means
  1130. that the openocd option @option{arm7_9 force_hw_bkpts} is not required when
  1131. using a memory map.
  1132. To view the configured memory map in gdb, use the gdb command @option{info mem}
  1133. All other unasigned addresses within gdb are treated as RAM.
  1134. GDB 6.8 and higher set any memory area not in the memory map as inaccessible,
  1135. this can be changed to the old behaviour by using the following gdb command.
  1136. @smallexample
  1137. set mem inaccessible-by-default off
  1138. @end smallexample
  1139. If @option{gdb_flash_program enable} is also used, gdb will be able to
  1140. program any flash memory using the vFlash interface.
  1141. gdb will look at the target memory map when a load command is given, if any
  1142. areas to be programmed lie within the target flash area the vFlash packets
  1143. will be used.
  1144. Incase the target needs configuring before gdb programming, a script can be executed.
  1145. @smallexample
  1146. target_script 0 gdb_program_config config.script
  1147. @end smallexample
  1148. To verify any flash programming the gdb command @option{compare-sections}
  1149. can be used.
  1150. @node Upgrading
  1151. @chapter Deprecated/Removed Commands
  1152. @cindex Deprecated/Removed Commands
  1153. Certain openocd commands have been deprecated/removed during the various revisions.
  1154. @itemize @bullet
  1155. @item @b{load_binary}
  1156. @cindex load_binary
  1157. use @option{load_image} command with same args
  1158. @item @b{dump_binary}
  1159. @cindex dump_binary
  1160. use @option{dump_image} command with same args
  1161. @item @b{flash erase}
  1162. @cindex flash erase
  1163. use @option{flash erase_sector} command with same args
  1164. @item @b{flash write}
  1165. @cindex flash write
  1166. use @option{flash write_bank} command with same args
  1167. @item @b{flash write_binary}
  1168. @cindex flash write_binary
  1169. use @option{flash write_bank} command with same args
  1170. @item @b{arm7_9 fast_writes}
  1171. @cindex arm7_9 fast_writes
  1172. use @option{arm7_9 fast_memory_access} command with same args
  1173. @item @b{flash auto_erase}
  1174. @cindex flash auto_erase
  1175. use @option{flash write_image} command passing @option{erase} as the first parameter.
  1176. @end itemize
  1177. @node FAQ
  1178. @chapter FAQ
  1179. @cindex faq
  1180. @enumerate
  1181. @item OpenOCD complains about a missing cygwin1.dll.
  1182. Make sure you have Cygwin installed, or at least a version of OpenOCD that
  1183. claims to come with all the necessary dlls. When using Cygwin, try launching
  1184. the OpenOCD from the Cygwin shell.
  1185. @item I'm trying to set a breakpoint using GDB (or a frontend like Insight or
  1186. Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213
  1187. arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".
  1188. GDB issues software breakpoints when a normal breakpoint is requested, or to implement
  1189. source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720t or ARM920t,
  1190. software breakpoints consume one of the two available hardware breakpoints,
  1191. and are therefore disabled by default. If your code is running from RAM, you
  1192. can enable software breakpoints with the @option{arm7_9 sw_bkpts enable} command. If
  1193. your code resides in Flash, you can't use software breakpoints, but you can force
  1194. OpenOCD to use hardware breakpoints instead: @option{arm7_9 force_hw_bkpts enable}.
  1195. @item When erasing or writing LPC2000 on-chip flash, the operation fails sometimes
  1196. and works sometimes fine.
  1197. Make sure the core frequency specified in the @option{flash lpc2000} line matches the
  1198. clock at the time you're programming the flash. If you've specified the crystal's
  1199. frequency, make sure the PLL is disabled, if you've specified the full core speed
  1200. (e.g. 60MHz), make sure the PLL is enabled.
  1201. @item When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
  1202. I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed
  1203. out while waiting for end of scan, rtck was disabled".
  1204. Make sure your PC's parallel port operates in EPP mode. You might have to try several
  1205. settings in your PC BIOS (ECP, EPP, and different versions of those).
  1206. @item When debugging with the OpenOCD and GDB (plain GDB, Insight, or Eclipse),
  1207. I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():
  1208. memory read caused data abort".
  1209. The errors are non-fatal, and are the result of GDB trying to trace stack frames
  1210. beyond the last valid frame. It might be possible to prevent this by setting up
  1211. a proper "initial" stack frame, if you happen to know what exactly has to
  1212. be done, feel free to add this here.
  1213. @item I get the following message in the OpenOCD console (or log file):
  1214. "Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".
  1215. This warning doesn't indicate any serious problem, as long as you don't want to
  1216. debug your core right out of reset. Your .cfg file specified @option{jtag_reset
  1217. trst_and_srst srst_pulls_trst} to tell the OpenOCD that either your board,
  1218. your debugger or your target uC (e.g. LPC2000) can't assert the two reset signals
  1219. independently. With this setup, it's not possible to halt the core right out of
  1220. reset, everything else should work fine.
  1221. @item When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto
  1222. Toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be
  1223. unstable. When single-stepping over large blocks of code, GDB and OpenOCD
  1224. quit with an error message. Is there a stability issue with OpenOCD?
  1225. No, this is not a stability issue concerning OpenOCD. Most users have solved
  1226. this issue by simply using a self-powered USB hub, which they connect their
  1227. Amontec JTAGkey to. Apparently, some computers do not provide a USB power
  1228. supply stable enough for the Amontec JTAGkey to be operated.
  1229. @item When using the Amontec JTAGkey, sometimes OpenOCD crashes with the
  1230. following error messages: "Error: ft2232.c:201 ft2232_read(): FT_Read returned:
  1231. 4" and "Error: ft2232.c:365 ft2232_send_and_recv(): couldn't read from FT2232".
  1232. What does that mean and what might be the reason for this?
  1233. First of all, the reason might be the USB power supply. Try using a self-powered
  1234. hub instead of a direct connection to your computer. Secondly, the error code 4
  1235. corresponds to an FT_IO_ERROR, which means that the driver for the FTDI USB
  1236. chip ran into some sort of error - this points us to a USB problem.
  1237. @item When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following
  1238. error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054".
  1239. What does that mean and what might be the reason for this?
  1240. Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB)
  1241. has closed the connection to OpenOCD. This might be a GDB issue.
  1242. @item In the configuration file in the section where flash device configurations
  1243. are described, there is a parameter for specifying the clock frequency for
  1244. LPC2000 internal flash devices (e.g.
  1245. @option{flash bank lpc2000 0x0 0x40000 0 0 0 lpc2000_v1 14746 calc_checksum}),
  1246. which must be specified in kilohertz. However, I do have a quartz crystal of a
  1247. frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz, i.e. 14,745.600 kHz).
  1248. Is it possible to specify real numbers for the clock frequency?
  1249. No. The clock frequency specified here must be given as an integral number.
  1250. However, this clock frequency is used by the In-Application-Programming (IAP)
  1251. routines of the LPC2000 family only, which seems to be very tolerant concerning
  1252. the given clock frequency, so a slight difference between the specified clock
  1253. frequency and the actual clock frequency will not cause any trouble.
  1254. @item Do I have to keep a specific order for the commands in the configuration file?
  1255. Well, yes and no. Commands can be given in arbitrary order, yet the devices
  1256. listed for the JTAG scan chain must be given in the right order (jtag_device),
  1257. with the device closest to the TDO-Pin being listed first. In general,
  1258. whenever objects of the same type exist which require an index number, then
  1259. these objects must be given in the right order (jtag_devices, targets and flash
  1260. banks - a target references a jtag_device and a flash bank references a target).
  1261. @item Sometimes my debugging session terminates with an error. When I look into the
  1262. log file, I can see these error messages: Error: arm7_9_common.c:561
  1263. arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP
  1264. TODO.
  1265. @end enumerate
  1266. @include fdl.texi
  1267. @node Index
  1268. @unnumbered Index
  1269. @printindex cp
  1270. @bye