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  1. /***************************************************************************
  2. * Copyright (C) 2005 by Dominic Rath *
  3. * Dominic.Rath@gmx.de *
  4. * *
  5. * This program is free software; you can redistribute it and/or modify *
  6. * it under the terms of the GNU General Public License as published by *
  7. * the Free Software Foundation; either version 2 of the License, or *
  8. * (at your option) any later version. *
  9. * *
  10. * This program is distributed in the hope that it will be useful, *
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  13. * GNU General Public License for more details. *
  14. * *
  15. * You should have received a copy of the GNU General Public License *
  16. * along with this program; if not, write to the *
  17. * Free Software Foundation, Inc., *
  18. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
  19. ***************************************************************************/
  20. #ifdef HAVE_CONFIG_H
  21. #include "config.h"
  22. #endif
  23. #include "replacements.h"
  24. #include "embeddedice.h"
  25. #include "target.h"
  26. #include "target_request.h"
  27. #include "armv4_5.h"
  28. #include "arm_jtag.h"
  29. #include "jtag.h"
  30. #include "log.h"
  31. #include "arm7_9_common.h"
  32. #include "breakpoints.h"
  33. #include <stdlib.h>
  34. #include <string.h>
  35. #include <unistd.h>
  36. #include <sys/types.h>
  37. #include <sys/stat.h>
  38. #include <sys/time.h>
  39. #include <errno.h>
  40. int arm7_9_debug_entry(target_t *target);
  41. int arm7_9_enable_sw_bkpts(struct target_s *target);
  42. /* command handler forward declarations */
  43. int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  44. int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  45. int handle_arm7_9_read_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  46. int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  47. int handle_arm7_9_sw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  48. int handle_arm7_9_force_hw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  49. int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  50. int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  51. int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  52. int handle_arm7_9_etm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  53. int arm7_9_reinit_embeddedice(target_t *target)
  54. {
  55. armv4_5_common_t *armv4_5 = target->arch_info;
  56. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  57. breakpoint_t *breakpoint = target->breakpoints;
  58. arm7_9->wp_available = 2;
  59. arm7_9->wp0_used = 0;
  60. arm7_9->wp1_used = 0;
  61. /* mark all hardware breakpoints as unset */
  62. while (breakpoint)
  63. {
  64. if (breakpoint->type == BKPT_HARD)
  65. {
  66. breakpoint->set = 0;
  67. }
  68. breakpoint = breakpoint->next;
  69. }
  70. if (arm7_9->sw_bkpts_enabled && arm7_9->sw_bkpts_use_wp)
  71. {
  72. arm7_9->sw_bkpts_enabled = 0;
  73. arm7_9_enable_sw_bkpts(target);
  74. }
  75. return ERROR_OK;
  76. }
  77. /* set things up after a reset / on startup */
  78. int arm7_9_setup(target_t *target)
  79. {
  80. /* a test-logic reset have occured
  81. * the EmbeddedICE registers have been reset
  82. * hardware breakpoints have been cleared
  83. */
  84. return arm7_9_reinit_embeddedice(target);
  85. }
  86. int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p)
  87. {
  88. armv4_5_common_t *armv4_5 = target->arch_info;
  89. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  90. if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
  91. {
  92. return -1;
  93. }
  94. if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
  95. {
  96. return -1;
  97. }
  98. *armv4_5_p = armv4_5;
  99. *arm7_9_p = arm7_9;
  100. return ERROR_OK;
  101. }
  102. int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
  103. {
  104. armv4_5_common_t *armv4_5 = target->arch_info;
  105. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  106. if (target->state != TARGET_HALTED)
  107. {
  108. LOG_WARNING("target not halted");
  109. return ERROR_TARGET_NOT_HALTED;
  110. }
  111. if (arm7_9->force_hw_bkpts)
  112. breakpoint->type = BKPT_HARD;
  113. if (breakpoint->set)
  114. {
  115. LOG_WARNING("breakpoint already set");
  116. return ERROR_OK;
  117. }
  118. if (breakpoint->type == BKPT_HARD)
  119. {
  120. /* either an ARM (4 byte) or Thumb (2 byte) breakpoint */
  121. u32 mask = (breakpoint->length == 4) ? 0x3u : 0x1u;
  122. if (!arm7_9->wp0_used)
  123. {
  124. embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], breakpoint->address);
  125. embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
  126. embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffffu);
  127. embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
  128. embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
  129. jtag_execute_queue();
  130. arm7_9->wp0_used = 1;
  131. breakpoint->set = 1;
  132. }
  133. else if (!arm7_9->wp1_used)
  134. {
  135. embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], breakpoint->address);
  136. embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
  137. embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffffu);
  138. embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
  139. embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
  140. jtag_execute_queue();
  141. arm7_9->wp1_used = 1;
  142. breakpoint->set = 2;
  143. }
  144. else
  145. {
  146. LOG_ERROR("BUG: no hardware comparator available");
  147. return ERROR_OK;
  148. }
  149. }
  150. else if (breakpoint->type == BKPT_SOFT)
  151. {
  152. if (breakpoint->length == 4)
  153. {
  154. u32 verify = 0xffffffff;
  155. /* keep the original instruction in target endianness */
  156. target->type->read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
  157. /* write the breakpoint instruction in target endianness (arm7_9->arm_bkpt is host endian) */
  158. target_write_u32(target, breakpoint->address, arm7_9->arm_bkpt);
  159. target->type->read_memory(target, breakpoint->address, 4, 1, (u8 *)&verify);
  160. if (verify != arm7_9->arm_bkpt)
  161. {
  162. LOG_ERROR("Unable to set 32 bit software breakpoint at address %08x", breakpoint->address);
  163. return ERROR_OK;
  164. }
  165. }
  166. else
  167. {
  168. u16 verify = 0xffff;
  169. /* keep the original instruction in target endianness */
  170. target->type->read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
  171. /* write the breakpoint instruction in target endianness (arm7_9->thumb_bkpt is host endian) */
  172. target_write_u16(target, breakpoint->address, arm7_9->thumb_bkpt);
  173. target->type->read_memory(target, breakpoint->address, 2, 1, (u8 *)&verify);
  174. if (verify != arm7_9->thumb_bkpt)
  175. {
  176. LOG_ERROR("Unable to set thumb software breakpoint at address %08x", breakpoint->address);
  177. return ERROR_OK;
  178. }
  179. }
  180. breakpoint->set = 1;
  181. }
  182. return ERROR_OK;
  183. }
  184. int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
  185. {
  186. armv4_5_common_t *armv4_5 = target->arch_info;
  187. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  188. if (target->state != TARGET_HALTED)
  189. {
  190. LOG_WARNING("target not halted");
  191. return ERROR_TARGET_NOT_HALTED;
  192. }
  193. if (!breakpoint->set)
  194. {
  195. LOG_WARNING("breakpoint not set");
  196. return ERROR_OK;
  197. }
  198. if (breakpoint->type == BKPT_HARD)
  199. {
  200. if (breakpoint->set == 1)
  201. {
  202. embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
  203. jtag_execute_queue();
  204. arm7_9->wp0_used = 0;
  205. }
  206. else if (breakpoint->set == 2)
  207. {
  208. embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
  209. jtag_execute_queue();
  210. arm7_9->wp1_used = 0;
  211. }
  212. breakpoint->set = 0;
  213. }
  214. else
  215. {
  216. /* restore original instruction (kept in target endianness) */
  217. if (breakpoint->length == 4)
  218. {
  219. u32 current_instr;
  220. /* check that user program as not modified breakpoint instruction */
  221. target->type->read_memory(target, breakpoint->address, 4, 1, (u8*)&current_instr);
  222. if (current_instr==arm7_9->arm_bkpt)
  223. target->type->write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
  224. }
  225. else
  226. {
  227. u16 current_instr;
  228. /* check that user program as not modified breakpoint instruction */
  229. target->type->read_memory(target, breakpoint->address, 2, 1, (u8*)&current_instr);
  230. if (current_instr==arm7_9->thumb_bkpt)
  231. target->type->write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
  232. }
  233. breakpoint->set = 0;
  234. }
  235. return ERROR_OK;
  236. }
  237. int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
  238. {
  239. armv4_5_common_t *armv4_5 = target->arch_info;
  240. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  241. if (target->state != TARGET_HALTED)
  242. {
  243. LOG_WARNING("target not halted");
  244. return ERROR_TARGET_NOT_HALTED;
  245. }
  246. if (arm7_9->force_hw_bkpts)
  247. {
  248. LOG_DEBUG("forcing use of hardware breakpoint at address 0x%8.8x", breakpoint->address);
  249. breakpoint->type = BKPT_HARD;
  250. }
  251. if ((breakpoint->type == BKPT_SOFT) && (arm7_9->sw_bkpts_enabled == 0))
  252. {
  253. LOG_INFO("sw breakpoint requested, but software breakpoints not enabled");
  254. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  255. }
  256. if ((breakpoint->type == BKPT_HARD) && (arm7_9->wp_available < 1))
  257. {
  258. LOG_INFO("no watchpoint unit available for hardware breakpoint");
  259. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  260. }
  261. if ((breakpoint->length != 2) && (breakpoint->length != 4))
  262. {
  263. LOG_INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
  264. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  265. }
  266. if (breakpoint->type == BKPT_HARD)
  267. arm7_9->wp_available--;
  268. return ERROR_OK;
  269. }
  270. int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
  271. {
  272. armv4_5_common_t *armv4_5 = target->arch_info;
  273. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  274. if (target->state != TARGET_HALTED)
  275. {
  276. LOG_WARNING("target not halted");
  277. return ERROR_TARGET_NOT_HALTED;
  278. }
  279. if (breakpoint->set)
  280. {
  281. arm7_9_unset_breakpoint(target, breakpoint);
  282. }
  283. if (breakpoint->type == BKPT_HARD)
  284. arm7_9->wp_available++;
  285. return ERROR_OK;
  286. }
  287. int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
  288. {
  289. armv4_5_common_t *armv4_5 = target->arch_info;
  290. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  291. int rw_mask = 1;
  292. u32 mask;
  293. mask = watchpoint->length - 1;
  294. if (target->state != TARGET_HALTED)
  295. {
  296. LOG_WARNING("target not halted");
  297. return ERROR_TARGET_NOT_HALTED;
  298. }
  299. if (watchpoint->rw == WPT_ACCESS)
  300. rw_mask = 0;
  301. else
  302. rw_mask = 1;
  303. if (!arm7_9->wp0_used)
  304. {
  305. embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], watchpoint->address);
  306. embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
  307. embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], watchpoint->mask);
  308. if( watchpoint->mask != 0xffffffffu )
  309. embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], watchpoint->value);
  310. embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
  311. embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
  312. jtag_execute_queue();
  313. watchpoint->set = 1;
  314. arm7_9->wp0_used = 2;
  315. }
  316. else if (!arm7_9->wp1_used)
  317. {
  318. embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], watchpoint->address);
  319. embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
  320. embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], watchpoint->mask);
  321. if( watchpoint->mask != 0xffffffffu )
  322. embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], watchpoint->value);
  323. embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
  324. embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
  325. jtag_execute_queue();
  326. watchpoint->set = 2;
  327. arm7_9->wp1_used = 2;
  328. }
  329. else
  330. {
  331. LOG_ERROR("BUG: no hardware comparator available");
  332. return ERROR_OK;
  333. }
  334. return ERROR_OK;
  335. }
  336. int arm7_9_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
  337. {
  338. armv4_5_common_t *armv4_5 = target->arch_info;
  339. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  340. if (target->state != TARGET_HALTED)
  341. {
  342. LOG_WARNING("target not halted");
  343. return ERROR_TARGET_NOT_HALTED;
  344. }
  345. if (!watchpoint->set)
  346. {
  347. LOG_WARNING("breakpoint not set");
  348. return ERROR_OK;
  349. }
  350. if (watchpoint->set == 1)
  351. {
  352. embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
  353. jtag_execute_queue();
  354. arm7_9->wp0_used = 0;
  355. }
  356. else if (watchpoint->set == 2)
  357. {
  358. embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
  359. jtag_execute_queue();
  360. arm7_9->wp1_used = 0;
  361. }
  362. watchpoint->set = 0;
  363. return ERROR_OK;
  364. }
  365. int arm7_9_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
  366. {
  367. armv4_5_common_t *armv4_5 = target->arch_info;
  368. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  369. if (target->state != TARGET_HALTED)
  370. {
  371. LOG_WARNING("target not halted");
  372. return ERROR_TARGET_NOT_HALTED;
  373. }
  374. if (arm7_9->wp_available < 1)
  375. {
  376. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  377. }
  378. if ((watchpoint->length != 1) && (watchpoint->length != 2) && (watchpoint->length != 4))
  379. {
  380. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  381. }
  382. arm7_9->wp_available--;
  383. return ERROR_OK;
  384. }
  385. int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
  386. {
  387. armv4_5_common_t *armv4_5 = target->arch_info;
  388. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  389. if (target->state != TARGET_HALTED)
  390. {
  391. LOG_WARNING("target not halted");
  392. return ERROR_TARGET_NOT_HALTED;
  393. }
  394. if (watchpoint->set)
  395. {
  396. arm7_9_unset_watchpoint(target, watchpoint);
  397. }
  398. arm7_9->wp_available++;
  399. return ERROR_OK;
  400. }
  401. int arm7_9_enable_sw_bkpts(struct target_s *target)
  402. {
  403. armv4_5_common_t *armv4_5 = target->arch_info;
  404. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  405. int retval;
  406. if (arm7_9->sw_bkpts_enabled)
  407. return ERROR_OK;
  408. if (arm7_9->wp_available < 1)
  409. {
  410. LOG_WARNING("can't enable sw breakpoints with no watchpoint unit available");
  411. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  412. }
  413. arm7_9->wp_available--;
  414. if (!arm7_9->wp0_used)
  415. {
  416. embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], arm7_9->arm_bkpt);
  417. embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0);
  418. embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffffu);
  419. embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
  420. embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
  421. arm7_9->sw_bkpts_enabled = 1;
  422. arm7_9->wp0_used = 3;
  423. }
  424. else if (!arm7_9->wp1_used)
  425. {
  426. embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], arm7_9->arm_bkpt);
  427. embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0x0);
  428. embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0xffffffffu);
  429. embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
  430. embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
  431. arm7_9->sw_bkpts_enabled = 2;
  432. arm7_9->wp1_used = 3;
  433. }
  434. else
  435. {
  436. LOG_ERROR("BUG: both watchpoints used, but wp_available >= 1");
  437. return ERROR_FAIL;
  438. }
  439. if ((retval = jtag_execute_queue()) != ERROR_OK)
  440. {
  441. LOG_ERROR("error writing EmbeddedICE registers to enable sw breakpoints");
  442. return ERROR_FAIL;
  443. };
  444. return ERROR_OK;
  445. }
  446. int arm7_9_disable_sw_bkpts(struct target_s *target)
  447. {
  448. armv4_5_common_t *armv4_5 = target->arch_info;
  449. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  450. if (!arm7_9->sw_bkpts_enabled)
  451. return ERROR_OK;
  452. if (arm7_9->sw_bkpts_enabled == 1)
  453. {
  454. embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
  455. arm7_9->sw_bkpts_enabled = 0;
  456. arm7_9->wp0_used = 0;
  457. arm7_9->wp_available++;
  458. }
  459. else if (arm7_9->sw_bkpts_enabled == 2)
  460. {
  461. embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
  462. arm7_9->sw_bkpts_enabled = 0;
  463. arm7_9->wp1_used = 0;
  464. arm7_9->wp_available++;
  465. }
  466. return ERROR_OK;
  467. }
  468. int arm7_9_execute_sys_speed(struct target_s *target)
  469. {
  470. int timeout;
  471. int retval;
  472. armv4_5_common_t *armv4_5 = target->arch_info;
  473. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  474. arm_jtag_t *jtag_info = &arm7_9->jtag_info;
  475. reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
  476. /* set RESTART instruction */
  477. jtag_add_end_state(TAP_RTI);
  478. arm_jtag_set_instr(jtag_info, 0x4, NULL);
  479. for (timeout=0; timeout<50; timeout++)
  480. {
  481. /* read debug status register */
  482. embeddedice_read_reg(dbg_stat);
  483. if ((retval = jtag_execute_queue()) != ERROR_OK)
  484. return retval;
  485. if ((buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
  486. && (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_SYSCOMP, 1)))
  487. break;
  488. usleep(100000);
  489. }
  490. if (timeout == 50)
  491. {
  492. LOG_ERROR("timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: %x", buf_get_u32(dbg_stat->value, 0, dbg_stat->size));
  493. return ERROR_TARGET_TIMEOUT;
  494. }
  495. return ERROR_OK;
  496. }
  497. int arm7_9_execute_fast_sys_speed(struct target_s *target)
  498. {
  499. static int set=0;
  500. static u8 check_value[4], check_mask[4];
  501. armv4_5_common_t *armv4_5 = target->arch_info;
  502. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  503. arm_jtag_t *jtag_info = &arm7_9->jtag_info;
  504. reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
  505. /* set RESTART instruction */
  506. jtag_add_end_state(TAP_RTI);
  507. arm_jtag_set_instr(jtag_info, 0x4, NULL);
  508. if (!set)
  509. {
  510. /* check for DBGACK and SYSCOMP set (others don't care) */
  511. /* NB! These are constants that must be available until after next jtag_execute() and
  512. we evaluate the values upon first execution in lieu of setting up these constants
  513. during early setup.
  514. */
  515. buf_set_u32(check_value, 0, 32, 0x9);
  516. buf_set_u32(check_mask, 0, 32, 0x9);
  517. set=1;
  518. }
  519. /* read debug status register */
  520. embeddedice_read_reg_w_check(dbg_stat, check_value, check_value);
  521. return ERROR_OK;
  522. }
  523. int arm7_9_target_request_data(target_t *target, u32 size, u8 *buffer)
  524. {
  525. armv4_5_common_t *armv4_5 = target->arch_info;
  526. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  527. arm_jtag_t *jtag_info = &arm7_9->jtag_info;
  528. u32 *data;
  529. int i;
  530. data = malloc(size * (sizeof(u32)));
  531. embeddedice_receive(jtag_info, data, size);
  532. for (i = 0; i < size; i++)
  533. {
  534. h_u32_to_le(buffer + (i * 4), data[i]);
  535. }
  536. free(data);
  537. return ERROR_OK;
  538. }
  539. int arm7_9_handle_target_request(void *priv)
  540. {
  541. target_t *target = priv;
  542. if (!target->type->examined)
  543. return ERROR_OK;
  544. armv4_5_common_t *armv4_5 = target->arch_info;
  545. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  546. arm_jtag_t *jtag_info = &arm7_9->jtag_info;
  547. reg_t *dcc_control = &arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL];
  548. if (!target->dbg_msg_enabled)
  549. return ERROR_OK;
  550. if (target->state == TARGET_RUNNING)
  551. {
  552. /* read DCC control register */
  553. embeddedice_read_reg(dcc_control);
  554. jtag_execute_queue();
  555. /* check W bit */
  556. if (buf_get_u32(dcc_control->value, 1, 1) == 1)
  557. {
  558. u32 request;
  559. embeddedice_receive(jtag_info, &request, 1);
  560. target_request(target, request);
  561. }
  562. }
  563. return ERROR_OK;
  564. }
  565. int arm7_9_poll(target_t *target)
  566. {
  567. int retval;
  568. armv4_5_common_t *armv4_5 = target->arch_info;
  569. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  570. reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
  571. /* read debug status register */
  572. embeddedice_read_reg(dbg_stat);
  573. if ((retval = jtag_execute_queue()) != ERROR_OK)
  574. {
  575. return retval;
  576. }
  577. if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
  578. {
  579. LOG_DEBUG("DBGACK set, dbg_state->value: 0x%x", buf_get_u32(dbg_stat->value, 0, 32));
  580. if (target->state == TARGET_UNKNOWN)
  581. {
  582. target->state = TARGET_RUNNING;
  583. LOG_WARNING("DBGACK set while target was in unknown state. Reset or initialize target.");
  584. }
  585. if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
  586. {
  587. target->state = TARGET_HALTED;
  588. if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
  589. return retval;
  590. target_call_event_callbacks(target, TARGET_EVENT_HALTED);
  591. }
  592. if (target->state == TARGET_DEBUG_RUNNING)
  593. {
  594. target->state = TARGET_HALTED;
  595. if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
  596. return retval;
  597. target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
  598. }
  599. if (target->state != TARGET_HALTED)
  600. {
  601. LOG_WARNING("DBGACK set, but the target did not end up in the halted stated %d", target->state);
  602. }
  603. }
  604. else
  605. {
  606. if (target->state != TARGET_DEBUG_RUNNING)
  607. target->state = TARGET_RUNNING;
  608. }
  609. return ERROR_OK;
  610. }
  611. /*
  612. Some -S targets (ARM966E-S in the STR912 isn't affected, ARM926EJ-S
  613. in the LPC3180 and AT91SAM9260 is affected) completely stop the JTAG clock
  614. while the core is held in reset(SRST). It isn't possible to program the halt
  615. condition once reset was asserted, hence a hook that allows the target to set
  616. up its reset-halt condition prior to asserting reset.
  617. */
  618. int arm7_9_assert_reset(target_t *target)
  619. {
  620. armv4_5_common_t *armv4_5 = target->arch_info;
  621. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  622. LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
  623. if (!(jtag_reset_config & RESET_HAS_SRST))
  624. {
  625. LOG_ERROR("Can't assert SRST");
  626. return ERROR_FAIL;
  627. }
  628. if ((target->reset_mode == RESET_HALT) || (target->reset_mode == RESET_INIT))
  629. {
  630. /*
  631. * Some targets do not support communication while SRST is asserted. We need to
  632. * set up the reset vector catch here.
  633. *
  634. * If TRST is asserted, then these settings will be reset anyway, so setting them
  635. * here is harmless.
  636. */
  637. if (arm7_9->has_vector_catch)
  638. {
  639. /* program vector catch register to catch reset vector */
  640. embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH], 0x1);
  641. }
  642. else
  643. {
  644. /* program watchpoint unit to match on reset vector address */
  645. embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0x3);
  646. embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0);
  647. embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x100);
  648. embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xf7);
  649. }
  650. }
  651. /* here we should issue a srst only, but we may have to assert trst as well */
  652. if (jtag_reset_config & RESET_SRST_PULLS_TRST)
  653. {
  654. jtag_add_reset(1, 1);
  655. } else
  656. {
  657. jtag_add_reset(0, 1);
  658. }
  659. target->state = TARGET_RESET;
  660. jtag_add_sleep(50000);
  661. armv4_5_invalidate_core_regs(target);
  662. return ERROR_OK;
  663. }
  664. int arm7_9_deassert_reset(target_t *target)
  665. {
  666. LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
  667. /* deassert reset lines */
  668. jtag_add_reset(0, 0);
  669. return ERROR_OK;
  670. }
  671. int arm7_9_clear_halt(target_t *target)
  672. {
  673. armv4_5_common_t *armv4_5 = target->arch_info;
  674. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  675. reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
  676. /* we used DBGRQ only if we didn't come out of reset */
  677. if (!arm7_9->debug_entry_from_reset && arm7_9->use_dbgrq)
  678. {
  679. /* program EmbeddedICE Debug Control Register to deassert DBGRQ
  680. */
  681. buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
  682. embeddedice_store_reg(dbg_ctrl);
  683. }
  684. else
  685. {
  686. if (arm7_9->debug_entry_from_reset && arm7_9->has_vector_catch)
  687. {
  688. /* if we came out of reset, and vector catch is supported, we used
  689. * vector catch to enter debug state
  690. * restore the register in that case
  691. */
  692. embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH]);
  693. }
  694. else
  695. {
  696. /* restore registers if watchpoint unit 0 was in use
  697. */
  698. if (arm7_9->wp0_used)
  699. {
  700. embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
  701. embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
  702. embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
  703. }
  704. /* control value always has to be restored, as it was either disabled,
  705. * or enabled with possibly different bits
  706. */
  707. embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
  708. }
  709. }
  710. return ERROR_OK;
  711. }
  712. int arm7_9_soft_reset_halt(struct target_s *target)
  713. {
  714. armv4_5_common_t *armv4_5 = target->arch_info;
  715. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  716. reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
  717. reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
  718. int i;
  719. int retval;
  720. if ((retval=target_halt(target))!=ERROR_OK)
  721. return retval;
  722. for (i=0; i<10; i++)
  723. {
  724. if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) != 0)
  725. break;
  726. embeddedice_read_reg(dbg_stat);
  727. if ((retval=jtag_execute_queue())!=ERROR_OK)
  728. return retval;
  729. /* do not eat all CPU, time out after 1 se*/
  730. usleep(100*1000);
  731. }
  732. if (i==10)
  733. {
  734. LOG_ERROR("Failed to halt CPU after 1 sec");
  735. return ERROR_TARGET_TIMEOUT;
  736. }
  737. target->state = TARGET_HALTED;
  738. /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
  739. * ensure that DBGRQ is cleared
  740. */
  741. buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
  742. buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
  743. buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
  744. embeddedice_store_reg(dbg_ctrl);
  745. arm7_9_clear_halt(target);
  746. /* if the target is in Thumb state, change to ARM state */
  747. if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
  748. {
  749. u32 r0_thumb, pc_thumb;
  750. LOG_DEBUG("target entered debug from Thumb state, changing to ARM");
  751. /* Entered debug from Thumb mode */
  752. armv4_5->core_state = ARMV4_5_STATE_THUMB;
  753. arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
  754. }
  755. /* all register content is now invalid */
  756. armv4_5_invalidate_core_regs(target);
  757. /* SVC, ARM state, IRQ and FIQ disabled */
  758. buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
  759. armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
  760. armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
  761. /* start fetching from 0x0 */
  762. buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
  763. armv4_5->core_cache->reg_list[15].dirty = 1;
  764. armv4_5->core_cache->reg_list[15].valid = 1;
  765. armv4_5->core_mode = ARMV4_5_MODE_SVC;
  766. armv4_5->core_state = ARMV4_5_STATE_ARM;
  767. /* reset registers */
  768. for (i = 0; i <= 14; i++)
  769. {
  770. buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, 0xffffffff);
  771. ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 1;
  772. ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
  773. }
  774. target_call_event_callbacks(target, TARGET_EVENT_HALTED);
  775. return ERROR_OK;
  776. }
  777. int arm7_9_halt(target_t *target)
  778. {
  779. armv4_5_common_t *armv4_5 = target->arch_info;
  780. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  781. reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
  782. LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
  783. if (target->state == TARGET_HALTED)
  784. {
  785. LOG_DEBUG("target was already halted");
  786. return ERROR_OK;
  787. }
  788. if (target->state == TARGET_UNKNOWN)
  789. {
  790. LOG_WARNING("target was in unknown state when halt was requested");
  791. }
  792. if (target->state == TARGET_RESET)
  793. {
  794. if ((jtag_reset_config & RESET_SRST_PULLS_TRST) && jtag_srst)
  795. {
  796. LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
  797. return ERROR_TARGET_FAILURE;
  798. }
  799. else
  800. {
  801. /* we came here in a reset_halt or reset_init sequence
  802. * debug entry was already prepared in arm7_9_prepare_reset_halt()
  803. */
  804. target->debug_reason = DBG_REASON_DBGRQ;
  805. return ERROR_OK;
  806. }
  807. }
  808. if (arm7_9->use_dbgrq)
  809. {
  810. /* program EmbeddedICE Debug Control Register to assert DBGRQ
  811. */
  812. buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 1);
  813. embeddedice_store_reg(dbg_ctrl);
  814. }
  815. else
  816. {
  817. /* program watchpoint unit to match on any address
  818. */
  819. embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
  820. embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
  821. embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x100);
  822. embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xf7);
  823. }
  824. target->debug_reason = DBG_REASON_DBGRQ;
  825. return ERROR_OK;
  826. }
  827. int arm7_9_debug_entry(target_t *target)
  828. {
  829. int i;
  830. u32 context[16];
  831. u32* context_p[16];
  832. u32 r0_thumb, pc_thumb;
  833. u32 cpsr;
  834. int retval;
  835. /* get pointers to arch-specific information */
  836. armv4_5_common_t *armv4_5 = target->arch_info;
  837. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  838. reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
  839. reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
  840. #ifdef _DEBUG_ARM7_9_
  841. LOG_DEBUG("-");
  842. #endif
  843. if (arm7_9->pre_debug_entry)
  844. arm7_9->pre_debug_entry(target);
  845. /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
  846. * ensure that DBGRQ is cleared
  847. */
  848. buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
  849. buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
  850. buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
  851. embeddedice_store_reg(dbg_ctrl);
  852. arm7_9_clear_halt(target);
  853. if ((retval = jtag_execute_queue()) != ERROR_OK)
  854. {
  855. switch (retval)
  856. {
  857. case ERROR_JTAG_QUEUE_FAILED:
  858. LOG_ERROR("JTAG queue failed while writing EmbeddedICE control register");
  859. exit(-1);
  860. break;
  861. default:
  862. break;
  863. }
  864. }
  865. if ((retval = arm7_9->examine_debug_reason(target)) != ERROR_OK)
  866. return retval;
  867. if (target->state != TARGET_HALTED)
  868. {
  869. LOG_WARNING("target not halted");
  870. return ERROR_TARGET_NOT_HALTED;
  871. }
  872. /* if the target is in Thumb state, change to ARM state */
  873. if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
  874. {
  875. LOG_DEBUG("target entered debug from Thumb state");
  876. /* Entered debug from Thumb mode */
  877. armv4_5->core_state = ARMV4_5_STATE_THUMB;
  878. arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
  879. LOG_DEBUG("r0_thumb: 0x%8.8x, pc_thumb: 0x%8.8x", r0_thumb, pc_thumb);
  880. }
  881. else
  882. {
  883. LOG_DEBUG("target entered debug from ARM state");
  884. /* Entered debug from ARM mode */
  885. armv4_5->core_state = ARMV4_5_STATE_ARM;
  886. }
  887. for (i = 0; i < 16; i++)
  888. context_p[i] = &context[i];
  889. /* save core registers (r0 - r15 of current core mode) */
  890. arm7_9->read_core_regs(target, 0xffff, context_p);
  891. arm7_9->read_xpsr(target, &cpsr, 0);
  892. if ((retval = jtag_execute_queue()) != ERROR_OK)
  893. return retval;
  894. /* if the core has been executing in Thumb state, set the T bit */
  895. if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
  896. cpsr |= 0x20;
  897. buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, cpsr);
  898. armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 0;
  899. armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
  900. armv4_5->core_mode = cpsr & 0x1f;
  901. if (armv4_5_mode_to_number(armv4_5->core_mode) == -1)
  902. {
  903. target->state = TARGET_UNKNOWN;
  904. LOG_ERROR("cpsr contains invalid mode value - communication failure");
  905. return ERROR_TARGET_FAILURE;
  906. }
  907. LOG_DEBUG("target entered debug state in %s mode", armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)]);
  908. if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
  909. {
  910. LOG_DEBUG("thumb state, applying fixups");
  911. context[0] = r0_thumb;
  912. context[15] = pc_thumb;
  913. } else if (armv4_5->core_state == ARMV4_5_STATE_ARM)
  914. {
  915. /* adjust value stored by STM */
  916. context[15] -= 3 * 4;
  917. }
  918. if ((target->debug_reason == DBG_REASON_BREAKPOINT)
  919. || (target->debug_reason == DBG_REASON_SINGLESTEP)
  920. || (target->debug_reason == DBG_REASON_WATCHPOINT)
  921. || (target->debug_reason == DBG_REASON_WPTANDBKPT)
  922. || ((target->debug_reason == DBG_REASON_DBGRQ) && (arm7_9->use_dbgrq == 0)))
  923. context[15] -= 3 * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
  924. else if (target->debug_reason == DBG_REASON_DBGRQ)
  925. context[15] -= arm7_9->dbgreq_adjust_pc * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
  926. else
  927. {
  928. LOG_ERROR("unknown debug reason: %i", target->debug_reason);
  929. }
  930. for (i=0; i<=15; i++)
  931. {
  932. LOG_DEBUG("r%i: 0x%8.8x", i, context[i]);
  933. buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, context[i]);
  934. ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 0;
  935. ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
  936. }
  937. LOG_DEBUG("entered debug state at PC 0x%x", context[15]);
  938. /* exceptions other than USR & SYS have a saved program status register */
  939. if ((armv4_5_mode_to_number(armv4_5->core_mode) != ARMV4_5_MODE_USR) && (armv4_5_mode_to_number(armv4_5->core_mode) != ARMV4_5_MODE_SYS))
  940. {
  941. u32 spsr;
  942. arm7_9->read_xpsr(target, &spsr, 1);
  943. jtag_execute_queue();
  944. buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).value, 0, 32, spsr);
  945. ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).dirty = 0;
  946. ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).valid = 1;
  947. }
  948. /* r0 and r15 (pc) have to be restored later */
  949. ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).valid;
  950. ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).valid;
  951. if ((retval = jtag_execute_queue()) != ERROR_OK)
  952. return retval;
  953. if (arm7_9->post_debug_entry)
  954. arm7_9->post_debug_entry(target);
  955. return ERROR_OK;
  956. }
  957. int arm7_9_full_context(target_t *target)
  958. {
  959. int i;
  960. int retval;
  961. armv4_5_common_t *armv4_5 = target->arch_info;
  962. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  963. LOG_DEBUG("-");
  964. if (target->state != TARGET_HALTED)
  965. {
  966. LOG_WARNING("target not halted");
  967. return ERROR_TARGET_NOT_HALTED;
  968. }
  969. /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
  970. * SYS shares registers with User, so we don't touch SYS
  971. */
  972. for(i = 0; i < 6; i++)
  973. {
  974. u32 mask = 0;
  975. u32* reg_p[16];
  976. int j;
  977. int valid = 1;
  978. /* check if there are invalid registers in the current mode
  979. */
  980. for (j = 0; j <= 16; j++)
  981. {
  982. if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
  983. valid = 0;
  984. }
  985. if (!valid)
  986. {
  987. u32 tmp_cpsr;
  988. /* change processor mode (and mask T bit) */
  989. tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
  990. tmp_cpsr |= armv4_5_number_to_mode(i);
  991. tmp_cpsr &= ~0x20;
  992. arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
  993. for (j = 0; j < 15; j++)
  994. {
  995. if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
  996. {
  997. reg_p[j] = (u32*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).value;
  998. mask |= 1 << j;
  999. ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid = 1;
  1000. ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).dirty = 0;
  1001. }
  1002. }
  1003. /* if only the PSR is invalid, mask is all zeroes */
  1004. if (mask)
  1005. arm7_9->read_core_regs(target, mask, reg_p);
  1006. /* check if the PSR has to be read */
  1007. if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid == 0)
  1008. {
  1009. arm7_9->read_xpsr(target, (u32*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).value, 1);
  1010. ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid = 1;
  1011. ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).dirty = 0;
  1012. }
  1013. }
  1014. }
  1015. /* restore processor mode (mask T bit) */
  1016. arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
  1017. if ((retval = jtag_execute_queue()) != ERROR_OK)
  1018. {
  1019. return retval;
  1020. }
  1021. return ERROR_OK;
  1022. }
  1023. int arm7_9_restore_context(target_t *target)
  1024. {
  1025. armv4_5_common_t *armv4_5 = target->arch_info;
  1026. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  1027. reg_t *reg;
  1028. armv4_5_core_reg_t *reg_arch_info;
  1029. enum armv4_5_mode current_mode = armv4_5->core_mode;
  1030. int i, j;
  1031. int dirty;
  1032. int mode_change;
  1033. LOG_DEBUG("-");
  1034. if (target->state != TARGET_HALTED)
  1035. {
  1036. LOG_WARNING("target not halted");
  1037. return ERROR_TARGET_NOT_HALTED;
  1038. }
  1039. if (arm7_9->pre_restore_context)
  1040. arm7_9->pre_restore_context(target);
  1041. /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
  1042. * SYS shares registers with User, so we don't touch SYS
  1043. */
  1044. for (i = 0; i < 6; i++)
  1045. {
  1046. LOG_DEBUG("examining %s mode", armv4_5_mode_strings[i]);
  1047. dirty = 0;
  1048. mode_change = 0;
  1049. /* check if there are dirty registers in the current mode
  1050. */
  1051. for (j = 0; j <= 16; j++)
  1052. {
  1053. reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j);
  1054. reg_arch_info = reg->arch_info;
  1055. if (reg->dirty == 1)
  1056. {
  1057. if (reg->valid == 1)
  1058. {
  1059. dirty = 1;
  1060. LOG_DEBUG("examining dirty reg: %s", reg->name);
  1061. if ((reg_arch_info->mode != ARMV4_5_MODE_ANY)
  1062. && (reg_arch_info->mode != current_mode)
  1063. && !((reg_arch_info->mode == ARMV4_5_MODE_USR) && (armv4_5->core_mode == ARMV4_5_MODE_SYS))
  1064. && !((reg_arch_info->mode == ARMV4_5_MODE_SYS) && (armv4_5->core_mode == ARMV4_5_MODE_USR)))
  1065. {
  1066. mode_change = 1;
  1067. LOG_DEBUG("require mode change");
  1068. }
  1069. }
  1070. else
  1071. {
  1072. LOG_ERROR("BUG: dirty register '%s', but no valid data", reg->name);
  1073. }
  1074. }
  1075. }
  1076. if (dirty)
  1077. {
  1078. u32 mask = 0x0;
  1079. int num_regs = 0;
  1080. u32 regs[16];
  1081. if (mode_change)
  1082. {
  1083. u32 tmp_cpsr;
  1084. /* change processor mode (mask T bit) */
  1085. tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
  1086. tmp_cpsr |= armv4_5_number_to_mode(i);
  1087. tmp_cpsr &= ~0x20;
  1088. arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
  1089. current_mode = armv4_5_number_to_mode(i);
  1090. }
  1091. for (j = 0; j <= 14; j++)
  1092. {
  1093. reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j);
  1094. reg_arch_info = reg->arch_info;
  1095. if (reg->dirty == 1)
  1096. {
  1097. regs[j] = buf_get_u32(reg->value, 0, 32);
  1098. mask |= 1 << j;
  1099. num_regs++;
  1100. reg->dirty = 0;
  1101. reg->valid = 1;
  1102. LOG_DEBUG("writing register %i of mode %s with value 0x%8.8x", j, armv4_5_mode_strings[i], regs[j]);
  1103. }
  1104. }
  1105. if (mask)
  1106. {
  1107. arm7_9->write_core_regs(target, mask, regs);
  1108. }
  1109. reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16);
  1110. reg_arch_info = reg->arch_info;
  1111. if ((reg->dirty) && (reg_arch_info->mode != ARMV4_5_MODE_ANY))
  1112. {
  1113. LOG_DEBUG("writing SPSR of mode %i with value 0x%8.8x", i, buf_get_u32(reg->value, 0, 32));
  1114. arm7_9->write_xpsr(target, buf_get_u32(reg->value, 0, 32), 1);
  1115. }
  1116. }
  1117. }
  1118. if ((armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty == 0) && (armv4_5->core_mode != current_mode))
  1119. {
  1120. /* restore processor mode (mask T bit) */
  1121. u32 tmp_cpsr;
  1122. tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
  1123. tmp_cpsr |= armv4_5_number_to_mode(i);
  1124. tmp_cpsr &= ~0x20;
  1125. LOG_DEBUG("writing lower 8 bit of cpsr with value 0x%2.2x", tmp_cpsr);
  1126. arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
  1127. }
  1128. else if (armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty == 1)
  1129. {
  1130. /* CPSR has been changed, full restore necessary (mask T bit) */
  1131. LOG_DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
  1132. arm7_9->write_xpsr(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32) & ~0x20, 0);
  1133. armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 0;
  1134. armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
  1135. }
  1136. /* restore PC */
  1137. LOG_DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
  1138. arm7_9->write_pc(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
  1139. armv4_5->core_cache->reg_list[15].dirty = 0;
  1140. if (arm7_9->post_restore_context)
  1141. arm7_9->post_restore_context(target);
  1142. return ERROR_OK;
  1143. }
  1144. int arm7_9_restart_core(struct target_s *target)
  1145. {
  1146. armv4_5_common_t *armv4_5 = target->arch_info;
  1147. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  1148. arm_jtag_t *jtag_info = &arm7_9->jtag_info;
  1149. /* set RESTART instruction */
  1150. jtag_add_end_state(TAP_RTI);
  1151. arm_jtag_set_instr(jtag_info, 0x4, NULL);
  1152. jtag_add_runtest(1, TAP_RTI);
  1153. return jtag_execute_queue();
  1154. }
  1155. void arm7_9_enable_watchpoints(struct target_s *target)
  1156. {
  1157. watchpoint_t *watchpoint = target->watchpoints;
  1158. while (watchpoint)
  1159. {
  1160. if (watchpoint->set == 0)
  1161. arm7_9_set_watchpoint(target, watchpoint);
  1162. watchpoint = watchpoint->next;
  1163. }
  1164. }
  1165. void arm7_9_enable_breakpoints(struct target_s *target)
  1166. {
  1167. breakpoint_t *breakpoint = target->breakpoints;
  1168. /* set any pending breakpoints */
  1169. while (breakpoint)
  1170. {
  1171. if (breakpoint->set == 0)
  1172. arm7_9_set_breakpoint(target, breakpoint);
  1173. breakpoint = breakpoint->next;
  1174. }
  1175. }
  1176. void arm7_9_disable_bkpts_and_wpts(struct target_s *target)
  1177. {
  1178. breakpoint_t *breakpoint = target->breakpoints;
  1179. watchpoint_t *watchpoint = target->watchpoints;
  1180. /* set any pending breakpoints */
  1181. while (breakpoint)
  1182. {
  1183. if (breakpoint->set != 0)
  1184. arm7_9_unset_breakpoint(target, breakpoint);
  1185. breakpoint = breakpoint->next;
  1186. }
  1187. while (watchpoint)
  1188. {
  1189. if (watchpoint->set != 0)
  1190. arm7_9_unset_watchpoint(target, watchpoint);
  1191. watchpoint = watchpoint->next;
  1192. }
  1193. }
  1194. int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
  1195. {
  1196. armv4_5_common_t *armv4_5 = target->arch_info;
  1197. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  1198. breakpoint_t *breakpoint = target->breakpoints;
  1199. reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
  1200. int err;
  1201. LOG_DEBUG("-");
  1202. if (target->state != TARGET_HALTED)
  1203. {
  1204. LOG_WARNING("target not halted");
  1205. return ERROR_TARGET_NOT_HALTED;
  1206. }
  1207. if (!debug_execution)
  1208. {
  1209. target_free_all_working_areas(target);
  1210. }
  1211. /* current = 1: continue on current pc, otherwise continue at <address> */
  1212. if (!current)
  1213. buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
  1214. /* the front-end may request us not to handle breakpoints */
  1215. if (handle_breakpoints)
  1216. {
  1217. if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
  1218. {
  1219. LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address);
  1220. arm7_9_unset_breakpoint(target, breakpoint);
  1221. LOG_DEBUG("enable single-step");
  1222. arm7_9->enable_single_step(target);
  1223. target->debug_reason = DBG_REASON_SINGLESTEP;
  1224. arm7_9_restore_context(target);
  1225. if (armv4_5->core_state == ARMV4_5_STATE_ARM)
  1226. arm7_9->branch_resume(target);
  1227. else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
  1228. {
  1229. arm7_9->branch_resume_thumb(target);
  1230. }
  1231. else
  1232. {
  1233. LOG_ERROR("unhandled core state");
  1234. return ERROR_FAIL;
  1235. }
  1236. buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
  1237. embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
  1238. err = arm7_9_execute_sys_speed(target);
  1239. LOG_DEBUG("disable single-step");
  1240. arm7_9->disable_single_step(target);
  1241. if (err != ERROR_OK)
  1242. {
  1243. arm7_9_set_breakpoint(target, breakpoint);
  1244. target->state = TARGET_UNKNOWN;
  1245. return err;
  1246. }
  1247. arm7_9_debug_entry(target);
  1248. LOG_DEBUG("new PC after step: 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
  1249. LOG_DEBUG("set breakpoint at 0x%8.8x", breakpoint->address);
  1250. arm7_9_set_breakpoint(target, breakpoint);
  1251. }
  1252. }
  1253. /* enable any pending breakpoints and watchpoints */
  1254. arm7_9_enable_breakpoints(target);
  1255. arm7_9_enable_watchpoints(target);
  1256. arm7_9_restore_context(target);
  1257. if (armv4_5->core_state == ARMV4_5_STATE_ARM)
  1258. {
  1259. arm7_9->branch_resume(target);
  1260. }
  1261. else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
  1262. {
  1263. arm7_9->branch_resume_thumb(target);
  1264. }
  1265. else
  1266. {
  1267. LOG_ERROR("unhandled core state");
  1268. return ERROR_FAIL;
  1269. }
  1270. /* deassert DBGACK and INTDIS */
  1271. buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
  1272. /* INTDIS only when we really resume, not during debug execution */
  1273. if (!debug_execution)
  1274. buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 0);
  1275. embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
  1276. arm7_9_restart_core(target);
  1277. target->debug_reason = DBG_REASON_NOTHALTED;
  1278. if (!debug_execution)
  1279. {
  1280. /* registers are now invalid */
  1281. armv4_5_invalidate_core_regs(target);
  1282. target->state = TARGET_RUNNING;
  1283. target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
  1284. }
  1285. else
  1286. {
  1287. target->state = TARGET_DEBUG_RUNNING;
  1288. target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
  1289. }
  1290. LOG_DEBUG("target resumed");
  1291. return ERROR_OK;
  1292. }
  1293. void arm7_9_enable_eice_step(target_t *target)
  1294. {
  1295. armv4_5_common_t *armv4_5 = target->arch_info;
  1296. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  1297. /* setup an inverse breakpoint on the current PC
  1298. * - comparator 1 matches the current address
  1299. * - rangeout from comparator 1 is connected to comparator 0 rangein
  1300. * - comparator 0 matches any address, as long as rangein is low */
  1301. embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
  1302. embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
  1303. embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x100);
  1304. embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0x77);
  1305. embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
  1306. embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0);
  1307. embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffff);
  1308. embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
  1309. embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], 0xf7);
  1310. }
  1311. void arm7_9_disable_eice_step(target_t *target)
  1312. {
  1313. armv4_5_common_t *armv4_5 = target->arch_info;
  1314. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  1315. embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
  1316. embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
  1317. embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
  1318. embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
  1319. embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE]);
  1320. embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK]);
  1321. embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK]);
  1322. embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK]);
  1323. embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE]);
  1324. }
  1325. int arm7_9_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
  1326. {
  1327. armv4_5_common_t *armv4_5 = target->arch_info;
  1328. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  1329. breakpoint_t *breakpoint = NULL;
  1330. int err;
  1331. if (target->state != TARGET_HALTED)
  1332. {
  1333. LOG_WARNING("target not halted");
  1334. return ERROR_TARGET_NOT_HALTED;
  1335. }
  1336. /* current = 1: continue on current pc, otherwise continue at <address> */
  1337. if (!current)
  1338. buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
  1339. /* the front-end may request us not to handle breakpoints */
  1340. if (handle_breakpoints)
  1341. if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
  1342. arm7_9_unset_breakpoint(target, breakpoint);
  1343. target->debug_reason = DBG_REASON_SINGLESTEP;
  1344. arm7_9_restore_context(target);
  1345. arm7_9->enable_single_step(target);
  1346. if (armv4_5->core_state == ARMV4_5_STATE_ARM)
  1347. {
  1348. arm7_9->branch_resume(target);
  1349. }
  1350. else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
  1351. {
  1352. arm7_9->branch_resume_thumb(target);
  1353. }
  1354. else
  1355. {
  1356. LOG_ERROR("unhandled core state");
  1357. return ERROR_FAIL;
  1358. }
  1359. target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
  1360. err = arm7_9_execute_sys_speed(target);
  1361. arm7_9->disable_single_step(target);
  1362. /* registers are now invalid */
  1363. armv4_5_invalidate_core_regs(target);
  1364. if (err != ERROR_OK)
  1365. {
  1366. target->state = TARGET_UNKNOWN;
  1367. } else {
  1368. arm7_9_debug_entry(target);
  1369. target_call_event_callbacks(target, TARGET_EVENT_HALTED);
  1370. LOG_DEBUG("target stepped");
  1371. }
  1372. if (breakpoint)
  1373. arm7_9_set_breakpoint(target, breakpoint);
  1374. return err;
  1375. }
  1376. int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode)
  1377. {
  1378. u32* reg_p[16];
  1379. u32 value;
  1380. int retval;
  1381. armv4_5_common_t *armv4_5 = target->arch_info;
  1382. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  1383. enum armv4_5_mode reg_mode = ((armv4_5_core_reg_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
  1384. if ((num < 0) || (num > 16))
  1385. return ERROR_INVALID_ARGUMENTS;
  1386. if ((mode != ARMV4_5_MODE_ANY)
  1387. && (mode != armv4_5->core_mode)
  1388. && (reg_mode != ARMV4_5_MODE_ANY))
  1389. {
  1390. u32 tmp_cpsr;
  1391. /* change processor mode (mask T bit) */
  1392. tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
  1393. tmp_cpsr |= mode;
  1394. tmp_cpsr &= ~0x20;
  1395. arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
  1396. }
  1397. if ((num >= 0) && (num <= 15))
  1398. {
  1399. /* read a normal core register */
  1400. reg_p[num] = &value;
  1401. arm7_9->read_core_regs(target, 1 << num, reg_p);
  1402. }
  1403. else
  1404. {
  1405. /* read a program status register
  1406. * if the register mode is MODE_ANY, we read the cpsr, otherwise a spsr
  1407. */
  1408. armv4_5_core_reg_t *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;
  1409. int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1;
  1410. arm7_9->read_xpsr(target, &value, spsr);
  1411. }
  1412. if ((retval = jtag_execute_queue()) != ERROR_OK)
  1413. {
  1414. return retval;
  1415. }
  1416. ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
  1417. ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
  1418. buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).value, 0, 32, value);
  1419. if ((mode != ARMV4_5_MODE_ANY)
  1420. && (mode != armv4_5->core_mode)
  1421. && (reg_mode != ARMV4_5_MODE_ANY)) {
  1422. /* restore processor mode (mask T bit) */
  1423. arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
  1424. }
  1425. return ERROR_OK;
  1426. }
  1427. int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mode, u32 value)
  1428. {
  1429. u32 reg[16];
  1430. armv4_5_common_t *armv4_5 = target->arch_info;
  1431. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  1432. enum armv4_5_mode reg_mode = ((armv4_5_core_reg_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
  1433. if ((num < 0) || (num > 16))
  1434. return ERROR_INVALID_ARGUMENTS;
  1435. if ((mode != ARMV4_5_MODE_ANY)
  1436. && (mode != armv4_5->core_mode)
  1437. && (reg_mode != ARMV4_5_MODE_ANY)) {
  1438. u32 tmp_cpsr;
  1439. /* change processor mode (mask T bit) */
  1440. tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
  1441. tmp_cpsr |= mode;
  1442. tmp_cpsr &= ~0x20;
  1443. arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
  1444. }
  1445. if ((num >= 0) && (num <= 15))
  1446. {
  1447. /* write a normal core register */
  1448. reg[num] = value;
  1449. arm7_9->write_core_regs(target, 1 << num, reg);
  1450. }
  1451. else
  1452. {
  1453. /* write a program status register
  1454. * if the register mode is MODE_ANY, we write the cpsr, otherwise a spsr
  1455. */
  1456. armv4_5_core_reg_t *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;
  1457. int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1;
  1458. /* if we're writing the CPSR, mask the T bit */
  1459. if (!spsr)
  1460. value &= ~0x20;
  1461. arm7_9->write_xpsr(target, value, spsr);
  1462. }
  1463. ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
  1464. ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
  1465. if ((mode != ARMV4_5_MODE_ANY)
  1466. && (mode != armv4_5->core_mode)
  1467. && (reg_mode != ARMV4_5_MODE_ANY)) {
  1468. /* restore processor mode (mask T bit) */
  1469. arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
  1470. }
  1471. return jtag_execute_queue();
  1472. }
  1473. int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
  1474. {
  1475. armv4_5_common_t *armv4_5 = target->arch_info;
  1476. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  1477. u32 reg[16];
  1478. int num_accesses = 0;
  1479. int thisrun_accesses;
  1480. int i;
  1481. u32 cpsr;
  1482. int retval;
  1483. int last_reg = 0;
  1484. LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
  1485. if (target->state != TARGET_HALTED)
  1486. {
  1487. LOG_WARNING("target not halted");
  1488. return ERROR_TARGET_NOT_HALTED;
  1489. }
  1490. /* sanitize arguments */
  1491. if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
  1492. return ERROR_INVALID_ARGUMENTS;
  1493. if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
  1494. return ERROR_TARGET_UNALIGNED_ACCESS;
  1495. /* load the base register with the address of the first word */
  1496. reg[0] = address;
  1497. arm7_9->write_core_regs(target, 0x1, reg);
  1498. switch (size)
  1499. {
  1500. case 4:
  1501. while (num_accesses < count)
  1502. {
  1503. u32 reg_list;
  1504. thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
  1505. reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
  1506. if (last_reg <= thisrun_accesses)
  1507. last_reg = thisrun_accesses;
  1508. arm7_9->load_word_regs(target, reg_list);
  1509. /* fast memory reads are only safe when the target is running
  1510. * from a sufficiently high clock (32 kHz is usually too slow)
  1511. */
  1512. if (arm7_9->fast_memory_access)
  1513. arm7_9_execute_fast_sys_speed(target);
  1514. else
  1515. arm7_9_execute_sys_speed(target);
  1516. arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 4);
  1517. /* advance buffer, count number of accesses */
  1518. buffer += thisrun_accesses * 4;
  1519. num_accesses += thisrun_accesses;
  1520. }
  1521. break;
  1522. case 2:
  1523. while (num_accesses < count)
  1524. {
  1525. u32 reg_list;
  1526. thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
  1527. reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
  1528. for (i = 1; i <= thisrun_accesses; i++)
  1529. {
  1530. if (i > last_reg)
  1531. last_reg = i;
  1532. arm7_9->load_hword_reg(target, i);
  1533. /* fast memory reads are only safe when the target is running
  1534. * from a sufficiently high clock (32 kHz is usually too slow)
  1535. */
  1536. if (arm7_9->fast_memory_access)
  1537. arm7_9_execute_fast_sys_speed(target);
  1538. else
  1539. arm7_9_execute_sys_speed(target);
  1540. }
  1541. arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 2);
  1542. /* advance buffer, count number of accesses */
  1543. buffer += thisrun_accesses * 2;
  1544. num_accesses += thisrun_accesses;
  1545. }
  1546. break;
  1547. case 1:
  1548. while (num_accesses < count)
  1549. {
  1550. u32 reg_list;
  1551. thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
  1552. reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
  1553. for (i = 1; i <= thisrun_accesses; i++)
  1554. {
  1555. if (i > last_reg)
  1556. last_reg = i;
  1557. arm7_9->load_byte_reg(target, i);
  1558. /* fast memory reads are only safe when the target is running
  1559. * from a sufficiently high clock (32 kHz is usually too slow)
  1560. */
  1561. if (arm7_9->fast_memory_access)
  1562. arm7_9_execute_fast_sys_speed(target);
  1563. else
  1564. arm7_9_execute_sys_speed(target);
  1565. }
  1566. arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 1);
  1567. /* advance buffer, count number of accesses */
  1568. buffer += thisrun_accesses * 1;
  1569. num_accesses += thisrun_accesses;
  1570. }
  1571. break;
  1572. default:
  1573. LOG_ERROR("BUG: we shouldn't get here");
  1574. exit(-1);
  1575. break;
  1576. }
  1577. for (i=0; i<=last_reg; i++)
  1578. ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid;
  1579. arm7_9->read_xpsr(target, &cpsr, 0);
  1580. if ((retval = jtag_execute_queue()) != ERROR_OK)
  1581. {
  1582. LOG_ERROR("JTAG error while reading cpsr");
  1583. return ERROR_TARGET_DATA_ABORT;
  1584. }
  1585. if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
  1586. {
  1587. LOG_WARNING("memory read caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address, size, count);
  1588. arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
  1589. return ERROR_TARGET_DATA_ABORT;
  1590. }
  1591. return ERROR_OK;
  1592. }
  1593. int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
  1594. {
  1595. armv4_5_common_t *armv4_5 = target->arch_info;
  1596. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  1597. reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
  1598. u32 reg[16];
  1599. int num_accesses = 0;
  1600. int thisrun_accesses;
  1601. int i;
  1602. u32 cpsr;
  1603. int retval;
  1604. int last_reg = 0;
  1605. #ifdef _DEBUG_ARM7_9_
  1606. LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
  1607. #endif
  1608. if (target->state != TARGET_HALTED)
  1609. {
  1610. LOG_WARNING("target not halted");
  1611. return ERROR_TARGET_NOT_HALTED;
  1612. }
  1613. /* sanitize arguments */
  1614. if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
  1615. return ERROR_INVALID_ARGUMENTS;
  1616. if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
  1617. return ERROR_TARGET_UNALIGNED_ACCESS;
  1618. /* load the base register with the address of the first word */
  1619. reg[0] = address;
  1620. arm7_9->write_core_regs(target, 0x1, reg);
  1621. /* Clear DBGACK, to make sure memory fetches work as expected */
  1622. buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
  1623. embeddedice_store_reg(dbg_ctrl);
  1624. switch (size)
  1625. {
  1626. case 4:
  1627. while (num_accesses < count)
  1628. {
  1629. u32 reg_list;
  1630. thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
  1631. reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
  1632. for (i = 1; i <= thisrun_accesses; i++)
  1633. {
  1634. if (i > last_reg)
  1635. last_reg = i;
  1636. reg[i] = target_buffer_get_u32(target, buffer);
  1637. buffer += 4;
  1638. }
  1639. arm7_9->write_core_regs(target, reg_list, reg);
  1640. arm7_9->store_word_regs(target, reg_list);
  1641. /* fast memory writes are only safe when the target is running
  1642. * from a sufficiently high clock (32 kHz is usually too slow)
  1643. */
  1644. if (arm7_9->fast_memory_access)
  1645. arm7_9_execute_fast_sys_speed(target);
  1646. else
  1647. arm7_9_execute_sys_speed(target);
  1648. num_accesses += thisrun_accesses;
  1649. }
  1650. break;
  1651. case 2:
  1652. while (num_accesses < count)
  1653. {
  1654. u32 reg_list;
  1655. thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
  1656. reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
  1657. for (i = 1; i <= thisrun_accesses; i++)
  1658. {
  1659. if (i > last_reg)
  1660. last_reg = i;
  1661. reg[i] = target_buffer_get_u16(target, buffer) & 0xffff;
  1662. buffer += 2;
  1663. }
  1664. arm7_9->write_core_regs(target, reg_list, reg);
  1665. for (i = 1; i <= thisrun_accesses; i++)
  1666. {
  1667. arm7_9->store_hword_reg(target, i);
  1668. /* fast memory writes are only safe when the target is running
  1669. * from a sufficiently high clock (32 kHz is usually too slow)
  1670. */
  1671. if (arm7_9->fast_memory_access)
  1672. arm7_9_execute_fast_sys_speed(target);
  1673. else
  1674. arm7_9_execute_sys_speed(target);
  1675. }
  1676. num_accesses += thisrun_accesses;
  1677. }
  1678. break;
  1679. case 1:
  1680. while (num_accesses < count)
  1681. {
  1682. u32 reg_list;
  1683. thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
  1684. reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
  1685. for (i = 1; i <= thisrun_accesses; i++)
  1686. {
  1687. if (i > last_reg)
  1688. last_reg = i;
  1689. reg[i] = *buffer++ & 0xff;
  1690. }
  1691. arm7_9->write_core_regs(target, reg_list, reg);
  1692. for (i = 1; i <= thisrun_accesses; i++)
  1693. {
  1694. arm7_9->store_byte_reg(target, i);
  1695. /* fast memory writes are only safe when the target is running
  1696. * from a sufficiently high clock (32 kHz is usually too slow)
  1697. */
  1698. if (arm7_9->fast_memory_access)
  1699. arm7_9_execute_fast_sys_speed(target);
  1700. else
  1701. arm7_9_execute_sys_speed(target);
  1702. }
  1703. num_accesses += thisrun_accesses;
  1704. }
  1705. break;
  1706. default:
  1707. LOG_ERROR("BUG: we shouldn't get here");
  1708. exit(-1);
  1709. break;
  1710. }
  1711. /* Re-Set DBGACK */
  1712. buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
  1713. embeddedice_store_reg(dbg_ctrl);
  1714. for (i=0; i<=last_reg; i++)
  1715. ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid;
  1716. arm7_9->read_xpsr(target, &cpsr, 0);
  1717. if ((retval = jtag_execute_queue()) != ERROR_OK)
  1718. {
  1719. LOG_ERROR("JTAG error while reading cpsr");
  1720. return ERROR_TARGET_DATA_ABORT;
  1721. }
  1722. if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
  1723. {
  1724. LOG_WARNING("memory write caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address, size, count);
  1725. arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
  1726. return ERROR_TARGET_DATA_ABORT;
  1727. }
  1728. return ERROR_OK;
  1729. }
  1730. int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer)
  1731. {
  1732. armv4_5_common_t *armv4_5 = target->arch_info;
  1733. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  1734. enum armv4_5_state core_state = armv4_5->core_state;
  1735. u32 r0 = buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32);
  1736. u32 r1 = buf_get_u32(armv4_5->core_cache->reg_list[1].value, 0, 32);
  1737. u32 pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
  1738. int i;
  1739. u32 dcc_code[] =
  1740. {
  1741. /* MRC TST BNE MRC STR B */
  1742. 0xee101e10, 0xe3110001, 0x0afffffc, 0xee111e10, 0xe4801004, 0xeafffff9
  1743. };
  1744. if (!arm7_9->dcc_downloads)
  1745. return target->type->write_memory(target, address, 4, count, buffer);
  1746. /* regrab previously allocated working_area, or allocate a new one */
  1747. if (!arm7_9->dcc_working_area)
  1748. {
  1749. u8 dcc_code_buf[6 * 4];
  1750. /* make sure we have a working area */
  1751. if (target_alloc_working_area(target, 24, &arm7_9->dcc_working_area) != ERROR_OK)
  1752. {
  1753. LOG_INFO("no working area available, falling back to memory writes");
  1754. return target->type->write_memory(target, address, 4, count, buffer);
  1755. }
  1756. /* copy target instructions to target endianness */
  1757. for (i = 0; i < 6; i++)
  1758. {
  1759. target_buffer_set_u32(target, dcc_code_buf + i*4, dcc_code[i]);
  1760. }
  1761. /* write DCC code to working area */
  1762. target->type->write_memory(target, arm7_9->dcc_working_area->address, 4, 6, dcc_code_buf);
  1763. }
  1764. buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, address);
  1765. armv4_5->core_cache->reg_list[0].valid = 1;
  1766. armv4_5->core_cache->reg_list[0].dirty = 1;
  1767. armv4_5->core_state = ARMV4_5_STATE_ARM;
  1768. arm7_9_resume(target, 0, arm7_9->dcc_working_area->address, 1, 1);
  1769. int little=target->endianness==TARGET_LITTLE_ENDIAN;
  1770. if (count>2)
  1771. {
  1772. /* Handle first & last using standard embeddedice_write_reg and the middle ones w/the
  1773. core function repeated.
  1774. */
  1775. embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
  1776. buffer+=4;
  1777. embeddedice_reg_t *ice_reg = arm7_9->eice_cache->reg_list[EICE_COMMS_DATA].arch_info;
  1778. u8 reg_addr = ice_reg->addr & 0x1f;
  1779. int chain_pos = ice_reg->jtag_info->chain_pos;
  1780. /* we want the compiler to duplicate the code, which it does not
  1781. * do automatically.
  1782. */
  1783. if (little)
  1784. {
  1785. for (i = 1; i < count - 1; i++)
  1786. {
  1787. embeddedice_write_reg_inner(chain_pos, reg_addr, fast_target_buffer_get_u32(buffer, little));
  1788. buffer += 4;
  1789. }
  1790. } else
  1791. {
  1792. for (i = 1; i < count - 1; i++)
  1793. {
  1794. embeddedice_write_reg_inner(chain_pos, reg_addr, fast_target_buffer_get_u32(buffer, little));
  1795. buffer += 4;
  1796. }
  1797. }
  1798. embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
  1799. } else
  1800. {
  1801. for (i = 0; i < count; i++)
  1802. {
  1803. embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
  1804. buffer += 4;
  1805. }
  1806. }
  1807. target_halt(target);
  1808. for (i=0; i<100; i++)
  1809. {
  1810. target_poll(target);
  1811. if (target->state == TARGET_HALTED)
  1812. break;
  1813. usleep(1000); /* sleep 1ms */
  1814. }
  1815. if (i == 100)
  1816. {
  1817. LOG_ERROR("bulk write timed out, target not halted");
  1818. return ERROR_TARGET_TIMEOUT;
  1819. }
  1820. /* restore target state */
  1821. buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, r0);
  1822. armv4_5->core_cache->reg_list[0].valid = 1;
  1823. armv4_5->core_cache->reg_list[0].dirty = 1;
  1824. buf_set_u32(armv4_5->core_cache->reg_list[1].value, 0, 32, r1);
  1825. armv4_5->core_cache->reg_list[1].valid = 1;
  1826. armv4_5->core_cache->reg_list[1].dirty = 1;
  1827. buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, pc);
  1828. armv4_5->core_cache->reg_list[15].valid = 1;
  1829. armv4_5->core_cache->reg_list[15].dirty = 1;
  1830. armv4_5->core_state = core_state;
  1831. return ERROR_OK;
  1832. }
  1833. int arm7_9_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum)
  1834. {
  1835. working_area_t *crc_algorithm;
  1836. armv4_5_algorithm_t armv4_5_info;
  1837. reg_param_t reg_params[2];
  1838. int retval;
  1839. u32 arm7_9_crc_code[] = {
  1840. 0xE1A02000, /* mov r2, r0 */
  1841. 0xE3E00000, /* mov r0, #0xffffffff */
  1842. 0xE1A03001, /* mov r3, r1 */
  1843. 0xE3A04000, /* mov r4, #0 */
  1844. 0xEA00000B, /* b ncomp */
  1845. /* nbyte: */
  1846. 0xE7D21004, /* ldrb r1, [r2, r4] */
  1847. 0xE59F7030, /* ldr r7, CRC32XOR */
  1848. 0xE0200C01, /* eor r0, r0, r1, asl 24 */
  1849. 0xE3A05000, /* mov r5, #0 */
  1850. /* loop: */
  1851. 0xE3500000, /* cmp r0, #0 */
  1852. 0xE1A06080, /* mov r6, r0, asl #1 */
  1853. 0xE2855001, /* add r5, r5, #1 */
  1854. 0xE1A00006, /* mov r0, r6 */
  1855. 0xB0260007, /* eorlt r0, r6, r7 */
  1856. 0xE3550008, /* cmp r5, #8 */
  1857. 0x1AFFFFF8, /* bne loop */
  1858. 0xE2844001, /* add r4, r4, #1 */
  1859. /* ncomp: */
  1860. 0xE1540003, /* cmp r4, r3 */
  1861. 0x1AFFFFF1, /* bne nbyte */
  1862. /* end: */
  1863. 0xEAFFFFFE, /* b end */
  1864. 0x04C11DB7 /* CRC32XOR: .word 0x04C11DB7 */
  1865. };
  1866. int i;
  1867. if (target_alloc_working_area(target, sizeof(arm7_9_crc_code), &crc_algorithm) != ERROR_OK)
  1868. {
  1869. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  1870. }
  1871. /* convert flash writing code into a buffer in target endianness */
  1872. for (i = 0; i < (sizeof(arm7_9_crc_code)/sizeof(u32)); i++)
  1873. target_write_u32(target, crc_algorithm->address + i*sizeof(u32), arm7_9_crc_code[i]);
  1874. armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
  1875. armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
  1876. armv4_5_info.core_state = ARMV4_5_STATE_ARM;
  1877. init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT);
  1878. init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
  1879. buf_set_u32(reg_params[0].value, 0, 32, address);
  1880. buf_set_u32(reg_params[1].value, 0, 32, count);
  1881. if ((retval = target->type->run_algorithm(target, 0, NULL, 2, reg_params,
  1882. crc_algorithm->address, crc_algorithm->address + (sizeof(arm7_9_crc_code) - 8), 20000, &armv4_5_info)) != ERROR_OK)
  1883. {
  1884. LOG_ERROR("error executing arm7_9 crc algorithm");
  1885. destroy_reg_param(&reg_params[0]);
  1886. destroy_reg_param(&reg_params[1]);
  1887. target_free_working_area(target, crc_algorithm);
  1888. return retval;
  1889. }
  1890. *checksum = buf_get_u32(reg_params[0].value, 0, 32);
  1891. destroy_reg_param(&reg_params[0]);
  1892. destroy_reg_param(&reg_params[1]);
  1893. target_free_working_area(target, crc_algorithm);
  1894. return ERROR_OK;
  1895. }
  1896. int arm7_9_register_commands(struct command_context_s *cmd_ctx)
  1897. {
  1898. command_t *arm7_9_cmd;
  1899. arm7_9_cmd = register_command(cmd_ctx, NULL, "arm7_9", NULL, COMMAND_ANY, "arm7/9 specific commands");
  1900. register_command(cmd_ctx, arm7_9_cmd, "write_xpsr", handle_arm7_9_write_xpsr_command, COMMAND_EXEC, "write program status register <value> <not cpsr|spsr>");
  1901. register_command(cmd_ctx, arm7_9_cmd, "write_xpsr_im8", handle_arm7_9_write_xpsr_im8_command, COMMAND_EXEC, "write program status register <8bit immediate> <rotate> <not cpsr|spsr>");
  1902. register_command(cmd_ctx, arm7_9_cmd, "write_core_reg", handle_arm7_9_write_core_reg_command, COMMAND_EXEC, "write core register <num> <mode> <value>");
  1903. register_command(cmd_ctx, arm7_9_cmd, "sw_bkpts", handle_arm7_9_sw_bkpts_command, COMMAND_EXEC, "support for software breakpoints <enable|disable>");
  1904. register_command(cmd_ctx, arm7_9_cmd, "force_hw_bkpts", handle_arm7_9_force_hw_bkpts_command, COMMAND_EXEC, "use hardware breakpoints for all breakpoints (disables sw breakpoint support) <enable|disable>");
  1905. register_command(cmd_ctx, arm7_9_cmd, "dbgrq", handle_arm7_9_dbgrq_command,
  1906. COMMAND_ANY, "use EmbeddedICE dbgrq instead of breakpoint for target halt requests <enable|disable>");
  1907. register_command(cmd_ctx, arm7_9_cmd, "fast_writes", handle_arm7_9_fast_memory_access_command,
  1908. COMMAND_ANY, "(deprecated, see: arm7_9 fast_memory_access)");
  1909. register_command(cmd_ctx, arm7_9_cmd, "fast_memory_access", handle_arm7_9_fast_memory_access_command,
  1910. COMMAND_ANY, "use fast memory accesses instead of slower but potentially unsafe slow accesses <enable|disable>");
  1911. register_command(cmd_ctx, arm7_9_cmd, "dcc_downloads", handle_arm7_9_dcc_downloads_command,
  1912. COMMAND_ANY, "use DCC downloads for larger memory writes <enable|disable>");
  1913. armv4_5_register_commands(cmd_ctx);
  1914. etm_register_commands(cmd_ctx);
  1915. return ERROR_OK;
  1916. }
  1917. int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
  1918. {
  1919. u32 value;
  1920. int spsr;
  1921. int retval;
  1922. target_t *target = get_current_target(cmd_ctx);
  1923. armv4_5_common_t *armv4_5;
  1924. arm7_9_common_t *arm7_9;
  1925. if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
  1926. {
  1927. command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
  1928. return ERROR_OK;
  1929. }
  1930. if (target->state != TARGET_HALTED)
  1931. {
  1932. command_print(cmd_ctx, "can't write registers while running");
  1933. return ERROR_OK;
  1934. }
  1935. if (argc < 2)
  1936. {
  1937. command_print(cmd_ctx, "usage: write_xpsr <value> <not cpsr|spsr>");
  1938. return ERROR_OK;
  1939. }
  1940. value = strtoul(args[0], NULL, 0);
  1941. spsr = strtol(args[1], NULL, 0);
  1942. /* if we're writing the CPSR, mask the T bit */
  1943. if (!spsr)
  1944. value &= ~0x20;
  1945. arm7_9->write_xpsr(target, value, spsr);
  1946. if ((retval = jtag_execute_queue()) != ERROR_OK)
  1947. {
  1948. LOG_ERROR("JTAG error while writing to xpsr");
  1949. return retval;
  1950. }
  1951. return ERROR_OK;
  1952. }
  1953. int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
  1954. {
  1955. u32 value;
  1956. int rotate;
  1957. int spsr;
  1958. int retval;
  1959. target_t *target = get_current_target(cmd_ctx);
  1960. armv4_5_common_t *armv4_5;
  1961. arm7_9_common_t *arm7_9;
  1962. if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
  1963. {
  1964. command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
  1965. return ERROR_OK;
  1966. }
  1967. if (target->state != TARGET_HALTED)
  1968. {
  1969. command_print(cmd_ctx, "can't write registers while running");
  1970. return ERROR_OK;
  1971. }
  1972. if (argc < 3)
  1973. {
  1974. command_print(cmd_ctx, "usage: write_xpsr_im8 <im8> <rotate> <not cpsr|spsr>");
  1975. return ERROR_OK;
  1976. }
  1977. value = strtoul(args[0], NULL, 0);
  1978. rotate = strtol(args[1], NULL, 0);
  1979. spsr = strtol(args[2], NULL, 0);
  1980. arm7_9->write_xpsr_im8(target, value, rotate, spsr);
  1981. if ((retval = jtag_execute_queue()) != ERROR_OK)
  1982. {
  1983. LOG_ERROR("JTAG error while writing 8-bit immediate to xpsr");
  1984. return retval;
  1985. }
  1986. return ERROR_OK;
  1987. }
  1988. int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
  1989. {
  1990. u32 value;
  1991. u32 mode;
  1992. int num;
  1993. target_t *target = get_current_target(cmd_ctx);
  1994. armv4_5_common_t *armv4_5;
  1995. arm7_9_common_t *arm7_9;
  1996. if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
  1997. {
  1998. command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
  1999. return ERROR_OK;
  2000. }
  2001. if (target->state != TARGET_HALTED)
  2002. {
  2003. command_print(cmd_ctx, "can't write registers while running");
  2004. return ERROR_OK;
  2005. }
  2006. if (argc < 3)
  2007. {
  2008. command_print(cmd_ctx, "usage: write_core_reg <num> <mode> <value>");
  2009. return ERROR_OK;
  2010. }
  2011. num = strtol(args[0], NULL, 0);
  2012. mode = strtoul(args[1], NULL, 0);
  2013. value = strtoul(args[2], NULL, 0);
  2014. arm7_9_write_core_reg(target, num, mode, value);
  2015. return ERROR_OK;
  2016. }
  2017. int handle_arm7_9_sw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
  2018. {
  2019. target_t *target = get_current_target(cmd_ctx);
  2020. armv4_5_common_t *armv4_5;
  2021. arm7_9_common_t *arm7_9;
  2022. if (target->state != TARGET_HALTED)
  2023. {
  2024. LOG_ERROR("target not halted");
  2025. return ERROR_TARGET_NOT_HALTED;
  2026. }
  2027. if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
  2028. {
  2029. command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
  2030. return ERROR_OK;
  2031. }
  2032. if (argc == 0)
  2033. {
  2034. command_print(cmd_ctx, "software breakpoints %s", (arm7_9->sw_bkpts_enabled) ? "enabled" : "disabled");
  2035. return ERROR_OK;
  2036. }
  2037. if (strcmp("enable", args[0]) == 0)
  2038. {
  2039. if (arm7_9->sw_bkpts_use_wp)
  2040. {
  2041. arm7_9_enable_sw_bkpts(target);
  2042. }
  2043. else
  2044. {
  2045. arm7_9->sw_bkpts_enabled = 1;
  2046. }
  2047. }
  2048. else if (strcmp("disable", args[0]) == 0)
  2049. {
  2050. if (arm7_9->sw_bkpts_use_wp)
  2051. {
  2052. arm7_9_disable_sw_bkpts(target);
  2053. }
  2054. else
  2055. {
  2056. arm7_9->sw_bkpts_enabled = 0;
  2057. }
  2058. }
  2059. else
  2060. {
  2061. command_print(cmd_ctx, "usage: arm7_9 sw_bkpts <enable|disable>");
  2062. }
  2063. command_print(cmd_ctx, "software breakpoints %s", (arm7_9->sw_bkpts_enabled) ? "enabled" : "disabled");
  2064. return ERROR_OK;
  2065. }
  2066. int handle_arm7_9_force_hw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
  2067. {
  2068. target_t *target = get_current_target(cmd_ctx);
  2069. armv4_5_common_t *armv4_5;
  2070. arm7_9_common_t *arm7_9;
  2071. if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
  2072. {
  2073. command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
  2074. return ERROR_OK;
  2075. }
  2076. if ((argc >= 1) && (strcmp("enable", args[0]) == 0))
  2077. {
  2078. arm7_9->force_hw_bkpts = 1;
  2079. if (arm7_9->sw_bkpts_use_wp)
  2080. {
  2081. arm7_9_disable_sw_bkpts(target);
  2082. }
  2083. }
  2084. else if ((argc >= 1) && (strcmp("disable", args[0]) == 0))
  2085. {
  2086. arm7_9->force_hw_bkpts = 0;
  2087. }
  2088. else
  2089. {
  2090. command_print(cmd_ctx, "usage: arm7_9 force_hw_bkpts <enable|disable>");
  2091. }
  2092. command_print(cmd_ctx, "force hardware breakpoints %s", (arm7_9->force_hw_bkpts) ? "enabled" : "disabled");
  2093. return ERROR_OK;
  2094. }
  2095. int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
  2096. {
  2097. target_t *target = get_current_target(cmd_ctx);
  2098. armv4_5_common_t *armv4_5;
  2099. arm7_9_common_t *arm7_9;
  2100. if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
  2101. {
  2102. command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
  2103. return ERROR_OK;
  2104. }
  2105. if (argc > 0)
  2106. {
  2107. if (strcmp("enable", args[0]) == 0)
  2108. {
  2109. arm7_9->use_dbgrq = 1;
  2110. }
  2111. else if (strcmp("disable", args[0]) == 0)
  2112. {
  2113. arm7_9->use_dbgrq = 0;
  2114. }
  2115. else
  2116. {
  2117. command_print(cmd_ctx, "usage: arm7_9 dbgrq <enable|disable>");
  2118. }
  2119. }
  2120. command_print(cmd_ctx, "use of EmbeddedICE dbgrq instead of breakpoint for target halt %s", (arm7_9->use_dbgrq) ? "enabled" : "disabled");
  2121. return ERROR_OK;
  2122. }
  2123. int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
  2124. {
  2125. target_t *target = get_current_target(cmd_ctx);
  2126. armv4_5_common_t *armv4_5;
  2127. arm7_9_common_t *arm7_9;
  2128. if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
  2129. {
  2130. command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
  2131. return ERROR_OK;
  2132. }
  2133. if (argc > 0)
  2134. {
  2135. if (strcmp("enable", args[0]) == 0)
  2136. {
  2137. arm7_9->fast_memory_access = 1;
  2138. }
  2139. else if (strcmp("disable", args[0]) == 0)
  2140. {
  2141. arm7_9->fast_memory_access = 0;
  2142. }
  2143. else
  2144. {
  2145. command_print(cmd_ctx, "usage: arm7_9 fast_memory_access <enable|disable>");
  2146. }
  2147. }
  2148. command_print(cmd_ctx, "fast memory access is %s", (arm7_9->fast_memory_access) ? "enabled" : "disabled");
  2149. return ERROR_OK;
  2150. }
  2151. int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
  2152. {
  2153. target_t *target = get_current_target(cmd_ctx);
  2154. armv4_5_common_t *armv4_5;
  2155. arm7_9_common_t *arm7_9;
  2156. if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
  2157. {
  2158. command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
  2159. return ERROR_OK;
  2160. }
  2161. if (argc > 0)
  2162. {
  2163. if (strcmp("enable", args[0]) == 0)
  2164. {
  2165. arm7_9->dcc_downloads = 1;
  2166. }
  2167. else if (strcmp("disable", args[0]) == 0)
  2168. {
  2169. arm7_9->dcc_downloads = 0;
  2170. }
  2171. else
  2172. {
  2173. command_print(cmd_ctx, "usage: arm7_9 dcc_downloads <enable|disable>");
  2174. }
  2175. }
  2176. command_print(cmd_ctx, "dcc downloads are %s", (arm7_9->dcc_downloads) ? "enabled" : "disabled");
  2177. return ERROR_OK;
  2178. }
  2179. int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9)
  2180. {
  2181. armv4_5_common_t *armv4_5 = &arm7_9->armv4_5_common;
  2182. arm7_9->common_magic = ARM7_9_COMMON_MAGIC;
  2183. arm_jtag_setup_connection(&arm7_9->jtag_info);
  2184. arm7_9->wp_available = 2;
  2185. arm7_9->wp0_used = 0;
  2186. arm7_9->wp1_used = 0;
  2187. arm7_9->force_hw_bkpts = 0;
  2188. arm7_9->use_dbgrq = 0;
  2189. arm7_9->etm_ctx = NULL;
  2190. arm7_9->has_single_step = 0;
  2191. arm7_9->has_monitor_mode = 0;
  2192. arm7_9->has_vector_catch = 0;
  2193. arm7_9->debug_entry_from_reset = 0;
  2194. arm7_9->dcc_working_area = NULL;
  2195. arm7_9->fast_memory_access = fast_and_dangerous;
  2196. arm7_9->dcc_downloads = fast_and_dangerous;
  2197. armv4_5->arch_info = arm7_9;
  2198. armv4_5->read_core_reg = arm7_9_read_core_reg;
  2199. armv4_5->write_core_reg = arm7_9_write_core_reg;
  2200. armv4_5->full_context = arm7_9_full_context;
  2201. armv4_5_init_arch_info(target, armv4_5);
  2202. target_register_timer_callback(arm7_9_handle_target_request, 1, 1, target);
  2203. return ERROR_OK;
  2204. }