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  1. /***************************************************************************
  2. * Copyright (C) 2005 by Dominic Rath *
  3. * Dominic.Rath@gmx.de *
  4. * *
  5. * Copyright (C) 2008 by Spencer Oliver *
  6. * spen@spen-soft.co.uk *
  7. * *
  8. * Copyright (C) 2011 by Andreas Fritiofson *
  9. * andreas.fritiofson@gmail.com *
  10. *
  11. * This program is free software; you can redistribute it and/or modify *
  12. * it under the terms of the GNU General Public License as published by *
  13. * the Free Software Foundation; either version 2 of the License, or *
  14. * (at your option) any later version. *
  15. * *
  16. * This program is distributed in the hope that it will be useful, *
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  19. * GNU General Public License for more details. *
  20. * *
  21. * You should have received a copy of the GNU General Public License *
  22. * along with this program; if not, write to the *
  23. * Free Software Foundation, Inc., *
  24. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
  25. ***************************************************************************/
  26. #ifdef HAVE_CONFIG_H
  27. #include "config.h"
  28. #endif
  29. #include "imp.h"
  30. #include <helper/binarybuffer.h>
  31. #include <target/algorithm.h>
  32. #include <target/armv7m.h>
  33. /* stm32x register locations */
  34. #define FLASH_REG_BASE_B0 0x40022000
  35. #define FLASH_REG_BASE_B1 0x40022040
  36. #define STM32_FLASH_ACR 0x00
  37. #define STM32_FLASH_KEYR 0x04
  38. #define STM32_FLASH_OPTKEYR 0x08
  39. #define STM32_FLASH_SR 0x0C
  40. #define STM32_FLASH_CR 0x10
  41. #define STM32_FLASH_AR 0x14
  42. #define STM32_FLASH_OBR 0x1C
  43. #define STM32_FLASH_WRPR 0x20
  44. /* TODO: Check if code using these really should be hard coded to bank 0.
  45. * There are valid cases, on dual flash devices the protection of the
  46. * second bank is done on the bank0 reg's. */
  47. #define STM32_FLASH_ACR_B0 0x40022000
  48. #define STM32_FLASH_KEYR_B0 0x40022004
  49. #define STM32_FLASH_OPTKEYR_B0 0x40022008
  50. #define STM32_FLASH_SR_B0 0x4002200C
  51. #define STM32_FLASH_CR_B0 0x40022010
  52. #define STM32_FLASH_AR_B0 0x40022014
  53. #define STM32_FLASH_OBR_B0 0x4002201C
  54. #define STM32_FLASH_WRPR_B0 0x40022020
  55. /* option byte location */
  56. #define STM32_OB_RDP 0x1FFFF800
  57. #define STM32_OB_USER 0x1FFFF802
  58. #define STM32_OB_DATA0 0x1FFFF804
  59. #define STM32_OB_DATA1 0x1FFFF806
  60. #define STM32_OB_WRP0 0x1FFFF808
  61. #define STM32_OB_WRP1 0x1FFFF80A
  62. #define STM32_OB_WRP2 0x1FFFF80C
  63. #define STM32_OB_WRP3 0x1FFFF80E
  64. /* FLASH_CR register bits */
  65. #define FLASH_PG (1 << 0)
  66. #define FLASH_PER (1 << 1)
  67. #define FLASH_MER (1 << 2)
  68. #define FLASH_OPTPG (1 << 4)
  69. #define FLASH_OPTER (1 << 5)
  70. #define FLASH_STRT (1 << 6)
  71. #define FLASH_LOCK (1 << 7)
  72. #define FLASH_OPTWRE (1 << 9)
  73. /* FLASH_SR register bits */
  74. #define FLASH_BSY (1 << 0)
  75. #define FLASH_PGERR (1 << 2)
  76. #define FLASH_WRPRTERR (1 << 4)
  77. #define FLASH_EOP (1 << 5)
  78. /* STM32_FLASH_OBR bit definitions (reading) */
  79. #define OPT_ERROR 0
  80. #define OPT_READOUT 1
  81. #define OPT_RDWDGSW 2
  82. #define OPT_RDRSTSTOP 3
  83. #define OPT_RDRSTSTDBY 4
  84. #define OPT_BFB2 5 /* dual flash bank only */
  85. /* register unlock keys */
  86. #define KEY1 0x45670123
  87. #define KEY2 0xCDEF89AB
  88. struct stm32x_options {
  89. uint16_t RDP;
  90. uint16_t user_options;
  91. uint16_t protection[4];
  92. };
  93. struct stm32x_flash_bank {
  94. struct stm32x_options option_bytes;
  95. struct working_area *write_algorithm;
  96. int ppage_size;
  97. int probed;
  98. bool has_dual_banks;
  99. /* used to access dual flash bank stm32xl */
  100. uint32_t register_base;
  101. };
  102. static int stm32x_mass_erase(struct flash_bank *bank);
  103. static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id);
  104. /* flash bank stm32x <base> <size> 0 0 <target#>
  105. */
  106. FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
  107. {
  108. struct stm32x_flash_bank *stm32x_info;
  109. if (CMD_ARGC < 6)
  110. return ERROR_COMMAND_SYNTAX_ERROR;
  111. stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
  112. bank->driver_priv = stm32x_info;
  113. stm32x_info->write_algorithm = NULL;
  114. stm32x_info->probed = 0;
  115. stm32x_info->has_dual_banks = false;
  116. stm32x_info->register_base = FLASH_REG_BASE_B0;
  117. return ERROR_OK;
  118. }
  119. static inline int stm32x_get_flash_reg(struct flash_bank *bank, uint32_t reg)
  120. {
  121. struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
  122. return reg + stm32x_info->register_base;
  123. }
  124. static inline int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
  125. {
  126. struct target *target = bank->target;
  127. return target_read_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), status);
  128. }
  129. static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
  130. {
  131. struct target *target = bank->target;
  132. uint32_t status;
  133. int retval = ERROR_OK;
  134. /* wait for busy to clear */
  135. for (;;) {
  136. retval = stm32x_get_flash_status(bank, &status);
  137. if (retval != ERROR_OK)
  138. return retval;
  139. LOG_DEBUG("status: 0x%" PRIx32 "", status);
  140. if ((status & FLASH_BSY) == 0)
  141. break;
  142. if (timeout-- <= 0) {
  143. LOG_ERROR("timed out waiting for flash");
  144. return ERROR_FAIL;
  145. }
  146. alive_sleep(1);
  147. }
  148. if (status & FLASH_WRPRTERR) {
  149. LOG_ERROR("stm32x device protected");
  150. retval = ERROR_FAIL;
  151. }
  152. if (status & FLASH_PGERR) {
  153. LOG_ERROR("stm32x device programming failed");
  154. retval = ERROR_FAIL;
  155. }
  156. /* Clear but report errors */
  157. if (status & (FLASH_WRPRTERR | FLASH_PGERR)) {
  158. /* If this operation fails, we ignore it and report the original
  159. * retval
  160. */
  161. target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR),
  162. FLASH_WRPRTERR | FLASH_PGERR);
  163. }
  164. return retval;
  165. }
  166. int stm32x_check_operation_supported(struct flash_bank *bank)
  167. {
  168. struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
  169. /* if we have a dual flash bank device then
  170. * we need to perform option byte stuff on bank0 only */
  171. if (stm32x_info->register_base != FLASH_REG_BASE_B0) {
  172. LOG_ERROR("Option Byte Operation's must use bank0");
  173. return ERROR_FLASH_OPERATION_FAILED;
  174. }
  175. return ERROR_OK;
  176. }
  177. static int stm32x_read_options(struct flash_bank *bank)
  178. {
  179. uint32_t optiondata;
  180. struct stm32x_flash_bank *stm32x_info = NULL;
  181. struct target *target = bank->target;
  182. stm32x_info = bank->driver_priv;
  183. /* read current option bytes */
  184. int retval = target_read_u32(target, STM32_FLASH_OBR_B0, &optiondata);
  185. if (retval != ERROR_OK)
  186. return retval;
  187. stm32x_info->option_bytes.user_options = (uint16_t)0xFFF8 | ((optiondata >> 2) & 0x07);
  188. stm32x_info->option_bytes.RDP = (optiondata & (1 << OPT_READOUT)) ? 0xFFFF : 0x5AA5;
  189. if (optiondata & (1 << OPT_READOUT))
  190. LOG_INFO("Device Security Bit Set");
  191. /* each bit refers to a 4bank protection */
  192. retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &optiondata);
  193. if (retval != ERROR_OK)
  194. return retval;
  195. stm32x_info->option_bytes.protection[0] = (uint16_t)optiondata;
  196. stm32x_info->option_bytes.protection[1] = (uint16_t)(optiondata >> 8);
  197. stm32x_info->option_bytes.protection[2] = (uint16_t)(optiondata >> 16);
  198. stm32x_info->option_bytes.protection[3] = (uint16_t)(optiondata >> 24);
  199. return ERROR_OK;
  200. }
  201. static int stm32x_erase_options(struct flash_bank *bank)
  202. {
  203. struct stm32x_flash_bank *stm32x_info = NULL;
  204. struct target *target = bank->target;
  205. stm32x_info = bank->driver_priv;
  206. /* stlink is currently does not support 16bit
  207. * read/writes. so we cannot write option bytes */
  208. struct armv7m_common *armv7m = target_to_armv7m(target);
  209. if (armv7m && armv7m->stlink) {
  210. LOG_ERROR("Option bytes currently unsupported for stlink");
  211. return ERROR_FAIL;
  212. }
  213. /* read current options */
  214. stm32x_read_options(bank);
  215. /* unlock flash registers */
  216. int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
  217. if (retval != ERROR_OK)
  218. return retval;
  219. retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
  220. if (retval != ERROR_OK)
  221. return retval;
  222. /* unlock option flash registers */
  223. retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
  224. if (retval != ERROR_OK)
  225. return retval;
  226. retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
  227. if (retval != ERROR_OK)
  228. return retval;
  229. /* erase option bytes */
  230. retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_OPTWRE);
  231. if (retval != ERROR_OK)
  232. return retval;
  233. retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_STRT | FLASH_OPTWRE);
  234. if (retval != ERROR_OK)
  235. return retval;
  236. retval = stm32x_wait_status_busy(bank, 10);
  237. if (retval != ERROR_OK)
  238. return retval;
  239. /* clear readout protection and complementary option bytes
  240. * this will also force a device unlock if set */
  241. stm32x_info->option_bytes.RDP = 0x5AA5;
  242. return ERROR_OK;
  243. }
  244. static int stm32x_write_options(struct flash_bank *bank)
  245. {
  246. struct stm32x_flash_bank *stm32x_info = NULL;
  247. struct target *target = bank->target;
  248. stm32x_info = bank->driver_priv;
  249. /* unlock flash registers */
  250. int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
  251. if (retval != ERROR_OK)
  252. return retval;
  253. retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
  254. if (retval != ERROR_OK)
  255. return retval;
  256. /* unlock option flash registers */
  257. retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
  258. if (retval != ERROR_OK)
  259. return retval;
  260. retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
  261. if (retval != ERROR_OK)
  262. return retval;
  263. /* program option bytes */
  264. retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTPG | FLASH_OPTWRE);
  265. if (retval != ERROR_OK)
  266. return retval;
  267. /* write user option byte */
  268. retval = target_write_u16(target, STM32_OB_USER, stm32x_info->option_bytes.user_options);
  269. if (retval != ERROR_OK)
  270. return retval;
  271. retval = stm32x_wait_status_busy(bank, 10);
  272. if (retval != ERROR_OK)
  273. return retval;
  274. /* write protection byte 1 */
  275. retval = target_write_u16(target, STM32_OB_WRP0, stm32x_info->option_bytes.protection[0]);
  276. if (retval != ERROR_OK)
  277. return retval;
  278. retval = stm32x_wait_status_busy(bank, 10);
  279. if (retval != ERROR_OK)
  280. return retval;
  281. /* write protection byte 2 */
  282. retval = target_write_u16(target, STM32_OB_WRP1, stm32x_info->option_bytes.protection[1]);
  283. if (retval != ERROR_OK)
  284. return retval;
  285. retval = stm32x_wait_status_busy(bank, 10);
  286. if (retval != ERROR_OK)
  287. return retval;
  288. /* write protection byte 3 */
  289. retval = target_write_u16(target, STM32_OB_WRP2, stm32x_info->option_bytes.protection[2]);
  290. if (retval != ERROR_OK)
  291. return retval;
  292. retval = stm32x_wait_status_busy(bank, 10);
  293. if (retval != ERROR_OK)
  294. return retval;
  295. /* write protection byte 4 */
  296. retval = target_write_u16(target, STM32_OB_WRP3, stm32x_info->option_bytes.protection[3]);
  297. if (retval != ERROR_OK)
  298. return retval;
  299. retval = stm32x_wait_status_busy(bank, 10);
  300. if (retval != ERROR_OK)
  301. return retval;
  302. /* write readout protection bit */
  303. retval = target_write_u16(target, STM32_OB_RDP, stm32x_info->option_bytes.RDP);
  304. if (retval != ERROR_OK)
  305. return retval;
  306. retval = stm32x_wait_status_busy(bank, 10);
  307. if (retval != ERROR_OK)
  308. return retval;
  309. retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_LOCK);
  310. if (retval != ERROR_OK)
  311. return retval;
  312. return ERROR_OK;
  313. }
  314. static int stm32x_protect_check(struct flash_bank *bank)
  315. {
  316. struct target *target = bank->target;
  317. struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
  318. uint32_t protection;
  319. int i, s;
  320. int num_bits;
  321. int set;
  322. if (target->state != TARGET_HALTED) {
  323. LOG_ERROR("Target not halted");
  324. return ERROR_TARGET_NOT_HALTED;
  325. }
  326. int retval = stm32x_check_operation_supported(bank);
  327. if (ERROR_OK != retval)
  328. return retval;
  329. /* medium density - each bit refers to a 4bank protection
  330. * high density - each bit refers to a 2bank protection */
  331. retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
  332. if (retval != ERROR_OK)
  333. return retval;
  334. /* medium density - each protection bit is for 4 * 1K pages
  335. * high density - each protection bit is for 2 * 2K pages */
  336. num_bits = (bank->num_sectors / stm32x_info->ppage_size);
  337. if (stm32x_info->ppage_size == 2) {
  338. /* high density flash/connectivity line protection */
  339. set = 1;
  340. if (protection & (1 << 31))
  341. set = 0;
  342. /* bit 31 controls sector 62 - 255 protection for high density
  343. * bit 31 controls sector 62 - 127 protection for connectivity line */
  344. for (s = 62; s < bank->num_sectors; s++)
  345. bank->sectors[s].is_protected = set;
  346. if (bank->num_sectors > 61)
  347. num_bits = 31;
  348. for (i = 0; i < num_bits; i++) {
  349. set = 1;
  350. if (protection & (1 << i))
  351. set = 0;
  352. for (s = 0; s < stm32x_info->ppage_size; s++)
  353. bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
  354. }
  355. } else {
  356. /* low/medium density flash protection */
  357. for (i = 0; i < num_bits; i++) {
  358. set = 1;
  359. if (protection & (1 << i))
  360. set = 0;
  361. for (s = 0; s < stm32x_info->ppage_size; s++)
  362. bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
  363. }
  364. }
  365. return ERROR_OK;
  366. }
  367. static int stm32x_erase(struct flash_bank *bank, int first, int last)
  368. {
  369. struct target *target = bank->target;
  370. int i;
  371. if (bank->target->state != TARGET_HALTED) {
  372. LOG_ERROR("Target not halted");
  373. return ERROR_TARGET_NOT_HALTED;
  374. }
  375. if ((first == 0) && (last == (bank->num_sectors - 1)))
  376. return stm32x_mass_erase(bank);
  377. /* unlock flash registers */
  378. int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
  379. if (retval != ERROR_OK)
  380. return retval;
  381. retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
  382. if (retval != ERROR_OK)
  383. return retval;
  384. for (i = first; i <= last; i++) {
  385. retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER);
  386. if (retval != ERROR_OK)
  387. return retval;
  388. retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_AR),
  389. bank->base + bank->sectors[i].offset);
  390. if (retval != ERROR_OK)
  391. return retval;
  392. retval = target_write_u32(target,
  393. stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER | FLASH_STRT);
  394. if (retval != ERROR_OK)
  395. return retval;
  396. retval = stm32x_wait_status_busy(bank, 100);
  397. if (retval != ERROR_OK)
  398. return retval;
  399. bank->sectors[i].is_erased = 1;
  400. }
  401. retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
  402. if (retval != ERROR_OK)
  403. return retval;
  404. return ERROR_OK;
  405. }
  406. static int stm32x_protect(struct flash_bank *bank, int set, int first, int last)
  407. {
  408. struct stm32x_flash_bank *stm32x_info = NULL;
  409. struct target *target = bank->target;
  410. uint16_t prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
  411. int i, reg, bit;
  412. int status;
  413. uint32_t protection;
  414. stm32x_info = bank->driver_priv;
  415. if (target->state != TARGET_HALTED) {
  416. LOG_ERROR("Target not halted");
  417. return ERROR_TARGET_NOT_HALTED;
  418. }
  419. int retval = stm32x_check_operation_supported(bank);
  420. if (ERROR_OK != retval)
  421. return retval;
  422. if ((first % stm32x_info->ppage_size) != 0) {
  423. LOG_WARNING("aligned start protect sector to a %d sector boundary",
  424. stm32x_info->ppage_size);
  425. first = first - (first % stm32x_info->ppage_size);
  426. }
  427. if (((last + 1) % stm32x_info->ppage_size) != 0) {
  428. LOG_WARNING("aligned end protect sector to a %d sector boundary",
  429. stm32x_info->ppage_size);
  430. last++;
  431. last = last - (last % stm32x_info->ppage_size);
  432. last--;
  433. }
  434. /* medium density - each bit refers to a 4bank protection
  435. * high density - each bit refers to a 2bank protection */
  436. retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
  437. if (retval != ERROR_OK)
  438. return retval;
  439. prot_reg[0] = (uint16_t)protection;
  440. prot_reg[1] = (uint16_t)(protection >> 8);
  441. prot_reg[2] = (uint16_t)(protection >> 16);
  442. prot_reg[3] = (uint16_t)(protection >> 24);
  443. if (stm32x_info->ppage_size == 2) {
  444. /* high density flash */
  445. /* bit 7 controls sector 62 - 255 protection */
  446. if (last > 61) {
  447. if (set)
  448. prot_reg[3] &= ~(1 << 7);
  449. else
  450. prot_reg[3] |= (1 << 7);
  451. }
  452. if (first > 61)
  453. first = 62;
  454. if (last > 61)
  455. last = 61;
  456. for (i = first; i <= last; i++) {
  457. reg = (i / stm32x_info->ppage_size) / 8;
  458. bit = (i / stm32x_info->ppage_size) - (reg * 8);
  459. if (set)
  460. prot_reg[reg] &= ~(1 << bit);
  461. else
  462. prot_reg[reg] |= (1 << bit);
  463. }
  464. } else {
  465. /* medium density flash */
  466. for (i = first; i <= last; i++) {
  467. reg = (i / stm32x_info->ppage_size) / 8;
  468. bit = (i / stm32x_info->ppage_size) - (reg * 8);
  469. if (set)
  470. prot_reg[reg] &= ~(1 << bit);
  471. else
  472. prot_reg[reg] |= (1 << bit);
  473. }
  474. }
  475. status = stm32x_erase_options(bank);
  476. if (status != ERROR_OK)
  477. return status;
  478. stm32x_info->option_bytes.protection[0] = prot_reg[0];
  479. stm32x_info->option_bytes.protection[1] = prot_reg[1];
  480. stm32x_info->option_bytes.protection[2] = prot_reg[2];
  481. stm32x_info->option_bytes.protection[3] = prot_reg[3];
  482. return stm32x_write_options(bank);
  483. }
  484. static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer,
  485. uint32_t offset, uint32_t count)
  486. {
  487. struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
  488. struct target *target = bank->target;
  489. uint32_t buffer_size = 16384;
  490. struct working_area *source;
  491. uint32_t address = bank->base + offset;
  492. struct reg_param reg_params[5];
  493. struct armv7m_algorithm armv7m_info;
  494. int retval = ERROR_OK;
  495. /* see contrib/loaders/flash/stm32f1x.S for src */
  496. static const uint8_t stm32x_flash_write_code[] = {
  497. /* #define STM32_FLASH_SR_OFFSET 0x0C */
  498. /* wait_fifo: */
  499. 0x16, 0x68, /* ldr r6, [r2, #0] */
  500. 0x00, 0x2e, /* cmp r6, #0 */
  501. 0x18, 0xd0, /* beq exit */
  502. 0x55, 0x68, /* ldr r5, [r2, #4] */
  503. 0xb5, 0x42, /* cmp r5, r6 */
  504. 0xf9, 0xd0, /* beq wait_fifo */
  505. 0x2e, 0x88, /* ldrh r6, [r5, #0] */
  506. 0x26, 0x80, /* strh r6, [r4, #0] */
  507. 0x02, 0x35, /* adds r5, #2 */
  508. 0x02, 0x34, /* adds r4, #2 */
  509. /* busy: */
  510. 0xc6, 0x68, /* ldr r6, [r0, #STM32_FLASH_SR_OFFSET] */
  511. 0x01, 0x27, /* movs r7, #1 */
  512. 0x3e, 0x42, /* tst r6, r7 */
  513. 0xfb, 0xd1, /* bne busy */
  514. 0x14, 0x27, /* movs r7, #0x14 */
  515. 0x3e, 0x42, /* tst r6, r7 */
  516. 0x08, 0xd1, /* bne error */
  517. 0x9d, 0x42, /* cmp r5, r3 */
  518. 0x01, 0xd3, /* bcc no_wrap */
  519. 0x15, 0x46, /* mov r5, r2 */
  520. 0x08, 0x35, /* adds r5, #8 */
  521. /* no_wrap: */
  522. 0x55, 0x60, /* str r5, [r2, #4] */
  523. 0x01, 0x39, /* subs r1, r1, #1 */
  524. 0x00, 0x29, /* cmp r1, #0 */
  525. 0x02, 0xd0, /* beq exit */
  526. 0xe5, 0xe7, /* b wait_fifo */
  527. /* error: */
  528. 0x00, 0x20, /* movs r0, #0 */
  529. 0x50, 0x60, /* str r0, [r2, #4] */
  530. /* exit: */
  531. 0x30, 0x46, /* mov r0, r6 */
  532. 0x00, 0xbe, /* bkpt #0 */
  533. };
  534. /* flash write code */
  535. if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
  536. &stm32x_info->write_algorithm) != ERROR_OK) {
  537. LOG_WARNING("no working area available, can't do block memory writes");
  538. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  539. };
  540. retval = target_write_buffer(target, stm32x_info->write_algorithm->address,
  541. sizeof(stm32x_flash_write_code), (uint8_t *)stm32x_flash_write_code);
  542. if (retval != ERROR_OK)
  543. return retval;
  544. /* memory buffer */
  545. while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
  546. buffer_size /= 2;
  547. buffer_size &= ~3UL; /* Make sure it's 4 byte aligned */
  548. if (buffer_size <= 256) {
  549. /* if we already allocated the writing code, but failed to get a
  550. * buffer, free the algorithm */
  551. if (stm32x_info->write_algorithm)
  552. target_free_working_area(target, stm32x_info->write_algorithm);
  553. LOG_WARNING("no large enough working area available, can't do block memory writes");
  554. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  555. }
  556. };
  557. init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* flash base (in), status (out) */
  558. init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* count (halfword-16bit) */
  559. init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT); /* buffer start */
  560. init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT); /* buffer end */
  561. init_reg_param(&reg_params[4], "r4", 32, PARAM_IN_OUT); /* target address */
  562. buf_set_u32(reg_params[0].value, 0, 32, stm32x_info->register_base);
  563. buf_set_u32(reg_params[1].value, 0, 32, count);
  564. buf_set_u32(reg_params[2].value, 0, 32, source->address);
  565. buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
  566. buf_set_u32(reg_params[4].value, 0, 32, address);
  567. armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
  568. armv7m_info.core_mode = ARMV7M_MODE_ANY;
  569. retval = target_run_flash_async_algorithm(target, buffer, count, 2,
  570. 0, NULL,
  571. 5, reg_params,
  572. source->address, source->size,
  573. stm32x_info->write_algorithm->address, 0,
  574. &armv7m_info);
  575. if (retval == ERROR_FLASH_OPERATION_FAILED) {
  576. LOG_ERROR("flash write failed at address 0x%"PRIx32,
  577. buf_get_u32(reg_params[4].value, 0, 32));
  578. if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_PGERR) {
  579. LOG_ERROR("flash memory not erased before writing");
  580. /* Clear but report errors */
  581. target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_PGERR);
  582. }
  583. if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_WRPRTERR) {
  584. LOG_ERROR("flash memory write protected");
  585. /* Clear but report errors */
  586. target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_WRPRTERR);
  587. }
  588. }
  589. target_free_working_area(target, source);
  590. target_free_working_area(target, stm32x_info->write_algorithm);
  591. destroy_reg_param(&reg_params[0]);
  592. destroy_reg_param(&reg_params[1]);
  593. destroy_reg_param(&reg_params[2]);
  594. destroy_reg_param(&reg_params[3]);
  595. destroy_reg_param(&reg_params[4]);
  596. return retval;
  597. }
  598. static int stm32x_write(struct flash_bank *bank, uint8_t *buffer,
  599. uint32_t offset, uint32_t count)
  600. {
  601. struct target *target = bank->target;
  602. uint8_t *new_buffer = NULL;
  603. if (bank->target->state != TARGET_HALTED) {
  604. LOG_ERROR("Target not halted");
  605. return ERROR_TARGET_NOT_HALTED;
  606. }
  607. if (offset & 0x1) {
  608. LOG_ERROR("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
  609. return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
  610. }
  611. /* If there's an odd number of bytes, the data has to be padded. Duplicate
  612. * the buffer and use the normal code path with a single block write since
  613. * it's probably cheaper than to special case the last odd write using
  614. * discrete accesses. */
  615. if (count & 1) {
  616. new_buffer = malloc(count + 1);
  617. if (new_buffer == NULL) {
  618. LOG_ERROR("odd number of bytes to write and no memory for padding buffer");
  619. return ERROR_FAIL;
  620. }
  621. LOG_INFO("odd number of bytes to write, padding with 0xff");
  622. buffer = memcpy(new_buffer, buffer, count);
  623. buffer[count++] = 0xff;
  624. }
  625. uint32_t words_remaining = count / 2;
  626. int retval, retval2;
  627. /* unlock flash registers */
  628. retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
  629. if (retval != ERROR_OK)
  630. goto cleanup;
  631. retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
  632. if (retval != ERROR_OK)
  633. goto cleanup;
  634. retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PG);
  635. if (retval != ERROR_OK)
  636. goto cleanup;
  637. /* try using a block write */
  638. retval = stm32x_write_block(bank, buffer, offset, words_remaining);
  639. if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
  640. /* if block write failed (no sufficient working area),
  641. * we use normal (slow) single halfword accesses */
  642. LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
  643. while (words_remaining > 0) {
  644. uint16_t value;
  645. memcpy(&value, buffer, sizeof(uint16_t));
  646. retval = target_write_u16(target, bank->base + offset, value);
  647. if (retval != ERROR_OK)
  648. goto reset_pg_and_lock;
  649. retval = stm32x_wait_status_busy(bank, 5);
  650. if (retval != ERROR_OK)
  651. goto reset_pg_and_lock;
  652. words_remaining--;
  653. buffer += 2;
  654. offset += 2;
  655. }
  656. }
  657. reset_pg_and_lock:
  658. retval2 = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
  659. if (retval == ERROR_OK)
  660. retval = retval2;
  661. cleanup:
  662. if (new_buffer)
  663. free(new_buffer);
  664. return retval;
  665. }
  666. static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id)
  667. {
  668. /* This check the device CPUID core register to detect
  669. * the M0 from the M3 devices. */
  670. struct target *target = bank->target;
  671. uint32_t cpuid, device_id_register = 0;
  672. /* Get the CPUID from the ARM Core
  673. * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0432c/DDI0432C_cortex_m0_r0p0_trm.pdf 4.2.1 */
  674. int retval = target_read_u32(target, 0xE000ED00, &cpuid);
  675. if (retval != ERROR_OK)
  676. return retval;
  677. if (((cpuid >> 4) & 0xFFF) == 0xC20) {
  678. /* 0xC20 is M0 devices */
  679. device_id_register = 0x40015800;
  680. } else if (((cpuid >> 4) & 0xFFF) == 0xC23) {
  681. /* 0xC23 is M3 devices */
  682. device_id_register = 0xE0042000;
  683. } else if (((cpuid >> 4) & 0xFFF) == 0xC24) {
  684. /* 0xC24 is M4 devices */
  685. device_id_register = 0xE0042000;
  686. } else {
  687. LOG_ERROR("Cannot identify target as a stm32x");
  688. return ERROR_FAIL;
  689. }
  690. /* read stm32 device id register */
  691. retval = target_read_u32(target, device_id_register, device_id);
  692. if (retval != ERROR_OK)
  693. return retval;
  694. return retval;
  695. }
  696. static int stm32x_get_flash_size(struct flash_bank *bank, uint16_t *flash_size_in_kb)
  697. {
  698. struct target *target = bank->target;
  699. uint32_t cpuid, flash_size_reg;
  700. int retval = target_read_u32(target, 0xE000ED00, &cpuid);
  701. if (retval != ERROR_OK)
  702. return retval;
  703. if (((cpuid >> 4) & 0xFFF) == 0xC20) {
  704. /* 0xC20 is M0 devices */
  705. flash_size_reg = 0x1FFFF7CC;
  706. } else if (((cpuid >> 4) & 0xFFF) == 0xC23) {
  707. /* 0xC23 is M3 devices */
  708. flash_size_reg = 0x1FFFF7E0;
  709. } else if (((cpuid >> 4) & 0xFFF) == 0xC24) {
  710. /* 0xC24 is M4 devices */
  711. flash_size_reg = 0x1FFFF7CC;
  712. } else {
  713. LOG_ERROR("Cannot identify target as a stm32x");
  714. return ERROR_FAIL;
  715. }
  716. retval = target_read_u16(target, flash_size_reg, flash_size_in_kb);
  717. if (retval != ERROR_OK)
  718. return retval;
  719. return retval;
  720. }
  721. static int stm32x_probe(struct flash_bank *bank)
  722. {
  723. struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
  724. int i;
  725. uint16_t flash_size_in_kb;
  726. uint16_t max_flash_size_in_kb;
  727. uint32_t device_id;
  728. int page_size;
  729. uint32_t base_address = 0x08000000;
  730. stm32x_info->probed = 0;
  731. stm32x_info->register_base = FLASH_REG_BASE_B0;
  732. /* read stm32 device id register */
  733. int retval = stm32x_get_device_id(bank, &device_id);
  734. if (retval != ERROR_OK)
  735. return retval;
  736. LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
  737. /* set page size, protection granularity and max flash size depending on family */
  738. switch (device_id & 0xfff) {
  739. case 0x410: /* medium density */
  740. page_size = 1024;
  741. stm32x_info->ppage_size = 4;
  742. max_flash_size_in_kb = 128;
  743. break;
  744. case 0x412: /* low density */
  745. page_size = 1024;
  746. stm32x_info->ppage_size = 4;
  747. max_flash_size_in_kb = 32;
  748. break;
  749. case 0x414: /* high density */
  750. page_size = 2048;
  751. stm32x_info->ppage_size = 2;
  752. max_flash_size_in_kb = 512;
  753. break;
  754. case 0x418: /* connectivity line density */
  755. page_size = 2048;
  756. stm32x_info->ppage_size = 2;
  757. max_flash_size_in_kb = 256;
  758. break;
  759. case 0x420: /* value line density */
  760. page_size = 1024;
  761. stm32x_info->ppage_size = 4;
  762. max_flash_size_in_kb = 128;
  763. break;
  764. case 0x422: /* stm32f30x */
  765. page_size = 2048;
  766. stm32x_info->ppage_size = 2;
  767. max_flash_size_in_kb = 256;
  768. break;
  769. case 0x428: /* value line High density */
  770. page_size = 2048;
  771. stm32x_info->ppage_size = 4;
  772. max_flash_size_in_kb = 128;
  773. break;
  774. case 0x430: /* xl line density (dual flash banks) */
  775. page_size = 2048;
  776. stm32x_info->ppage_size = 2;
  777. max_flash_size_in_kb = 1024;
  778. stm32x_info->has_dual_banks = true;
  779. break;
  780. case 0x432: /* stm32f37x */
  781. page_size = 2048;
  782. stm32x_info->ppage_size = 2;
  783. max_flash_size_in_kb = 256;
  784. break;
  785. case 0x440: /* stm32f0x */
  786. page_size = 1024;
  787. stm32x_info->ppage_size = 4;
  788. max_flash_size_in_kb = 64;
  789. break;
  790. default:
  791. LOG_WARNING("Cannot identify target as a STM32 family.");
  792. return ERROR_FAIL;
  793. }
  794. /* get flash size from target. */
  795. retval = stm32x_get_flash_size(bank, &flash_size_in_kb);
  796. /* failed reading flash size or flash size invalid (early silicon),
  797. * default to max target family */
  798. if (retval != ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0) {
  799. LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
  800. max_flash_size_in_kb);
  801. flash_size_in_kb = max_flash_size_in_kb;
  802. }
  803. if (stm32x_info->has_dual_banks) {
  804. /* split reported size into matching bank */
  805. if (bank->base != 0x08080000) {
  806. /* bank 0 will be fixed 512k */
  807. flash_size_in_kb = 512;
  808. } else {
  809. flash_size_in_kb -= 512;
  810. /* bank1 also uses a register offset */
  811. stm32x_info->register_base = FLASH_REG_BASE_B1;
  812. base_address = 0x08080000;
  813. }
  814. }
  815. LOG_INFO("flash size = %dkbytes", flash_size_in_kb);
  816. /* did we assign flash size? */
  817. assert(flash_size_in_kb != 0xffff);
  818. /* calculate numbers of pages */
  819. int num_pages = flash_size_in_kb * 1024 / page_size;
  820. /* check that calculation result makes sense */
  821. assert(num_pages > 0);
  822. if (bank->sectors) {
  823. free(bank->sectors);
  824. bank->sectors = NULL;
  825. }
  826. bank->base = base_address;
  827. bank->size = (num_pages * page_size);
  828. bank->num_sectors = num_pages;
  829. bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
  830. for (i = 0; i < num_pages; i++) {
  831. bank->sectors[i].offset = i * page_size;
  832. bank->sectors[i].size = page_size;
  833. bank->sectors[i].is_erased = -1;
  834. bank->sectors[i].is_protected = 1;
  835. }
  836. stm32x_info->probed = 1;
  837. return ERROR_OK;
  838. }
  839. static int stm32x_auto_probe(struct flash_bank *bank)
  840. {
  841. struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
  842. if (stm32x_info->probed)
  843. return ERROR_OK;
  844. return stm32x_probe(bank);
  845. }
  846. #if 0
  847. COMMAND_HANDLER(stm32x_handle_part_id_command)
  848. {
  849. return ERROR_OK;
  850. }
  851. #endif
  852. static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
  853. {
  854. uint32_t device_id;
  855. int printed;
  856. /* read stm32 device id register */
  857. int retval = stm32x_get_device_id(bank, &device_id);
  858. if (retval != ERROR_OK)
  859. return retval;
  860. if ((device_id & 0xfff) == 0x410) {
  861. printed = snprintf(buf, buf_size, "stm32x (Medium Density) - Rev: ");
  862. buf += printed;
  863. buf_size -= printed;
  864. switch (device_id >> 16) {
  865. case 0x0000:
  866. snprintf(buf, buf_size, "A");
  867. break;
  868. case 0x2000:
  869. snprintf(buf, buf_size, "B");
  870. break;
  871. case 0x2001:
  872. snprintf(buf, buf_size, "Z");
  873. break;
  874. case 0x2003:
  875. snprintf(buf, buf_size, "Y");
  876. break;
  877. default:
  878. snprintf(buf, buf_size, "unknown");
  879. break;
  880. }
  881. } else if ((device_id & 0xfff) == 0x412) {
  882. printed = snprintf(buf, buf_size, "stm32x (Low Density) - Rev: ");
  883. buf += printed;
  884. buf_size -= printed;
  885. switch (device_id >> 16) {
  886. case 0x1000:
  887. snprintf(buf, buf_size, "A");
  888. break;
  889. default:
  890. snprintf(buf, buf_size, "unknown");
  891. break;
  892. }
  893. } else if ((device_id & 0xfff) == 0x414) {
  894. printed = snprintf(buf, buf_size, "stm32x (High Density) - Rev: ");
  895. buf += printed;
  896. buf_size -= printed;
  897. switch (device_id >> 16) {
  898. case 0x1000:
  899. snprintf(buf, buf_size, "A");
  900. break;
  901. case 0x1001:
  902. snprintf(buf, buf_size, "Z");
  903. break;
  904. default:
  905. snprintf(buf, buf_size, "unknown");
  906. break;
  907. }
  908. } else if ((device_id & 0xfff) == 0x418) {
  909. printed = snprintf(buf, buf_size, "stm32x (Connectivity) - Rev: ");
  910. buf += printed;
  911. buf_size -= printed;
  912. switch (device_id >> 16) {
  913. case 0x1000:
  914. snprintf(buf, buf_size, "A");
  915. break;
  916. case 0x1001:
  917. snprintf(buf, buf_size, "Z");
  918. break;
  919. default:
  920. snprintf(buf, buf_size, "unknown");
  921. break;
  922. }
  923. } else if ((device_id & 0xfff) == 0x420) {
  924. printed = snprintf(buf, buf_size, "stm32x (Value) - Rev: ");
  925. buf += printed;
  926. buf_size -= printed;
  927. switch (device_id >> 16) {
  928. case 0x1000:
  929. snprintf(buf, buf_size, "A");
  930. break;
  931. case 0x1001:
  932. snprintf(buf, buf_size, "Z");
  933. break;
  934. default:
  935. snprintf(buf, buf_size, "unknown");
  936. break;
  937. }
  938. } else if ((device_id & 0xfff) == 0x422) {
  939. printed = snprintf(buf, buf_size, "stm32f30x - Rev: ");
  940. buf += printed;
  941. buf_size -= printed;
  942. switch (device_id >> 16) {
  943. case 0x1000:
  944. snprintf(buf, buf_size, "1.0");
  945. break;
  946. case 0x2000:
  947. snprintf(buf, buf_size, "2.0");
  948. break;
  949. default:
  950. snprintf(buf, buf_size, "unknown");
  951. break;
  952. }
  953. } else if ((device_id & 0xfff) == 0x428) {
  954. printed = snprintf(buf, buf_size, "stm32x (Value HD) - Rev: ");
  955. buf += printed;
  956. buf_size -= printed;
  957. switch (device_id >> 16) {
  958. case 0x1000:
  959. snprintf(buf, buf_size, "A");
  960. break;
  961. case 0x1001:
  962. snprintf(buf, buf_size, "Z");
  963. break;
  964. default:
  965. snprintf(buf, buf_size, "unknown");
  966. break;
  967. }
  968. } else if ((device_id & 0xfff) == 0x430) {
  969. printed = snprintf(buf, buf_size, "stm32x (XL) - Rev: ");
  970. buf += printed;
  971. buf_size -= printed;
  972. switch (device_id >> 16) {
  973. case 0x1000:
  974. snprintf(buf, buf_size, "A");
  975. break;
  976. default:
  977. snprintf(buf, buf_size, "unknown");
  978. break;
  979. }
  980. } else if ((device_id & 0xfff) == 0x432) {
  981. printed = snprintf(buf, buf_size, "stm32f37x - Rev: ");
  982. buf += printed;
  983. buf_size -= printed;
  984. switch (device_id >> 16) {
  985. case 0x1000:
  986. snprintf(buf, buf_size, "1.0");
  987. break;
  988. case 0x2000:
  989. snprintf(buf, buf_size, "2.0");
  990. break;
  991. default:
  992. snprintf(buf, buf_size, "unknown");
  993. break;
  994. }
  995. } else if ((device_id & 0xfff) == 0x440) {
  996. printed = snprintf(buf, buf_size, "stm32f0x - Rev: ");
  997. buf += printed;
  998. buf_size -= printed;
  999. switch (device_id >> 16) {
  1000. case 0x1000:
  1001. snprintf(buf, buf_size, "1.0");
  1002. break;
  1003. case 0x2000:
  1004. snprintf(buf, buf_size, "2.0");
  1005. break;
  1006. default:
  1007. snprintf(buf, buf_size, "unknown");
  1008. break;
  1009. }
  1010. } else {
  1011. snprintf(buf, buf_size, "Cannot identify target as a stm32x\n");
  1012. return ERROR_FAIL;
  1013. }
  1014. return ERROR_OK;
  1015. }
  1016. COMMAND_HANDLER(stm32x_handle_lock_command)
  1017. {
  1018. struct target *target = NULL;
  1019. struct stm32x_flash_bank *stm32x_info = NULL;
  1020. if (CMD_ARGC < 1)
  1021. return ERROR_COMMAND_SYNTAX_ERROR;
  1022. struct flash_bank *bank;
  1023. int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
  1024. if (ERROR_OK != retval)
  1025. return retval;
  1026. stm32x_info = bank->driver_priv;
  1027. target = bank->target;
  1028. if (target->state != TARGET_HALTED) {
  1029. LOG_ERROR("Target not halted");
  1030. return ERROR_TARGET_NOT_HALTED;
  1031. }
  1032. retval = stm32x_check_operation_supported(bank);
  1033. if (ERROR_OK != retval)
  1034. return retval;
  1035. if (stm32x_erase_options(bank) != ERROR_OK) {
  1036. command_print(CMD_CTX, "stm32x failed to erase options");
  1037. return ERROR_OK;
  1038. }
  1039. /* set readout protection */
  1040. stm32x_info->option_bytes.RDP = 0;
  1041. if (stm32x_write_options(bank) != ERROR_OK) {
  1042. command_print(CMD_CTX, "stm32x failed to lock device");
  1043. return ERROR_OK;
  1044. }
  1045. command_print(CMD_CTX, "stm32x locked");
  1046. return ERROR_OK;
  1047. }
  1048. COMMAND_HANDLER(stm32x_handle_unlock_command)
  1049. {
  1050. struct target *target = NULL;
  1051. if (CMD_ARGC < 1)
  1052. return ERROR_COMMAND_SYNTAX_ERROR;
  1053. struct flash_bank *bank;
  1054. int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
  1055. if (ERROR_OK != retval)
  1056. return retval;
  1057. target = bank->target;
  1058. if (target->state != TARGET_HALTED) {
  1059. LOG_ERROR("Target not halted");
  1060. return ERROR_TARGET_NOT_HALTED;
  1061. }
  1062. retval = stm32x_check_operation_supported(bank);
  1063. if (ERROR_OK != retval)
  1064. return retval;
  1065. if (stm32x_erase_options(bank) != ERROR_OK) {
  1066. command_print(CMD_CTX, "stm32x failed to unlock device");
  1067. return ERROR_OK;
  1068. }
  1069. if (stm32x_write_options(bank) != ERROR_OK) {
  1070. command_print(CMD_CTX, "stm32x failed to lock device");
  1071. return ERROR_OK;
  1072. }
  1073. command_print(CMD_CTX, "stm32x unlocked.\n"
  1074. "INFO: a reset or power cycle is required "
  1075. "for the new settings to take effect.");
  1076. return ERROR_OK;
  1077. }
  1078. COMMAND_HANDLER(stm32x_handle_options_read_command)
  1079. {
  1080. uint32_t optionbyte;
  1081. struct target *target = NULL;
  1082. struct stm32x_flash_bank *stm32x_info = NULL;
  1083. if (CMD_ARGC < 1)
  1084. return ERROR_COMMAND_SYNTAX_ERROR;
  1085. struct flash_bank *bank;
  1086. int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
  1087. if (ERROR_OK != retval)
  1088. return retval;
  1089. stm32x_info = bank->driver_priv;
  1090. target = bank->target;
  1091. if (target->state != TARGET_HALTED) {
  1092. LOG_ERROR("Target not halted");
  1093. return ERROR_TARGET_NOT_HALTED;
  1094. }
  1095. retval = stm32x_check_operation_supported(bank);
  1096. if (ERROR_OK != retval)
  1097. return retval;
  1098. retval = target_read_u32(target, STM32_FLASH_OBR_B0, &optionbyte);
  1099. if (retval != ERROR_OK)
  1100. return retval;
  1101. command_print(CMD_CTX, "Option Byte: 0x%" PRIx32 "", optionbyte);
  1102. if (buf_get_u32((uint8_t *)&optionbyte, OPT_ERROR, 1))
  1103. command_print(CMD_CTX, "Option Byte Complement Error");
  1104. if (buf_get_u32((uint8_t *)&optionbyte, OPT_READOUT, 1))
  1105. command_print(CMD_CTX, "Readout Protection On");
  1106. else
  1107. command_print(CMD_CTX, "Readout Protection Off");
  1108. if (buf_get_u32((uint8_t *)&optionbyte, OPT_RDWDGSW, 1))
  1109. command_print(CMD_CTX, "Software Watchdog");
  1110. else
  1111. command_print(CMD_CTX, "Hardware Watchdog");
  1112. if (buf_get_u32((uint8_t *)&optionbyte, OPT_RDRSTSTOP, 1))
  1113. command_print(CMD_CTX, "Stop: No reset generated");
  1114. else
  1115. command_print(CMD_CTX, "Stop: Reset generated");
  1116. if (buf_get_u32((uint8_t *)&optionbyte, OPT_RDRSTSTDBY, 1))
  1117. command_print(CMD_CTX, "Standby: No reset generated");
  1118. else
  1119. command_print(CMD_CTX, "Standby: Reset generated");
  1120. if (stm32x_info->has_dual_banks) {
  1121. if (buf_get_u32((uint8_t *)&optionbyte, OPT_BFB2, 1))
  1122. command_print(CMD_CTX, "Boot: Bank 0");
  1123. else
  1124. command_print(CMD_CTX, "Boot: Bank 1");
  1125. }
  1126. return ERROR_OK;
  1127. }
  1128. COMMAND_HANDLER(stm32x_handle_options_write_command)
  1129. {
  1130. struct target *target = NULL;
  1131. struct stm32x_flash_bank *stm32x_info = NULL;
  1132. uint16_t optionbyte = 0xF8;
  1133. if (CMD_ARGC < 4)
  1134. return ERROR_COMMAND_SYNTAX_ERROR;
  1135. struct flash_bank *bank;
  1136. int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
  1137. if (ERROR_OK != retval)
  1138. return retval;
  1139. stm32x_info = bank->driver_priv;
  1140. target = bank->target;
  1141. if (target->state != TARGET_HALTED) {
  1142. LOG_ERROR("Target not halted");
  1143. return ERROR_TARGET_NOT_HALTED;
  1144. }
  1145. retval = stm32x_check_operation_supported(bank);
  1146. if (ERROR_OK != retval)
  1147. return retval;
  1148. /* REVISIT: ignores some options which we will display...
  1149. * and doesn't insist on the specified syntax.
  1150. */
  1151. /* OPT_RDWDGSW */
  1152. if (strcmp(CMD_ARGV[1], "SWWDG") == 0)
  1153. optionbyte |= (1 << 0);
  1154. else /* REVISIT must be "HWWDG" then ... */
  1155. optionbyte &= ~(1 << 0);
  1156. /* OPT_RDRSTSTOP */
  1157. if (strcmp(CMD_ARGV[2], "NORSTSTOP") == 0)
  1158. optionbyte |= (1 << 1);
  1159. else /* REVISIT must be "RSTSTNDBY" then ... */
  1160. optionbyte &= ~(1 << 1);
  1161. /* OPT_RDRSTSTDBY */
  1162. if (strcmp(CMD_ARGV[3], "NORSTSTNDBY") == 0)
  1163. optionbyte |= (1 << 2);
  1164. else /* REVISIT must be "RSTSTOP" then ... */
  1165. optionbyte &= ~(1 << 2);
  1166. if (CMD_ARGC > 4 && stm32x_info->has_dual_banks) {
  1167. /* OPT_BFB2 */
  1168. if (strcmp(CMD_ARGV[4], "BOOT0") == 0)
  1169. optionbyte |= (1 << 3);
  1170. else
  1171. optionbyte &= ~(1 << 3);
  1172. }
  1173. if (stm32x_erase_options(bank) != ERROR_OK) {
  1174. command_print(CMD_CTX, "stm32x failed to erase options");
  1175. return ERROR_OK;
  1176. }
  1177. stm32x_info->option_bytes.user_options = optionbyte;
  1178. if (stm32x_write_options(bank) != ERROR_OK) {
  1179. command_print(CMD_CTX, "stm32x failed to write options");
  1180. return ERROR_OK;
  1181. }
  1182. command_print(CMD_CTX, "stm32x write options complete.\n"
  1183. "INFO: a reset or power cycle is required "
  1184. "for the new settings to take effect.");
  1185. return ERROR_OK;
  1186. }
  1187. static int stm32x_mass_erase(struct flash_bank *bank)
  1188. {
  1189. struct target *target = bank->target;
  1190. if (target->state != TARGET_HALTED) {
  1191. LOG_ERROR("Target not halted");
  1192. return ERROR_TARGET_NOT_HALTED;
  1193. }
  1194. /* unlock option flash registers */
  1195. int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
  1196. if (retval != ERROR_OK)
  1197. return retval;
  1198. retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
  1199. if (retval != ERROR_OK)
  1200. return retval;
  1201. /* mass erase flash memory */
  1202. retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_MER);
  1203. if (retval != ERROR_OK)
  1204. return retval;
  1205. retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR),
  1206. FLASH_MER | FLASH_STRT);
  1207. if (retval != ERROR_OK)
  1208. return retval;
  1209. retval = stm32x_wait_status_busy(bank, 100);
  1210. if (retval != ERROR_OK)
  1211. return retval;
  1212. retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
  1213. if (retval != ERROR_OK)
  1214. return retval;
  1215. return ERROR_OK;
  1216. }
  1217. COMMAND_HANDLER(stm32x_handle_mass_erase_command)
  1218. {
  1219. int i;
  1220. if (CMD_ARGC < 1)
  1221. return ERROR_COMMAND_SYNTAX_ERROR;
  1222. struct flash_bank *bank;
  1223. int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
  1224. if (ERROR_OK != retval)
  1225. return retval;
  1226. retval = stm32x_mass_erase(bank);
  1227. if (retval == ERROR_OK) {
  1228. /* set all sectors as erased */
  1229. for (i = 0; i < bank->num_sectors; i++)
  1230. bank->sectors[i].is_erased = 1;
  1231. command_print(CMD_CTX, "stm32x mass erase complete");
  1232. } else
  1233. command_print(CMD_CTX, "stm32x mass erase failed");
  1234. return retval;
  1235. }
  1236. static const struct command_registration stm32x_exec_command_handlers[] = {
  1237. {
  1238. .name = "lock",
  1239. .handler = stm32x_handle_lock_command,
  1240. .mode = COMMAND_EXEC,
  1241. .usage = "bank_id",
  1242. .help = "Lock entire flash device.",
  1243. },
  1244. {
  1245. .name = "unlock",
  1246. .handler = stm32x_handle_unlock_command,
  1247. .mode = COMMAND_EXEC,
  1248. .usage = "bank_id",
  1249. .help = "Unlock entire protected flash device.",
  1250. },
  1251. {
  1252. .name = "mass_erase",
  1253. .handler = stm32x_handle_mass_erase_command,
  1254. .mode = COMMAND_EXEC,
  1255. .usage = "bank_id",
  1256. .help = "Erase entire flash device.",
  1257. },
  1258. {
  1259. .name = "options_read",
  1260. .handler = stm32x_handle_options_read_command,
  1261. .mode = COMMAND_EXEC,
  1262. .usage = "bank_id",
  1263. .help = "Read and display device option byte.",
  1264. },
  1265. {
  1266. .name = "options_write",
  1267. .handler = stm32x_handle_options_write_command,
  1268. .mode = COMMAND_EXEC,
  1269. .usage = "bank_id ('SWWDG'|'HWWDG') "
  1270. "('RSTSTNDBY'|'NORSTSTNDBY') "
  1271. "('RSTSTOP'|'NORSTSTOP')",
  1272. .help = "Replace bits in device option byte.",
  1273. },
  1274. COMMAND_REGISTRATION_DONE
  1275. };
  1276. static const struct command_registration stm32x_command_handlers[] = {
  1277. {
  1278. .name = "stm32f1x",
  1279. .mode = COMMAND_ANY,
  1280. .help = "stm32f1x flash command group",
  1281. .usage = "",
  1282. .chain = stm32x_exec_command_handlers,
  1283. },
  1284. COMMAND_REGISTRATION_DONE
  1285. };
  1286. struct flash_driver stm32f1x_flash = {
  1287. .name = "stm32f1x",
  1288. .commands = stm32x_command_handlers,
  1289. .flash_bank_command = stm32x_flash_bank_command,
  1290. .erase = stm32x_erase,
  1291. .protect = stm32x_protect,
  1292. .write = stm32x_write,
  1293. .read = default_flash_read,
  1294. .probe = stm32x_probe,
  1295. .auto_probe = stm32x_auto_probe,
  1296. .erase_check = default_flash_blank_check,
  1297. .protect_check = stm32x_protect_check,
  1298. .info = get_stm32x_info,
  1299. };