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  1. \input texinfo @c -*-texinfo-*-
  2. @c %**start of header
  3. @setfilename
  4. @settitle OpenOCD User's Guide
  5. @dircategory Development
  6. @direntry
  7. * OpenOCD: (openocd). OpenOCD User's Guide
  8. @end direntry
  9. @paragraphindent 0
  10. @c %**end of header
  11. @include version.texi
  12. @copying
  13. This User's Guide documents
  14. release @value{VERSION},
  15. dated @value{UPDATED},
  16. of the Open On-Chip Debugger (OpenOCD).
  17. @itemize @bullet
  18. @item Copyright @copyright{} 2008 The OpenOCD Project
  19. @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{}
  20. @item Copyright @copyright{} 2008 Oyvind Harboe @email{}
  21. @item Copyright @copyright{} 2008 Duane Ellis @email{}
  22. @item Copyright @copyright{} 2009 David Brownell
  23. @end itemize
  24. @quotation
  25. Permission is granted to copy, distribute and/or modify this document
  26. under the terms of the GNU Free Documentation License, Version 1.2 or
  27. any later version published by the Free Software Foundation; with no
  28. Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
  29. Texts. A copy of the license is included in the section entitled ``GNU
  30. Free Documentation License''.
  31. @end quotation
  32. @end copying
  33. @titlepage
  34. @titlefont{@emph{Open On-Chip Debugger:}}
  35. @sp 1
  36. @title OpenOCD User's Guide
  37. @subtitle for release @value{VERSION}
  38. @subtitle @value{UPDATED}
  39. @page
  40. @vskip 0pt plus 1filll
  41. @insertcopying
  42. @end titlepage
  43. @summarycontents
  44. @contents
  45. @ifnottex
  46. @node Top
  47. @top OpenOCD User's Guide
  48. @insertcopying
  49. @end ifnottex
  50. @menu
  51. * About:: About OpenOCD
  52. * Developers:: OpenOCD Developers
  53. * JTAG Hardware Dongles:: JTAG Hardware Dongles
  54. * About JIM-Tcl:: About JIM-Tcl
  55. * Running:: Running OpenOCD
  56. * OpenOCD Project Setup:: OpenOCD Project Setup
  57. * Config File Guidelines:: Config File Guidelines
  58. * Daemon Configuration:: Daemon Configuration
  59. * Interface - Dongle Configuration:: Interface - Dongle Configuration
  60. * Reset Configuration:: Reset Configuration
  61. * TAP Declaration:: TAP Declaration
  62. * CPU Configuration:: CPU Configuration
  63. * Flash Commands:: Flash Commands
  64. * NAND Flash Commands:: NAND Flash Commands
  65. * PLD/FPGA Commands:: PLD/FPGA Commands
  66. * General Commands:: General Commands
  67. * Architecture and Core Commands:: Architecture and Core Commands
  68. * JTAG Commands:: JTAG Commands
  69. * Boundary Scan Commands:: Boundary Scan Commands
  70. * TFTP:: TFTP
  71. * GDB and OpenOCD:: Using GDB and OpenOCD
  72. * Tcl Scripting API:: Tcl Scripting API
  73. * Upgrading:: Deprecated/Removed Commands
  74. * Target Library:: Target Library
  75. * FAQ:: Frequently Asked Questions
  76. * Tcl Crash Course:: Tcl Crash Course
  77. * License:: GNU Free Documentation License
  78. @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
  79. @comment case issue with ``Index.html'' and ``index.html''
  80. @comment Occurs when creating ``--html --no-split'' output
  81. @comment This fix is based on:
  82. * OpenOCD Concept Index:: Concept Index
  83. * Command and Driver Index:: Command and Driver Index
  84. @end menu
  85. @node About
  86. @unnumbered About
  87. @cindex about
  88. OpenOCD was created by Dominic Rath as part of a diploma thesis written at the
  89. University of Applied Sciences Augsburg (@uref{}).
  90. Since that time, the project has grown into an active open-source project,
  91. supported by a diverse community of software and hardware developers from
  92. around the world.
  93. @section What is OpenOCD?
  94. @cindex TAP
  95. @cindex JTAG
  96. The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
  97. in-system programming and boundary-scan testing for embedded target
  98. devices.
  99. @b{JTAG:} OpenOCD uses a ``hardware interface dongle'' to communicate
  100. with the JTAG (IEEE 1149.1) compliant TAPs on your target board.
  101. A @dfn{TAP} is a ``Test Access Port'', a module which processes
  102. special instructions and data. TAPs are daisy-chained within and
  103. between chips and boards.
  104. @b{Dongles:} OpenOCD currently supports many types of hardware dongles: USB
  105. based, parallel port based, and other standalone boxes that run
  106. OpenOCD internally. @xref{JTAG Hardware Dongles}.
  107. @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
  108. ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x) and
  109. Cortex-M3 (Stellaris LM3 and ST STM32) based cores to be
  110. debugged via the GDB protocol.
  111. @b{Flash Programing:} Flash writing is supported for external CFI
  112. compatible NOR flashes (Intel and AMD/Spansion command set) and several
  113. internal flashes (LPC2000, AT91SAM7, AT91SAM3U, STR7x, STR9x, LM3, and
  114. STM32x). Preliminary support for various NAND flash controllers
  115. (LPC3180, Orion, S3C24xx, more) controller is included.
  116. @section OpenOCD Web Site
  117. The OpenOCD web site provides the latest public news from the community:
  118. @uref{}
  119. @section Latest User's Guide:
  120. The user's guide you are now reading may not be the latest one
  121. available. A version for more recent code may be available.
  122. Its HTML form is published irregularly at:
  123. @uref{}
  124. PDF form is likewise published at:
  125. @uref{}
  126. @section OpenOCD User's Forum
  127. There is an OpenOCD forum (phpBB) hosted by SparkFun:
  128. @uref{}
  129. @node Developers
  130. @chapter OpenOCD Developer Resources
  131. @cindex developers
  132. If you are interested in improving the state of OpenOCD's debugging and
  133. testing support, new contributions will be welcome. Motivated developers
  134. can produce new target, flash or interface drivers, improve the
  135. documentation, as well as more conventional bug fixes and enhancements.
  136. The resources in this chapter are available for developers wishing to explore
  137. or expand the OpenOCD source code.
  138. @section OpenOCD Subversion Repository
  139. You can download the current SVN version with an SVN client of your
  140. choice from the following repositories:
  141. @uref{svn://}
  142. or
  143. @uref{}
  144. Using the SVN command line client, you can use the following command to
  145. fetch the latest version (make sure there is no (non-svn) directory
  146. called "openocd" in the current directory):
  147. svn checkout svn:// openocd
  148. If you prefer GIT based tools, the @command{git-svn} package works too:
  149. git svn clone -s svn://
  150. The ``README'' file contains the instructions for building the project
  151. from the repository.
  152. Developers that want to contribute patches to the OpenOCD system are
  153. @b{strongly} encouraged to base their work off of the most recent trunk
  154. revision. Patches created against older versions may require additional
  155. work from their submitter in order to be updated for newer releases.
  156. @section Doxygen Developer Manual
  157. During the development of the 0.2.0 release, the OpenOCD project began
  158. providing a Doxygen reference manual. This document contains more
  159. technical information about the software internals, development
  160. processes, and similar documentation:
  161. @uref{}
  162. This document is a work-in-progress, but contributions would be welcome
  163. to fill in the gaps. All of the source files are provided in-tree,
  164. listed in the Doxyfile configuration in the top of the repository trunk.
  165. @section OpenOCD Developer Mailing List
  166. The OpenOCD Developer Mailing List provides the primary means of
  167. communication between developers:
  168. @uref{}
  169. All drivers developers are enouraged to also subscribe to the list of
  170. SVN commits to keep pace with the ongoing changes:
  171. @uref{}
  172. @node JTAG Hardware Dongles
  173. @chapter JTAG Hardware Dongles
  174. @cindex dongles
  175. @cindex FTDI
  176. @cindex wiggler
  177. @cindex zy1000
  178. @cindex printer port
  179. @cindex USB Adapter
  180. @cindex RTCK
  181. Defined: @b{dongle}: A small device that plugins into a computer and serves as
  182. an adapter .... [snip]
  183. In the OpenOCD case, this generally refers to @b{a small adapater} one
  184. attaches to your computer via USB or the Parallel Printer Port. The
  185. execption being the Zylin ZY1000 which is a small box you attach via
  186. an ethernet cable. The Zylin ZY1000 has the advantage that it does not
  187. require any drivers to be installed on the developer PC. It also has
  188. a built in web interface. It supports RTCK/RCLK or adaptive clocking
  189. and has a built in relay to power cycle targets remotely.
  190. @section Choosing a Dongle
  191. There are three things you should keep in mind when choosing a dongle.
  192. @enumerate
  193. @item @b{Voltage} What voltage is your target? 1.8, 2.8, 3.3, or 5V? Does your dongle support it?
  194. @item @b{Connection} Printer Ports - Does your computer have one?
  195. @item @b{Connection} Is that long printer bit-bang cable practical?
  196. @item @b{RTCK} Do you require RTCK? Also known as ``adaptive clocking''
  197. @end enumerate
  198. @section Stand alone Systems
  199. @b{ZY1000} See: @url{} Technically, not a
  200. dongle, but a standalone box. The ZY1000 has the advantage that it does
  201. not require any drivers installed on the developer PC. It also has
  202. a built in web interface. It supports RTCK/RCLK or adaptive clocking
  203. and has a built in relay to power cycle targets remotely.
  204. @section USB FT2232 Based
  205. There are many USB JTAG dongles on the market, many of them are based
  206. on a chip from ``Future Technology Devices International'' (FTDI)
  207. known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
  208. See: @url{} for more information.
  209. In summer 2009, USB high speed (480 Mbps) versions of these FTDI
  210. chips are starting to become available in JTAG adapters.
  211. @itemize @bullet
  212. @item @b{usbjtag}
  213. @* Link @url{}
  214. @item @b{jtagkey}
  215. @* See: @url{}
  216. @item @b{oocdlink}
  217. @* See: @url{} By Joern Kaipf
  218. @item @b{signalyzer}
  219. @* See: @url{}
  220. @item @b{evb_lm3s811}
  221. @* See: @url{} - The Stellaris LM3S811 eval board has an FTD2232C chip built in.
  222. @item @b{luminary_icdi}
  223. @* See: @url{} - Luminary In-Circuit Debug Interface (ICDI) Board, included in the Stellaris LM3S9B90 and LM3S9B92 Evaluation Kits.
  224. @item @b{olimex-jtag}
  225. @* See: @url{}
  226. @item @b{flyswatter}
  227. @* See: @url{}
  228. @item @b{turtelizer2}
  229. @* See:
  230. @uref{, Turtelizer 2}, or
  231. @url{}
  232. @item @b{comstick}
  233. @* Link: @url{}
  234. @item @b{stm32stick}
  235. @* Link @url{}
  236. @item @b{axm0432_jtag}
  237. @* Axiom AXM-0432 Link @url{}
  238. @item @b{cortino}
  239. @* Link @url{}
  240. @end itemize
  241. @section USB JLINK based
  242. There are several OEM versions of the Segger @b{JLINK} adapter. It is
  243. an example of a micro controller based JTAG adapter, it uses an
  244. AT91SAM764 internally.
  245. @itemize @bullet
  246. @item @b{ATMEL SAMICE} Only works with ATMEL chips!
  247. @* Link: @url{}
  248. @item @b{SEGGER JLINK}
  249. @* Link: @url{}
  250. @item @b{IAR J-Link}
  251. @* Link: @url{}
  252. @end itemize
  253. @section USB RLINK based
  254. Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer, permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for SWD and not JTAG, thus not supported.
  255. @itemize @bullet
  256. @item @b{Raisonance RLink}
  257. @* Link: @url{}
  258. @item @b{STM32 Primer}
  259. @* Link: @url{}
  260. @item @b{STM32 Primer2}
  261. @* Link: @url{}
  262. @end itemize
  263. @section USB Other
  264. @itemize @bullet
  265. @item @b{USBprog}
  266. @* Link: @url{} - which uses an Atmel MEGA32 and a UBN9604
  267. @item @b{USB - Presto}
  268. @* Link: @url{}
  269. @item @b{Versaloon-Link}
  270. @* Link: @url{}
  271. @item @b{ARM-JTAG-EW}
  272. @* Link: @url{}
  273. @end itemize
  274. @section IBM PC Parallel Printer Port Based
  275. The two well known ``JTAG Parallel Ports'' cables are the Xilnx DLC5
  276. and the MacGraigor Wiggler. There are many clones and variations of
  277. these on the market.
  278. @itemize @bullet
  279. @item @b{Wiggler} - There are many clones of this.
  280. @* Link: @url{}
  281. @item @b{DLC5} - From XILINX - There are many clones of this
  282. @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
  283. produced, PDF schematics are easily found and it is easy to make.
  284. @item @b{Amontec - JTAG Accelerator}
  285. @* Link: @url{}
  286. @item @b{GW16402}
  287. @* Link: @url{}
  288. @item @b{Wiggler2}
  289. @*@uref{,
  290. Improved parallel-port wiggler-style JTAG adapter}
  291. @item @b{Wiggler_ntrst_inverted}
  292. @* Yet another variation - See the source code, src/jtag/parport.c
  293. @item @b{old_amt_wiggler}
  294. @* Unknown - probably not on the market today
  295. @item @b{arm-jtag}
  296. @* Link: Most likely @url{} [another wiggler clone]
  297. @item @b{chameleon}
  298. @* Link: @url{}
  299. @item @b{Triton}
  300. @* Unknown.
  301. @item @b{Lattice}
  302. @* ispDownload from Lattice Semiconductor
  303. @url{}
  304. @item @b{flashlink}
  305. @* From ST Microsystems;
  306. @uref{,
  307. FlashLINK JTAG programing cable for PSD and uPSD}
  308. @end itemize
  309. @section Other...
  310. @itemize @bullet
  311. @item @b{ep93xx}
  312. @* An EP93xx based Linux machine using the GPIO pins directly.
  313. @item @b{at91rm9200}
  314. @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
  315. @end itemize
  316. @node About JIM-Tcl
  317. @chapter About JIM-Tcl
  318. @cindex JIM Tcl
  319. @cindex tcl
  320. OpenOCD includes a small ``Tcl Interpreter'' known as JIM-Tcl.
  321. This programming language provides a simple and extensible
  322. command interpreter.
  323. All commands presented in this Guide are extensions to JIM-Tcl.
  324. You can use them as simple commands, without needing to learn
  325. much of anything about Tcl.
  326. Alternatively, can write Tcl programs with them.
  327. You can learn more about JIM at its website, @url{}.
  328. @itemize @bullet
  329. @item @b{JIM vs. Tcl}
  330. @* JIM-TCL is a stripped down version of the well known Tcl language,
  331. which can be found here: @url{}. JIM-Tcl has far
  332. fewer features. JIM-Tcl is a single .C file and a single .H file and
  333. implements the basic Tcl command set. In contrast: Tcl 8.6 is a
  334. 4.2 MB .zip file containing 1540 files.
  335. @item @b{Missing Features}
  336. @* Our practice has been: Add/clone the real Tcl feature if/when
  337. needed. We welcome JIM Tcl improvements, not bloat.
  338. @item @b{Scripts}
  339. @* OpenOCD configuration scripts are JIM Tcl Scripts. OpenOCD's
  340. command interpreter today is a mixture of (newer)
  341. JIM-Tcl commands, and (older) the orginal command interpreter.
  342. @item @b{Commands}
  343. @* At the OpenOCD telnet command line (or via the GDB mon command) one
  344. can type a Tcl for() loop, set variables, etc.
  345. Some of the commands documented in this guide are implemented
  346. as Tcl scripts, from a @file{startup.tcl} file internal to the server.
  347. @item @b{Historical Note}
  348. @* JIM-Tcl was introduced to OpenOCD in spring 2008.
  349. @item @b{Need a crash course in Tcl?}
  350. @*@xref{Tcl Crash Course}.
  351. @end itemize
  352. @node Running
  353. @chapter Running
  354. @cindex command line options
  355. @cindex logfile
  356. @cindex directory search
  357. The @option{--help} option shows:
  358. @verbatim
  359. bash$ openocd --help
  360. --help | -h display this help
  361. --version | -v display OpenOCD version
  362. --file | -f use configuration file <name>
  363. --search | -s dir to search for config files and scripts
  364. --debug | -d set debug level <0-3>
  365. --log_output | -l redirect log output to file <name>
  366. --command | -c run <command>
  367. --pipe | -p use pipes when talking to gdb
  368. @end verbatim
  369. By default OpenOCD reads the file configuration file ``openocd.cfg''
  370. in the current directory. To specify a different (or multiple)
  371. configuration file, you can use the ``-f'' option. For example:
  372. @example
  373. openocd -f config1.cfg -f config2.cfg -f config3.cfg
  374. @end example
  375. Once started, OpenOCD runs as a daemon, waiting for connections from
  376. clients (Telnet, GDB, Other).
  377. If you are having problems, you can enable internal debug messages via
  378. the ``-d'' option.
  379. Also it is possible to interleave JIM-Tcl commands w/config scripts using the
  380. @option{-c} command line switch.
  381. To enable debug output (when reporting problems or working on OpenOCD
  382. itself), use the @option{-d} command line switch. This sets the
  383. @option{debug_level} to "3", outputting the most information,
  384. including debug messages. The default setting is "2", outputting only
  385. informational messages, warnings and errors. You can also change this
  386. setting from within a telnet or gdb session using @command{debug_level
  387. <n>} (@pxref{debug_level}).
  388. You can redirect all output from the daemon to a file using the
  389. @option{-l <logfile>} switch.
  390. Search paths for config/script files can be added to OpenOCD by using
  391. the @option{-s <search>} switch. The current directory and the OpenOCD
  392. target library is in the search path by default.
  393. For details on the @option{-p} option. @xref{Connecting to GDB}.
  394. Note! OpenOCD will launch the GDB & telnet server even if it can not
  395. establish a connection with the target. In general, it is possible for
  396. the JTAG controller to be unresponsive until the target is set up
  397. correctly via e.g. GDB monitor commands in a GDB init script.
  398. @node OpenOCD Project Setup
  399. @chapter OpenOCD Project Setup
  400. To use OpenOCD with your development projects, you need to do more than
  401. just connecting the JTAG adapter hardware (dongle) to your development board
  402. and then starting the OpenOCD server.
  403. You also need to configure that server so that it knows
  404. about that adapter and board, and helps your work.
  405. @section Hooking up the JTAG Adapter
  406. Today's most common case is a dongle with a JTAG cable on one side
  407. (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
  408. and a USB cable on the other.
  409. Instead of USB, some cables use Ethernet;
  410. older ones may use a PC parallel port, or even a serial port.
  411. @enumerate
  412. @item @emph{Start with power to your target board turned off},
  413. and nothing connected to your JTAG adapter.
  414. If you're particularly paranoid, unplug power to the board.
  415. It's important to have the ground signal properly set up,
  416. unless you are using a JTAG adapter which provides
  417. galvanic isolation between the target board and the
  418. debugging host.
  419. @item @emph{Be sure it's the right kind of JTAG connector.}
  420. If your dongle has a 20-pin ARM connector, you need some kind
  421. of adapter (or octopus, see below) to hook it up to
  422. boards using 14-pin or 10-pin connectors ... or to 20-pin
  423. connectors which don't use ARM's pinout.
  424. In the same vein, make sure the voltage levels are compatible.
  425. Not all JTAG adapters have the level shifters needed to work
  426. with 1.2 Volt boards.
  427. @item @emph{Be certain the cable is properly oriented} or you might
  428. damage your board. In most cases there are only two possible
  429. ways to connect the cable.
  430. Connect the JTAG cable from your adapter to the board.
  431. Be sure it's firmly connected.
  432. In the best case, the connector is keyed to physically
  433. prevent you from inserting it wrong.
  434. This is most often done using a slot on the board's male connector
  435. housing, which must match a key on the JTAG cable's female connector.
  436. If there's no housing, then you must look carefully and
  437. make sure pin 1 on the cable hooks up to pin 1 on the board.
  438. Ribbon cables are frequently all grey except for a wire on one
  439. edge, which is red. The red wire is pin 1.
  440. Sometimes dongles provide cables where one end is an ``octopus'' of
  441. color coded single-wire connectors, instead of a connector block.
  442. These are great when converting from one JTAG pinout to another,
  443. but are tedious to set up.
  444. Use these with connector pinout diagrams to help you match up the
  445. adapter signals to the right board pins.
  446. @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
  447. A USB, parallel, or serial port connector will go to the host which
  448. you are using to run OpenOCD.
  449. For Ethernet, consult the documentation and your network administrator.
  450. For USB based JTAG adapters you have an easy sanity check at this point:
  451. does the host operating system see the JTAG adapter?
  452. @item @emph{Connect the adapter's power supply, if needed.}
  453. This step is primarily for non-USB adapters,
  454. but sometimes USB adapters need extra power.
  455. @item @emph{Power up the target board.}
  456. Unless you just let the magic smoke escape,
  457. you're now ready to set up the OpenOCD server
  458. so you can use JTAG to work with that board.
  459. @end enumerate
  460. Talk with the OpenOCD server using
  461. telnet (@code{telnet localhost 4444} on many systems) or GDB.
  462. @xref{GDB and OpenOCD}.
  463. @section Project Directory
  464. There are many ways you can configure OpenOCD and start it up.
  465. A simple way to organize them all involves keeping a
  466. single directory for your work with a given board.
  467. When you start OpenOCD from that directory,
  468. it searches there first for configuration files, scripts,
  469. and for code you upload to the target board.
  470. It is also the natural place to write files,
  471. such as log files and data you download from the board.
  472. @section Configuration Basics
  473. There are two basic ways of configuring OpenOCD, and
  474. a variety of ways you can mix them.
  475. Think of the difference as just being how you start the server:
  476. @itemize
  477. @item Many @option{-f file} or @option{-c command} options on the command line
  478. @item No options, but a @dfn{user config file}
  479. in the current directory named @file{openocd.cfg}
  480. @end itemize
  481. Here is an example @file{openocd.cfg} file for a setup
  482. using a Signalyzer FT2232-based JTAG adapter to talk to
  483. a board with an Atmel AT91SAM7X256 microcontroller:
  484. @example
  485. source [find interface/signalyzer.cfg]
  486. # GDB can also flash my flash!
  487. gdb_memory_map enable
  488. gdb_flash_program enable
  489. source [find target/sam7x256.cfg]
  490. @end example
  491. Here is the command line equivalent of that configuration:
  492. @example
  493. openocd -f interface/signalyzer.cfg \
  494. -c "gdb_memory_map enable" \
  495. -c "gdb_flash_program enable" \
  496. -f target/sam7x256.cfg
  497. @end example
  498. You could wrap such long command lines in shell scripts,
  499. each supporting a different development task.
  500. One might re-flash the board with a specific firmware version.
  501. Another might set up a particular debugging or run-time environment.
  502. Here we will focus on the simpler solution: one user config
  503. file, including basic configuration plus any TCL procedures
  504. to simplify your work.
  505. @section User Config Files
  506. @cindex config file, user
  507. @cindex user config file
  508. @cindex config file, overview
  509. A user configuration file ties together all the parts of a project
  510. in one place.
  511. One of the following will match your situation best:
  512. @itemize
  513. @item Ideally almost everything comes from configuration files
  514. provided by someone else.
  515. For example, OpenOCD distributes a @file{scripts} directory
  516. (probably in @file{/usr/share/openocd/scripts} on Linux).
  517. Board and tool vendors can provide these too, as can individual
  518. user sites; the @option{-s} command line option lets you say
  519. where to find these files. (@xref{Running}.)
  520. The AT91SAM7X256 example above works this way.
  521. Three main types of non-user configuration file each have their
  522. own subdirectory in the @file{scripts} directory:
  523. @enumerate
  524. @item @b{interface} -- one for each kind of JTAG adapter/dongle
  525. @item @b{board} -- one for each different board
  526. @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
  527. @end enumerate
  528. Best case: include just two files, and they handle everything else.
  529. The first is an interface config file.
  530. The second is board-specific, and it sets up the JTAG TAPs and
  531. their GDB targets (by deferring to some @file{target.cfg} file),
  532. declares all flash memory, and leaves you nothing to do except
  533. meet your deadline:
  534. @example
  535. source [find interface/olimex-jtag-tiny.cfg]
  536. source [find board/csb337.cfg]
  537. @end example
  538. Boards with a single microcontroller often won't need more
  539. than the target config file, as in the AT91SAM7X256 example.
  540. That's because there is no external memory (flash, DDR RAM), and
  541. the board differences are encapsulated by application code.
  542. @item You can often reuse some standard config files but
  543. need to write a few new ones, probably a @file{board.cfg} file.
  544. You will be using commands described later in this User's Guide,
  545. and working with the guidelines in the next chapter.
  546. For example, there may be configuration files for your JTAG adapter
  547. and target chip, but you need a new board-specific config file
  548. giving access to your particular flash chips.
  549. Or you might need to write another target chip configuration file
  550. for a new chip built around the Cortex M3 core.
  551. @quotation Note
  552. When you write new configuration files, please submit
  553. them for inclusion in the next OpenOCD release.
  554. For example, a @file{board/newboard.cfg} file will help the
  555. next users of that board, and a @file{target/newcpu.cfg}
  556. will help support users of any board using that chip.
  557. @end quotation
  558. @item
  559. You may may need to write some C code.
  560. It may be as simple as a supporting a new ft2232 or parport
  561. based dongle; a bit more involved, like a NAND or NOR flash
  562. controller driver; or a big piece of work like supporting
  563. a new chip architecture.
  564. @end itemize
  565. Reuse the existing config files when you can.
  566. Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
  567. You may find a board configuration that's a good example to follow.
  568. When you write config files, separate the reusable parts
  569. (things every user of that interface, chip, or board needs)
  570. from ones specific to your environment and debugging approach.
  571. For example, a @code{gdb-attach} event handler that invokes
  572. the @command{reset init} command will interfere with debugging
  573. early boot code, which performs some of the same actions
  574. that the @code{reset-init} event handler does.
  575. Likewise, the @command{arm9tdmi vector_catch} command (or
  576. its @command{xscale vector_catch} sibling) can be a timesaver
  577. during some debug sessions, but don't make everyone use that either.
  578. Keep those kinds of debugging aids in your user config file,
  579. along with messaging and tracing setup.
  580. (@xref{Software Debug Messages and Tracing}.)
  581. TCP/IP port configuration is another example of something which
  582. is environment-specific, and should only appear in
  583. a user config file. @xref{TCP/IP Ports}.
  584. @section Project-Specific Utilities
  585. A few project-specific utility
  586. routines may well speed up your work.
  587. Write them, and keep them in your project's user config file.
  588. For example, if you are making a boot loader work on a
  589. board, it's nice to be able to debug the ``after it's
  590. loaded to RAM'' parts separately from the finicky early
  591. code which sets up the DDR RAM controller and clocks.
  592. A script like this one, or a more GDB-aware sibling,
  593. may help:
  594. @example
  595. proc ramboot @{ @} @{
  596. # Reset, running the target's "reset-init" scripts
  597. # to initialize clocks and the DDR RAM controller.
  598. # Leave the CPU halted.
  599. reset init
  600. # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
  601. load_image u-boot.bin 0x20000000
  602. # Start running.
  603. resume 0x20000000
  604. @}
  605. @end example
  606. Then once that code is working you will need to make it
  607. boot from NOR flash; a different utility would help.
  608. Alternatively, some developers write to flash using GDB.
  609. (You might use a similar script if you're working with a flash
  610. based microcontroller application instead of a boot loader.)
  611. @example
  612. proc newboot @{ @} @{
  613. # Reset, leaving the CPU halted. The "reset-init" event
  614. # proc gives faster access to the CPU and to NOR flash;
  615. # "reset halt" would be slower.
  616. reset init
  617. # Write standard version of U-Boot into the first two
  618. # sectors of NOR flash ... the standard version should
  619. # do the same lowlevel init as "reset-init".
  620. flash protect 0 0 1 off
  621. flash erase_sector 0 0 1
  622. flash write_bank 0 u-boot.bin 0x0
  623. flash protect 0 0 1 on
  624. # Reboot from scratch using that new boot loader.
  625. reset run
  626. @}
  627. @end example
  628. You may need more complicated utility procedures when booting
  629. from NAND.
  630. That often involves an extra bootloader stage,
  631. running from on-chip SRAM to perform DDR RAM setup so it can load
  632. the main bootloader code (which won't fit into that SRAM).
  633. Other helper scripts might be used to write production system images,
  634. involving considerably more than just a three stage bootloader.
  635. @node Config File Guidelines
  636. @chapter Config File Guidelines
  637. This chapter is aimed at any user who needs to write a config file,
  638. including developers and integrators of OpenOCD and any user who
  639. needs to get a new board working smoothly.
  640. It provides guidelines for creating those files.
  641. You should find the following directories under @t{$(INSTALLDIR)/scripts}:
  642. @itemize @bullet
  643. @item @file{interface} ...
  644. think JTAG Dongle. Files that configure JTAG adapters go here.
  645. @item @file{board} ...
  646. think Circuit Board, PWA, PCB, they go by many names. Board files
  647. contain initialization items that are specific to a board. For
  648. example, the SDRAM initialization sequence for the board, or the type
  649. of external flash and what address it uses. Any initialization
  650. sequence to enable that external flash or SDRAM should be found in the
  651. board file. Boards may also contain multiple targets: two CPUs; or
  652. a CPU and an FPGA or CPLD.
  653. @item @file{target} ...
  654. think chip. The ``target'' directory represents the JTAG TAPs
  655. on a chip
  656. which OpenOCD should control, not a board. Two common types of targets
  657. are ARM chips and FPGA or CPLD chips.
  658. When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
  659. the target config file defines all of them.
  660. @end itemize
  661. The @file{openocd.cfg} user config
  662. file may override features in any of the above files by
  663. setting variables before sourcing the target file, or by adding
  664. commands specific to their situation.
  665. @section Interface Config Files
  666. The user config file
  667. should be able to source one of these files with a command like this:
  668. @example
  669. source [find interface/FOOBAR.cfg]
  670. @end example
  671. A preconfigured interface file should exist for every interface in use
  672. today, that said, perhaps some interfaces have only been used by the
  673. sole developer who created it.
  674. A separate chapter gives information about how to set these up.
  675. @xref{Interface - Dongle Configuration}.
  676. Read the OpenOCD source code if you have a new kind of hardware interface
  677. and need to provide a driver for it.
  678. @section Board Config Files
  679. @cindex config file, board
  680. @cindex board config file
  681. The user config file
  682. should be able to source one of these files with a command like this:
  683. @example
  684. source [find board/FOOBAR.cfg]
  685. @end example
  686. The point of a board config file is to package everything
  687. about a given board that user config files need to know.
  688. In summary the board files should contain (if present)
  689. @enumerate
  690. @item One or more @command{source [target/...cfg]} statements
  691. @item NOR flash configuration (@pxref{NOR Configuration})
  692. @item NAND flash configuration (@pxref{NAND Configuration})
  693. @item Target @code{reset} handlers for SDRAM and I/O configuration
  694. @item JTAG adapter reset configuration (@pxref{Reset Configuration})
  695. @item All things that are not ``inside a chip''
  696. @end enumerate
  697. Generic things inside target chips belong in target config files,
  698. not board config files. So for example a @code{reset-init} event
  699. handler should know board-specific oscillator and PLL parameters,
  700. which it passes to target-specific utility code.
  701. The most complex task of a board config file is creating such a
  702. @code{reset-init} event handler.
  703. Define those handlers last, after you verify the rest of the board
  704. configuration works.
  705. @subsection Communication Between Config files
  706. In addition to target-specific utility code, another way that
  707. board and target config files communicate is by following a
  708. convention on how to use certain variables.
  709. The full Tcl/Tk language supports ``namespaces'', but JIM-Tcl does not.
  710. Thus the rule we follow in OpenOCD is this: Variables that begin with
  711. a leading underscore are temporary in nature, and can be modified and
  712. used at will within a target configuration file.
  713. Complex board config files can do the things like this,
  714. for a board with three chips:
  715. @example
  716. # Chip #1: PXA270 for network side, big endian
  717. set CHIPNAME network
  718. set ENDIAN big
  719. source [find target/pxa270.cfg]
  720. # on return: _TARGETNAME = network.cpu
  721. # other commands can refer to the "network.cpu" target.
  722. $_TARGETNAME configure .... events for this CPU..
  723. # Chip #2: PXA270 for video side, little endian
  724. set CHIPNAME video
  725. set ENDIAN little
  726. source [find target/pxa270.cfg]
  727. # on return: _TARGETNAME = video.cpu
  728. # other commands can refer to the "video.cpu" target.
  729. $_TARGETNAME configure .... events for this CPU..
  730. # Chip #3: Xilinx FPGA for glue logic
  731. set CHIPNAME xilinx
  732. unset ENDIAN
  733. source [find target/spartan3.cfg]
  734. @end example
  735. That example is oversimplified because it doesn't show any flash memory,
  736. or the @code{reset-init} event handlers to initialize external DRAM
  737. or (assuming it needs it) load a configuration into the FPGA.
  738. Such features are usually needed for low-level work with many boards,
  739. where ``low level'' implies that the board initialization software may
  740. not be working. (That's a common reason to need JTAG tools. Another
  741. is to enable working with microcontroller-based systems, which often
  742. have no debugging support except a JTAG connector.)
  743. Target config files may also export utility functions to board and user
  744. config files. Such functions should use name prefixes, to help avoid
  745. naming collisions.
  746. Board files could also accept input variables from user config files.
  747. For example, there might be a @code{J4_JUMPER} setting used to identify
  748. what kind of flash memory a development board is using, or how to set
  749. up other clocks and peripherals.
  750. @subsection Variable Naming Convention
  751. @cindex variable names
  752. Most boards have only one instance of a chip.
  753. However, it should be easy to create a board with more than
  754. one such chip (as shown above).
  755. Accordingly, we encourage these conventions for naming
  756. variables associated with different @file{target.cfg} files,
  757. to promote consistency and
  758. so that board files can override target defaults.
  759. Inputs to target config files include:
  760. @itemize @bullet
  761. @item @code{CHIPNAME} ...
  762. This gives a name to the overall chip, and is used as part of
  763. tap identifier dotted names.
  764. While the default is normally provided by the chip manufacturer,
  765. board files may need to distinguish between instances of a chip.
  766. @item @code{ENDIAN} ...
  767. By default @option{little} - although chips may hard-wire @option{big}.
  768. Chips that can't change endianness don't need to use this variable.
  769. @item @code{CPUTAPID} ...
  770. When OpenOCD examines the JTAG chain, it can be told verify the
  771. chips against the JTAG IDCODE register.
  772. The target file will hold one or more defaults, but sometimes the
  773. chip in a board will use a different ID (perhaps a newer revision).
  774. @end itemize
  775. Outputs from target config files include:
  776. @itemize @bullet
  777. @item @code{_TARGETNAME} ...
  778. By convention, this variable is created by the target configuration
  779. script. The board configuration file may make use of this variable to
  780. configure things like a ``reset init'' script, or other things
  781. specific to that board and that target.
  782. If the chip has 2 targets, the names are @code{_TARGETNAME0},
  783. @code{_TARGETNAME1}, ... etc.
  784. @end itemize
  785. @subsection The reset-init Event Handler
  786. @cindex event, reset-init
  787. @cindex reset-init handler
  788. Board config files run in the OpenOCD configuration stage;
  789. they can't use TAPs or targets, since they haven't been
  790. fully set up yet.
  791. This means you can't write memory or access chip registers;
  792. you can't even verify that a flash chip is present.
  793. That's done later in event handlers, of which the target @code{reset-init}
  794. handler is one of the most important.
  795. Except on microcontrollers, the basic job of @code{reset-init} event
  796. handlers is setting up flash and DRAM, as normally handled by boot loaders.
  797. Microcontrollers rarely use boot loaders; they run right out of their
  798. on-chip flash and SRAM memory. But they may want to use one of these
  799. handlers too, if just for developer convenience.
  800. @quotation Note
  801. Because this is so very board-specific, and chip-specific, no examples
  802. are included here.
  803. Instead, look at the board config files distributed with OpenOCD.
  804. If you have a boot loader, its source code may also be useful.
  805. @end quotation
  806. Some of this code could probably be shared between different boards.
  807. For example, setting up a DRAM controller often doesn't differ by
  808. much except the bus width (16 bits or 32?) and memory timings, so a
  809. reusable TCL procedure loaded by the @file{target.cfg} file might take
  810. those as parameters.
  811. Similarly with oscillator, PLL, and clock setup;
  812. and disabling the watchdog.
  813. Structure the code cleanly, and provide comments to help
  814. the next developer doing such work.
  815. (@emph{You might be that next person} trying to reuse init code!)
  816. The last thing normally done in a @code{reset-init} handler is probing
  817. whatever flash memory was configured. For most chips that needs to be
  818. done while the associated target is halted, either because JTAG memory
  819. access uses the CPU or to prevent conflicting CPU access.
  820. @subsection JTAG Clock Rate
  821. Before your @code{reset-init} handler has set up
  822. the PLLs and clocking, you may need to use
  823. a low JTAG clock rate; then you'd increase it later.
  824. (The rule of thumb for ARM-based processors is 1/8 the CPU clock.)
  825. If the board supports adaptive clocking, use the @command{jtag_rclk}
  826. command, in case your board is used with JTAG adapter which
  827. also supports it. Otherwise use @command{jtag_khz}.
  828. Set the slow rate at the beginning of the reset sequence,
  829. and the faster rate as soon as the clocks are at full speed.
  830. @section Target Config Files
  831. @cindex config file, target
  832. @cindex target config file
  833. Board config files communicate with target config files using
  834. naming conventions as described above, and may source one or
  835. more target config files like this:
  836. @example
  837. source [find target/FOOBAR.cfg]
  838. @end example
  839. The point of a target config file is to package everything
  840. about a given chip that board config files need to know.
  841. In summary the target files should contain
  842. @enumerate
  843. @item Set defaults
  844. @item Add TAPs to the scan chain
  845. @item Add CPU targets (includes GDB support)
  846. @item CPU/Chip/CPU-Core specific features
  847. @item On-Chip flash
  848. @end enumerate
  849. As a rule of thumb, a target file sets up only one chip.
  850. For a microcontroller, that will often include a single TAP,
  851. which is a CPU needing a GDB target, and its on-chip flash.
  852. More complex chips may include multiple TAPs, and the target
  853. config file may need to define them all before OpenOCD
  854. can talk to the chip.
  855. For example, some phone chips have JTAG scan chains that include
  856. an ARM core for operating system use, a DSP,
  857. another ARM core embedded in an image processing engine,
  858. and other processing engines.
  859. @subsection Default Value Boiler Plate Code
  860. All target configuration files should start with code like this,
  861. letting board config files express environment-specific
  862. differences in how things should be set up.
  863. @example
  864. # Boards may override chip names, perhaps based on role,
  865. # but the default should match what the vendor uses
  866. if @{ [info exists CHIPNAME] @} @{
  868. @} else @{
  869. set _CHIPNAME sam7x256
  870. @}
  871. # ONLY use ENDIAN with targets that can change it.
  872. if @{ [info exists ENDIAN] @} @{
  873. set _ENDIAN $ENDIAN
  874. @} else @{
  875. set _ENDIAN little
  876. @}
  877. # TAP identifiers may change as chips mature, for example with
  878. # new revision fields (the "3" here). Pick a good default; you
  879. # can pass several such identifiers to the "jtag newtap" command.
  880. if @{ [info exists CPUTAPID ] @} @{
  882. @} else @{
  883. set _CPUTAPID 0x3f0f0f0f
  884. @}
  885. @end example
  886. @c but 0x3f0f0f0f is for an str73x part ...
  887. @emph{Remember:} Board config files may include multiple target
  888. config files, or the same target file multiple times
  889. (changing at least @code{CHIPNAME}).
  890. Likewise, the target configuration file should define
  891. @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
  892. use it later on when defining debug targets:
  893. @example
  894. set _TARGETNAME $_CHIPNAME.cpu
  895. target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
  896. @end example
  897. @subsection Adding TAPs to the Scan Chain
  898. After the ``defaults'' are set up,
  899. add the TAPs on each chip to the JTAG scan chain.
  900. @xref{TAP Declaration}, and the naming convention
  901. for taps.
  902. In the simplest case the chip has only one TAP,
  903. probably for a CPU or FPGA.
  904. The config file for the Atmel AT91SAM7X256
  905. looks (in part) like this:
  906. @example
  907. jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \
  908. -expected-id $_CPUTAPID
  909. @end example
  910. A board with two such at91sam7 chips would be able
  911. to source such a config file twice, with different
  912. values for @code{CHIPNAME}, so
  913. it adds a different TAP each time.
  914. If there are one or more nonzero @option{-expected-id} values,
  915. OpenOCD attempts to verify the actual tap id against those values.
  916. It will issue error messages if there is mismatch, which
  917. can help to pinpoint problems in OpenOCD configurations.
  918. @example
  919. JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
  920. (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
  921. ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
  922. ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
  923. ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
  924. @end example
  925. There are more complex examples too, with chips that have
  926. multiple TAPs. Ones worth looking at include:
  927. @itemize
  928. @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
  929. plus a JRC to enable them
  930. @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
  931. @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
  932. is not currently used)
  933. @end itemize
  934. @subsection Add CPU targets
  935. After adding a TAP for a CPU, you should set it up so that
  936. GDB and other commands can use it.
  937. @xref{CPU Configuration}.
  938. For the at91sam7 example above, the command can look like this;
  939. note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
  940. to little endian, and this chip doesn't support changing that.
  941. @example
  942. set _TARGETNAME $_CHIPNAME.cpu
  943. target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
  944. @end example
  945. Work areas are small RAM areas associated with CPU targets.
  946. They are used by OpenOCD to speed up downloads,
  947. and to download small snippets of code to program flash chips.
  948. If the chip includes a form of ``on-chip-ram'' - and many do - define
  949. a work area if you can.
  950. Again using the at91sam7 as an example, this can look like:
  951. @example
  952. $_TARGETNAME configure -work-area-phys 0x00200000 \
  953. -work-area-size 0x4000 -work-area-backup 0
  954. @end example
  955. @subsection Chip Reset Setup
  956. As a rule, you should put the @command{reset_config} command
  957. into the board file. Most things you think you know about a
  958. chip can be tweaked by the board.
  959. Some chips have specific ways the TRST and SRST signals are
  960. managed. In the unusual case that these are @emph{chip specific}
  961. and can never be changed by board wiring, they could go here.
  962. Some chips need special attention during reset handling if
  963. they're going to be used with JTAG.
  964. An example might be needing to send some commands right
  965. after the target's TAP has been reset, providing a
  966. @code{reset-deassert-post} event handler that writes a chip
  967. register to report that JTAG debugging is being done.
  968. @subsection ARM Core Specific Hacks
  969. If the chip has a DCC, enable it. If the chip is an ARM9 with some
  970. special high speed download features - enable it.
  971. If present, the MMU, the MPU and the CACHE should be disabled.
  972. Some ARM cores are equipped with trace support, which permits
  973. examination of the instruction and data bus activity. Trace
  974. activity is controlled through an ``Embedded Trace Module'' (ETM)
  975. on one of the core's scan chains. The ETM emits voluminous data
  976. through a ``trace port''. (@xref{ARM Hardware Tracing}.)
  977. If you are using an external trace port,
  978. configure it in your board config file.
  979. If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
  980. configure it in your target config file.
  981. @example
  982. etm config $_TARGETNAME 16 normal full etb
  983. etb config $_TARGETNAME $_CHIPNAME.etb
  984. @end example
  985. @subsection Internal Flash Configuration
  986. This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
  987. @b{Never ever} in the ``target configuration file'' define any type of
  988. flash that is external to the chip. (For example a BOOT flash on
  989. Chip Select 0.) Such flash information goes in a board file - not
  990. the TARGET (chip) file.
  991. Examples:
  992. @itemize @bullet
  993. @item at91sam7x256 - has 256K flash YES enable it.
  994. @item str912 - has flash internal YES enable it.
  995. @item imx27 - uses boot flash on CS0 - it goes in the board file.
  996. @item pxa270 - again - CS0 flash - it goes in the board file.
  997. @end itemize
  998. @node Daemon Configuration
  999. @chapter Daemon Configuration
  1000. @cindex initialization
  1001. The commands here are commonly found in the openocd.cfg file and are
  1002. used to specify what TCP/IP ports are used, and how GDB should be
  1003. supported.
  1004. @section Configuration Stage
  1005. @cindex configuration stage
  1006. @cindex config command
  1007. When the OpenOCD server process starts up, it enters a
  1008. @emph{configuration stage} which is the only time that
  1009. certain commands, @emph{configuration commands}, may be issued.
  1010. In this manual, the definition of a configuration command is
  1011. presented as a @emph{Config Command}, not as a @emph{Command}
  1012. which may be issued interactively.
  1013. Those configuration commands include declaration of TAPs,
  1014. flash banks,
  1015. the interface used for JTAG communication,
  1016. and other basic setup.
  1017. The server must leave the configuration stage before it
  1018. may access or activate TAPs.
  1019. After it leaves this stage, configuration commands may no
  1020. longer be issued.
  1021. @deffn {Config Command} init
  1022. This command terminates the configuration stage and
  1023. enters the normal command mode. This can be useful to add commands to
  1024. the startup scripts and commands such as resetting the target,
  1025. programming flash, etc. To reset the CPU upon startup, add "init" and
  1026. "reset" at the end of the config script or at the end of the OpenOCD
  1027. command line using the @option{-c} command line switch.
  1028. If this command does not appear in any startup/configuration file
  1029. OpenOCD executes the command for you after processing all
  1030. configuration files and/or command line options.
  1031. @b{NOTE:} This command normally occurs at or near the end of your
  1032. openocd.cfg file to force OpenOCD to ``initialize'' and make the
  1033. targets ready. For example: If your openocd.cfg file needs to
  1034. read/write memory on your target, @command{init} must occur before
  1035. the memory read/write commands. This includes @command{nand probe}.
  1036. @end deffn
  1037. @anchor{TCP/IP Ports}
  1038. @section TCP/IP Ports
  1039. @cindex TCP port
  1040. @cindex server
  1041. @cindex port
  1042. @cindex security
  1043. The OpenOCD server accepts remote commands in several syntaxes.
  1044. Each syntax uses a different TCP/IP port, which you may specify
  1045. only during configuration (before those ports are opened).
  1046. For reasons including security, you may wish to prevent remote
  1047. access using one or more of these ports.
  1048. In such cases, just specify the relevant port number as zero.
  1049. If you disable all access through TCP/IP, you will need to
  1050. use the command line @option{-pipe} option.
  1051. @deffn {Command} gdb_port (number)
  1052. @cindex GDB server
  1053. Specify or query the first port used for incoming GDB connections.
  1054. The GDB port for the
  1055. first target will be gdb_port, the second target will listen on gdb_port + 1, and so on.
  1056. When not specified during the configuration stage,
  1057. the port @var{number} defaults to 3333.
  1058. When specified as zero, this port is not activated.
  1059. @end deffn
  1060. @deffn {Command} tcl_port (number)
  1061. Specify or query the port used for a simplified RPC
  1062. connection that can be used by clients to issue TCL commands and get the
  1063. output from the Tcl engine.
  1064. Intended as a machine interface.
  1065. When not specified during the configuration stage,
  1066. the port @var{number} defaults to 6666.
  1067. When specified as zero, this port is not activated.
  1068. @end deffn
  1069. @deffn {Command} telnet_port (number)
  1070. Specify or query the
  1071. port on which to listen for incoming telnet connections.
  1072. This port is intended for interaction with one human through TCL commands.
  1073. When not specified during the configuration stage,
  1074. the port @var{number} defaults to 4444.
  1075. When specified as zero, this port is not activated.
  1076. @end deffn
  1077. @anchor{GDB Configuration}
  1078. @section GDB Configuration
  1079. @cindex GDB
  1080. @cindex GDB configuration
  1081. You can reconfigure some GDB behaviors if needed.
  1082. The ones listed here are static and global.
  1083. @xref{Target Configuration}, about configuring individual targets.
  1084. @xref{Target Events}, about configuring target-specific event handling.
  1085. @anchor{gdb_breakpoint_override}
  1086. @deffn {Command} gdb_breakpoint_override [@option{hard}|@option{soft}|@option{disable}]
  1087. Force breakpoint type for gdb @command{break} commands.
  1088. This option supports GDB GUIs which don't
  1089. distinguish hard versus soft breakpoints, if the default OpenOCD and
  1090. GDB behaviour is not sufficient. GDB normally uses hardware
  1091. breakpoints if the memory map has been set up for flash regions.
  1092. @end deffn
  1093. @deffn {Config Command} gdb_detach (@option{resume}|@option{reset}|@option{halt}|@option{nothing})
  1094. Configures what OpenOCD will do when GDB detaches from the daemon.
  1095. Default behaviour is @option{resume}.
  1096. @end deffn
  1097. @anchor{gdb_flash_program}
  1098. @deffn {Config Command} gdb_flash_program (@option{enable}|@option{disable})
  1099. Set to @option{enable} to cause OpenOCD to program the flash memory when a
  1100. vFlash packet is received.
  1101. The default behaviour is @option{enable}.
  1102. @end deffn
  1103. @deffn {Config Command} gdb_memory_map (@option{enable}|@option{disable})
  1104. Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
  1105. requested. GDB will then know when to set hardware breakpoints, and program flash
  1106. using the GDB load command. @command{gdb_flash_program enable} must also be enabled
  1107. for flash programming to work.
  1108. Default behaviour is @option{enable}.
  1109. @xref{gdb_flash_program}.
  1110. @end deffn
  1111. @deffn {Config Command} gdb_report_data_abort (@option{enable}|@option{disable})
  1112. Specifies whether data aborts cause an error to be reported
  1113. by GDB memory read packets.
  1114. The default behaviour is @option{disable};
  1115. use @option{enable} see these errors reported.
  1116. @end deffn
  1117. @anchor{Event Polling}
  1118. @section Event Polling
  1119. Hardware debuggers are parts of asynchronous systems,
  1120. where significant events can happen at any time.
  1121. The OpenOCD server needs to detect some of these events,
  1122. so it can report them to through TCL command line
  1123. or to GDB.
  1124. Examples of such events include:
  1125. @itemize
  1126. @item One of the targets can stop running ... maybe it triggers
  1127. a code breakpoint or data watchpoint, or halts itself.
  1128. @item Messages may be sent over ``debug message'' channels ... many
  1129. targets support such messages sent over JTAG,
  1130. for receipt by the person debugging or tools.
  1131. @item Loss of power ... some adapters can detect these events.
  1132. @item Resets not issued through JTAG ... such reset sources
  1133. can include button presses or other system hardware, sometimes
  1134. including the target itself (perhaps through a watchdog).
  1135. @item Debug instrumentation sometimes supports event triggering
  1136. such as ``trace buffer full'' (so it can quickly be emptied)
  1137. or other signals (to correlate with code behavior).
  1138. @end itemize
  1139. None of those events are signaled through standard JTAG signals.
  1140. However, most conventions for JTAG connectors include voltage
  1141. level and system reset (SRST) signal detection.
  1142. Some connectors also include instrumentation signals, which
  1143. can imply events when those signals are inputs.
  1144. In general, OpenOCD needs to periodically check for those events,
  1145. either by looking at the status of signals on the JTAG connector
  1146. or by sending synchronous ``tell me your status'' JTAG requests
  1147. to the various active targets.
  1148. There is a command to manage and monitor that polling,
  1149. which is normally done in the background.
  1150. @deffn Command poll [@option{on}|@option{off}]
  1151. Poll the current target for its current state.
  1152. (Also, @pxref{target curstate}.)
  1153. If that target is in debug mode, architecture
  1154. specific information about the current state is printed.
  1155. An optional parameter
  1156. allows background polling to be enabled and disabled.
  1157. You could use this from the TCL command shell, or
  1158. from GDB using @command{monitor poll} command.
  1159. @example
  1160. > poll
  1161. background polling: on
  1162. target state: halted
  1163. target halted in ARM state due to debug-request, \
  1164. current mode: Supervisor
  1165. cpsr: 0x800000d3 pc: 0x11081bfc
  1166. MMU: disabled, D-Cache: disabled, I-Cache: enabled
  1167. >
  1168. @end example
  1169. @end deffn
  1170. @node Interface - Dongle Configuration
  1171. @chapter Interface - Dongle Configuration
  1172. @cindex config file, interface
  1173. @cindex interface config file
  1174. JTAG Adapters/Interfaces/Dongles are normally configured
  1175. through commands in an interface configuration
  1176. file which is sourced by your @file{openocd.cfg} file, or
  1177. through a command line @option{-f interface/....cfg} option.
  1178. @example
  1179. source [find interface/olimex-jtag-tiny.cfg]
  1180. @end example
  1181. These commands tell
  1182. OpenOCD what type of JTAG adapter you have, and how to talk to it.
  1183. A few cases are so simple that you only need to say what driver to use:
  1184. @example
  1185. # jlink interface
  1186. interface jlink
  1187. @end example
  1188. Most adapters need a bit more configuration than that.
  1189. @section Interface Configuration
  1190. The interface command tells OpenOCD what type of JTAG dongle you are
  1191. using. Depending on the type of dongle, you may need to have one or
  1192. more additional commands.
  1193. @deffn {Config Command} {interface} name
  1194. Use the interface driver @var{name} to connect to the
  1195. target.
  1196. @end deffn
  1197. @deffn Command {interface_list}
  1198. List the interface drivers that have been built into
  1199. the running copy of OpenOCD.
  1200. @end deffn
  1201. @deffn Command {jtag interface}
  1202. Returns the name of the interface driver being used.
  1203. @end deffn
  1204. @section Interface Drivers
  1205. Each of the interface drivers listed here must be explicitly
  1206. enabled when OpenOCD is configured, in order to be made
  1207. available at run time.
  1208. @deffn {Interface Driver} {amt_jtagaccel}
  1209. Amontec Chameleon in its JTAG Accelerator configuration,
  1210. connected to a PC's EPP mode parallel port.
  1211. This defines some driver-specific commands:
  1212. @deffn {Config Command} {parport_port} number
  1213. Specifies either the address of the I/O port (default: 0x378 for LPT1) or
  1214. the number of the @file{/dev/parport} device.
  1215. @end deffn
  1216. @deffn {Config Command} rtck [@option{enable}|@option{disable}]
  1217. Displays status of RTCK option.
  1218. Optionally sets that option first.
  1219. @end deffn
  1220. @end deffn
  1221. @deffn {Interface Driver} {arm-jtag-ew}
  1222. Olimex ARM-JTAG-EW USB adapter
  1223. This has one driver-specific command:
  1224. @deffn Command {armjtagew_info}
  1225. Logs some status
  1226. @end deffn
  1227. @end deffn
  1228. @deffn {Interface Driver} {at91rm9200}
  1229. Supports bitbanged JTAG from the local system,
  1230. presuming that system is an Atmel AT91rm9200
  1231. and a specific set of GPIOs is used.
  1232. @c command: at91rm9200_device NAME
  1233. @c chooses among list of bit configs ... only one option
  1234. @end deffn
  1235. @deffn {Interface Driver} {dummy}
  1236. A dummy software-only driver for debugging.
  1237. @end deffn
  1238. @deffn {Interface Driver} {ep93xx}
  1239. Cirrus Logic EP93xx based single-board computer bit-banging (in development)
  1240. @end deffn
  1241. @deffn {Interface Driver} {ft2232}
  1242. FTDI FT2232 (USB) based devices over one of the userspace libraries.
  1243. These interfaces have several commands, used to configure the driver
  1244. before initializing the JTAG scan chain:
  1245. @deffn {Config Command} {ft2232_device_desc} description
  1246. Provides the USB device description (the @emph{iProduct string})
  1247. of the FTDI FT2232 device. If not
  1248. specified, the FTDI default value is used. This setting is only valid
  1249. if compiled with FTD2XX support.
  1250. @end deffn
  1251. @deffn {Config Command} {ft2232_serial} serial-number
  1252. Specifies the @var{serial-number} of the FTDI FT2232 device to use,
  1253. in case the vendor provides unique IDs and more than one FT2232 device
  1254. is connected to the host.
  1255. If not specified, serial numbers are not considered.
  1256. (Note that USB serial numbers can be arbitrary Unicode strings,
  1257. and are not restricted to containing only decimal digits.)
  1258. @end deffn
  1259. @deffn {Config Command} {ft2232_layout} name
  1260. Each vendor's FT2232 device can use different GPIO signals
  1261. to control output-enables, reset signals, and LEDs.
  1262. Currently valid layout @var{name} values include:
  1263. @itemize @minus
  1264. @item @b{axm0432_jtag} Axiom AXM-0432
  1265. @item @b{comstick} Hitex STR9 comstick
  1266. @item @b{cortino} Hitex Cortino JTAG interface
  1267. @item @b{evb_lm3s811} Luminary Micro EVB_LM3S811 as a JTAG interface,
  1268. either for the local Cortex-M3 (SRST only)
  1269. or in a passthrough mode (neither SRST nor TRST)
  1270. @item @b{luminary_icdi} Luminary In-Circuit Debug Interface (ICDI) Board
  1271. @item @b{flyswatter} Tin Can Tools Flyswatter
  1272. @item @b{icebear} ICEbear JTAG adapter from Section 5
  1273. @item @b{jtagkey} Amontec JTAGkey and JTAGkey-Tiny (and compatibles)
  1274. @item @b{m5960} American Microsystems M5960
  1275. @item @b{olimex-jtag} Olimex ARM-USB-OCD and ARM-USB-Tiny
  1276. @item @b{oocdlink} OOCDLink
  1277. @c oocdlink ~= jtagkey_prototype_v1
  1278. @item @b{sheevaplug} Marvell Sheevaplug development kit
  1279. @item @b{signalyzer} Xverve Signalyzer
  1280. @item @b{stm32stick} Hitex STM32 Performance Stick
  1281. @item @b{turtelizer2} egnite Software turtelizer2
  1282. @item @b{usbjtag} "USBJTAG-1" layout described in the OpenOCD diploma thesis
  1283. @end itemize
  1284. @end deffn
  1285. @deffn {Config Command} {ft2232_vid_pid} [vid pid]+
  1286. The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
  1287. default values are used.
  1288. Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
  1289. @example
  1290. ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
  1291. @end example
  1292. @end deffn
  1293. @deffn {Config Command} {ft2232_latency} ms
  1294. On some systems using FT2232 based JTAG interfaces the FT_Read function call in
  1295. ft2232_read() fails to return the expected number of bytes. This can be caused by
  1296. USB communication delays and has proved hard to reproduce and debug. Setting the
  1297. FT2232 latency timer to a larger value increases delays for short USB packets but it
  1298. also reduces the risk of timeouts before receiving the expected number of bytes.
  1299. The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
  1300. @end deffn
  1301. For example, the interface config file for a
  1302. Turtelizer JTAG Adapter looks something like this:
  1303. @example
  1304. interface ft2232
  1305. ft2232_device_desc "Turtelizer JTAG/RS232 Adapter"
  1306. ft2232_layout turtelizer2
  1307. ft2232_vid_pid 0x0403 0xbdc8
  1308. @end example
  1309. @end deffn
  1310. @deffn {Interface Driver} {gw16012}
  1311. Gateworks GW16012 JTAG programmer.
  1312. This has one driver-specific command:
  1313. @deffn {Config Command} {parport_port} number
  1314. Specifies either the address of the I/O port (default: 0x378 for LPT1) or
  1315. the number of the @file{/dev/parport} device.
  1316. @end deffn
  1317. @end deffn
  1318. @deffn {Interface Driver} {jlink}
  1319. Segger jlink USB adapter
  1320. @c command: jlink_info
  1321. @c dumps status
  1322. @c command: jlink_hw_jtag (2|3)
  1323. @c sets version 2 or 3
  1324. @end deffn
  1325. @deffn {Interface Driver} {parport}
  1326. Supports PC parallel port bit-banging cables:
  1327. Wigglers, PLD download cable, and more.
  1328. These interfaces have several commands, used to configure the driver
  1329. before initializing the JTAG scan chain:
  1330. @deffn {Config Command} {parport_cable} name
  1331. The layout of the parallel port cable used to connect to the target.
  1332. Currently valid cable @var{name} values include:
  1333. @itemize @minus
  1334. @item @b{altium} Altium Universal JTAG cable.
  1335. @item @b{arm-jtag} Same as original wiggler except SRST and
  1336. TRST connections reversed and TRST is also inverted.
  1337. @item @b{chameleon} The Amontec Chameleon's CPLD when operated
  1338. in configuration mode. This is only used to
  1339. program the Chameleon itself, not a connected target.
  1340. @item @b{dlc5} The Xilinx Parallel cable III.
  1341. @item @b{flashlink} The ST Parallel cable.
  1342. @item @b{lattice} Lattice ispDOWNLOAD Cable
  1343. @item @b{old_amt_wiggler} The Wiggler configuration that comes with
  1344. some versions of
  1345. Amontec's Chameleon Programmer. The new version available from
  1346. the website uses the original Wiggler layout ('@var{wiggler}')
  1347. @item @b{triton} The parallel port adapter found on the
  1348. ``Karo Triton 1 Development Board''.
  1349. This is also the layout used by the HollyGates design
  1350. (see @uref{}).
  1351. @item @b{wiggler} The original Wiggler layout, also supported by
  1352. several clones, such as the Olimex ARM-JTAG
  1353. @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
  1354. @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
  1355. @end itemize
  1356. @end deffn
  1357. @deffn {Config Command} {parport_port} number
  1358. Either the address of the I/O port (default: 0x378 for LPT1) or the number of
  1359. the @file{/dev/parport} device
  1360. When using PPDEV to access the parallel port, use the number of the parallel port:
  1361. @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
  1362. you may encounter a problem.
  1363. @end deffn
  1364. @deffn {Config Command} {parport_write_on_exit} (on|off)
  1365. This will configure the parallel driver to write a known
  1366. cable-specific value to the parallel interface on exiting OpenOCD
  1367. @end deffn
  1368. For example, the interface configuration file for a
  1369. classic ``Wiggler'' cable might look something like this:
  1370. @example
  1371. interface parport
  1372. parport_port 0xc8b8
  1373. parport_cable wiggler
  1374. @end example
  1375. @end deffn
  1376. @deffn {Interface Driver} {presto}
  1377. ASIX PRESTO USB JTAG programmer.
  1378. @c command: presto_serial str
  1379. @c sets serial number
  1380. @end deffn
  1381. @deffn {Interface Driver} {rlink}
  1382. Raisonance RLink USB adapter
  1383. @end deffn
  1384. @deffn {Interface Driver} {usbprog}
  1385. usbprog is a freely programmable USB adapter.
  1386. @end deffn
  1387. @deffn {Interface Driver} {vsllink}
  1388. vsllink is part of Versaloon which is a versatile USB programmer.
  1389. @quotation Note
  1390. This defines quite a few driver-specific commands,
  1391. which are not currently documented here.
  1392. @end quotation
  1393. @end deffn
  1394. @deffn {Interface Driver} {ZY1000}
  1395. This is the Zylin ZY1000 JTAG debugger.
  1396. @quotation Note
  1397. This defines some driver-specific commands,
  1398. which are not currently documented here.
  1399. @end quotation
  1400. @deffn Command power [@option{on}|@option{off}]
  1401. Turn power switch to target on/off.
  1402. No arguments: print status.
  1403. @end deffn
  1404. @end deffn
  1405. @anchor{JTAG Speed}
  1406. @section JTAG Speed
  1407. JTAG clock setup is part of system setup.
  1408. It @emph{does not belong with interface setup} since any interface
  1409. only knows a few of the constraints for the JTAG clock speed.
  1410. Sometimes the JTAG speed is
  1411. changed during the target initialization process: (1) slow at
  1412. reset, (2) program the CPU clocks, (3) run fast.
  1413. Both the "slow" and "fast" clock rates are functions of the
  1414. oscillators used, the chip, the board design, and sometimes
  1415. power management software that may be active.
  1416. The speed used during reset can be adjusted using pre_reset
  1417. and post_reset event handlers.
  1418. @xref{Target Events}.
  1419. If your system supports adaptive clocking (RTCK), configuring
  1420. JTAG to use that is probably the most robust approach.
  1421. However, it introduces delays to synchronize clocks; so it
  1422. may not be the fastest solution.
  1423. @b{NOTE:} Script writers should consider using @command{jtag_rclk}
  1424. instead of @command{jtag_khz}.
  1425. @deffn {Command} jtag_khz max_speed_kHz
  1426. A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
  1427. JTAG interfaces usually support a limited number of
  1428. speeds. The speed actually used won't be faster
  1429. than the speed specified.
  1430. As a rule of thumb, if you specify a clock rate make
  1431. sure the JTAG clock is no more than @math{1/6th CPU-Clock}.
  1432. This is especially true for synthesized cores (ARMxxx-S).
  1433. Speed 0 (khz) selects RTCK method.
  1434. @xref{FAQ RTCK}.
  1435. If your system uses RTCK, you won't need to change the
  1436. JTAG clocking after setup.
  1437. Not all interfaces, boards, or targets support ``rtck''.
  1438. If the interface device can not
  1439. support it, an error is returned when you try to use RTCK.
  1440. @end deffn
  1441. @defun jtag_rclk fallback_speed_kHz
  1442. @cindex RTCK
  1443. This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
  1444. If that fails (maybe the interface, board, or target doesn't
  1445. support it), falls back to the specified frequency.
  1446. @example
  1447. # Fall back to 3mhz if RTCK is not supported
  1448. jtag_rclk 3000
  1449. @end example
  1450. @end defun
  1451. @node Reset Configuration
  1452. @chapter Reset Configuration
  1453. @cindex Reset Configuration
  1454. Every system configuration may require a different reset
  1455. configuration. This can also be quite confusing.
  1456. Resets also interact with @var{reset-init} event handlers,
  1457. which do things like setting up clocks and DRAM, and
  1458. JTAG clock rates. (@xref{JTAG Speed}.)
  1459. They can also interact with JTAG routers.
  1460. Please see the various board files for examples.
  1461. @quotation Note
  1462. To maintainers and integrators:
  1463. Reset configuration touches several things at once.
  1464. Normally the board configuration file
  1465. should define it and assume that the JTAG adapter supports
  1466. everything that's wired up to the board's JTAG connector.
  1467. However, the target configuration file could also make note
  1468. of something the silicon vendor has done inside the chip,
  1469. which will be true for most (or all) boards using that chip.
  1470. And when the JTAG adapter doesn't support everything, the
  1471. user configuration file will need to override parts of
  1472. the reset configuration provided by other files.
  1473. @end quotation
  1474. @section Types of Reset
  1475. There are many kinds of reset possible through JTAG, but
  1476. they may not all work with a given board and adapter.
  1477. That's part of why reset configuration can be error prone.
  1478. @itemize @bullet
  1479. @item
  1480. @emph{System Reset} ... the @emph{SRST} hardware signal
  1481. resets all chips connected to the JTAG adapter, such as processors,
  1482. power management chips, and I/O controllers. Normally resets triggered
  1483. with this signal behave exactly like pressing a RESET button.
  1484. @item
  1485. @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
  1486. just the TAP controllers connected to the JTAG adapter.
  1487. Such resets should not be visible to the rest of the system; resetting a
  1488. device's the TAP controller just puts that controller into a known state.
  1489. @item
  1490. @emph{Emulation Reset} ... many devices can be reset through JTAG
  1491. commands. These resets are often distinguishable from system
  1492. resets, either explicitly (a "reset reason" register says so)
  1493. or implicitly (not all parts of the chip get reset).
  1494. @item
  1495. @emph{Other Resets} ... system-on-chip devices often support
  1496. several other types of reset.
  1497. You may need to arrange that a watchdog timer stops
  1498. while debugging, preventing a watchdog reset.
  1499. There may be individual module resets.
  1500. @end itemize
  1501. In the best case, OpenOCD can hold SRST, then reset
  1502. the TAPs via TRST and send commands through JTAG to halt the
  1503. CPU at the reset vector before the 1st instruction is executed.
  1504. Then when it finally releases the SRST signal, the system is
  1505. halted under debugger control before any code has executed.
  1506. This is the behavior required to support the @command{reset halt}
  1507. and @command{reset init} commands; after @command{reset init} a
  1508. board-specific script might do things like setting up DRAM.
  1509. (@xref{Reset Command}.)
  1510. @anchor{SRST and TRST Issues}
  1511. @section SRST and TRST Issues
  1512. Because SRST and TRST are hardware signals, they can have a
  1513. variety of system-specific constraints. Some of the most
  1514. common issues are:
  1515. @itemize @bullet
  1516. @item @emph{Signal not available} ... Some boards don't wire
  1517. SRST or TRST to the JTAG connector. Some JTAG adapters don't
  1518. support such signals even if they are wired up.
  1519. Use the @command{reset_config} @var{signals} options to say
  1520. when either of those signals is not connected.
  1521. When SRST is not available, your code might not be able to rely
  1522. on controllers having been fully reset during code startup.
  1523. Missing TRST is not a problem, since JTAG level resets can
  1524. be triggered using with TMS signaling.
  1525. @item @emph{Signals shorted} ... Sometimes a chip, board, or
  1526. adapter will connect SRST to TRST, instead of keeping them separate.
  1527. Use the @command{reset_config} @var{combination} options to say
  1528. when those signals aren't properly independent.
  1529. @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
  1530. delay circuit, reset supervisor, or on-chip features can extend
  1531. the effect of a JTAG adapter's reset for some time after the adapter
  1532. stops issuing the reset. For example, there may be chip or board
  1533. requirements that all reset pulses last for at least a
  1534. certain amount of time; and reset buttons commonly have
  1535. hardware debouncing.
  1536. Use the @command{jtag_nsrst_delay} and @command{jtag_ntrst_delay}
  1537. commands to say when extra delays are needed.
  1538. @item @emph{Drive type} ... Reset lines often have a pullup
  1539. resistor, letting the JTAG interface treat them as open-drain
  1540. signals. But that's not a requirement, so the adapter may need
  1541. to use push/pull output drivers.
  1542. Also, with weak pullups it may be advisable to drive
  1543. signals to both levels (push/pull) to minimize rise times.
  1544. Use the @command{reset_config} @var{trst_type} and
  1545. @var{srst_type} parameters to say how to drive reset signals.
  1546. @item @emph{Special initialization} ... Targets sometimes need
  1547. special JTAG initialization sequences to handle chip-specific
  1548. issues (not limited to errata).
  1549. For example, certain JTAG commands might need to be issued while
  1550. the system as a whole is in a reset state (SRST active)
  1551. but the JTAG scan chain is usable (TRST inactive).
  1552. (@xref{JTAG Commands}, where the @command{jtag_reset}
  1553. command is presented.)
  1554. @end itemize
  1555. There can also be other issues.
  1556. Some devices don't fully conform to the JTAG specifications.
  1557. Trivial system-specific differences are common, such as
  1558. SRST and TRST using slightly different names.
  1559. There are also vendors who distribute key JTAG documentation for
  1560. their chips only to developers who have signed a Non-Disclosure
  1561. Agreement (NDA).
  1562. Sometimes there are chip-specific extensions like a requirement to use
  1563. the normally-optional TRST signal (precluding use of JTAG adapters which
  1564. don't pass TRST through), or needing extra steps to complete a TAP reset.
  1565. In short, SRST and especially TRST handling may be very finicky,
  1566. needing to cope with both architecture and board specific constraints.
  1567. @section Commands for Handling Resets
  1568. @deffn {Command} jtag_nsrst_delay milliseconds
  1569. How long (in milliseconds) OpenOCD should wait after deasserting
  1570. nSRST (active-low system reset) before starting new JTAG operations.
  1571. When a board has a reset button connected to SRST line it will
  1572. probably have hardware debouncing, implying you should use this.
  1573. @end deffn
  1574. @deffn {Command} jtag_ntrst_delay milliseconds
  1575. How long (in milliseconds) OpenOCD should wait after deasserting
  1576. nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
  1577. @end deffn
  1578. @deffn {Command} reset_config mode_flag ...
  1579. This command tells OpenOCD the reset configuration
  1580. of your combination of JTAG board and target in target
  1581. configuration scripts.
  1582. Information earlier in this section describes the kind of problems
  1583. the command is intended to address (@pxref{SRST and TRST Issues}).
  1584. As a rule this command belongs only in board config files,
  1585. describing issues like @emph{board doesn't connect TRST};
  1586. or in user config files, addressing limitations derived
  1587. from a particular combination of interface and board.
  1588. (An unlikely example would be using a TRST-only adapter
  1589. with a board that only wires up SRST.)
  1590. The @var{mode_flag} options can be specified in any order, but only one
  1591. of each type -- @var{signals}, @var{combination}, @var{trst_type},
  1592. and @var{srst_type} -- may be specified at a time.
  1593. If you don't provide a new value for a given type, its previous
  1594. value (perhaps the default) is unchanged.
  1595. For example, this means that you don't need to say anything at all about
  1596. TRST just to declare that if the JTAG adapter should want to drive SRST,
  1597. it must explicitly be driven high (@option{srst_push_pull}).
  1598. @var{signals} can specify which of the reset signals are connected.
  1599. For example, If the JTAG interface provides SRST, but the board doesn't
  1600. connect that signal properly, then OpenOCD can't use it.
  1601. Possible values are @option{none} (the default), @option{trst_only},
  1602. @option{srst_only} and @option{trst_and_srst}.
  1603. @quotation Tip
  1604. If your board provides SRST or TRST through the JTAG connector,
  1605. you must declare that or else those signals will not be used.
  1606. @end quotation
  1607. The @var{combination} is an optional value specifying broken reset
  1608. signal implementations.
  1609. The default behaviour if no option given is @option{separate},
  1610. indicating everything behaves normally.
  1611. @option{srst_pulls_trst} states that the
  1612. test logic is reset together with the reset of the system (e.g. Philips
  1613. LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
  1614. the system is reset together with the test logic (only hypothetical, I
  1615. haven't seen hardware with such a bug, and can be worked around).
  1616. @option{combined} implies both @option{srst_pulls_trst} and
  1617. @option{trst_pulls_srst}.
  1618. The optional @var{trst_type} and @var{srst_type} parameters allow the
  1619. driver mode of each reset line to be specified. These values only affect
  1620. JTAG interfaces with support for different driver modes, like the Amontec
  1621. JTAGkey and JTAGAccelerator. Also, they are necessarily ignored if the
  1622. relevant signal (TRST or SRST) is not connected.
  1623. Possible @var{trst_type} driver modes for the test reset signal (TRST)
  1624. are @option{trst_push_pull} (default) and @option{trst_open_drain}.
  1625. Most boards connect this signal to a pulldown, so the JTAG TAPs
  1626. never leave reset unless they are hooked up to a JTAG adapter.
  1627. Possible @var{srst_type} driver modes for the system reset signal (SRST)
  1628. are the default @option{srst_open_drain}, and @option{srst_push_pull}.
  1629. Most boards connect this signal to a pullup, and allow the
  1630. signal to be pulled low by various events including system
  1631. powerup and pressing a reset button.
  1632. @end deffn
  1633. @node TAP Declaration
  1634. @chapter TAP Declaration
  1635. @cindex TAP declaration
  1636. @cindex TAP configuration
  1637. @emph{Test Access Ports} (TAPs) are the core of JTAG.
  1638. TAPs serve many roles, including:
  1639. @itemize @bullet
  1640. @item @b{Debug Target} A CPU TAP can be used as a GDB debug target
  1641. @item @b{Flash Programing} Some chips program the flash directly via JTAG.
  1642. Others do it indirectly, making a CPU do it.
  1643. @item @b{Program Download} Using the same CPU support GDB uses,
  1644. you can initialize a DRAM controller, download code to DRAM, and then
  1645. start running that code.
  1646. @item @b{Boundary Scan} Most chips support boundary scan, which
  1647. helps test for board assembly problems like solder bridges
  1648. and missing connections
  1649. @end itemize
  1650. OpenOCD must know about the active TAPs on your board(s).
  1651. Setting up the TAPs is the core task of your configuration files.
  1652. Once those TAPs are set up, you can pass their names to code
  1653. which sets up CPUs and exports them as GDB targets,
  1654. probes flash memory, performs low-level JTAG operations, and more.
  1655. @section Scan Chains
  1656. @cindex scan chain
  1657. TAPs are part of a hardware @dfn{scan chain},
  1658. which is daisy chain of TAPs.
  1659. They also need to be added to
  1660. OpenOCD's software mirror of that hardware list,
  1661. giving each member a name and associating other data with it.
  1662. Simple scan chains, with a single TAP, are common in
  1663. systems with a single microcontroller or microprocessor.
  1664. More complex chips may have several TAPs internally.
  1665. Very complex scan chains might have a dozen or more TAPs:
  1666. several in one chip, more in the next, and connecting
  1667. to other boards with their own chips and TAPs.
  1668. You can display the list with the @command{scan_chain} command.
  1669. (Don't confuse this with the list displayed by the @command{targets}
  1670. command, presented in the next chapter.
  1671. That only displays TAPs for CPUs which are configured as
  1672. debugging targets.)
  1673. Here's what the scan chain might look like for a chip more than one TAP:
  1674. @verbatim
  1675. TapName Enabled IdCode Expected IrLen IrCap IrMask Instr
  1676. -- ------------------ ------- ---------- ---------- ----- ----- ------ -----
  1677. 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0 0 0x...
  1678. 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x1 0 0xc
  1679. 2 omap5912.unknown Y 0x00000000 0x00000000 8 0 0 0xff
  1680. @end verbatim
  1681. Unfortunately those TAPs can't always be autoconfigured,
  1682. because not all devices provide good support for that.
  1683. JTAG doesn't require supporting IDCODE instructions, and
  1684. chips with JTAG routers may not link TAPs into the chain
  1685. until they are told to do so.
  1686. The configuration mechanism currently supported by OpenOCD
  1687. requires explicit configuration of all TAP devices using
  1688. @command{jtag newtap} commands, as detailed later in this chapter.
  1689. A command like this would declare one tap and name it @code{chip1.cpu}:
  1690. @example
  1691. jtag newtap chip1 cpu -irlen 7 -ircapture 0x01 -irmask 0x55
  1692. @end example
  1693. Each target configuration file lists the TAPs provided
  1694. by a given chip.
  1695. Board configuration files combine all the targets on a board,
  1696. and so forth.
  1697. Note that @emph{the order in which TAPs are declared is very important.}
  1698. It must match the order in the JTAG scan chain, both inside
  1699. a single chip and between them.
  1700. @xref{FAQ TAP Order}.
  1701. For example, the ST Microsystems STR912 chip has
  1702. three separate TAPs@footnote{See the ST
  1703. document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
  1704. 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
  1705. @url{}}.
  1706. To configure those taps, @file{target/str912.cfg}
  1707. includes commands something like this:
  1708. @example
  1709. jtag newtap str912 flash ... params ...
  1710. jtag newtap str912 cpu ... params ...
  1711. jtag newtap str912 bs ... params ...
  1712. @end example
  1713. Actual config files use a variable instead of literals like
  1714. @option{str912}, to support more than one chip of each type.
  1715. @xref{Config File Guidelines}.
  1716. @deffn Command {jtag names}
  1717. Returns the names of all current TAPs in the scan chain.
  1718. Use @command{jtag cget} or @command{jtag tapisenabled}
  1719. to examine attributes and state of each TAP.
  1720. @example
  1721. foreach t [jtag names] @{
  1722. puts [format "TAP: %s\n" $t]
  1723. @}
  1724. @end example
  1725. @end deffn
  1726. @deffn Command {scan_chain}
  1727. Displays the TAPs in the scan chain configuration,
  1728. and their status.
  1729. The set of TAPs listed by this command is fixed by
  1730. exiting the OpenOCD configuration stage,
  1731. but systems with a JTAG router can
  1732. enable or disable TAPs dynamically.
  1733. In addition to the enable/disable status, the contents of
  1734. each TAP's instruction register can also change.
  1735. @end deffn
  1736. @c FIXME! "jtag cget" should be able to return all TAP
  1737. @c attributes, like "$target_name cget" does for targets.
  1738. @c Probably want "jtag eventlist", and a "tap-reset" event
  1739. @c (on entry to RESET state).
  1740. @section TAP Names
  1741. @cindex dotted name
  1742. When TAP objects are declared with @command{jtag newtap},
  1743. a @dfn{} is created for the TAP, combining the
  1744. name of a module (usually a chip) and a label for the TAP.
  1745. For example: @code{xilinx.tap}, @code{str912.flash},
  1746. @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
  1747. Many other commands use that to manipulate or
  1748. refer to the TAP. For example, CPU configuration uses the
  1749. name, as does declaration of NAND or NOR flash banks.
  1750. The components of a dotted name should follow ``C'' symbol
  1751. name rules: start with an alphabetic character, then numbers
  1752. and underscores are OK; while others (including dots!) are not.
  1753. @quotation Tip
  1754. In older code, JTAG TAPs were numbered from 0..N.
  1755. This feature is still present.
  1756. However its use is highly discouraged, and
  1757. should not be relied on; it will be removed by mid-2010.
  1758. Update all of your scripts to use TAP names rather than numbers,
  1759. by paying attention to the runtime warnings they trigger.
  1760. Using TAP numbers in target configuration scripts prevents
  1761. reusing those scripts on boards with multiple targets.
  1762. @end quotation
  1763. @section TAP Declaration Commands
  1764. @c shouldn't this be(come) a {Config Command}?
  1765. @anchor{jtag newtap}
  1766. @deffn Command {jtag newtap} chipname tapname configparams...
  1767. Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
  1768. and configured according to the various @var{configparams}.
  1769. The @var{chipname} is a symbolic name for the chip.
  1770. Conventionally target config files use @code{$_CHIPNAME},
  1771. defaulting to the model name given by the chip vendor but
  1772. overridable.
  1773. @cindex TAP naming convention
  1774. The @var{tapname} reflects the role of that TAP,
  1775. and should follow this convention:
  1776. @itemize @bullet
  1777. @item @code{bs} -- For boundary scan if this is a seperate TAP;
  1778. @item @code{cpu} -- The main CPU of the chip, alternatively
  1779. @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
  1780. @code{arm1} and @code{arm2} on chips two ARMs, and so forth;
  1781. @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
  1782. @item @code{flash} -- If the chip has a flash TAP, like the str912;
  1783. @item @code{jrc} -- For JTAG route controller (example: the ICEpick modules
  1784. on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
  1785. @item @code{tap} -- Should be used only FPGA or CPLD like devices
  1786. with a single TAP;
  1787. @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
  1788. @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
  1789. For example, the Freescale IMX31 has a SDMA (Smart DMA) with
  1790. a JTAG TAP; that TAP should be named @code{sdma}.
  1791. @end itemize
  1792. Every TAP requires at least the following @var{configparams}:
  1793. @itemize @bullet
  1794. @item @code{-ircapture} @var{NUMBER}
  1795. @*The IDCODE capture command, such as 0x01.
  1796. @item @code{-irlen} @var{NUMBER}
  1797. @*The length in bits of the
  1798. instruction register, such as 4 or 5 bits.
  1799. @item @code{-irmask} @var{NUMBER}
  1800. @*A mask for the IR register.
  1801. For some devices, there are bits in the IR that aren't used.
  1802. This lets OpenOCD mask them off when doing IDCODE comparisons.
  1803. In general, this should just be all ones for the size of the IR.
  1804. @end itemize
  1805. A TAP may also provide optional @var{configparams}:
  1806. @itemize @bullet
  1807. @item @code{-disable} (or @code{-enable})
  1808. @*Use the @code{-disable} parameter to flag a TAP which is not
  1809. linked in to the scan chain after a reset using either TRST
  1810. or the JTAG state machine's @sc{reset} state.
  1811. You may use @code{-enable} to highlight the default state
  1812. (the TAP is linked in).
  1813. @xref{Enabling and Disabling TAPs}.
  1814. @item @code{-expected-id} @var{number}
  1815. @*A non-zero value represents the expected 32-bit IDCODE
  1816. found when the JTAG chain is examined.
  1817. These codes are not required by all JTAG devices.
  1818. @emph{Repeat the option} as many times as required if more than one
  1819. ID code could appear (for example, multiple versions).
  1820. @end itemize
  1821. @end deffn
  1822. @c @deffn Command {jtag arp_init-reset}
  1823. @c ... more or less "init" ?
  1824. @anchor{Enabling and Disabling TAPs}
  1825. @section Enabling and Disabling TAPs
  1826. @cindex TAP events
  1827. @cindex JTAG Route Controller
  1828. @cindex jrc
  1829. In some systems, a @dfn{JTAG Route Controller} (JRC)
  1830. is used to enable and/or disable specific JTAG TAPs.
  1831. Many ARM based chips from Texas Instruments include
  1832. an ``ICEpick'' module, which is a JRC.
  1833. Such chips include DaVinci and OMAP3 processors.
  1834. A given TAP may not be visible until the JRC has been
  1835. told to link it into the scan chain; and if the JRC
  1836. has been told to unlink that TAP, it will no longer
  1837. be visible.
  1838. Such routers address problems that JTAG ``bypass mode''
  1839. ignores, such as:
  1840. @itemize
  1841. @item The scan chain can only go as fast as its slowest TAP.
  1842. @item Having many TAPs slows instruction scans, since all
  1843. TAPs receive new instructions.
  1844. @item TAPs in the scan chain must be powered up, which wastes
  1845. power and prevents debugging some power management mechanisms.
  1846. @end itemize
  1847. The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
  1848. as implied by the existence of JTAG routers.
  1849. However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
  1850. does include a kind of JTAG router functionality.
  1851. @c (a) currently the event handlers don't seem to be able to
  1852. @c fail in a way that could lead to no-change-of-state.
  1853. @c (b) eventually non-event configuration should be possible,
  1854. @c in which case some this documentation must move.
  1855. @deffn Command {jtag cget} @option{-event} name
  1856. @deffnx Command {jtag configure} @option{-event} name string
  1857. At this writing this mechanism is used only for event handling,
  1858. and the only two events relate to TAP enabling and disabling.
  1859. The @code{configure} subcommand assigns an event handler,
  1860. a TCL string which is evaluated when the event is triggered.
  1861. The @code{cget} subcommand returns that handler.
  1862. The two possible values for an event @var{name}
  1863. are @option{tap-disable} and @option{tap-enable}.
  1864. So for example, when defining a TAP for a CPU connected to
  1865. a JTAG router, you should define TAP event handlers using
  1866. code that looks something like this:
  1867. @example
  1868. jtag configure CHIP.cpu -event tap-enable @{
  1869. echo "Enabling CPU TAP"
  1870. ... jtag operations using CHIP.jrc
  1871. @}
  1872. jtag configure CHIP.cpu -event tap-disable @{
  1873. echo "Disabling CPU TAP"
  1874. ... jtag operations using CHIP.jrc
  1875. @}
  1876. @end example
  1877. @end deffn
  1878. @deffn Command {jtag tapdisable}
  1879. @deffnx Command {jtag tapenable}
  1880. @deffnx Command {jtag tapisenabled}
  1881. These three commands all return the string "1" if the tap
  1882. specified by @var{} is enabled,
  1883. and "0" if it is disbabled.
  1884. The @command{tapenable} variant first enables the tap
  1885. by sending it a @option{tap-enable} event.
  1886. The @command{tapdisable} variant first disables the tap
  1887. by sending it a @option{tap-disable} event.
  1888. @quotation Note
  1889. Humans will find the @command{scan_chain} command more helpful
  1890. than the script-oriented @command{tapisenabled}
  1891. for querying the state of the JTAG taps.
  1892. @end quotation
  1893. @end deffn
  1894. @node CPU Configuration
  1895. @chapter CPU Configuration
  1896. @cindex GDB target
  1897. This chapter discusses how to set up GDB debug targets for CPUs.
  1898. You can also access these targets without GDB
  1899. (@pxref{Architecture and Core Commands},
  1900. and @ref{Target State handling}) and
  1901. through various kinds of NAND and NOR flash commands.
  1902. If you have multiple CPUs you can have multiple such targets.
  1903. We'll start by looking at how to examine the targets you have,
  1904. then look at how to add one more target and how to configure it.
  1905. @section Target List
  1906. @cindex target, current
  1907. @cindex target, list
  1908. All targets that have been set up are part of a list,
  1909. where each member has a name.
  1910. That name should normally be the same as the TAP name.
  1911. You can display the list with the @command{targets}
  1912. (plural!) command.
  1913. This display often has only one CPU; here's what it might
  1914. look like with more than one:
  1915. @verbatim
  1916. TargetName Type Endian TapName State
  1917. -- ------------------ ---------- ------ ------------------ ------------
  1918. 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
  1919. 1 MyTarget cortex_m3 little tap-disabled
  1920. @end verbatim
  1921. One member of that list is the @dfn{current target}, which
  1922. is implicitly referenced by many commands.
  1923. It's the one marked with a @code{*} near the target name.
  1924. In particular, memory addresses often refer to the address
  1925. space seen by that current target.
  1926. Commands like @command{mdw} (memory display words)
  1927. and @command{flash erase_address} (erase NOR flash blocks)
  1928. are examples; and there are many more.
  1929. Several commands let you examine the list of targets:
  1930. @deffn Command {target count}
  1931. Returns the number of targets, @math{N}.
  1932. The highest numbered target is @math{N - 1}.
  1933. @example
  1934. set c [target count]
  1935. for @{ set x 0 @} @{ $x < $c @} @{ incr x @} @{
  1936. # Assuming you have created this function
  1937. print_target_details $x
  1938. @}
  1939. @end example
  1940. @end deffn
  1941. @deffn Command {target current}
  1942. Returns the name of the current target.
  1943. @end deffn
  1944. @deffn Command {target names}
  1945. Lists the names of all current targets in the list.
  1946. @example
  1947. foreach t [target names] @{
  1948. puts [format "Target: %s\n" $t]
  1949. @}
  1950. @end example
  1951. @end deffn
  1952. @deffn Command {target number} number
  1953. The list of targets is numbered starting at zero.
  1954. This command returns the name of the target at index @var{number}.
  1955. @example
  1956. set thename [target number $x]
  1957. puts [format "Target %d is: %s\n" $x $thename]
  1958. @end example
  1959. @end deffn
  1960. @c yep, "target list" would have been better.
  1961. @c plus maybe "target setdefault".
  1962. @deffn Command targets [name]
  1963. @emph{Note: the name of this command is plural. Other target
  1964. command names are singular.}
  1965. With no parameter, this command displays a table of all known
  1966. targets in a user friendly form.
  1967. With a parameter, this command sets the current target to
  1968. the given target with the given @var{name}; this is
  1969. only relevant on boards which have more than one target.
  1970. @end deffn
  1971. @section Target CPU Types and Variants
  1972. @cindex target type
  1973. @cindex CPU type
  1974. @cindex CPU variant
  1975. Each target has a @dfn{CPU type}, as shown in the output of
  1976. the @command{targets} command. You need to specify that type
  1977. when calling @command{target create}.
  1978. The CPU type indicates more than just the instruction set.
  1979. It also indicates how that instruction set is implemented,
  1980. what kind of debug support it integrates,
  1981. whether it has an MMU (and if so, what kind),
  1982. what core-specific commands may be available
  1983. (@pxref{Architecture and Core Commands}),
  1984. and more.
  1985. For some CPU types, OpenOCD also defines @dfn{variants} which
  1986. indicate differences that affect their handling.
  1987. For example, a particular implementation bug might need to be
  1988. worked around in some chip versions.
  1989. It's easy to see what target types are supported,
  1990. since there's a command to list them.
  1991. However, there is currently no way to list what target variants
  1992. are supported (other than by reading the OpenOCD source code).
  1993. @anchor{target types}
  1994. @deffn Command {target types}
  1995. Lists all supported target types.
  1996. At this writing, the supported CPU types and variants are:
  1997. @itemize @bullet
  1998. @item @code{arm11} -- this is a generation of ARMv6 cores
  1999. @item @code{arm720t} -- this is an ARMv4 core
  2000. @item @code{arm7tdmi} -- this is an ARMv4 core
  2001. @item @code{arm920t} -- this is an ARMv5 core
  2002. @item @code{arm926ejs} -- this is an ARMv5 core
  2003. @item @code{arm966e} -- this is an ARMv5 core
  2004. @item @code{arm9tdmi} -- this is an ARMv4 core
  2005. @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
  2006. (Support for this is preliminary and incomplete.)
  2007. @item @code{cortex_a8} -- this is an ARMv7 core
  2008. @item @code{cortex_m3} -- this is an ARMv7 core, supporting only the
  2009. compact Thumb2 instruction set. It supports one variant:
  2010. @itemize @minus
  2011. @item @code{lm3s} ... Use this when debugging older Stellaris LM3S targets.
  2012. This will cause OpenOCD to use a software reset rather than asserting
  2013. SRST, to avoid a issue with clearing the debug registers.
  2014. This is fixed in Fury Rev B, DustDevil Rev B, Tempest; these revisions will
  2015. be detected and the normal reset behaviour used.
  2016. @end itemize
  2017. @item @code{fa526} -- resembles arm920 (w/o Thumb)
  2018. @item @code{feroceon} -- resembles arm926
  2019. @item @code{mips_m4k} -- a MIPS core. This supports one variant:
  2020. @itemize @minus
  2021. @item @code{ejtag_srst} ... Use this when debugging targets that do not
  2022. provide a functional SRST line on the EJTAG connector. This causes
  2023. OpenOCD to instead use an EJTAG software reset command to reset the
  2024. processor.
  2025. You still need to enable @option{srst} on the @command{reset_config}
  2026. command to enable OpenOCD hardware reset functionality.
  2027. @end itemize
  2028. @item @code{xscale} -- this is actually an architecture,
  2029. not a CPU type. It is based on the ARMv5 architecture.
  2030. There are several variants defined:
  2031. @itemize @minus
  2032. @item @code{ixp42x}, @code{ixp45x}, @code{ixp46x},
  2033. @code{pxa27x} ... instruction register length is 7 bits
  2034. @item @code{pxa250}, @code{pxa255},
  2035. @code{pxa26x} ... instruction register length is 5 bits
  2036. @end itemize
  2037. @end itemize
  2038. @end deffn
  2039. To avoid being confused by the variety of ARM based cores, remember
  2040. this key point: @emph{ARM is a technology licencing company}.
  2041. (See: @url{}.)
  2042. The CPU name used by OpenOCD will reflect the CPU design that was
  2043. licenced, not a vendor brand which incorporates that design.
  2044. Name prefixes like arm7, arm9, arm11, and cortex
  2045. reflect design generations;
  2046. while names like ARMv4, ARMv5, ARMv6, and ARMv7
  2047. reflect an architecture version implemented by a CPU design.
  2048. @anchor{Target Configuration}
  2049. @section Target Configuration
  2050. Before creating a ``target'', you must have added its TAP to the scan chain.
  2051. When you've added that TAP, you will have a @code{}
  2052. which is used to set up the CPU support.
  2053. The chip-specific configuration file will normally configure its CPU(s)
  2054. right after it adds all of the chip's TAPs to the scan chain.
  2055. Although you can set up a target in one step, it's often clearer if you
  2056. use shorter commands and do it in two steps: create it, then configure
  2057. optional parts.
  2058. All operations on the target after it's created will use a new
  2059. command, created as part of target creation.
  2060. The two main things to configure after target creation are
  2061. a work area, which usually has target-specific defaults even
  2062. if the board setup code overrides them later;
  2063. and event handlers (@pxref{Target Events}), which tend
  2064. to be much more board-specific.
  2065. The key steps you use might look something like this
  2066. @example
  2067. target create MyTarget cortex_m3 -chain-position mychip.cpu
  2068. $MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
  2069. $MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
  2070. $MyTarget configure -event reset-init @{ myboard_reinit @}
  2071. @end example
  2072. You should specify a working area if you can; typically it uses some
  2073. on-chip SRAM.
  2074. Such a working area can speed up many things, including bulk
  2075. writes to target memory;
  2076. flash operations like checking to see if memory needs to be erased;
  2077. GDB memory checksumming;
  2078. and more.
  2079. @quotation Warning
  2080. On more complex chips, the work area can become
  2081. inaccessible when application code
  2082. (such as an operating system)
  2083. enables or disables the MMU.
  2084. For example, the particular MMU context used to acess the virtual
  2085. address will probably matter ... and that context might not have
  2086. easy access to other addresses needed.
  2087. At this writing, OpenOCD doesn't have much MMU intelligence.
  2088. @end quotation
  2089. It's often very useful to define a @code{reset-init} event handler.
  2090. For systems that are normally used with a boot loader,
  2091. common tasks include updating clocks and initializing memory
  2092. controllers.
  2093. That may be needed to let you write the boot loader into flash,
  2094. in order to ``de-brick'' your board; or to load programs into
  2095. external DDR memory without having run the boot loader.
  2096. @deffn Command {target create} target_name type configparams...
  2097. This command creates a GDB debug target that refers to a specific JTAG tap.
  2098. It enters that target into a list, and creates a new
  2099. command (@command{@var{target_name}}) which is used for various
  2100. purposes including additional configuration.
  2101. @itemize @bullet
  2102. @item @var{target_name} ... is the name of the debug target.
  2103. By convention this should be the same as the @emph{}
  2104. of the TAP associated with this target, which must be specified here
  2105. using the @code{-chain-position @var{}} configparam.
  2106. This name is also used to create the target object command,
  2107. referred to here as @command{$target_name},
  2108. and in other places the target needs to be identified.
  2109. @item @var{type} ... specifies the target type. @xref{target types}.
  2110. @item @var{configparams} ... all parameters accepted by
  2111. @command{$target_name configure} are permitted.
  2112. If the target is big-endian, set it here with @code{-endian big}.
  2113. If the variant matters, set it here with @code{-variant}.
  2114. You @emph{must} set the @code{-chain-position @var{}} here.
  2115. @end itemize
  2116. @end deffn
  2117. @deffn Command {$target_name configure} configparams...
  2118. The options accepted by this command may also be
  2119. specified as parameters to @command{target create}.
  2120. Their values can later be queried one at a time by
  2121. using the @command{$target_name cget} command.
  2122. @emph{Warning:} changing some of these after setup is dangerous.
  2123. For example, moving a target from one TAP to another;
  2124. and changing its endianness or variant.
  2125. @itemize @bullet
  2126. @item @code{-chain-position} @var{} -- names the TAP
  2127. used to access this target.
  2128. @item @code{-endian} (@option{big}|@option{little}) -- specifies
  2129. whether the CPU uses big or little endian conventions
  2130. @item @code{-event} @var{event_name} @var{event_body} --
  2131. @xref{Target Events}.
  2132. Note that this updates a list of named event handlers.
  2133. Calling this twice with two different event names assigns
  2134. two different handlers, but calling it twice with the
  2135. same event name assigns only one handler.
  2136. @item @code{-variant} @var{name} -- specifies a variant of the target,
  2137. which OpenOCD needs to know about.
  2138. @item @code{-work-area-backup} (@option{0}|@option{1}) -- says
  2139. whether the work area gets backed up; by default, it doesn't.
  2140. When possible, use a working_area that doesn't need to be backed up,
  2141. since performing a backup slows down operations.
  2142. @item @code{-work-area-size} @var{size} -- specify/set the work area
  2143. @item @code{-work-area-phys} @var{address} -- set the work area
  2144. base @var{address} to be used when no MMU is active.
  2145. @item @code{-work-area-virt} @var{address} -- set the work area
  2146. base @var{address} to be used when an MMU is active.
  2147. @end itemize
  2148. @end deffn
  2149. @section Other $target_name Commands
  2150. @cindex object command
  2151. The Tcl/Tk language has the concept of object commands,
  2152. and OpenOCD adopts that same model for targets.
  2153. A good Tk example is a on screen button.
  2154. Once a button is created a button
  2155. has a name (a path in Tk terms) and that name is useable as a first
  2156. class command. For example in Tk, one can create a button and later
  2157. configure it like this:
  2158. @example
  2159. # Create
  2160. button .foobar -background red -command @{ foo @}
  2161. # Modify
  2162. .foobar configure -foreground blue
  2163. # Query
  2164. set x [.foobar cget -background]
  2165. # Report
  2166. puts [format "The button is %s" $x]
  2167. @end example
  2168. In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
  2169. button, and its object commands are invoked the same way.
  2170. @example
  2171. str912.cpu mww 0x1234 0x42
  2172. omap3530.cpu mww 0x5555 123
  2173. @end example
  2174. The commands supported by OpenOCD target objects are:
  2175. @deffn Command {$target_name arp_examine}
  2176. @deffnx Command {$target_name arp_halt}
  2177. @deffnx Command {$target_name arp_poll}
  2178. @deffnx Command {$target_name arp_reset}
  2179. @deffnx Command {$target_name arp_waitstate}
  2180. Internal OpenOCD scripts (most notably @file{startup.tcl})
  2181. use these to deal with specific reset cases.
  2182. They are not otherwise documented here.
  2183. @end deffn
  2184. @deffn Command {$target_name array2mem} arrayname width address count
  2185. @deffnx Command {$target_name mem2array} arrayname width address count
  2186. These provide an efficient script-oriented interface to memory.
  2187. The @code{array2mem} primitive writes bytes, halfwords, or words;
  2188. while @code{mem2array} reads them.
  2189. In both cases, the TCL side uses an array, and
  2190. the target side uses raw memory.
  2191. The efficiency comes from enabling the use of
  2192. bulk JTAG data transfer operations.
  2193. The script orientation comes from working with data
  2194. values that are packaged for use by TCL scripts;
  2195. @command{mdw} type primitives only print data they retrieve,
  2196. and neither store nor return those values.
  2197. @itemize
  2198. @item @var{arrayname} ... is the name of an array variable
  2199. @item @var{width} ... is 8/16/32 - indicating the memory access size
  2200. @item @var{address} ... is the target memory address
  2201. @item @var{count} ... is the number of elements to process
  2202. @end itemize
  2203. @end deffn
  2204. @deffn Command {$target_name cget} queryparm
  2205. Each configuration parameter accepted by
  2206. @command{$target_name configure}
  2207. can be individually queried, to return its current value.
  2208. The @var{queryparm} is a parameter name
  2209. accepted by that command, such as @code{-work-area-phys}.
  2210. There are a few special cases:
  2211. @itemize @bullet
  2212. @item @code{-event} @var{event_name} -- returns the handler for the
  2213. event named @var{event_name}.
  2214. This is a special case because setting a handler requires
  2215. two parameters.
  2216. @item @code{-type} -- returns the target type.
  2217. This is a special case because this is set using
  2218. @command{target create} and can't be changed
  2219. using @command{$target_name configure}.
  2220. @end itemize
  2221. For example, if you wanted to summarize information about
  2222. all the targets you might use something like this:
  2223. @example
  2224. for @{ set x 0 @} @{ $x < [target count] @} @{ incr x @} @{
  2225. set name [target number $x]
  2226. set y [$name cget -endian]
  2227. set z [$name cget -type]
  2228. puts [format "Chip %d is %s, Endian: %s, type: %s" \
  2229. $x $name $y $z]
  2230. @}
  2231. @end example
  2232. @end deffn
  2233. @anchor{target curstate}
  2234. @deffn Command {$target_name curstate}
  2235. Displays the current target state:
  2236. @code{debug-running},
  2237. @code{halted},
  2238. @code{reset},
  2239. @code{running}, or @code{unknown}.
  2240. (Also, @pxref{Event Polling}.)
  2241. @end deffn
  2242. @deffn Command {$target_name eventlist}
  2243. Displays a table listing all event handlers
  2244. currently associated with this target.
  2245. @xref{Target Events}.
  2246. @end deffn
  2247. @deffn Command {$target_name invoke-event} event_name
  2248. Invokes the handler for the event named @var{event_name}.
  2249. (This is primarily intended for use by OpenOCD framework
  2250. code, for example by the reset code in @file{startup.tcl}.)
  2251. @end deffn
  2252. @deffn Command {$target_name mdw} addr [count]
  2253. @deffnx Command {$target_name mdh} addr [count]
  2254. @deffnx Command {$target_name mdb} addr [count]
  2255. Display contents of address @var{addr}, as
  2256. 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
  2257. or 8-bit bytes (@command{mdb}).
  2258. If @var{count} is specified, displays that many units.
  2259. (If you want to manipulate the data instead of displaying it,
  2260. see the @code{mem2array} primitives.)
  2261. @end deffn
  2262. @deffn Command {$target_name mww} addr word
  2263. @deffnx Command {$target_name mwh} addr halfword
  2264. @deffnx Command {$target_name mwb} addr byte
  2265. Writes the specified @var{word} (32 bits),
  2266. @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
  2267. at the specified address @var{addr}.
  2268. @end deffn
  2269. @anchor{Target Events}
  2270. @section Target Events
  2271. @cindex events
  2272. At various times, certain things can happen, or you want them to happen.
  2273. For example:
  2274. @itemize @bullet
  2275. @item What should happen when GDB connects? Should your target reset?
  2276. @item When GDB tries to flash the target, do you need to enable the flash via a special command?
  2277. @item During reset, do you need to write to certain memory locations
  2278. to set up system clocks or
  2279. to reconfigure the SDRAM?
  2280. @end itemize
  2281. All of the above items can be addressed by target event handlers.
  2282. These are set up by @command{$target_name configure -event} or
  2283. @command{target create ... -event}.
  2284. The programmer's model matches the @code{-command} option used in Tcl/Tk
  2285. buttons and events. The two examples below act the same, but one creates
  2286. and invokes a small procedure while the other inlines it.
  2287. @example
  2288. proc my_attach_proc @{ @} @{
  2289. echo "Reset..."
  2290. reset halt
  2291. @}
  2292. mychip.cpu configure -event gdb-attach my_attach_proc
  2293. mychip.cpu configure -event gdb-attach @{
  2294. echo "Reset..."
  2295. reset halt
  2296. @}
  2297. @end example
  2298. The following target events are defined:
  2299. @itemize @bullet
  2300. @item @b{debug-halted}
  2301. @* The target has halted for debug reasons (i.e.: breakpoint)
  2302. @item @b{debug-resumed}
  2303. @* The target has resumed (i.e.: gdb said run)
  2304. @item @b{early-halted}
  2305. @* Occurs early in the halt process
  2306. @ignore
  2307. @item @b{examine-end}
  2308. @* Currently not used (goal: when JTAG examine completes)
  2309. @item @b{examine-start}
  2310. @* Currently not used (goal: when JTAG examine starts)
  2311. @end ignore
  2312. @item @b{gdb-attach}
  2313. @* When GDB connects
  2314. @item @b{gdb-detach}
  2315. @* When GDB disconnects
  2316. @item @b{gdb-end}
  2317. @* When the target has halted and GDB is not doing anything (see early halt)
  2318. @item @b{gdb-flash-erase-start}
  2319. @* Before the GDB flash process tries to erase the flash
  2320. @item @b{gdb-flash-erase-end}
  2321. @* After the GDB flash process has finished erasing the flash
  2322. @item @b{gdb-flash-write-start}
  2323. @* Before GDB writes to the flash
  2324. @item @b{gdb-flash-write-end}
  2325. @* After GDB writes to the flash
  2326. @item @b{gdb-start}
  2327. @* Before the target steps, gdb is trying to start/resume the target
  2328. @item @b{halted}
  2329. @* The target has halted
  2330. @ignore
  2331. @item @b{old-gdb_program_config}
  2332. @* DO NOT USE THIS: Used internally
  2333. @item @b{old-pre_resume}
  2334. @* DO NOT USE THIS: Used internally
  2335. @end ignore
  2336. @item @b{reset-assert-pre}
  2337. @* Issued as part of @command{reset} processing
  2338. after SRST and/or TRST were activated and deactivated,
  2339. but before reset is asserted on the tap.
  2340. @item @b{reset-assert-post}
  2341. @* Issued as part of @command{reset} processing
  2342. when reset is asserted on the tap.
  2343. @item @b{reset-deassert-pre}
  2344. @* Issued as part of @command{reset} processing
  2345. when reset is about to be released on the tap.
  2346. For some chips, this may be a good place to make sure
  2347. the JTAG clock is slow enough to work before the PLL
  2348. has been set up to allow faster JTAG speeds.
  2349. @item @b{reset-deassert-post}
  2350. @* Issued as part of @command{reset} processing
  2351. when reset has been released on the tap.
  2352. @item @b{reset-end}
  2353. @* Issued as the final step in @command{reset} processing.
  2354. @ignore
  2355. @item @b{reset-halt-post}
  2356. @* Currently not used
  2357. @item @b{reset-halt-pre}
  2358. @* Currently not used
  2359. @end ignore
  2360. @item @b{reset-init}
  2361. @* Used by @b{reset init} command for board-specific initialization.
  2362. This event fires after @emph{reset-deassert-post}.
  2363. This is where you would configure PLLs and clocking, set up DRAM so
  2364. you can download programs that don't fit in on-chip SRAM, set up pin
  2365. multiplexing, and so on.
  2366. @item @b{reset-start}
  2367. @* Issued as part of @command{reset} processing
  2368. before either SRST or TRST are activated.
  2369. @ignore
  2370. @item @b{reset-wait-pos}
  2371. @* Currently not used
  2372. @item @b{reset-wait-pre}
  2373. @* Currently not used
  2374. @end ignore
  2375. @item @b{resume-start}
  2376. @* Before any target is resumed
  2377. @item @b{resume-end}
  2378. @* After all targets have resumed
  2379. @item @b{resume-ok}
  2380. @* Success
  2381. @item @b{resumed}
  2382. @* Target has resumed
  2383. @end itemize
  2384. @node Flash Commands
  2385. @chapter Flash Commands
  2386. OpenOCD has different commands for NOR and NAND flash;
  2387. the ``flash'' command works with NOR flash, while
  2388. the ``nand'' command works with NAND flash.
  2389. This partially reflects different hardware technologies:
  2390. NOR flash usually supports direct CPU instruction and data bus access,
  2391. while data from a NAND flash must be copied to memory before it can be
  2392. used. (SPI flash must also be copied to memory before use.)
  2393. However, the documentation also uses ``flash'' as a generic term;
  2394. for example, ``Put flash configuration in board-specific files''.
  2395. Flash Steps:
  2396. @enumerate
  2397. @item Configure via the command @command{flash bank}
  2398. @* Do this in a board-specific configuration file,
  2399. passing parameters as needed by the driver.
  2400. @item Operate on the flash via @command{flash subcommand}
  2401. @* Often commands to manipulate the flash are typed by a human, or run
  2402. via a script in some automated way. Common tasks include writing a
  2403. boot loader, operating system, or other data.
  2404. @item GDB Flashing
  2405. @* Flashing via GDB requires the flash be configured via ``flash
  2406. bank'', and the GDB flash features be enabled.
  2407. @xref{GDB Configuration}.
  2408. @end enumerate
  2409. Many CPUs have the ablity to ``boot'' from the first flash bank.
  2410. This means that misprogramming that bank can ``brick'' a system,
  2411. so that it can't boot.
  2412. JTAG tools, like OpenOCD, are often then used to ``de-brick'' the
  2413. board by (re)installing working boot firmware.
  2414. @anchor{NOR Configuration}
  2415. @section Flash Configuration Commands
  2416. @cindex flash configuration
  2417. @deffn {Config Command} {flash bank} driver base size chip_width bus_width target [driver_options]
  2418. Configures a flash bank which provides persistent storage
  2419. for addresses from @math{base} to @math{base + size - 1}.
  2420. These banks will often be visible to GDB through the target's memory map.
  2421. In some cases, configuring a flash bank will activate extra commands;
  2422. see the driver-specific documentation.
  2423. @itemize @bullet
  2424. @item @var{driver} ... identifies the controller driver
  2425. associated with the flash bank being declared.
  2426. This is usually @code{cfi} for external flash, or else
  2427. the name of a microcontroller with embedded flash memory.
  2428. @xref{Flash Driver List}.
  2429. @item @var{base} ... Base address of the flash chip.
  2430. @item @var{size} ... Size of the chip, in bytes.
  2431. For some drivers, this value is detected from the hardware.
  2432. @item @var{chip_width} ... Width of the flash chip, in bytes;
  2433. ignored for most microcontroller drivers.
  2434. @item @var{bus_width} ... Width of the data bus used to access the
  2435. chip, in bytes; ignored for most microcontroller drivers.
  2436. @item @var{target} ... Names the target used to issue
  2437. commands to the flash controller.
  2438. @comment Actually, it's currently a controller-specific parameter...
  2439. @item @var{driver_options} ... drivers may support, or require,
  2440. additional parameters. See the driver-specific documentation
  2441. for more information.
  2442. @end itemize
  2443. @quotation Note
  2444. This command is not available after OpenOCD initialization has completed.
  2445. Use it in board specific configuration files, not interactively.
  2446. @end quotation
  2447. @end deffn
  2448. @comment the REAL name for this command is "ocd_flash_banks"
  2449. @comment less confusing would be: "flash list" (like "nand list")
  2450. @deffn Command {flash banks}
  2451. Prints a one-line summary of each device declared
  2452. using @command{flash bank}, numbered from zero.
  2453. Note that this is the @emph{plural} form;
  2454. the @emph{singular} form is a very different command.
  2455. @end deffn
  2456. @deffn Command {flash probe} num
  2457. Identify the flash, or validate the parameters of the configured flash. Operation
  2458. depends on the flash type.
  2459. The @var{num} parameter is a value shown by @command{flash banks}.
  2460. Most flash commands will implicitly @emph{autoprobe} the bank;
  2461. flash drivers can distinguish between probing and autoprobing,
  2462. but most don't bother.
  2463. @end deffn
  2464. @section Erasing, Reading, Writing to Flash
  2465. @cindex flash erasing
  2466. @cindex flash reading
  2467. @cindex flash writing
  2468. @cindex flash programming
  2469. One feature distinguishing NOR flash from NAND or serial flash technologies
  2470. is that for read access, it acts exactly like any other addressible memory.
  2471. This means you can use normal memory read commands like @command{mdw} or
  2472. @command{dump_image} with it, with no special @command{flash} subcommands.
  2473. @xref{Memory access}, and @ref{Image access}.
  2474. Write access works differently. Flash memory normally needs to be erased
  2475. before it's written. Erasing a sector turns all of its bits to ones, and
  2476. writing can turn ones into zeroes. This is why there are special commands
  2477. for interactive erasing and writing, and why GDB needs to know which parts
  2478. of the address space hold NOR flash memory.
  2479. @quotation Note
  2480. Most of these erase and write commands leverage the fact that NOR flash
  2481. chips consume target address space. They implicitly refer to the current
  2482. JTAG target, and map from an address in that target's address space
  2483. back to a flash bank.
  2484. @comment In May 2009, those mappings may fail if any bank associated
  2485. @comment with that target doesn't succesfuly autoprobe ... bug worth fixing?
  2486. A few commands use abstract addressing based on bank and sector numbers,
  2487. and don't depend on searching the current target and its address space.
  2488. Avoid confusing the two command models.
  2489. @end quotation
  2490. Some flash chips implement software protection against accidental writes,
  2491. since such buggy writes could in some cases ``brick'' a system.
  2492. For such systems, erasing and writing may require sector protection to be
  2493. disabled first.
  2494. Examples include CFI flash such as ``Intel Advanced Bootblock flash'',
  2495. and AT91SAM7 on-chip flash.
  2496. @xref{flash protect}.
  2497. @anchor{flash erase_sector}
  2498. @deffn Command {flash erase_sector} num first last
  2499. Erase sectors in bank @var{num}, starting at sector @var{first} up to and including
  2500. @var{last}. Sector numbering starts at 0.
  2501. The @var{num} parameter is a value shown by @command{flash banks}.
  2502. @end deffn
  2503. @deffn Command {flash erase_address} address length
  2504. Erase sectors starting at @var{address} for @var{length} bytes.
  2505. The flash bank to use is inferred from the @var{address}, and
  2506. the specified length must stay within that bank.
  2507. As a special case, when @var{length} is zero and @var{address} is
  2508. the start of the bank, the whole flash is erased.
  2509. @end deffn
  2510. @deffn Command {flash fillw} address word length
  2511. @deffnx Command {flash fillh} address halfword length
  2512. @deffnx Command {flash fillb} address byte length
  2513. Fills flash memory with the specified @var{word} (32 bits),
  2514. @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
  2515. starting at @var{address} and continuing
  2516. for @var{length} units (word/halfword/byte).
  2517. No erasure is done before writing; when needed, that must be done
  2518. before issuing this command.
  2519. Writes are done in blocks of up to 1024 bytes, and each write is
  2520. verified by reading back the data and comparing it to what was written.
  2521. The flash bank to use is inferred from the @var{address} of
  2522. each block, and the specified length must stay within that bank.
  2523. @end deffn
  2524. @comment no current checks for errors if fill blocks touch multiple banks!
  2525. @anchor{flash write_bank}
  2526. @deffn Command {flash write_bank} num filename offset
  2527. Write the binary @file{filename} to flash bank @var{num},
  2528. starting at @var{offset} bytes from the beginning of the bank.
  2529. The @var{num} parameter is a value shown by @command{flash banks}.
  2530. @end deffn
  2531. @anchor{flash write_image}
  2532. @deffn Command {flash write_image} [erase] filename [offset] [type]
  2533. Write the image @file{filename} to the current target's flash bank(s).
  2534. A relocation @var{offset} may be specified, in which case it is added
  2535. to the base address for each section in the image.
  2536. The file [@var{type}] can be specified
  2537. explicitly as @option{bin} (binary), @option{ihex} (Intel hex),
  2538. @option{elf} (ELF file), @option{s19} (Motorola s19).
  2539. @option{mem}, or @option{builder}.
  2540. The relevant flash sectors will be erased prior to programming
  2541. if the @option{erase} parameter is given.
  2542. The flash bank to use is inferred from the @var{address} of
  2543. each image segment.
  2544. @end deffn
  2545. @section Other Flash commands
  2546. @cindex flash protection
  2547. @deffn Command {flash erase_check} num
  2548. Check erase state of sectors in flash bank @var{num},
  2549. and display that status.
  2550. The @var{num} parameter is a value shown by @command{flash banks}.
  2551. This is the only operation that
  2552. updates the erase state information displayed by @option{flash info}. That means you have
  2553. to issue an @command{flash erase_check} command after erasing or programming the device
  2554. to get updated information.
  2555. (Code execution may have invalidated any state records kept by OpenOCD.)
  2556. @end deffn
  2557. @deffn Command {flash info} num
  2558. Print info about flash bank @var{num}
  2559. The @var{num} parameter is a value shown by @command{flash banks}.
  2560. The information includes per-sector protect status.
  2561. @end deffn
  2562. @anchor{flash protect}
  2563. @deffn Command {flash protect} num first last (on|off)
  2564. Enable (@var{on}) or disable (@var{off}) protection of flash sectors
  2565. @var{first} to @var{last} of flash bank @var{num}.
  2566. The @var{num} parameter is a value shown by @command{flash banks}.
  2567. @end deffn
  2568. @deffn Command {flash protect_check} num
  2569. Check protection state of sectors in flash bank @var{num}.
  2570. The @var{num} parameter is a value shown by @command{flash banks}.
  2571. @comment @option{flash erase_sector} using the same syntax.
  2572. @end deffn
  2573. @anchor{Flash Driver List}
  2574. @section Flash Drivers, Options, and Commands
  2575. As noted above, the @command{flash bank} command requires a driver name,
  2576. and allows driver-specific options and behaviors.
  2577. Some drivers also activate driver-specific commands.
  2578. @subsection External Flash
  2579. @deffn {Flash Driver} cfi
  2580. @cindex Common Flash Interface
  2581. @cindex CFI
  2582. The ``Common Flash Interface'' (CFI) is the main standard for
  2583. external NOR flash chips, each of which connects to a
  2584. specific external chip select on the CPU.
  2585. Frequently the first such chip is used to boot the system.
  2586. Your board's @code{reset-init} handler might need to
  2587. configure additional chip selects using other commands (like: @command{mww} to
  2588. configure a bus and its timings) , or
  2589. perhaps configure a GPIO pin that controls the ``write protect'' pin
  2590. on the flash chip.
  2591. The CFI driver can use a target-specific working area to significantly
  2592. speed up operation.
  2593. The CFI driver can accept the following optional parameters, in any order:
  2594. @itemize
  2595. @item @var{jedec_probe} ... is used to detect certain non-CFI flash ROMs,
  2596. like AM29LV010 and similar types.
  2597. @item @var{x16_as_x8} ... when a 16-bit flash is hooked up to an 8-bit bus.
  2598. @end itemize
  2599. To configure two adjacent banks of 16 MBytes each, both sixteen bits (two bytes)
  2600. wide on a sixteen bit bus:
  2601. @example
  2602. flash bank cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
  2603. flash bank cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
  2604. @end example
  2605. @c "cfi part_id" disabled
  2606. @end deffn
  2607. @subsection Internal Flash (Microcontrollers)
  2608. @deffn {Flash Driver} aduc702x
  2609. The ADUC702x analog microcontrollers from ST Micro
  2610. include internal flash and use ARM7TDMI cores.
  2611. The aduc702x flash driver works with models ADUC7019 through ADUC7028.
  2612. The setup command only requires the @var{target} argument
  2613. since all devices in this family have the same memory layout.
  2614. @example
  2615. flash bank aduc702x 0 0 0 0 $_TARGETNAME
  2616. @end example
  2617. @end deffn
  2618. @deffn {Flash Driver} at91sam3
  2619. @cindex at91sam3
  2620. All members of the AT91SAM3 microcontroller family from
  2621. Atmel include internal flash and use ARM's Cortex-M3 core. The driver
  2622. currently (6/22/09) recognizes the AT91SAM3U[1/2/4][C/E] chips. Note
  2623. that the driver was orginaly developed and tested using the
  2624. AT91SAM3U4E, using a SAM3U-EK eval board. Support for other chips in
  2625. the family was cribbed from the data sheet. @emph{Note to future
  2626. readers/updaters: Please remove this worrysome comment after other
  2627. chips are confirmed.}
  2628. The AT91SAM3U4[E/C] (256K) chips have two flash banks; most other chips
  2629. have one flash bank. In all cases the flash banks are at
  2630. the following fixed locations:
  2631. @example
  2632. # Flash bank 0 - all chips
  2633. flash bank at91sam3 0x00080000 0 1 1 $_TARGETNAME
  2634. # Flash bank 1 - only 256K chips
  2635. flash bank at91sam3 0x00100000 0 1 1 $_TARGETNAME
  2636. @end example
  2637. Internally, the AT91SAM3 flash memory is organized as follows.
  2638. Unlike the AT91SAM7 chips, these are not used as parameters
  2639. to the @command{flash bank} command:
  2640. @itemize
  2641. @item @emph{N-Banks:} 256K chips have 2 banks, others have 1 bank.
  2642. @item @emph{Bank Size:} 128K/64K Per flash bank
  2643. @item @emph{Sectors:} 16 or 8 per bank
  2644. @item @emph{SectorSize:} 8K Per Sector
  2645. @item @emph{PageSize:} 256 bytes per page. Note that OpenOCD operates on 'sector' sizes, not page sizes.
  2646. @end itemize
  2647. The AT91SAM3 driver adds some additional commands:
  2648. @deffn Command {at91sam3 gpnvm}
  2649. @deffnx Command {at91sam3 gpnvm clear} number
  2650. @deffnx Command {at91sam3 gpnvm set} number
  2651. @deffnx Command {at91sam3 gpnvm show} [@option{all}|number]
  2652. With no parameters, @command{show} or @command{show all},
  2653. shows the status of all GPNVM bits.
  2654. With @command{show} @var{number}, displays that bit.
  2655. With @command{set} @var{number} or @command{clear} @var{number},
  2656. modifies that GPNVM bit.
  2657. @end deffn
  2658. @deffn Command {at91sam3 info}
  2659. This command attempts to display information about the AT91SAM3
  2660. chip. @emph{First} it read the @code{CHIPID_CIDR} [address 0x400e0740, see
  2661. Section 28.2.1, page 505 of the AT91SAM3U 29/may/2009 datasheet,
  2662. document id: doc6430A] and decodes the values. @emph{Second} it reads the
  2663. various clock configuration registers and attempts to display how it
  2664. believes the chip is configured. By default, the SLOWCLK is assumed to
  2665. be 32768 Hz, see the command @command{at91sam3 slowclk}.
  2666. @end deffn
  2667. @deffn Command {at91sam3 slowclk} [value]
  2668. This command shows/sets the slow clock frequency used in the
  2669. @command{at91sam3 info} command calculations above.
  2670. @end deffn
  2671. @end deffn
  2672. @deffn {Flash Driver} at91sam7
  2673. All members of the AT91SAM7 microcontroller family from Atmel include
  2674. internal flash and use ARM7TDMI cores. The driver automatically
  2675. recognizes a number of these chips using the chip identification
  2676. register, and autoconfigures itself.
  2677. @example
  2678. flash bank at91sam7 0 0 0 0 $_TARGETNAME
  2679. @end example
  2680. For chips which are not recognized by the controller driver, you must
  2681. provide additional parameters in the following order:
  2682. @itemize
  2683. @item @var{chip_model} ... label used with @command{flash info}
  2684. @item @var{banks}
  2685. @item @var{sectors_per_bank}
  2686. @item @var{pages_per_sector}
  2687. @item @var{pages_size}
  2688. @item @var{num_nvm_bits}
  2689. @item @var{freq_khz} ... required if an external clock is provided,
  2690. optional (but recommended) when the oscillator frequency is known
  2691. @end itemize
  2692. It is recommended that you provide zeroes for all of those values
  2693. except the clock frequency, so that everything except that frequency
  2694. will be autoconfigured.
  2695. Knowing the frequency helps ensure correct timings for flash access.
  2696. The flash controller handles erases automatically on a page (128/256 byte)
  2697. basis, so explicit erase commands are not necessary for flash programming.
  2698. However, there is an ``EraseAll`` command that can erase an entire flash
  2699. plane (of up to 256KB), and it will be used automatically when you issue
  2700. @command{flash erase_sector} or @command{flash erase_address} commands.
  2701. @deffn Command {at91sam7 gpnvm} bitnum (@option{set}|@option{clear})
  2702. Set or clear a ``General Purpose Non-Volatle Memory'' (GPNVM)
  2703. bit for the processor. Each processor has a number of such bits,
  2704. used for controlling features such as brownout detection (so they
  2705. are not truly general purpose).
  2706. @quotation Note
  2707. This assumes that the first flash bank (number 0) is associated with
  2708. the appropriate at91sam7 target.
  2709. @end quotation
  2710. @end deffn
  2711. @end deffn
  2712. @deffn {Flash Driver} avr
  2713. The AVR 8-bit microcontrollers from Atmel integrate flash memory.
  2714. @emph{The current implementation is incomplete.}
  2715. @comment - defines mass_erase ... pointless given flash_erase_address
  2716. @end deffn
  2717. @deffn {Flash Driver} ecosflash
  2718. @emph{No idea what this is...}
  2719. The @var{ecosflash} driver defines one mandatory parameter,
  2720. the name of a modules of target code which is downloaded
  2721. and executed.
  2722. @end deffn
  2723. @deffn {Flash Driver} lpc2000
  2724. Most members of the LPC2000 microcontroller family from NXP
  2725. include internal flash and use ARM7TDMI cores.
  2726. The @var{lpc2000} driver defines two mandatory and one optional parameters,
  2727. which must appear in the following order:
  2728. @itemize
  2729. @item @var{variant} ... required, may be
  2730. @var{lpc2000_v1} (older LPC21xx and LPC22xx)
  2731. or @var{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx)
  2732. @item @var{clock_kHz} ... the frequency, in kiloHertz,
  2733. at which the core is running
  2734. @item @var{calc_checksum} ... optional (but you probably want to provide this!),
  2735. telling the driver to calculate a valid checksum for the exception vector table.
  2736. @end itemize
  2737. LPC flashes don't require the chip and bus width to be specified.
  2738. @example
  2739. flash bank lpc2000 0x0 0x7d000 0 0 $_TARGETNAME \
  2740. lpc2000_v2 14765 calc_checksum
  2741. @end example
  2742. @deffn {Command} {lpc2000 part_id} bank
  2743. Displays the four byte part identifier associated with
  2744. the specified flash @var{bank}.
  2745. @end deffn
  2746. @end deffn
  2747. @deffn {Flash Driver} lpc288x
  2748. The LPC2888 microcontroller from NXP needs slightly different flash
  2749. support from its lpc2000 siblings.
  2750. The @var{lpc288x} driver defines one mandatory parameter,
  2751. the programming clock rate in Hz.
  2752. LPC flashes don't require the chip and bus width to be specified.
  2753. @example
  2754. flash bank lpc288x 0 0 0 0 $_TARGETNAME 12000000
  2755. @end example
  2756. @end deffn
  2757. @deffn {Flash Driver} ocl
  2758. @emph{No idea what this is, other than using some arm7/arm9 core.}
  2759. @example
  2760. flash bank ocl 0 0 0 0 $_TARGETNAME
  2761. @end example
  2762. @end deffn
  2763. @deffn {Flash Driver} pic32mx
  2764. The PIC32MX microcontrollers are based on the MIPS 4K cores,
  2765. and integrate flash memory.
  2766. @emph{The current implementation is incomplete.}
  2767. @example
  2768. flash bank pix32mx 0 0 0 0 $_TARGETNAME
  2769. @end example
  2770. @comment numerous *disabled* commands are defined:
  2771. @comment - chip_erase ... pointless given flash_erase_address
  2772. @comment - lock, unlock ... pointless given protect on/off (yes?)
  2773. @comment - pgm_word ... shouldn't bank be deduced from address??
  2774. Some pic32mx-specific commands are defined:
  2775. @deffn Command {pic32mx pgm_word} address value bank
  2776. Programs the specified 32-bit @var{value} at the given @var{address}
  2777. in the specified chip @var{bank}.
  2778. @end deffn
  2779. @end deffn
  2780. @deffn {Flash Driver} stellaris
  2781. All members of the Stellaris LM3Sxxx microcontroller family from
  2782. Texas Instruments
  2783. include internal flash and use ARM Cortex M3 cores.
  2784. The driver automatically recognizes a number of these chips using
  2785. the chip identification register, and autoconfigures itself.
  2786. @footnote{Currently there is a @command{stellaris mass_erase} command.
  2787. That seems pointless since the same effect can be had using the
  2788. standard @command{flash erase_address} command.}
  2789. @example
  2790. flash bank stellaris 0 0 0 0 $_TARGETNAME
  2791. @end example
  2792. @end deffn
  2793. @deffn {Flash Driver} stm32x
  2794. All members of the STM32 microcontroller family from ST Microelectronics
  2795. include internal flash and use ARM Cortex M3 cores.
  2796. The driver automatically recognizes a number of these chips using
  2797. the chip identification register, and autoconfigures itself.
  2798. @example
  2799. flash bank stm32x 0 0 0 0 $_TARGETNAME
  2800. @end example
  2801. Some stm32x-specific commands
  2802. @footnote{Currently there is a @command{stm32x mass_erase} command.
  2803. That seems pointless since the same effect can be had using the
  2804. standard @command{flash erase_address} command.}
  2805. are defined:
  2806. @deffn Command {stm32x lock} num
  2807. Locks the entire stm32 device.
  2808. The @var{num} parameter is a value shown by @command{flash banks}.
  2809. @end deffn
  2810. @deffn Command {stm32x unlock} num
  2811. Unlocks the entire stm32 device.
  2812. The @var{num} parameter is a value shown by @command{flash banks}.
  2813. @end deffn
  2814. @deffn Command {stm32x options_read} num
  2815. Read and display the stm32 option bytes written by
  2816. the @command{stm32x options_write} command.
  2817. The @var{num} parameter is a value shown by @command{flash banks}.
  2818. @end deffn
  2819. @deffn Command {stm32x options_write} num (@option{SWWDG}|@option{HWWDG}) (@option{RSTSTNDBY}|@option{NORSTSTNDBY}) (@option{RSTSTOP}|@option{NORSTSTOP})
  2820. Writes the stm32 option byte with the specified values.
  2821. The @var{num} parameter is a value shown by @command{flash banks}.
  2822. @end deffn
  2823. @end deffn
  2824. @deffn {Flash Driver} str7x
  2825. All members of the STR7 microcontroller family from ST Microelectronics
  2826. include internal flash and use ARM7TDMI cores.
  2827. The @var{str7x} driver defines one mandatory parameter, @var{variant},
  2828. which is either @code{STR71x}, @code{STR73x} or @code{STR75x}.
  2829. @example
  2830. flash bank str7x 0x40000000 0x00040000 0 0 $_TARGETNAME STR71x
  2831. @end example
  2832. @deffn Command {str7x disable_jtag} bank
  2833. Activate the Debug/Readout protection mechanism
  2834. for the specified flash bank.
  2835. @end deffn
  2836. @end deffn
  2837. @deffn {Flash Driver} str9x
  2838. Most members of the STR9 microcontroller family from ST Microelectronics
  2839. include internal flash and use ARM966E cores.
  2840. The str9 needs the flash controller to be configured using
  2841. the @command{str9x flash_config} command prior to Flash programming.
  2842. @example
  2843. flash bank str9x 0x40000000 0x00040000 0 0 $_TARGETNAME
  2844. str9x flash_config 0 4 2 0 0x80000
  2845. @end example
  2846. @deffn Command {str9x flash_config} num bbsr nbbsr bbadr nbbadr
  2847. Configures the str9 flash controller.
  2848. The @var{num} parameter is a value shown by @command{flash banks}.
  2849. @itemize @bullet
  2850. @item @var{bbsr} - Boot Bank Size register
  2851. @item @var{nbbsr} - Non Boot Bank Size register
  2852. @item @var{bbadr} - Boot Bank Start Address register
  2853. @item @var{nbbadr} - Boot Bank Start Address register
  2854. @end itemize
  2855. @end deffn
  2856. @end deffn
  2857. @deffn {Flash Driver} tms470
  2858. Most members of the TMS470 microcontroller family from Texas Instruments
  2859. include internal flash and use ARM7TDMI cores.
  2860. This driver doesn't require the chip and bus width to be specified.
  2861. Some tms470-specific commands are defined:
  2862. @deffn Command {tms470 flash_keyset} key0 key1 key2 key3
  2863. Saves programming keys in a register, to enable flash erase and write commands.
  2864. @end deffn
  2865. @deffn Command {tms470 osc_mhz} clock_mhz
  2866. Reports the clock speed, which is used to calculate timings.
  2867. @end deffn
  2868. @deffn Command {tms470 plldis} (0|1)
  2869. Disables (@var{1}) or enables (@var{0}) use of the PLL to speed up
  2870. the flash clock.
  2871. @end deffn
  2872. @end deffn
  2873. @subsection str9xpec driver
  2874. @cindex str9xpec
  2875. Here is some background info to help
  2876. you better understand how this driver works. OpenOCD has two flash drivers for
  2877. the str9:
  2878. @enumerate
  2879. @item
  2880. Standard driver @option{str9x} programmed via the str9 core. Normally used for
  2881. flash programming as it is faster than the @option{str9xpec} driver.
  2882. @item
  2883. Direct programming @option{str9xpec} using the flash controller. This is an
  2884. ISC compilant (IEEE 1532) tap connected in series with the str9 core. The str9
  2885. core does not need to be running to program using this flash driver. Typical use
  2886. for this driver is locking/unlocking the target and programming the option bytes.
  2887. @end enumerate
  2888. Before we run any commands using the @option{str9xpec} driver we must first disable
  2889. the str9 core. This example assumes the @option{str9xpec} driver has been
  2890. configured for flash bank 0.
  2891. @example
  2892. # assert srst, we do not want core running
  2893. # while accessing str9xpec flash driver
  2894. jtag_reset 0 1
  2895. # turn off target polling
  2896. poll off
  2897. # disable str9 core
  2898. str9xpec enable_turbo 0
  2899. # read option bytes
  2900. str9xpec options_read 0
  2901. # re-enable str9 core
  2902. str9xpec disable_turbo 0
  2903. poll on
  2904. reset halt
  2905. @end example
  2906. The above example will read the str9 option bytes.
  2907. When performing a unlock remember that you will not be able to halt the str9 - it
  2908. has been locked. Halting the core is not required for the @option{str9xpec} driver
  2909. as mentioned above, just issue the commands above manually or from a telnet prompt.
  2910. @deffn {Flash Driver} str9xpec
  2911. Only use this driver for locking/unlocking the device or configuring the option bytes.
  2912. Use the standard str9 driver for programming.
  2913. Before using the flash commands the turbo mode must be enabled using the
  2914. @command{str9xpec enable_turbo} command.
  2915. Several str9xpec-specific commands are defined:
  2916. @deffn Command {str9xpec disable_turbo} num
  2917. Restore the str9 into JTAG chain.
  2918. @end deffn
  2919. @deffn Command {str9xpec enable_turbo} num
  2920. Enable turbo mode, will simply remove the str9 from the chain and talk
  2921. directly to the embedded flash controller.
  2922. @end deffn
  2923. @deffn Command {str9xpec lock} num
  2924. Lock str9 device. The str9 will only respond to an unlock command that will
  2925. erase the device.
  2926. @end deffn
  2927. @deffn Command {str9xpec part_id} num
  2928. Prints the part identifier for bank @var{num}.
  2929. @end deffn
  2930. @deffn Command {str9xpec options_cmap} num (@option{bank0}|@option{bank1})
  2931. Configure str9 boot bank.
  2932. @end deffn
  2933. @deffn Command {str9xpec options_lvdsel} num (@option{vdd}|@option{vdd_vddq})
  2934. Configure str9 lvd source.
  2935. @end deffn
  2936. @deffn Command {str9xpec options_lvdthd} num (@option{2.4v}|@option{2.7v})
  2937. Configure str9 lvd threshold.
  2938. @end deffn
  2939. @deffn Command {str9xpec options_lvdwarn} bank (@option{vdd}|@option{vdd_vddq})
  2940. Configure str9 lvd reset warning source.
  2941. @end deffn
  2942. @deffn Command {str9xpec options_read} num
  2943. Read str9 option bytes.
  2944. @end deffn
  2945. @deffn Command {str9xpec options_write} num
  2946. Write str9 option bytes.
  2947. @end deffn
  2948. @deffn Command {str9xpec unlock} num
  2949. unlock str9 device.
  2950. @end deffn
  2951. @end deffn
  2952. @section mFlash
  2953. @subsection mFlash Configuration
  2954. @cindex mFlash Configuration
  2955. @deffn {Config Command} {mflash bank} soc base RST_pin target
  2956. Configures a mflash for @var{soc} host bank at
  2957. address @var{base}.
  2958. The pin number format depends on the host GPIO naming convention.
  2959. Currently, the mflash driver supports s3c2440 and pxa270.
  2960. Example for s3c2440 mflash where @var{RST pin} is GPIO B1:
  2961. @example
  2962. mflash bank s3c2440 0x10000000 1b 0
  2963. @end example
  2964. Example for pxa270 mflash where @var{RST pin} is GPIO 43:
  2965. @example
  2966. mflash bank pxa270 0x08000000 43 0
  2967. @end example
  2968. @end deffn
  2969. @subsection mFlash commands
  2970. @cindex mFlash commands
  2971. @deffn Command {mflash config pll} frequency
  2972. Configure mflash PLL.
  2973. The @var{frequency} is the mflash input frequency, in Hz.
  2974. Issuing this command will erase mflash's whole internal nand and write new pll.
  2975. After this command, mflash needs power-on-reset for normal operation.
  2976. If pll was newly configured, storage and boot(optional) info also need to be update.
  2977. @end deffn
  2978. @deffn Command {mflash config boot}
  2979. Configure bootable option.
  2980. If bootable option is set, mflash offer the first 8 sectors
  2981. (4kB) for boot.
  2982. @end deffn
  2983. @deffn Command {mflash config storage}
  2984. Configure storage information.
  2985. For the normal storage operation, this information must be
  2986. written.
  2987. @end deffn
  2988. @deffn Command {mflash dump} num filename offset size
  2989. Dump @var{size} bytes, starting at @var{offset} bytes from the
  2990. beginning of the bank @var{num}, to the file named @var{filename}.
  2991. @end deffn
  2992. @deffn Command {mflash probe}
  2993. Probe mflash.
  2994. @end deffn
  2995. @deffn Command {mflash write} num filename offset
  2996. Write the binary file @var{filename} to mflash bank @var{num}, starting at
  2997. @var{offset} bytes from the beginning of the bank.
  2998. @end deffn
  2999. @node NAND Flash Commands
  3000. @chapter NAND Flash Commands
  3001. @cindex NAND
  3002. Compared to NOR or SPI flash, NAND devices are inexpensive
  3003. and high density. Today's NAND chips, and multi-chip modules,
  3004. commonly hold multiple GigaBytes of data.
  3005. NAND chips consist of a number of ``erase blocks'' of a given
  3006. size (such as 128 KBytes), each of which is divided into a
  3007. number of pages (of perhaps 512 or 2048 bytes each). Each
  3008. page of a NAND flash has an ``out of band'' (OOB) area to hold
  3009. Error Correcting Code (ECC) and other metadata, usually 16 bytes
  3010. of OOB for every 512 bytes of page data.
  3011. One key characteristic of NAND flash is that its error rate
  3012. is higher than that of NOR flash. In normal operation, that
  3013. ECC is used to correct and detect errors. However, NAND
  3014. blocks can also wear out and become unusable; those blocks
  3015. are then marked "bad". NAND chips are even shipped from the
  3016. manufacturer with a few bad blocks. The highest density chips
  3017. use a technology (MLC) that wears out more quickly, so ECC
  3018. support is increasingly important as a way to detect blocks
  3019. that have begun to fail, and help to preserve data integrity
  3020. with techniques such as wear leveling.
  3021. Software is used to manage the ECC. Some controllers don't
  3022. support ECC directly; in those cases, software ECC is used.
  3023. Other controllers speed up the ECC calculations with hardware.
  3024. Single-bit error correction hardware is routine. Controllers
  3025. geared for newer MLC chips may correct 4 or more errors for
  3026. every 512 bytes of data.
  3027. You will need to make sure that any data you write using
  3028. OpenOCD includes the apppropriate kind of ECC. For example,
  3029. that may mean passing the @code{oob_softecc} flag when
  3030. writing NAND data, or ensuring that the correct hardware
  3031. ECC mode is used.
  3032. The basic steps for using NAND devices include:
  3033. @enumerate
  3034. @item Declare via the command @command{nand device}
  3035. @* Do this in a board-specific configuration file,
  3036. passing parameters as needed by the controller.
  3037. @item Configure each device using @command{nand probe}.
  3038. @* Do this only after the associated target is set up,
  3039. such as in its reset-init script or in procures defined
  3040. to access that device.
  3041. @item Operate on the flash via @command{nand subcommand}
  3042. @* Often commands to manipulate the flash are typed by a human, or run
  3043. via a script in some automated way. Common task include writing a
  3044. boot loader, operating system, or other data needed to initialize or
  3045. de-brick a board.
  3046. @end enumerate
  3047. @b{NOTE:} At the time this text was written, the largest NAND
  3048. flash fully supported by OpenOCD is 2 GiBytes (16 GiBits).
  3049. This is because the variables used to hold offsets and lengths
  3050. are only 32 bits wide.
  3051. (Larger chips may work in some cases, unless an offset or length
  3052. is larger than 0xffffffff, the largest 32-bit unsigned integer.)
  3053. Some larger devices will work, since they are actually multi-chip
  3054. modules with two smaller chips and individual chipselect lines.
  3055. @anchor{NAND Configuration}
  3056. @section NAND Configuration Commands
  3057. @cindex NAND configuration
  3058. NAND chips must be declared in configuration scripts,
  3059. plus some additional configuration that's done after
  3060. OpenOCD has initialized.
  3061. @deffn {Config Command} {nand device} controller target [configparams...]
  3062. Declares a NAND device, which can be read and written to
  3063. after it has been configured through @command{nand probe}.
  3064. In OpenOCD, devices are single chips; this is unlike some
  3065. operating systems, which may manage multiple chips as if
  3066. they were a single (larger) device.
  3067. In some cases, configuring a device will activate extra
  3068. commands; see the controller-specific documentation.
  3069. @b{NOTE:} This command is not available after OpenOCD
  3070. initialization has completed. Use it in board specific
  3071. configuration files, not interactively.
  3072. @itemize @bullet
  3073. @item @var{controller} ... identifies the controller driver
  3074. associated with the NAND device being declared.
  3075. @xref{NAND Driver List}.
  3076. @item @var{target} ... names the target used when issuing
  3077. commands to the NAND controller.
  3078. @comment Actually, it's currently a controller-specific parameter...
  3079. @item @var{configparams} ... controllers may support, or require,
  3080. additional parameters. See the controller-specific documentation
  3081. for more information.
  3082. @end itemize
  3083. @end deffn
  3084. @deffn Command {nand list}
  3085. Prints a one-line summary of each device declared
  3086. using @command{nand device}, numbered from zero.
  3087. Note that un-probed devices show no details.
  3088. @end deffn
  3089. @deffn Command {nand probe} num
  3090. Probes the specified device to determine key characteristics
  3091. like its page and block sizes, and how many blocks it has.
  3092. The @var{num} parameter is the value shown by @command{nand list}.
  3093. You must (successfully) probe a device before you can use
  3094. it with most other NAND commands.
  3095. @end deffn
  3096. @section Erasing, Reading, Writing to NAND Flash
  3097. @deffn Command {nand dump} num filename offset length [oob_option]
  3098. @cindex NAND reading
  3099. Reads binary data from the NAND device and writes it to the file,
  3100. starting at the specified offset.
  3101. The @var{num} parameter is the value shown by @command{nand list}.
  3102. Use a complete path name for @var{filename}, so you don't depend
  3103. on the directory used to start the OpenOCD server.
  3104. The @var{offset} and @var{length} must be exact multiples of the
  3105. device's page size. They describe a data region; the OOB data
  3106. associated with each such page may also be accessed.
  3107. @b{NOTE:} At the time this text was written, no error correction
  3108. was done on the data that's read, unless raw access was disabled
  3109. and the underlying NAND controller driver had a @code{read_page}
  3110. method which handled that error correction.
  3111. By default, only page data is saved to the specified file.
  3112. Use an @var{oob_option} parameter to save OOB data:
  3113. @itemize @bullet
  3114. @item no oob_* parameter
  3115. @*Output file holds only page data; OOB is discarded.
  3116. @item @code{oob_raw}
  3117. @*Output file interleaves page data and OOB data;
  3118. the file will be longer than "length" by the size of the
  3119. spare areas associated with each data page.
  3120. Note that this kind of "raw" access is different from
  3121. what's implied by @command{nand raw_access}, which just
  3122. controls whether a hardware-aware access method is used.
  3123. @item @code{oob_only}
  3124. @*Output file has only raw OOB data, and will
  3125. be smaller than "length" since it will contain only the
  3126. spare areas associated with each data page.
  3127. @end itemize
  3128. @end deffn
  3129. @deffn Command {nand erase} num offset length
  3130. @cindex NAND erasing
  3131. @cindex NAND programming
  3132. Erases blocks on the specified NAND device, starting at the
  3133. specified @var{offset} and continuing for @var{length} bytes.
  3134. Both of those values must be exact multiples of the device's
  3135. block size, and the region they specify must fit entirely in the chip.
  3136. The @var{num} parameter is the value shown by @command{nand list}.
  3137. @b{NOTE:} This command will try to erase bad blocks, when told
  3138. to do so, which will probably invalidate the manufacturer's bad
  3139. block marker.
  3140. For the remainder of the current server session, @command{nand info}
  3141. will still report that the block ``is'' bad.
  3142. @end deffn
  3143. @deffn Command {nand write} num filename offset [option...]
  3144. @cindex NAND writing
  3145. @cindex NAND programming
  3146. Writes binary data from the file into the specified NAND device,
  3147. starting at the specified offset. Those pages should already
  3148. have been erased; you can't change zero bits to one bits.
  3149. The @var{num} parameter is the value shown by @command{nand list}.
  3150. Use a complete path name for @var{filename}, so you don't depend
  3151. on the directory used to start the OpenOCD server.
  3152. The @var{offset} must be an exact multiple of the device's page size.
  3153. All data in the file will be written, assuming it doesn't run
  3154. past the end of the device.
  3155. Only full pages are written, and any extra space in the last
  3156. page will be filled with 0xff bytes. (That includes OOB data,
  3157. if that's being written.)
  3158. @b{NOTE:} At the time this text was written, bad blocks are
  3159. ignored. That is, this routine will not skip bad blocks,
  3160. but will instead try to write them. This can cause problems.
  3161. Provide at most one @var{option} parameter. With some
  3162. NAND drivers, the meanings of these parameters may change
  3163. if @command{nand raw_access} was used to disable hardware ECC.
  3164. @itemize @bullet
  3165. @item no oob_* parameter
  3166. @*File has only page data, which is written.
  3167. If raw acccess is in use, the OOB area will not be written.
  3168. Otherwise, if the underlying NAND controller driver has
  3169. a @code{write_page} routine, that routine may write the OOB
  3170. with hardware-computed ECC data.
  3171. @item @code{oob_only}
  3172. @*File has only raw OOB data, which is written to the OOB area.
  3173. Each page's data area stays untouched. @i{This can be a dangerous
  3174. option}, since it can invalidate the ECC data.
  3175. You may need to force raw access to use this mode.
  3176. @item @code{oob_raw}
  3177. @*File interleaves data and OOB data, both of which are written
  3178. If raw access is enabled, the data is written first, then the
  3179. un-altered OOB.
  3180. Otherwise, if the underlying NAND controller driver has
  3181. a @code{write_page} routine, that routine may modify the OOB
  3182. before it's written, to include hardware-computed ECC data.
  3183. @item @code{oob_softecc}
  3184. @*File has only page data, which is written.
  3185. The OOB area is filled with 0xff, except for a standard 1-bit
  3186. software ECC code stored in conventional locations.
  3187. You might need to force raw access to use this mode, to prevent
  3188. the underlying driver from applying hardware ECC.
  3189. @item @code{oob_softecc_kw}
  3190. @*File has only page data, which is written.
  3191. The OOB area is filled with 0xff, except for a 4-bit software ECC
  3192. specific to the boot ROM in Marvell Kirkwood SoCs.
  3193. You might need to force raw access to use this mode, to prevent
  3194. the underlying driver from applying hardware ECC.
  3195. @end itemize
  3196. @end deffn
  3197. @section Other NAND commands
  3198. @cindex NAND other commands
  3199. @deffn Command {nand check_bad_blocks} [offset length]
  3200. Checks for manufacturer bad block markers on the specified NAND
  3201. device. If no parameters are provided, checks the whole
  3202. device; otherwise, starts at the specified @var{offset} and
  3203. continues for @var{length} bytes.
  3204. Both of those values must be exact multiples of the device's
  3205. block size, and the region they specify must fit entirely in the chip.
  3206. The @var{num} parameter is the value shown by @command{nand list}.
  3207. @b{NOTE:} Before using this command you should force raw access
  3208. with @command{nand raw_access enable} to ensure that the underlying
  3209. driver will not try to apply hardware ECC.
  3210. @end deffn
  3211. @deffn Command {nand info} num
  3212. The @var{num} parameter is the value shown by @command{nand list}.
  3213. This prints the one-line summary from "nand list", plus for
  3214. devices which have been probed this also prints any known
  3215. status for each block.
  3216. @end deffn
  3217. @deffn Command {nand raw_access} num (@option{enable}|@option{disable})
  3218. Sets or clears an flag affecting how page I/O is done.
  3219. The @var{num} parameter is the value shown by @command{nand list}.
  3220. This flag is cleared (disabled) by default, but changing that
  3221. value won't affect all NAND devices. The key factor is whether
  3222. the underlying driver provides @code{read_page} or @code{write_page}
  3223. methods. If it doesn't provide those methods, the setting of
  3224. this flag is irrelevant; all access is effectively ``raw''.
  3225. When those methods exist, they are normally used when reading
  3226. data (@command{nand dump} or reading bad block markers) or
  3227. writing it (@command{nand write}). However, enabling
  3228. raw access (setting the flag) prevents use of those methods,
  3229. bypassing hardware ECC logic.
  3230. @i{This can be a dangerous option}, since writing blocks
  3231. with the wrong ECC data can cause them to be marked as bad.
  3232. @end deffn
  3233. @anchor{NAND Driver List}
  3234. @section NAND Drivers, Options, and Commands
  3235. As noted above, the @command{nand device} command allows
  3236. driver-specific options and behaviors.
  3237. Some controllers also activate controller-specific commands.
  3238. @deffn {NAND Driver} davinci
  3239. This driver handles the NAND controllers found on DaVinci family
  3240. chips from Texas Instruments.
  3241. It takes three extra parameters:
  3242. address of the NAND chip;
  3243. hardware ECC mode to use (hwecc1, hwecc4, hwecc4_infix);
  3244. address of the AEMIF controller on this processor.
  3245. @example
  3246. nand device davinci dm355.arm 0x02000000 hwecc4 0x01e10000
  3247. @end example
  3248. All DaVinci processors support the single-bit ECC hardware,
  3249. and newer ones also support the four-bit ECC hardware.
  3250. The @code{write_page} and @code{read_page} methods are used
  3251. to implement those ECC modes, unless they are disabled using
  3252. the @command{nand raw_access} command.
  3253. @end deffn
  3254. @deffn {NAND Driver} lpc3180
  3255. These controllers require an extra @command{nand device}
  3256. parameter: the clock rate used by the controller.
  3257. @deffn Command {lpc3180 select} num [mlc|slc]
  3258. Configures use of the MLC or SLC controller mode.
  3259. MLC implies use of hardware ECC.
  3260. The @var{num} parameter is the value shown by @command{nand list}.
  3261. @end deffn
  3262. At this writing, this driver includes @code{write_page}
  3263. and @code{read_page} methods. Using @command{nand raw_access}
  3264. to disable those methods will prevent use of hardware ECC
  3265. in the MLC controller mode, but won't change SLC behavior.
  3266. @end deffn
  3267. @comment current lpc3180 code won't issue 5-byte address cycles
  3268. @deffn {NAND Driver} orion
  3269. These controllers require an extra @command{nand device}
  3270. parameter: the address of the controller.
  3271. @example
  3272. nand device orion 0xd8000000
  3273. @end example
  3274. These controllers don't define any specialized commands.
  3275. At this writing, their drivers don't include @code{write_page}
  3276. or @code{read_page} methods, so @command{nand raw_access} won't
  3277. change any behavior.
  3278. @end deffn
  3279. @deffn {NAND Driver} s3c2410
  3280. @deffnx {NAND Driver} s3c2412
  3281. @deffnx {NAND Driver} s3c2440
  3282. @deffnx {NAND Driver} s3c2443
  3283. These S3C24xx family controllers don't have any special
  3284. @command{nand device} options, and don't define any
  3285. specialized commands.
  3286. At this writing, their drivers don't include @code{write_page}
  3287. or @code{read_page} methods, so @command{nand raw_access} won't
  3288. change any behavior.
  3289. @end deffn
  3290. @node PLD/FPGA Commands
  3291. @chapter PLD/FPGA Commands
  3292. @cindex PLD
  3293. @cindex FPGA
  3294. Programmable Logic Devices (PLDs) and the more flexible
  3295. Field Programmable Gate Arrays (FPGAs) are both types of programmable hardware.
  3296. OpenOCD can support programming them.
  3297. Although PLDs are generally restrictive (cells are less functional, and
  3298. there are no special purpose cells for memory or computational tasks),
  3299. they share the same OpenOCD infrastructure.
  3300. Accordingly, both are called PLDs here.
  3301. @section PLD/FPGA Configuration and Commands
  3302. As it does for JTAG TAPs, debug targets, and flash chips (both NOR and NAND),
  3303. OpenOCD maintains a list of PLDs available for use in various commands.
  3304. Also, each such PLD requires a driver.
  3305. They are referenced by the number shown by the @command{pld devices} command,
  3306. and new PLDs are defined by @command{pld device driver_name}.
  3307. @deffn {Config Command} {pld device} driver_name tap_name [driver_options]
  3308. Defines a new PLD device, supported by driver @var{driver_name},
  3309. using the TAP named @var{tap_name}.
  3310. The driver may make use of any @var{driver_options} to configure its
  3311. behavior.
  3312. @end deffn
  3313. @deffn {Command} {pld devices}
  3314. Lists the PLDs and their numbers.
  3315. @end deffn
  3316. @deffn {Command} {pld load} num filename
  3317. Loads the file @file{filename} into the PLD identified by @var{num}.
  3318. The file format must be inferred by the driver.
  3319. @end deffn
  3320. @section PLD/FPGA Drivers, Options, and Commands
  3321. Drivers may support PLD-specific options to the @command{pld device}
  3322. definition command, and may also define commands usable only with
  3323. that particular type of PLD.
  3324. @deffn {FPGA Driver} virtex2
  3325. Virtex-II is a family of FPGAs sold by Xilinx.
  3326. It supports the IEEE 1532 standard for In-System Configuration (ISC).
  3327. No driver-specific PLD definition options are used,
  3328. and one driver-specific command is defined.
  3329. @deffn {Command} {virtex2 read_stat} num
  3330. Reads and displays the Virtex-II status register (STAT)
  3331. for FPGA @var{num}.
  3332. @end deffn
  3333. @end deffn
  3334. @node General Commands
  3335. @chapter General Commands
  3336. @cindex commands
  3337. The commands documented in this chapter here are common commands that
  3338. you, as a human, may want to type and see the output of. Configuration type
  3339. commands are documented elsewhere.
  3340. Intent:
  3341. @itemize @bullet
  3342. @item @b{Source Of Commands}
  3343. @* OpenOCD commands can occur in a configuration script (discussed
  3344. elsewhere) or typed manually by a human or supplied programatically,
  3345. or via one of several TCP/IP Ports.
  3346. @item @b{From the human}
  3347. @* A human should interact with the telnet interface (default port: 4444)
  3348. or via GDB (default port 3333).
  3349. To issue commands from within a GDB session, use the @option{monitor}
  3350. command, e.g. use @option{monitor poll} to issue the @option{poll}
  3351. command. All output is relayed through the GDB session.
  3352. @item @b{Machine Interface}
  3353. The Tcl interface's intent is to be a machine interface. The default Tcl
  3354. port is 5555.
  3355. @end itemize
  3356. @section Daemon Commands
  3357. @deffn {Command} exit
  3358. Exits the current telnet session.
  3359. @end deffn
  3360. @c note EXTREMELY ANNOYING word wrap at column 75
  3361. @c even when lines are e.g. 100+ columns ...
  3362. @c coded in startup.tcl
  3363. @deffn {Command} help [string]
  3364. With no parameters, prints help text for all commands.
  3365. Otherwise, prints each helptext containing @var{string}.
  3366. Not every command provides helptext.
  3367. @end deffn
  3368. @deffn Command sleep msec [@option{busy}]
  3369. Wait for at least @var{msec} milliseconds before resuming.
  3370. If @option{busy} is passed, busy-wait instead of sleeping.
  3371. (This option is strongly discouraged.)
  3372. Useful in connection with script files
  3373. (@command{script} command and @command{target_name} configuration).
  3374. @end deffn
  3375. @deffn Command shutdown
  3376. Close the OpenOCD daemon, disconnecting all clients (GDB, telnet, other).
  3377. @end deffn
  3378. @anchor{debug_level}
  3379. @deffn Command debug_level [n]
  3380. @cindex message level
  3381. Display debug level.
  3382. If @var{n} (from 0..3) is provided, then set it to that level.
  3383. This affects the kind of messages sent to the server log.
  3384. Level 0 is error messages only;
  3385. level 1 adds warnings;
  3386. level 2 adds informational messages;
  3387. and level 3 adds debugging messages.
  3388. The default is level 2, but that can be overridden on
  3389. the command line along with the location of that log
  3390. file (which is normally the server's standard output).
  3391. @xref{Running}.
  3392. @end deffn
  3393. @deffn Command fast (@option{enable}|@option{disable})
  3394. Default disabled.
  3395. Set default behaviour of OpenOCD to be "fast and dangerous".
  3396. At this writing, this only affects the defaults for two ARM7/ARM9 parameters:
  3397. fast memory access, and DCC downloads. Those parameters may still be
  3398. individually overridden.
  3399. The target specific "dangerous" optimisation tweaking options may come and go
  3400. as more robust and user friendly ways are found to ensure maximum throughput
  3401. and robustness with a minimum of configuration.
  3402. Typically the "fast enable" is specified first on the command line:
  3403. @example
  3404. openocd -c "fast enable" -c "interface dummy" -f target/str710.cfg
  3405. @end example
  3406. @end deffn
  3407. @deffn Command echo message
  3408. Logs a message at "user" priority.
  3409. Output @var{message} to stdout.
  3410. @example
  3411. echo "Downloading kernel -- please wait"
  3412. @end example
  3413. @end deffn
  3414. @deffn Command log_output [filename]
  3415. Redirect logging to @var{filename};
  3416. the initial log output channel is stderr.
  3417. @end deffn
  3418. @anchor{Target State handling}
  3419. @section Target State handling
  3420. @cindex reset
  3421. @cindex halt
  3422. @cindex target initialization
  3423. In this section ``target'' refers to a CPU configured as
  3424. shown earlier (@pxref{CPU Configuration}).
  3425. These commands, like many, implicitly refer to
  3426. a current target which is used to perform the
  3427. various operations. The current target may be changed
  3428. by using @command{targets} command with the name of the
  3429. target which should become current.
  3430. @deffn Command reg [(number|name) [value]]
  3431. Access a single register by @var{number} or by its @var{name}.
  3432. @emph{With no arguments}:
  3433. list all available registers for the current target,
  3434. showing number, name, size, value, and cache status.
  3435. @emph{With number/name}: display that register's value.
  3436. @emph{With both number/name and value}: set register's value.
  3437. Cores may have surprisingly many registers in their
  3438. Debug and trace infrastructure:
  3439. @example
  3440. > reg
  3441. (0) r0 (/32): 0x0000D3C2 (dirty: 1, valid: 1)
  3442. (1) r1 (/32): 0xFD61F31C (dirty: 0, valid: 1)
  3443. (2) r2 (/32): 0x00022551 (dirty: 0, valid: 1)
  3444. ...
  3445. (164) ETM_CONTEXTID_COMPARATOR_MASK (/32): \
  3446. 0x00000000 (dirty: 0, valid: 0)
  3447. >
  3448. @end example
  3449. @end deffn
  3450. @deffn Command halt [ms]
  3451. @deffnx Command wait_halt [ms]
  3452. The @command{halt} command first sends a halt request to the target,
  3453. which @command{wait_halt} doesn't.
  3454. Otherwise these behave the same: wait up to @var{ms} milliseconds,
  3455. or 5 seconds if there is no parameter, for the target to halt
  3456. (and enter debug mode).
  3457. Using 0 as the @var{ms} parameter prevents OpenOCD from waiting.
  3458. @end deffn
  3459. @deffn Command resume [address]
  3460. Resume the target at its current code position,
  3461. or the optional @var{address} if it is provided.
  3462. OpenOCD will wait 5 seconds for the target to resume.
  3463. @end deffn
  3464. @deffn Command step [address]
  3465. Single-step the target at its current code position,
  3466. or the optional @var{address} if it is provided.
  3467. @end deffn
  3468. @anchor{Reset Command}
  3469. @deffn Command reset
  3470. @deffnx Command {reset run}
  3471. @deffnx Command {reset halt}
  3472. @deffnx Command {reset init}
  3473. Perform as hard a reset as possible, using SRST if possible.
  3474. @emph{All defined targets will be reset, and target
  3475. events will fire during the reset sequence.}
  3476. The optional parameter specifies what should
  3477. happen after the reset.
  3478. If there is no parameter, a @command{reset run} is executed.
  3479. The other options will not work on all systems.
  3480. @xref{Reset Configuration}.
  3481. @itemize @minus
  3482. @item @b{run} Let the target run
  3483. @item @b{halt} Immediately halt the target
  3484. @item @b{init} Immediately halt the target, and execute the reset-init script
  3485. @end itemize
  3486. @end deffn
  3487. @deffn Command soft_reset_halt
  3488. Requesting target halt and executing a soft reset. This is often used
  3489. when a target cannot be reset and halted. The target, after reset is
  3490. released begins to execute code. OpenOCD attempts to stop the CPU and
  3491. then sets the program counter back to the reset vector. Unfortunately
  3492. the code that was executed may have left the hardware in an unknown
  3493. state.
  3494. @end deffn
  3495. @section I/O Utilities
  3496. These commands are available when
  3497. OpenOCD is built with @option{--enable-ioutil}.
  3498. They are mainly useful on embedded targets,
  3499. notably the ZY1000.
  3500. Hosts with operating systems have complementary tools.
  3501. @emph{Note:} there are several more such commands.
  3502. @deffn Command append_file filename [string]*
  3503. Appends the @var{string} parameters to
  3504. the text file @file{filename}.
  3505. Each string except the last one is followed by one space.
  3506. The last string is followed by a newline.
  3507. @end deffn
  3508. @deffn Command cat filename
  3509. Reads and displays the text file @file{filename}.
  3510. @end deffn
  3511. @deffn Command cp src_filename dest_filename
  3512. Copies contents from the file @file{src_filename}
  3513. into @file{dest_filename}.
  3514. @end deffn
  3515. @deffn Command ip
  3516. @emph{No description provided.}
  3517. @end deffn
  3518. @deffn Command ls
  3519. @emph{No description provided.}
  3520. @end deffn
  3521. @deffn Command mac
  3522. @emph{No description provided.}
  3523. @end deffn
  3524. @deffn Command meminfo
  3525. Display available RAM memory on OpenOCD host.
  3526. Used in OpenOCD regression testing scripts.
  3527. @end deffn
  3528. @deffn Command peek
  3529. @emph{No description provided.}
  3530. @end deffn
  3531. @deffn Command poke
  3532. @emph{No description provided.}
  3533. @end deffn
  3534. @deffn Command rm filename
  3535. @c "rm" has both normal and Jim-level versions??
  3536. Unlinks the file @file{filename}.
  3537. @end deffn
  3538. @deffn Command trunc filename
  3539. Removes all data in the file @file{filename}.
  3540. @end deffn
  3541. @anchor{Memory access}
  3542. @section Memory access commands
  3543. @cindex memory access
  3544. These commands allow accesses of a specific size to the memory
  3545. system. Often these are used to configure the current target in some
  3546. special way. For example - one may need to write certain values to the
  3547. SDRAM controller to enable SDRAM.
  3548. @enumerate
  3549. @item Use the @command{targets} (plural) command
  3550. to change the current target.
  3551. @item In system level scripts these commands are deprecated.
  3552. Please use their TARGET object siblings to avoid making assumptions
  3553. about what TAP is the current target, or about MMU configuration.
  3554. @end enumerate
  3555. @deffn Command mdw addr [count]
  3556. @deffnx Command mdh addr [count]
  3557. @deffnx Command mdb addr [count]
  3558. Display contents of address @var{addr}, as
  3559. 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
  3560. or 8-bit bytes (@command{mdb}).
  3561. If @var{count} is specified, displays that many units.
  3562. (If you want to manipulate the data instead of displaying it,
  3563. see the @code{mem2array} primitives.)
  3564. @end deffn
  3565. @deffn Command mww addr word
  3566. @deffnx Command mwh addr halfword
  3567. @deffnx Command mwb addr byte
  3568. Writes the specified @var{word} (32 bits),
  3569. @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
  3570. at the specified address @var{addr}.
  3571. @end deffn
  3572. @anchor{Image access}
  3573. @section Image loading commands
  3574. @cindex image loading
  3575. @cindex image dumping
  3576. @anchor{dump_image}
  3577. @deffn Command {dump_image} filename address size
  3578. Dump @var{size} bytes of target memory starting at @var{address} to the
  3579. binary file named @var{filename}.
  3580. @end deffn
  3581. @deffn Command {fast_load}
  3582. Loads an image stored in memory by @command{fast_load_image} to the
  3583. current target. Must be preceeded by fast_load_image.
  3584. @end deffn
  3585. @deffn Command {fast_load_image} filename address [@option{bin}|@option{ihex}|@option{elf}]
  3586. Normally you should be using @command{load_image} or GDB load. However, for
  3587. testing purposes or when I/O overhead is significant(OpenOCD running on an embedded
  3588. host), storing the image in memory and uploading the image to the target
  3589. can be a way to upload e.g. multiple debug sessions when the binary does not change.
  3590. Arguments are the same as @command{load_image}, but the image is stored in OpenOCD host
  3591. memory, i.e. does not affect target. This approach is also useful when profiling
  3592. target programming performance as I/O and target programming can easily be profiled
  3593. separately.
  3594. @end deffn
  3595. @anchor{load_image}
  3596. @deffn Command {load_image} filename address [@option{bin}|@option{ihex}|@option{elf}]
  3597. Load image from file @var{filename} to target memory at @var{address}.
  3598. The file format may optionally be specified
  3599. (@option{bin}, @option{ihex}, or @option{elf})
  3600. @end deffn
  3601. @deffn Command {test_image} filename [address [@option{bin}|@option{ihex}|@option{elf}]]
  3602. Displays image section sizes and addresses
  3603. as if @var{filename} were loaded into target memory
  3604. starting at @var{address} (defaults to zero).
  3605. The file format may optionally be specified
  3606. (@option{bin}, @option{ihex}, or @option{elf})
  3607. @end deffn
  3608. @deffn Command {verify_image} filename address [@option{bin}|@option{ihex}|@option{elf}]
  3609. Verify @var{filename} against target memory starting at @var{address}.
  3610. The file format may optionally be specified
  3611. (@option{bin}, @option{ihex}, or @option{elf})
  3612. This will first attempt a comparison using a CRC checksum, if this fails it will try a binary compare.
  3613. @end deffn
  3614. @section Breakpoint and Watchpoint commands
  3615. @cindex breakpoint
  3616. @cindex watchpoint
  3617. CPUs often make debug modules accessible through JTAG, with
  3618. hardware support for a handful of code breakpoints and data
  3619. watchpoints.
  3620. In addition, CPUs almost always support software breakpoints.
  3621. @deffn Command {bp} [address len [@option{hw}]]
  3622. With no parameters, lists all active breakpoints.
  3623. Else sets a breakpoint on code execution starting
  3624. at @var{address} for @var{length} bytes.
  3625. This is a software breakpoint, unless @option{hw} is specified
  3626. in which case it will be a hardware breakpoint.
  3627. (@xref{arm9tdmi vector_catch}, or @pxref{xscale vector_catch},
  3628. for similar mechanisms that do not consume hardware breakpoints.)
  3629. @end deffn
  3630. @deffn Command {rbp} address
  3631. Remove the breakpoint at @var{address}.
  3632. @end deffn
  3633. @deffn Command {rwp} address
  3634. Remove data watchpoint on @var{address}
  3635. @end deffn
  3636. @deffn Command {wp} [address len [(@option{r}|@option{w}|@option{a}) [value [mask]]]]
  3637. With no parameters, lists all active watchpoints.
  3638. Else sets a data watchpoint on data from @var{address} for @var{length} bytes.
  3639. The watch point is an "access" watchpoint unless
  3640. the @option{r} or @option{w} parameter is provided,
  3641. defining it as respectively a read or write watchpoint.
  3642. If a @var{value} is provided, that value is used when determining if
  3643. the watchpoint should trigger. The value may be first be masked
  3644. using @var{mask} to mark ``don't care'' fields.
  3645. @end deffn
  3646. @section Misc Commands
  3647. @cindex profiling
  3648. @deffn Command {profile} seconds filename
  3649. Profiling samples the CPU's program counter as quickly as possible,
  3650. which is useful for non-intrusive stochastic profiling.
  3651. Saves up to 10000 sampines in @file{filename} using ``gmon.out'' format.
  3652. @end deffn
  3653. @deffn Command {version}
  3654. Displays a string identifying the version of this OpenOCD server.
  3655. @end deffn
  3656. @deffn Command {virt2phys} virtual_address
  3657. Requests the current target to map the specified @var{virtual_address}
  3658. to its corresponding physical address, and displays the result.
  3659. @end deffn
  3660. @node Architecture and Core Commands
  3661. @chapter Architecture and Core Commands
  3662. @cindex Architecture Specific Commands
  3663. @cindex Core Specific Commands
  3664. Most CPUs have specialized JTAG operations to support debugging.
  3665. OpenOCD packages most such operations in its standard command framework.
  3666. Some of those operations don't fit well in that framework, so they are
  3667. exposed here as architecture or implementation (core) specific commands.
  3668. @anchor{ARM Hardware Tracing}
  3669. @section ARM Hardware Tracing
  3670. @cindex tracing
  3671. @cindex ETM
  3672. @cindex ETB
  3673. CPUs based on ARM cores may include standard tracing interfaces,
  3674. based on an ``Embedded Trace Module'' (ETM) which sends voluminous
  3675. address and data bus trace records to a ``Trace Port''.
  3676. @itemize
  3677. @item
  3678. Development-oriented boards will sometimes provide a high speed
  3679. trace connector for collecting that data, when the particular CPU
  3680. supports such an interface.
  3681. (The standard connector is a 38-pin Mictor, with both JTAG
  3682. and trace port support.)
  3683. Those trace connectors are supported by higher end JTAG adapters
  3684. and some logic analyzer modules; frequently those modules can
  3685. buffer several megabytes of trace data.
  3686. Configuring an ETM coupled to such an external trace port belongs
  3687. in the board-specific configuration file.
  3688. @item
  3689. If the CPU doesn't provide an external interface, it probably
  3690. has an ``Embedded Trace Buffer'' (ETB) on the chip, which is a
  3691. dedicated SRAM. 4KBytes is one common ETB size.
  3692. Configuring an ETM coupled only to an ETB belongs in the CPU-specific
  3693. (target) configuration file, since it works the same on all boards.
  3694. @end itemize
  3695. ETM support in OpenOCD doesn't seem to be widely used yet.
  3696. @quotation Issues
  3697. ETM support may be buggy, and at least some @command{etm config}
  3698. parameters should be detected by asking the ETM for them.
  3699. It seems like a GDB hookup should be possible,
  3700. as well as triggering trace on specific events
  3701. (perhaps @emph{handling IRQ 23} or @emph{calls foo()}).
  3702. There should be GUI tools to manipulate saved trace data and help
  3703. analyse it in conjunction with the source code.
  3704. It's unclear how much of a common interface is shared
  3705. with the current XScale trace support, or should be
  3706. shared with eventual Nexus-style trace module support.
  3707. @end quotation
  3708. @subsection ETM Configuration
  3709. ETM setup is coupled with the trace port driver configuration.
  3710. @deffn {Config Command} {etm config} target width mode clocking driver
  3711. Declares the ETM associated with @var{target}, and associates it
  3712. with a given trace port @var{driver}. @xref{Trace Port Drivers}.
  3713. Several of the parameters must reflect the trace port configuration.
  3714. The @var{width} must be either 4, 8, or 16.
  3715. The @var{mode} must be @option{normal}, @option{multiplexted},
  3716. or @option{demultiplexted}.
  3717. The @var{clocking} must be @option{half} or @option{full}.
  3718. @quotation Note
  3719. You can see the ETM registers using the @command{reg} command, although
  3720. not all of those possible registers are present in every ETM.
  3721. @end quotation
  3722. @end deffn
  3723. @deffn Command {etm info}
  3724. Displays information about the current target's ETM.
  3725. @end deffn
  3726. @deffn Command {etm status}
  3727. Displays status of the current target's ETM:
  3728. is the ETM idle, or is it collecting data?
  3729. Did trace data overflow?
  3730. Was it triggered?
  3731. @end deffn
  3732. @deffn Command {etm tracemode} [type context_id_bits cycle_accurate branch_output]
  3733. Displays what data that ETM will collect.
  3734. If arguments are provided, first configures that data.
  3735. When the configuration changes, tracing is stopped
  3736. and any buffered trace data is invalidated.
  3737. @itemize
  3738. @item @var{type} ... one of
  3739. @option{none} (save nothing),
  3740. @option{data} (save data),
  3741. @option{address} (save addresses),
  3742. @option{all} (save data and addresses)
  3743. @item @var{context_id_bits} ... 0, 8, 16, or 32
  3744. @item @var{cycle_accurate} ... @option{enable} or @option{disable}
  3745. @item @var{branch_output} ... @option{enable} or @option{disable}
  3746. @end itemize
  3747. @end deffn
  3748. @deffn Command {etm trigger_percent} percent
  3749. @emph{Buggy and effectively a NOP ... @var{percent} from 2..100}
  3750. @end deffn
  3751. @subsection ETM Trace Operation
  3752. After setting up the ETM, you can use it to collect data.
  3753. That data can be exported to files for later analysis.
  3754. It can also be parsed with OpenOCD, for basic sanity checking.
  3755. @deffn Command {etm analyze}
  3756. Reads trace data into memory, if it wasn't already present.
  3757. Decodes and prints the data that was collected.
  3758. @end deffn
  3759. @deffn Command {etm dump} filename
  3760. Stores the captured trace data in @file{filename}.
  3761. @end deffn
  3762. @deffn Command {etm image} filename [base_address] [type]
  3763. Opens an image file.
  3764. @end deffn
  3765. @deffn Command {etm load} filename
  3766. Loads captured trace data from @file{filename}.
  3767. @end deffn
  3768. @deffn Command {etm start}
  3769. Starts trace data collection.
  3770. @end deffn
  3771. @deffn Command {etm stop}
  3772. Stops trace data collection.
  3773. @end deffn
  3774. @anchor{Trace Port Drivers}
  3775. @subsection Trace Port Drivers
  3776. To use an ETM trace port it must be associated with a driver.
  3777. @deffn {Trace Port Driver} dummy
  3778. Use the @option{dummy} driver if you are configuring an ETM that's
  3779. not connected to anything (on-chip ETB or off-chip trace connector).
  3780. @emph{This driver lets OpenOCD talk to the ETM, but it does not expose
  3781. any trace data collection.}
  3782. @deffn {Config Command} {etm_dummy config} target
  3783. Associates the ETM for @var{target} with a dummy driver.
  3784. @end deffn
  3785. @end deffn
  3786. @deffn {Trace Port Driver} etb
  3787. Use the @option{etb} driver if you are configuring an ETM
  3788. to use on-chip ETB memory.
  3789. @deffn {Config Command} {etb config} target etb_tap
  3790. Associates the ETM for @var{target} with the ETB at @var{etb_tap}.
  3791. You can see the ETB registers using the @command{reg} command.
  3792. @end deffn
  3793. @end deffn
  3794. @deffn {Trace Port Driver} oocd_trace
  3795. This driver isn't available unless OpenOCD was explicitly configured
  3796. with the @option{--enable-oocd_trace} option. You probably don't want
  3797. to configure it unless you've built the appropriate prototype hardware;
  3798. it's @emph{proof-of-concept} software.
  3799. Use the @option{oocd_trace} driver if you are configuring an ETM that's
  3800. connected to an off-chip trace connector.
  3801. @deffn {Config Command} {oocd_trace config} target tty
  3802. Associates the ETM for @var{target} with a trace driver which
  3803. collects data through the serial port @var{tty}.
  3804. @end deffn
  3805. @deffn Command {oocd_trace resync}
  3806. Re-synchronizes with the capture clock.
  3807. @end deffn
  3808. @deffn Command {oocd_trace status}
  3809. Reports whether the capture clock is locked or not.
  3810. @end deffn
  3811. @end deffn
  3812. @section ARMv4 and ARMv5 Architecture
  3813. @cindex ARMv4
  3814. @cindex ARMv5
  3815. These commands are specific to ARM architecture v4 and v5,
  3816. including all ARM7 or ARM9 systems and Intel XScale.
  3817. They are available in addition to other core-specific
  3818. commands that may be available.
  3819. @deffn Command {armv4_5 core_state} [@option{arm}|@option{thumb}]
  3820. Displays the core_state, optionally changing it to process
  3821. either @option{arm} or @option{thumb} instructions.
  3822. The target may later be resumed in the currently set core_state.
  3823. (Processors may also support the Jazelle state, but
  3824. that is not currently supported in OpenOCD.)
  3825. @end deffn
  3826. @deffn Command {armv4_5 disassemble} address count [thumb]
  3827. @cindex disassemble
  3828. Disassembles @var{count} instructions starting at @var{address}.
  3829. If @option{thumb} is specified, Thumb (16-bit) instructions are used;
  3830. else ARM (32-bit) instructions are used.
  3831. (Processors may also support the Jazelle state, but
  3832. those instructions are not currently understood by OpenOCD.)
  3833. @end deffn
  3834. @deffn Command {armv4_5 reg}
  3835. Display a table of all banked core registers, fetching the current value from every
  3836. core mode if necessary. OpenOCD versions before rev. 60 didn't fetch the current
  3837. register value.
  3838. @end deffn
  3839. @subsection ARM7 and ARM9 specific commands
  3840. @cindex ARM7
  3841. @cindex ARM9
  3842. These commands are specific to ARM7 and ARM9 cores, like ARM7TDMI, ARM720T,
  3843. ARM9TDMI, ARM920T or ARM926EJ-S.
  3844. They are available in addition to the ARMv4/5 commands,
  3845. and any other core-specific commands that may be available.
  3846. @deffn Command {arm7_9 dbgrq} (@option{enable}|@option{disable})
  3847. Control use of the EmbeddedIce DBGRQ signal to force entry into debug mode,
  3848. instead of breakpoints. This should be
  3849. safe for all but ARM7TDMI--S cores (like Philips LPC).
  3850. This feature is enabled by default on most ARM9 cores,
  3851. including ARM9TDMI, ARM920T, and ARM926EJ-S.
  3852. @end deffn
  3853. @deffn Command {arm7_9 dcc_downloads} (@option{enable}|@option{disable})
  3854. @cindex DCC
  3855. Control the use of the debug communications channel (DCC) to write larger (>128 byte)
  3856. amounts of memory. DCC downloads offer a huge speed increase, but might be
  3857. unsafe, especially with targets running at very low speeds. This command was introduced
  3858. with OpenOCD rev. 60, and requires a few bytes of working area.
  3859. @end deffn
  3860. @anchor{arm7_9 fast_memory_access}
  3861. @deffn Command {arm7_9 fast_memory_access} (@option{enable}|@option{disable})
  3862. Enable or disable memory writes and reads that don't check completion of
  3863. the operation. This provides a huge speed increase, especially with USB JTAG
  3864. cables (FT2232), but might be unsafe if used with targets running at very low
  3865. speeds, like the 32kHz startup clock of an AT91RM9200.
  3866. @end deffn
  3867. @deffn {Debug Command} {arm7_9 write_core_reg} num mode word
  3868. @emph{This is intended for use while debugging OpenOCD; you probably
  3869. shouldn't use it.}
  3870. Writes a 32-bit @var{word} to register @var{num} (from 0 to 16)
  3871. as used in the specified @var{mode}
  3872. (where e.g. mode 16 is "user" and mode 19 is "supervisor";
  3873. the M4..M0 bits of the PSR).
  3874. Registers 0..15 are the normal CPU registers such as r0(0), r1(1) ... pc(15).
  3875. Register 16 is the mode-specific SPSR,
  3876. unless the specified mode is 0xffffffff (32-bit all-ones)
  3877. in which case register 16 is the CPSR.
  3878. The write goes directly to the CPU, bypassing the register cache.
  3879. @end deffn
  3880. @deffn {Debug Command} {arm7_9 write_xpsr} word (@option{0}|@option{1})
  3881. @emph{This is intended for use while debugging OpenOCD; you probably
  3882. shouldn't use it.}
  3883. If the second parameter is zero, writes @var{word} to the
  3884. Current Program Status register (CPSR).
  3885. Else writes @var{word} to the current mode's Saved PSR (SPSR).
  3886. In both cases, this bypasses the register cache.
  3887. @end deffn
  3888. @deffn {Debug Command} {arm7_9 write_xpsr_im8} byte rotate (@option{0}|@option{1})
  3889. @emph{This is intended for use while debugging OpenOCD; you probably
  3890. shouldn't use it.}
  3891. Writes eight bits to the CPSR or SPSR,
  3892. first rotating them by @math{2*rotate} bits,
  3893. and bypassing the register cache.
  3894. This has lower JTAG overhead than writing the entire CPSR or SPSR
  3895. with @command{arm7_9 write_xpsr}.
  3896. @end deffn
  3897. @subsection ARM720T specific commands
  3898. @cindex ARM720T
  3899. These commands are available to ARM720T based CPUs,
  3900. which are implementations of the ARMv4T architecture
  3901. based on the ARM7TDMI-S integer core.
  3902. They are available in addition to the ARMv4/5 and ARM7/ARM9 commands.
  3903. @deffn Command {arm720t cp15} regnum [value]
  3904. Display cp15 register @var{regnum};
  3905. else if a @var{value} is provided, that value is written to that register.
  3906. @end deffn
  3907. @deffn Command {arm720t mdw_phys} addr [count]
  3908. @deffnx Command {arm720t mdh_phys} addr [count]
  3909. @deffnx Command {arm720t mdb_phys} addr [count]
  3910. Display contents of physical address @var{addr}, as
  3911. 32-bit words (@command{mdw_phys}), 16-bit halfwords (@command{mdh_phys}),
  3912. or 8-bit bytes (@command{mdb_phys}).
  3913. If @var{count} is specified, displays that many units.
  3914. @end deffn
  3915. @deffn Command {arm720t mww_phys} addr word
  3916. @deffnx Command {arm720t mwh_phys} addr halfword
  3917. @deffnx Command {arm720t mwb_phys} addr byte
  3918. Writes the specified @var{word} (32 bits),
  3919. @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
  3920. at the specified physical address @var{addr}.
  3921. @end deffn
  3922. @deffn Command {arm720t virt2phys} va
  3923. Translate a virtual address @var{va} to a physical address
  3924. and display the result.
  3925. @end deffn
  3926. @subsection ARM9TDMI specific commands
  3927. @cindex ARM9TDMI
  3928. Many ARM9-family CPUs are built around ARM9TDMI integer cores,
  3929. or processors resembling ARM9TDMI, and can use these commands.
  3930. Such cores include the ARM920T, ARM926EJ-S, and ARM966.
  3931. @c 9-june-2009: tried this on arm920t, it didn't work.
  3932. @c no-params always lists nothing caught, and that's how it acts.
  3933. @anchor{arm9tdmi vector_catch}
  3934. @deffn Command {arm9tdmi vector_catch} [@option{all}|@option{none}|list]
  3935. Vector Catch hardware provides a sort of dedicated breakpoint
  3936. for hardware events such as reset, interrupt, and abort.
  3937. You can use this to conserve normal breakpoint resources,
  3938. so long as you're not concerned with code that branches directly
  3939. to those hardware vectors.
  3940. This always finishes by listing the current configuration.
  3941. If parameters are provided, it first reconfigures the
  3942. vector catch hardware to intercept
  3943. @option{all} of the hardware vectors,
  3944. @option{none} of them,
  3945. or a list with one or more of the following:
  3946. @option{reset} @option{undef} @option{swi} @option{pabt} @option{dabt} @option{reserved}
  3947. @option{irq} @option{fiq}.
  3948. @end deffn
  3949. @subsection ARM920T specific commands
  3950. @cindex ARM920T
  3951. These commands are available to ARM920T based CPUs,
  3952. which are implementations of the ARMv4T architecture
  3953. built using the ARM9TDMI integer core.
  3954. They are available in addition to the ARMv4/5, ARM7/ARM9,
  3955. and ARM9TDMI commands.
  3956. @deffn Command {arm920t cache_info}
  3957. Print information about the caches found. This allows to see whether your target
  3958. is an ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
  3959. @end deffn
  3960. @deffn Command {arm920t cp15} regnum [value]
  3961. Display cp15 register @var{regnum};
  3962. else if a @var{value} is provided, that value is written to that register.
  3963. @end deffn
  3964. @deffn Command {arm920t cp15i} opcode [value [address]]
  3965. Interpreted access using cp15 @var{opcode}.
  3966. If no @var{value} is provided, the result is displayed.
  3967. Else if that value is written using the specified @var{address},
  3968. or using zero if no other address is not provided.
  3969. @end deffn
  3970. @deffn Command {arm920t mdw_phys} addr [count]
  3971. @deffnx Command {arm920t mdh_phys} addr [count]
  3972. @deffnx Command {arm920t mdb_phys} addr [count]
  3973. Display contents of physical address @var{addr}, as
  3974. 32-bit words (@command{mdw_phys}), 16-bit halfwords (@command{mdh_phys}),
  3975. or 8-bit bytes (@command{mdb_phys}).
  3976. If @var{count} is specified, displays that many units.
  3977. @end deffn
  3978. @deffn Command {arm920t mww_phys} addr word
  3979. @deffnx Command {arm920t mwh_phys} addr halfword
  3980. @deffnx Command {arm920t mwb_phys} addr byte
  3981. Writes the specified @var{word} (32 bits),
  3982. @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
  3983. at the specified physical address @var{addr}.
  3984. @end deffn
  3985. @deffn Command {arm920t read_cache} filename
  3986. Dump the content of ICache and DCache to a file named @file{filename}.
  3987. @end deffn
  3988. @deffn Command {arm920t read_mmu} filename
  3989. Dump the content of the ITLB and DTLB to a file named @file{filename}.
  3990. @end deffn
  3991. @deffn Command {arm920t virt2phys} va
  3992. Translate a virtual address @var{va} to a physical address
  3993. and display the result.
  3994. @end deffn
  3995. @subsection ARM926ej-s specific commands
  3996. @cindex ARM926ej-s
  3997. These commands are available to ARM926ej-s based CPUs,
  3998. which are implementations of the ARMv5TEJ architecture
  3999. based on the ARM9EJ-S integer core.
  4000. They are available in addition to the ARMv4/5, ARM7/ARM9,
  4001. and ARM9TDMI commands.
  4002. The Feroceon cores also support these commands, although
  4003. they are not built from ARM926ej-s designs.
  4004. @deffn Command {arm926ejs cache_info}
  4005. Print information about the caches found.
  4006. @end deffn
  4007. @deffn Command {arm926ejs cp15} opcode1 opcode2 CRn CRm regnum [value]
  4008. Accesses cp15 register @var{regnum} using
  4009. @var{opcode1}, @var{opcode2}, @var{CRn}, and @var{CRm}.
  4010. If a @var{value} is provided, that value is written to that register.
  4011. Else that register is read and displayed.
  4012. @end deffn
  4013. @deffn Command {arm926ejs mdw_phys} addr [count]
  4014. @deffnx Command {arm926ejs mdh_phys} addr [count]
  4015. @deffnx Command {arm926ejs mdb_phys} addr [count]
  4016. Display contents of physical address @var{addr}, as
  4017. 32-bit words (@command{mdw_phys}), 16-bit halfwords (@command{mdh_phys}),
  4018. or 8-bit bytes (@command{mdb_phys}).
  4019. If @var{count} is specified, displays that many units.
  4020. @end deffn
  4021. @deffn Command {arm926ejs mww_phys} addr word
  4022. @deffnx Command {arm926ejs mwh_phys} addr halfword
  4023. @deffnx Command {arm926ejs mwb_phys} addr byte
  4024. Writes the specified @var{word} (32 bits),
  4025. @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
  4026. at the specified physical address @var{addr}.
  4027. @end deffn
  4028. @deffn Command {arm926ejs virt2phys} va
  4029. Translate a virtual address @var{va} to a physical address
  4030. and display the result.
  4031. @end deffn
  4032. @subsection ARM966E specific commands
  4033. @cindex ARM966E
  4034. These commands are available to ARM966 based CPUs,
  4035. which are implementations of the ARMv5TE architecture.
  4036. They are available in addition to the ARMv4/5, ARM7/ARM9,
  4037. and ARM9TDMI commands.
  4038. @deffn Command {arm966e cp15} regnum [value]
  4039. Display cp15 register @var{regnum};
  4040. else if a @var{value} is provided, that value is written to that register.
  4041. @end deffn
  4042. @subsection XScale specific commands
  4043. @cindex XScale
  4044. These commands are available to XScale based CPUs,
  4045. which are implementations of the ARMv5TE architecture.
  4046. @deffn Command {xscale analyze_trace}
  4047. Displays the contents of the trace buffer.
  4048. @end deffn
  4049. @deffn Command {xscale cache_clean_address} address
  4050. Changes the address used when cleaning the data cache.
  4051. @end deffn
  4052. @deffn Command {xscale cache_info}
  4053. Displays information about the CPU caches.
  4054. @end deffn
  4055. @deffn Command {xscale cp15} regnum [value]
  4056. Display cp15 register @var{regnum};
  4057. else if a @var{value} is provided, that value is written to that register.
  4058. @end deffn
  4059. @deffn Command {xscale debug_handler} target address
  4060. Changes the address used for the specified target's debug handler.
  4061. @end deffn
  4062. @deffn Command {xscale dcache} (@option{enable}|@option{disable})
  4063. Enables or disable the CPU's data cache.
  4064. @end deffn
  4065. @deffn Command {xscale dump_trace} filename
  4066. Dumps the raw contents of the trace buffer to @file{filename}.
  4067. @end deffn
  4068. @deffn Command {xscale icache} (@option{enable}|@option{disable})
  4069. Enables or disable the CPU's instruction cache.
  4070. @end deffn
  4071. @deffn Command {xscale mmu} (@option{enable}|@option{disable})
  4072. Enables or disable the CPU's memory management unit.
  4073. @end deffn
  4074. @deffn Command {xscale trace_buffer} (@option{enable}|@option{disable}) [@option{fill} [n] | @option{wrap}]
  4075. Enables or disables the trace buffer,
  4076. and controls how it is emptied.
  4077. @end deffn
  4078. @deffn Command {xscale trace_image} filename [offset [type]]
  4079. Opens a trace image from @file{filename}, optionally rebasing
  4080. its segment addresses by @var{offset}.
  4081. The image @var{type} may be one of
  4082. @option{bin} (binary), @option{ihex} (Intel hex),
  4083. @option{elf} (ELF file), @option{s19} (Motorola s19),
  4084. @option{mem}, or @option{builder}.
  4085. @end deffn
  4086. @anchor{xscale vector_catch}
  4087. @deffn Command {xscale vector_catch} [mask]
  4088. Display a bitmask showing the hardware vectors to catch.
  4089. If the optional parameter is provided, first set the bitmask to that value.
  4090. @end deffn
  4091. @section ARMv6 Architecture
  4092. @cindex ARMv6
  4093. @subsection ARM11 specific commands
  4094. @cindex ARM11
  4095. @deffn Command {arm11 mcr} p1 p2 p3 p4 p5
  4096. Read coprocessor register
  4097. @end deffn
  4098. @deffn Command {arm11 memwrite burst} [value]
  4099. Displays the value of the memwrite burst-enable flag,
  4100. which is enabled by default.
  4101. If @var{value} is defined, first assigns that.
  4102. @end deffn
  4103. @deffn Command {arm11 memwrite error_fatal} [value]
  4104. Displays the value of the memwrite error_fatal flag,
  4105. which is enabled by default.
  4106. If @var{value} is defined, first assigns that.
  4107. @end deffn
  4108. @deffn Command {arm11 mrc} p1 p2 p3 p4 p5 value
  4109. Write coprocessor register
  4110. @end deffn
  4111. @deffn Command {arm11 no_increment} [value]
  4112. Displays the value of the flag controlling whether
  4113. some read or write operations increment the pointer
  4114. (the default behavior) or not (acting like a FIFO).
  4115. If @var{value} is defined, first assigns that.
  4116. @end deffn
  4117. @deffn Command {arm11 step_irq_enable} [value]
  4118. Displays the value of the flag controlling whether
  4119. IRQs are enabled during single stepping;
  4120. they is disabled by default.
  4121. If @var{value} is defined, first assigns that.
  4122. @end deffn
  4123. @section ARMv7 Architecture
  4124. @cindex ARMv7
  4125. @subsection ARMv7 Debug Access Port (DAP) specific commands
  4126. @cindex Debug Access Port
  4127. @cindex DAP
  4128. These commands are specific to ARM architecture v7 Debug Access Port (DAP),
  4129. included on cortex-m3 and cortex-a8 systems.
  4130. They are available in addition to other core-specific commands that may be available.
  4131. @deffn Command {dap info} [num]
  4132. Displays dap info for ap @var{num}, defaulting to the currently selected AP.
  4133. @end deffn
  4134. @deffn Command {dap apsel} [num]
  4135. Select AP @var{num}, defaulting to 0.
  4136. @end deffn
  4137. @deffn Command {dap apid} [num]
  4138. Displays id register from AP @var{num},
  4139. defaulting to the currently selected AP.
  4140. @end deffn
  4141. @deffn Command {dap baseaddr} [num]
  4142. Displays debug base address from AP @var{num},
  4143. defaulting to the currently selected AP.
  4144. @end deffn
  4145. @deffn Command {dap memaccess} [value]
  4146. Displays the number of extra tck for mem-ap memory bus access [0-255].
  4147. If @var{value} is defined, first assigns that.
  4148. @end deffn
  4149. @subsection Cortex-M3 specific commands
  4150. @cindex Cortex-M3
  4151. @deffn Command {cortex_m3 maskisr} (@option{on}|@option{off})
  4152. Control masking (disabling) interrupts during target step/resume.
  4153. @end deffn
  4154. @anchor{Software Debug Messages and Tracing}
  4155. @section Software Debug Messages and Tracing
  4156. @cindex Linux-ARM DCC support
  4157. @cindex tracing
  4158. @cindex libdcc
  4159. @cindex DCC
  4160. OpenOCD can process certain requests from target software. Currently
  4161. @command{target_request debugmsgs}
  4162. is supported only for @option{arm7_9} and @option{cortex_m3} cores.
  4163. These messages are received as part of target polling, so
  4164. you need to have @command{poll on} active to receive them.
  4165. They are intrusive in that they will affect program execution
  4166. times. If that is a problem, @pxref{ARM Hardware Tracing}.
  4167. See @file{libdcc} in the contrib dir for more details.
  4168. In addition to sending strings, characters, and
  4169. arrays of various size integers from the target,
  4170. @file{libdcc} also exports a software trace point mechanism.
  4171. The target being debugged may
  4172. issue trace messages which include a 24-bit @dfn{trace point} number.
  4173. Trace point support includes two distinct mechanisms,
  4174. each supported by a command:
  4175. @itemize
  4176. @item @emph{History} ... A circular buffer of trace points
  4177. can be set up, and then displayed at any time.
  4178. This tracks where code has been, which can be invaluable in
  4179. finding out how some fault was triggered.
  4180. The buffer may overflow, since it collects records continuously.
  4181. It may be useful to use some of the 24 bits to represent a
  4182. particular event, and other bits to hold data.
  4183. @item @emph{Counting} ... An array of counters can be set up,
  4184. and then displayed at any time.
  4185. This can help establish code coverage and identify hot spots.
  4186. The array of counters is directly indexed by the trace point
  4187. number, so trace points with higher numbers are not counted.
  4188. @end itemize
  4189. Linux-ARM kernels have a ``Kernel low-level debugging
  4190. via EmbeddedICE DCC channel'' option (CONFIG_DEBUG_ICEDCC,
  4191. depends on CONFIG_DEBUG_LL) which uses this mechanism to
  4192. deliver messages before a serial console can be activated.
  4193. This is not the same format used by @file{libdcc}.
  4194. Other software, such as the U-Boot boot loader, sometimes
  4195. does the same thing.
  4196. @deffn Command {target_request debugmsgs} [@option{enable}|@option{disable}|@option{charmsg}]
  4197. Displays current handling of target DCC message requests.
  4198. These messages may be sent to the debugger while the target is running.
  4199. The optional @option{enable} and @option{charmsg} parameters
  4200. both enable the messages, while @option{disable} disables them.
  4201. With @option{charmsg} the DCC words each contain one character,
  4202. as used by Linux with CONFIG_DEBUG_ICEDCC;
  4203. otherwise the libdcc format is used.
  4204. @end deffn
  4205. @deffn Command {trace history} (@option{clear}|count)
  4206. With no parameter, displays all the trace points that have triggered
  4207. in the order they triggered.
  4208. With the parameter @option{clear}, erases all current trace history records.
  4209. With a @var{count} parameter, allocates space for that many
  4210. history records.
  4211. @end deffn
  4212. @deffn Command {trace point} (@option{clear}|identifier)
  4213. With no parameter, displays all trace point identifiers and how many times
  4214. they have been triggered.
  4215. With the parameter @option{clear}, erases all current trace point counters.
  4216. With a numeric @var{identifier} parameter, creates a new a trace point counter
  4217. and associates it with that identifier.
  4218. @emph{Important:} The identifier and the trace point number
  4219. are not related except by this command.
  4220. These trace point numbers always start at zero (from server startup,
  4221. or after @command{trace point clear}) and count up from there.
  4222. @end deffn
  4223. @node JTAG Commands
  4224. @chapter JTAG Commands
  4225. @cindex JTAG Commands
  4226. Most general purpose JTAG commands have been presented earlier.
  4227. (@xref{JTAG Speed}, @ref{Reset Configuration}, and @ref{TAP Declaration}.)
  4228. Lower level JTAG commands, as presented here,
  4229. may be needed to work with targets which require special
  4230. attention during operations such as reset or initialization.
  4231. To use these commands you will need to understand some
  4232. of the basics of JTAG, including:
  4233. @itemize @bullet
  4234. @item A JTAG scan chain consists of a sequence of individual TAP
  4235. devices such as a CPUs.
  4236. @item Control operations involve moving each TAP through the same
  4237. standard state machine (in parallel)
  4238. using their shared TMS and clock signals.
  4239. @item Data transfer involves shifting data through the chain of
  4240. instruction or data registers of each TAP, writing new register values
  4241. while the reading previous ones.
  4242. @item Data register sizes are a function of the instruction active in
  4243. a given TAP, while instruction register sizes are fixed for each TAP.
  4244. All TAPs support a BYPASS instruction with a single bit data register.
  4245. @item The way OpenOCD differentiates between TAP devices is by
  4246. shifting different instructions into (and out of) their instruction
  4247. registers.
  4248. @end itemize
  4249. @section Low Level JTAG Commands
  4250. These commands are used by developers who need to access
  4251. JTAG instruction or data registers, possibly controlling
  4252. the order of TAP state transitions.
  4253. If you're not debugging OpenOCD internals, or bringing up a
  4254. new JTAG adapter or a new type of TAP device (like a CPU or
  4255. JTAG router), you probably won't need to use these commands.
  4256. @deffn Command {drscan} tap [numbits value]+ [@option{-endstate} tap_state]
  4257. Loads the data register of @var{tap} with a series of bit fields
  4258. that specify the entire register.
  4259. Each field is @var{numbits} bits long with
  4260. a numeric @var{value} (hexadecimal encouraged).
  4261. The return value holds the original value of each
  4262. of those fields.
  4263. For example, a 38 bit number might be specified as one
  4264. field of 32 bits then one of 6 bits.
  4265. @emph{For portability, never pass fields which are more
  4266. than 32 bits long. Many OpenOCD implementations do not
  4267. support 64-bit (or larger) integer values.}
  4268. All TAPs other than @var{tap} must be in BYPASS mode.
  4269. The single bit in their data registers does not matter.
  4270. When @var{tap_state} is specified, the JTAG state machine is left
  4271. in that state.
  4272. For example @sc{drpause} might be specified, so that more
  4273. instructions can be issued before re-entering the @sc{run/idle} state.
  4274. If the end state is not specified, the @sc{run/idle} state is entered.
  4275. @quotation Warning
  4276. OpenOCD does not record information about data register lengths,
  4277. so @emph{it is important that you get the bit field lengths right}.
  4278. Remember that different JTAG instructions refer to different
  4279. data registers, which may have different lengths.
  4280. Moreover, those lengths may not be fixed;
  4281. the SCAN_N instruction can change the length of
  4282. the register accessed by the INTEST instruction
  4283. (by connecting a different scan chain).
  4284. @end quotation
  4285. @end deffn
  4286. @deffn Command {flush_count}
  4287. Returns the number of times the JTAG queue has been flushed.
  4288. This may be used for performance tuning.
  4289. For example, flushing a queue over USB involves a
  4290. minimum latency, often several milliseconds, which does
  4291. not change with the amount of data which is written.
  4292. You may be able to identify performance problems by finding
  4293. tasks which waste bandwidth by flushing small transfers too often,
  4294. instead of batching them into larger operations.
  4295. @end deffn
  4296. @deffn Command {irscan} [tap instruction]+ [@option{-endstate} tap_state]
  4297. For each @var{tap} listed, loads the instruction register
  4298. with its associated numeric @var{instruction}.
  4299. (The number of bits in that instruction may be displayed
  4300. using the @command{scan_chain} command.)
  4301. For other TAPs, a BYPASS instruction is loaded.
  4302. When @var{tap_state} is specified, the JTAG state machine is left
  4303. in that state.
  4304. For example @sc{irpause} might be specified, so the data register
  4305. can be loaded before re-entering the @sc{run/idle} state.
  4306. If the end state is not specified, the @sc{run/idle} state is entered.
  4307. @quotation Note
  4308. OpenOCD currently supports only a single field for instruction
  4309. register values, unlike data register values.
  4310. For TAPs where the instruction register length is more than 32 bits,
  4311. portable scripts currently must issue only BYPASS instructions.
  4312. @end quotation
  4313. @end deffn
  4314. @deffn Command {jtag_reset} trst srst
  4315. Set values of reset signals.
  4316. The @var{trst} and @var{srst} parameter values may be
  4317. @option{0}, indicating that reset is inactive (pulled or driven high),
  4318. or @option{1}, indicating it is active (pulled or driven low).
  4319. The @command{reset_config} command should already have been used
  4320. to configure how the board and JTAG adapter treat these two
  4321. signals, and to say if either signal is even present.
  4322. @xref{Reset Configuration}.
  4323. @end deffn
  4324. @deffn Command {runtest} @var{num_cycles}
  4325. Move to the @sc{run/idle} state, and execute at least
  4326. @var{num_cycles} of the JTAG clock (TCK).
  4327. Instructions often need some time
  4328. to execute before they take effect.
  4329. @end deffn
  4330. @c tms_sequence (short|long)
  4331. @c ... temporary, debug-only, probably gone before 0.2 ships
  4332. @deffn Command {verify_ircapture} (@option{enable}|@option{disable})
  4333. Verify values captured during @sc{ircapture} and returned
  4334. during IR scans. Default is enabled, but this can be
  4335. overridden by @command{verify_jtag}.
  4336. @end deffn
  4337. @deffn Command {verify_jtag} (@option{enable}|@option{disable})
  4338. Enables verification of DR and IR scans, to help detect
  4339. programming errors. For IR scans, @command{verify_ircapture}
  4340. must also be enabled.
  4341. Default is enabled.
  4342. @end deffn
  4343. @section TAP state names
  4344. @cindex TAP state names
  4345. The @var{tap_state} names used by OpenOCD in the @command{drscan},
  4346. and @command{irscan} commands are:
  4347. @itemize @bullet
  4348. @item @b{RESET} ... should act as if TRST were active
  4349. @item @b{RUN/IDLE} ... don't assume this always means IDLE
  4350. @item @b{DRSELECT}
  4351. @item @b{DRCAPTURE}
  4352. @item @b{DRSHIFT} ... TDI/TDO shifting through the data register
  4353. @item @b{DREXIT1}
  4354. @item @b{DRPAUSE} ... data register ready for update or more shifting
  4355. @item @b{DREXIT2}
  4356. @item @b{DRUPDATE}
  4357. @item @b{IRSELECT}
  4358. @item @b{IRCAPTURE}
  4359. @item @b{IRSHIFT} ... TDI/TDO shifting through the instruction register
  4360. @item @b{IREXIT1}
  4361. @item @b{IRPAUSE} ... instruction register ready for update or more shifting
  4362. @item @b{IREXIT2}
  4363. @item @b{IRUPDATE}
  4364. @end itemize
  4365. Note that only six of those states are fully ``stable'' in the
  4366. face of TMS fixed (low except for @sc{reset})
  4367. and a free-running JTAG clock. For all the
  4368. others, the next TCK transition changes to a new state.
  4369. @itemize @bullet
  4370. @item From @sc{drshift} and @sc{irshift}, clock transitions will
  4371. produce side effects by changing register contents. The values
  4372. to be latched in upcoming @sc{drupdate} or @sc{irupdate} states
  4373. may not be as expected.
  4374. @item @sc{run/idle}, @sc{drpause}, and @sc{irpause} are reasonable
  4375. choices after @command{drscan} or @command{irscan} commands,
  4376. since they are free of JTAG side effects.
  4377. However, @sc{run/idle} may have side effects that appear at other
  4378. levels, such as advancing the ARM9E-S instruction pipeline.
  4379. Consult the documentation for the TAP(s) you are working with.
  4380. @end itemize
  4381. @node Boundary Scan Commands
  4382. @chapter Boundary Scan Commands
  4383. One of the original purposes of JTAG was to support
  4384. boundary scan based hardware testing.
  4385. Although its primary focus is to support On-Chip Debugging,
  4386. OpenOCD also includes some boundary scan commands.
  4387. @section SVF: Serial Vector Format
  4388. @cindex Serial Vector Format
  4389. @cindex SVF
  4390. The Serial Vector Format, better known as @dfn{SVF}, is a
  4391. way to represent JTAG test patterns in text files.
  4392. OpenOCD supports running such test files.
  4393. @deffn Command {svf} filename [@option{quiet}]
  4394. This issues a JTAG reset (Test-Logic-Reset) and then
  4395. runs the SVF script from @file{filename}.
  4396. Unless the @option{quiet} option is specified,
  4397. each command is logged before it is executed.
  4398. @end deffn
  4399. @section XSVF: Xilinx Serial Vector Format
  4400. @cindex Xilinx Serial Vector Format
  4401. @cindex XSVF
  4402. The Xilinx Serial Vector Format, better known as @dfn{XSVF}, is a
  4403. binary representation of SVF which is optimized for use with
  4404. Xilinx devices.
  4405. OpenOCD supports running such test files.
  4406. @quotation Important
  4407. Not all XSVF commands are supported.
  4408. @end quotation
  4409. @deffn Command {xsvf} (tapname|@option{plain}) filename [@option{virt2}] [@option{quiet}]
  4410. This issues a JTAG reset (Test-Logic-Reset) and then
  4411. runs the XSVF script from @file{filename}.
  4412. When a @var{tapname} is specified, the commands are directed at
  4413. that TAP.
  4414. When @option{virt2} is specified, the @sc{xruntest} command counts
  4415. are interpreted as TCK cycles instead of microseconds.
  4416. Unless the @option{quiet} option is specified,
  4417. messages are logged for comments and some retries.
  4418. @end deffn
  4419. @node TFTP
  4420. @chapter TFTP
  4421. @cindex TFTP
  4422. If OpenOCD runs on an embedded host(as ZY1000 does), then TFTP can
  4423. be used to access files on PCs (either the developer's PC or some other PC).
  4424. The way this works on the ZY1000 is to prefix a filename by
  4425. "/tftp/ip/" and append the TFTP path on the TFTP
  4426. server (tftpd). For example,
  4427. @example
  4428. load_image /tftp/\temp\abc.elf
  4429. @end example
  4430. will load c:\temp\abc.elf from the developer pc ( into memory as
  4431. if the file was hosted on the embedded host.
  4432. In order to achieve decent performance, you must choose a TFTP server
  4433. that supports a packet size bigger than the default packet size (512 bytes). There
  4434. are numerous TFTP servers out there (free and commercial) and you will have to do
  4435. a bit of googling to find something that fits your requirements.
  4436. @node GDB and OpenOCD
  4437. @chapter GDB and OpenOCD
  4438. @cindex GDB
  4439. OpenOCD complies with the remote gdbserver protocol, and as such can be used
  4440. to debug remote targets.
  4441. @anchor{Connecting to GDB}
  4442. @section Connecting to GDB
  4443. @cindex Connecting to GDB
  4444. Use GDB 6.7 or newer with OpenOCD if you run into trouble. For
  4445. instance GDB 6.3 has a known bug that produces bogus memory access
  4446. errors, which has since been fixed: look up 1836 in
  4447. @url{}
  4448. OpenOCD can communicate with GDB in two ways:
  4449. @enumerate
  4450. @item
  4451. A socket (TCP/IP) connection is typically started as follows:
  4452. @example
  4453. target remote localhost:3333
  4454. @end example
  4455. This would cause GDB to connect to the gdbserver on the local pc using port 3333.
  4456. @item
  4457. A pipe connection is typically started as follows:
  4458. @example
  4459. target remote | openocd --pipe
  4460. @end example
  4461. This would cause GDB to run OpenOCD and communicate using pipes (stdin/stdout).
  4462. Using this method has the advantage of GDB starting/stopping OpenOCD for the debug
  4463. session.
  4464. @end enumerate
  4465. To list the available OpenOCD commands type @command{monitor help} on the
  4466. GDB command line.
  4467. OpenOCD supports the gdb @option{qSupported} packet, this enables information
  4468. to be sent by the GDB remote server (i.e. OpenOCD) to GDB. Typical information includes
  4469. packet size and the device's memory map.
  4470. Previous versions of OpenOCD required the following GDB options to increase
  4471. the packet size and speed up GDB communication:
  4472. @example
  4473. set remote memory-write-packet-size 1024
  4474. set remote memory-write-packet-size fixed
  4475. set remote memory-read-packet-size 1024
  4476. set remote memory-read-packet-size fixed
  4477. @end example
  4478. This is now handled in the @option{qSupported} PacketSize and should not be required.
  4479. @section Programming using GDB
  4480. @cindex Programming using GDB
  4481. By default the target memory map is sent to GDB. This can be disabled by
  4482. the following OpenOCD configuration option:
  4483. @example
  4484. gdb_memory_map disable
  4485. @end example
  4486. For this to function correctly a valid flash configuration must also be set
  4487. in OpenOCD. For faster performance you should also configure a valid
  4488. working area.
  4489. Informing GDB of the memory map of the target will enable GDB to protect any
  4490. flash areas of the target and use hardware breakpoints by default. This means
  4491. that the OpenOCD option @command{gdb_breakpoint_override} is not required when
  4492. using a memory map. @xref{gdb_breakpoint_override}.
  4493. To view the configured memory map in GDB, use the GDB command @option{info mem}
  4494. All other unassigned addresses within GDB are treated as RAM.
  4495. GDB 6.8 and higher set any memory area not in the memory map as inaccessible.
  4496. This can be changed to the old behaviour by using the following GDB command
  4497. @example
  4498. set mem inaccessible-by-default off
  4499. @end example
  4500. If @command{gdb_flash_program enable} is also used, GDB will be able to
  4501. program any flash memory using the vFlash interface.
  4502. GDB will look at the target memory map when a load command is given, if any
  4503. areas to be programmed lie within the target flash area the vFlash packets
  4504. will be used.
  4505. If the target needs configuring before GDB programming, an event
  4506. script can be executed:
  4507. @example
  4508. $_TARGETNAME configure -event EVENTNAME BODY
  4509. @end example
  4510. To verify any flash programming the GDB command @option{compare-sections}
  4511. can be used.
  4512. @node Tcl Scripting API
  4513. @chapter Tcl Scripting API
  4514. @cindex Tcl Scripting API
  4515. @cindex Tcl scripts
  4516. @section API rules
  4517. The commands are stateless. E.g. the telnet command line has a concept
  4518. of currently active target, the Tcl API proc's take this sort of state
  4519. information as an argument to each proc.
  4520. There are three main types of return values: single value, name value
  4521. pair list and lists.
  4522. Name value pair. The proc 'foo' below returns a name/value pair
  4523. list.
  4524. @verbatim
  4525. > set foo(me) Duane
  4526. > set foo(you) Oyvind
  4527. > set foo(mouse) Micky
  4528. > set foo(duck) Donald
  4529. If one does this:
  4530. > set foo
  4531. The result is:
  4532. me Duane you Oyvind mouse Micky duck Donald
  4533. Thus, to get the names of the associative array is easy:
  4534. foreach { name value } [set foo] {
  4535. puts "Name: $name, Value: $value"
  4536. }
  4537. @end verbatim
  4538. Lists returned must be relatively small. Otherwise a range
  4539. should be passed in to the proc in question.
  4540. @section Internal low-level Commands
  4541. By low-level, the intent is a human would not directly use these commands.
  4542. Low-level commands are (should be) prefixed with "ocd_", e.g.
  4543. @command{ocd_flash_banks}
  4544. is the low level API upon which @command{flash banks} is implemented.
  4545. @itemize @bullet
  4546. @item @b{ocd_mem2array} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
  4547. Read memory and return as a Tcl array for script processing
  4548. @item @b{ocd_array2mem} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
  4549. Convert a Tcl array to memory locations and write the values
  4550. @item @b{ocd_flash_banks} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}> <@var{target}> [@option{driver options} ...]
  4551. Return information about the flash banks
  4552. @end itemize
  4553. OpenOCD commands can consist of two words, e.g. "flash banks". The
  4554. @file{startup.tcl} "unknown" proc will translate this into a Tcl proc
  4555. called "flash_banks".
  4556. @section OpenOCD specific Global Variables
  4557. @subsection HostOS
  4558. Real Tcl has ::tcl_platform(), and platform::identify, and many other
  4559. variables. JimTCL, as implemented in OpenOCD creates $HostOS which
  4560. holds one of the following values:
  4561. @itemize @bullet
  4562. @item @b{winxx} Built using Microsoft Visual Studio
  4563. @item @b{linux} Linux is the underlying operating sytem
  4564. @item @b{darwin} Darwin (mac-os) is the underlying operating sytem.
  4565. @item @b{cygwin} Running under Cygwin
  4566. @item @b{mingw32} Running under MingW32
  4567. @item @b{other} Unknown, none of the above.
  4568. @end itemize
  4569. Note: 'winxx' was choosen because today (March-2009) no distinction is made between Win32 and Win64.
  4570. @quotation Note
  4571. We should add support for a variable like Tcl variable
  4572. @code{tcl_platform(platform)}, it should be called
  4573. @code{jim_platform} (because it
  4574. is jim, not real tcl).
  4575. @end quotation
  4576. @node Upgrading
  4577. @chapter Deprecated/Removed Commands
  4578. @cindex Deprecated/Removed Commands
  4579. Certain OpenOCD commands have been deprecated or
  4580. removed during the various revisions.
  4581. Upgrade your scripts as soon as possible.
  4582. These descriptions for old commands may be removed
  4583. a year after the command itself was removed.
  4584. This means that in January 2010 this chapter may
  4585. become much shorter.
  4586. @itemize @bullet
  4587. @item @b{arm7_9 fast_writes}
  4588. @cindex arm7_9 fast_writes
  4589. @*Use @command{arm7_9 fast_memory_access} instead.
  4590. @xref{arm7_9 fast_memory_access}.
  4591. @item @b{endstate}
  4592. @cindex endstate
  4593. @*An buggy old command that would not really work since background polling would wipe out the global endstate
  4594. @item @b{arm7_9 force_hw_bkpts}
  4595. @*Use @command{gdb_breakpoint_override} instead. Note that GDB will use hardware breakpoints
  4596. for flash if the GDB memory map has been set up(default when flash is declared in
  4597. target configuration). @xref{gdb_breakpoint_override}.
  4598. @item @b{arm7_9 sw_bkpts}
  4599. @*On by default. @xref{gdb_breakpoint_override}.
  4600. @item @b{daemon_startup}
  4601. @*this config option has been removed, simply adding @option{init} and @option{reset halt} to
  4602. the end of your config script will give the same behaviour as using @option{daemon_startup reset}
  4603. and @option{target cortex_m3 little reset_halt 0}.
  4604. @item @b{dump_binary}
  4605. @*use @option{dump_image} command with same args. @xref{dump_image}.
  4606. @item @b{flash erase}
  4607. @*use @option{flash erase_sector} command with same args. @xref{flash erase_sector}.
  4608. @item @b{flash write}
  4609. @*use @option{flash write_bank} command with same args. @xref{flash write_bank}.
  4610. @item @b{flash write_binary}
  4611. @*use @option{flash write_bank} command with same args. @xref{flash write_bank}.
  4612. @item @b{flash auto_erase}
  4613. @*use @option{flash write_image} command passing @option{erase} as the first parameter. @xref{flash write_image}.
  4614. @item @b{jtag_device}
  4615. @*use the @command{jtag newtap} command, converting from positional syntax
  4616. to named prefixes, and naming the TAP.
  4617. @xref{jtag newtap}.
  4618. Note that if you try to use the old command, a message will tell you the
  4619. right new command to use; and that the fourth parameter in the old syntax
  4620. was never actually used.
  4621. @example
  4622. OLD: jtag_device 8 0x01 0xe3 0xfe
  4623. NEW: jtag newtap CHIPNAME TAPNAME \
  4624. -irlen 8 -ircapture 0x01 -irmask 0xe3
  4625. @end example
  4626. @item @b{jtag_speed} value
  4627. @*@xref{JTAG Speed}.
  4628. Usually, a value of zero means maximum
  4629. speed. The actual effect of this option depends on the JTAG interface used.
  4630. @itemize @minus
  4631. @item wiggler: maximum speed / @var{number}
  4632. @item ft2232: 6MHz / (@var{number}+1)
  4633. @item amt jtagaccel: 8 / 2**@var{number}
  4634. @item jlink: maximum speed in kHz (0-12000), 0 will use RTCK
  4635. @item rlink: 24MHz / @var{number}, but only for certain values of @var{number}
  4636. @comment end speed list.
  4637. @end itemize
  4638. @item @b{load_binary}
  4639. @*use @option{load_image} command with same args. @xref{load_image}.
  4640. @item @b{run_and_halt_time}
  4641. @*This command has been removed for simpler reset behaviour, it can be simulated with the
  4642. following commands:
  4643. @smallexample
  4644. reset run
  4645. sleep 100
  4646. halt
  4647. @end smallexample
  4648. @item @b{target} <@var{type}> <@var{endian}> <@var{jtag-position}>
  4649. @*use the create subcommand of @option{target}.
  4650. @item @b{target_script} <@var{target#}> <@var{eventname}> <@var{scriptname}>
  4651. @*use <@var{target_name}> configure -event <@var{eventname}> "script <@var{scriptname}>"
  4652. @item @b{working_area}
  4653. @*use the @option{configure} subcommand of @option{target} to set the work-area-virt, work-area-phy, work-area-size, and work-area-backup properties of the target.
  4654. @end itemize
  4655. @node FAQ
  4656. @chapter FAQ
  4657. @cindex faq
  4658. @enumerate
  4659. @anchor{FAQ RTCK}
  4660. @item @b{RTCK, also known as: Adaptive Clocking - What is it?}
  4661. @cindex RTCK
  4662. @cindex adaptive clocking
  4663. @*
  4664. In digital circuit design it is often refered to as ``clock
  4665. synchronisation'' the JTAG interface uses one clock (TCK or TCLK)
  4666. operating at some speed, your target is operating at another. The two
  4667. clocks are not synchronised, they are ``asynchronous''
  4668. In order for the two to work together they must be synchronised. Otherwise
  4669. the two systems will get out of sync with each other and nothing will
  4670. work. There are 2 basic options:
  4671. @enumerate
  4672. @item
  4673. Use a special circuit.
  4674. @item
  4675. One clock must be some multiple slower than the other.
  4676. @end enumerate
  4677. @b{Does this really matter?} For some chips and some situations, this
  4678. is a non-issue (i.e.: A 500MHz ARM926) but for others - for example some
  4679. Atmel SAM7 and SAM9 chips start operation from reset at 32kHz -
  4680. program/enable the oscillators and eventually the main clock. It is in
  4681. those critical times you must slow the JTAG clock to sometimes 1 to
  4682. 4kHz.
  4683. Imagine debugging a 500MHz ARM926 hand held battery powered device
  4684. that ``deep sleeps'' at 32kHz between every keystroke. It can be
  4685. painful.
  4686. @b{Solution #1 - A special circuit}
  4687. In order to make use of this, your JTAG dongle must support the RTCK
  4688. feature. Not all dongles support this - keep reading!
  4689. The RTCK signal often found in some ARM chips is used to help with
  4690. this problem. ARM has a good description of the problem described at
  4691. this link: @url{} [checked
  4692. 28/nov/2008]. Link title: ``How does the JTAG synchronisation logic
  4693. work? / how does adaptive clocking work?''.
  4694. The nice thing about adaptive clocking is that ``battery powered hand
  4695. held device example'' - the adaptiveness works perfectly all the
  4696. time. One can set a break point or halt the system in the deep power
  4697. down code, slow step out until the system speeds up.
  4698. Note that adaptive clocking may also need to work at the board level,
  4699. when a board-level scan chain has multiple chips.
  4700. Parallel clock voting schemes are good way to implement this,
  4701. both within and between chips, and can easily be implemented
  4702. with a CPLD.
  4703. It's not difficult to have logic fan a module's input TCK signal out
  4704. to each TAP in the scan chain, and then wait until each TAP's RTCK comes
  4705. back with the right polarity before changing the output RTCK signal.
  4706. Texas Instruments makes some clock voting logic available
  4707. for free (with no support) in VHDL form; see
  4708. @url{}
  4709. @b{Solution #2 - Always works - but may be slower}
  4710. Often this is a perfectly acceptable solution.
  4711. In most simple terms: Often the JTAG clock must be 1/10 to 1/12 of
  4712. the target clock speed. But what that ``magic division'' is varies
  4713. depending on the chips on your board. @b{ARM rule of thumb} Most ARM
  4714. based systems require an 8:1 division. @b{Xilinx rule of thumb} is
  4715. 1/12 the clock speed.
  4716. Note: Many FTDI2232C based JTAG dongles are limited to 6MHz.
  4717. You can still debug the 'low power' situations - you just need to
  4718. manually adjust the clock speed at every step. While painful and
  4719. tedious, it is not always practical.
  4720. It is however easy to ``code your way around it'' - i.e.: Cheat a little,
  4721. have a special debug mode in your application that does a ``high power
  4722. sleep''. If you are careful - 98% of your problems can be debugged
  4723. this way.
  4724. To set the JTAG frequency use the command:
  4725. @example
  4726. # Example: 1.234MHz
  4727. jtag_khz 1234
  4728. @end example
  4729. @item @b{Win32 Pathnames} Why don't backslashes work in Windows paths?
  4730. OpenOCD uses Tcl and a backslash is an escape char. Use @{ and @}
  4731. around Windows filenames.
  4732. @example
  4733. > echo \a
  4734. > echo @{\a@}
  4735. \a
  4736. > echo "\a"
  4737. >
  4738. @end example
  4739. @item @b{Missing: cygwin1.dll} OpenOCD complains about a missing cygwin1.dll.
  4740. Make sure you have Cygwin installed, or at least a version of OpenOCD that
  4741. claims to come with all the necessary DLLs. When using Cygwin, try launching
  4742. OpenOCD from the Cygwin shell.
  4743. @item @b{Breakpoint Issue} I'm trying to set a breakpoint using GDB (or a frontend like Insight or
  4744. Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213
  4745. arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".
  4746. GDB issues software breakpoints when a normal breakpoint is requested, or to implement
  4747. source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720T or ARM920T,
  4748. software breakpoints consume one of the two available hardware breakpoints.
  4749. @item @b{LPC2000 Flash} When erasing or writing LPC2000 on-chip flash, the operation fails at random.
  4750. Make sure the core frequency specified in the @option{flash lpc2000} line matches the
  4751. clock at the time you're programming the flash. If you've specified the crystal's
  4752. frequency, make sure the PLL is disabled. If you've specified the full core speed
  4753. (e.g. 60MHz), make sure the PLL is enabled.
  4754. @item @b{Amontec Chameleon} When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
  4755. I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed
  4756. out while waiting for end of scan, rtck was disabled".
  4757. Make sure your PC's parallel port operates in EPP mode. You might have to try several
  4758. settings in your PC BIOS (ECP, EPP, and different versions of those).
  4759. @item @b{Data Aborts} When debugging with OpenOCD and GDB (plain GDB, Insight, or Eclipse),
  4760. I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():
  4761. memory read caused data abort".
  4762. The errors are non-fatal, and are the result of GDB trying to trace stack frames
  4763. beyond the last valid frame. It might be possible to prevent this by setting up
  4764. a proper "initial" stack frame, if you happen to know what exactly has to
  4765. be done, feel free to add this here.
  4766. @b{Simple:} In your startup code - push 8 registers of zeros onto the
  4767. stack before calling main(). What GDB is doing is ``climbing'' the run
  4768. time stack by reading various values on the stack using the standard
  4769. call frame for the target. GDB keeps going - until one of 2 things
  4770. happen @b{#1} an invalid frame is found, or @b{#2} some huge number of
  4771. stackframes have been processed. By pushing zeros on the stack, GDB
  4772. gracefully stops.
  4773. @b{Debugging Interrupt Service Routines} - In your ISR before you call
  4774. your C code, do the same - artifically push some zeros onto the stack,
  4775. remember to pop them off when the ISR is done.
  4776. @b{Also note:} If you have a multi-threaded operating system, they
  4777. often do not @b{in the intrest of saving memory} waste these few
  4778. bytes. Painful...
  4779. @item @b{JTAG Reset Config} I get the following message in the OpenOCD console (or log file):
  4780. "Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".
  4781. This warning doesn't indicate any serious problem, as long as you don't want to
  4782. debug your core right out of reset. Your .cfg file specified @option{jtag_reset
  4783. trst_and_srst srst_pulls_trst} to tell OpenOCD that either your board,
  4784. your debugger or your target uC (e.g. LPC2000) can't assert the two reset signals
  4785. independently. With this setup, it's not possible to halt the core right out of
  4786. reset, everything else should work fine.
  4787. @item @b{USB Power} When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto
  4788. toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be
  4789. unstable. When single-stepping over large blocks of code, GDB and OpenOCD
  4790. quit with an error message. Is there a stability issue with OpenOCD?
  4791. No, this is not a stability issue concerning OpenOCD. Most users have solved
  4792. this issue by simply using a self-powered USB hub, which they connect their
  4793. Amontec JTAGkey to. Apparently, some computers do not provide a USB power
  4794. supply stable enough for the Amontec JTAGkey to be operated.
  4795. @b{Laptops running on battery have this problem too...}
  4796. @item @b{USB Power} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the
  4797. following error messages: "Error: ft2232.c:201 ft2232_read(): FT_Read returned:
  4798. 4" and "Error: ft2232.c:365 ft2232_send_and_recv(): couldn't read from FT2232".
  4799. What does that mean and what might be the reason for this?
  4800. First of all, the reason might be the USB power supply. Try using a self-powered
  4801. hub instead of a direct connection to your computer. Secondly, the error code 4
  4802. corresponds to an FT_IO_ERROR, which means that the driver for the FTDI USB
  4803. chip ran into some sort of error - this points us to a USB problem.
  4804. @item @b{GDB Disconnects} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following
  4805. error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054".
  4806. What does that mean and what might be the reason for this?
  4807. Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB)
  4808. has closed the connection to OpenOCD. This might be a GDB issue.
  4809. @item @b{LPC2000 Flash} In the configuration file in the section where flash device configurations
  4810. are described, there is a parameter for specifying the clock frequency
  4811. for LPC2000 internal flash devices (e.g. @option{flash bank lpc2000
  4812. 0x0 0x40000 0 0 0 lpc2000_v1 14746 calc_checksum}), which must be
  4813. specified in kilohertz. However, I do have a quartz crystal of a
  4814. frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz,
  4815. i.e. 14,745.600 kHz). Is it possible to specify real numbers for the
  4816. clock frequency?
  4817. No. The clock frequency specified here must be given as an integral number.
  4818. However, this clock frequency is used by the In-Application-Programming (IAP)
  4819. routines of the LPC2000 family only, which seems to be very tolerant concerning
  4820. the given clock frequency, so a slight difference between the specified clock
  4821. frequency and the actual clock frequency will not cause any trouble.
  4822. @item @b{Command Order} Do I have to keep a specific order for the commands in the configuration file?
  4823. Well, yes and no. Commands can be given in arbitrary order, yet the
  4824. devices listed for the JTAG scan chain must be given in the right
  4825. order (jtag newdevice), with the device closest to the TDO-Pin being
  4826. listed first. In general, whenever objects of the same type exist
  4827. which require an index number, then these objects must be given in the
  4828. right order (jtag newtap, targets and flash banks - a target
  4829. references a jtag newtap and a flash bank references a target).
  4830. You can use the ``scan_chain'' command to verify and display the tap order.
  4831. Also, some commands can't execute until after @command{init} has been
  4832. processed. Such commands include @command{nand probe} and everything
  4833. else that needs to write to controller registers, perhaps for setting
  4834. up DRAM and loading it with code.
  4835. @anchor{FAQ TAP Order}
  4836. @item @b{JTAG TAP Order} Do I have to declare the TAPS in some
  4837. particular order?
  4838. Yes; whenever you have more than one, you must declare them in
  4839. the same order used by the hardware.
  4840. Many newer devices have multiple JTAG TAPs. For example: ST
  4841. Microsystems STM32 chips have two TAPs, a ``boundary scan TAP'' and
  4842. ``Cortex-M3'' TAP. Example: The STM32 reference manual, Document ID:
  4843. RM0008, Section 26.5, Figure 259, page 651/681, the ``TDI'' pin is
  4844. connected to the boundary scan TAP, which then connects to the
  4845. Cortex-M3 TAP, which then connects to the TDO pin.
  4846. Thus, the proper order for the STM32 chip is: (1) The Cortex-M3, then
  4847. (2) The boundary scan TAP. If your board includes an additional JTAG
  4848. chip in the scan chain (for example a Xilinx CPLD or FPGA) you could
  4849. place it before or after the STM32 chip in the chain. For example:
  4850. @itemize @bullet
  4851. @item OpenOCD_TDI(output) -> STM32 TDI Pin (BS Input)
  4852. @item STM32 BS TDO (output) -> STM32 Cortex-M3 TDI (input)
  4853. @item STM32 Cortex-M3 TDO (output) -> SM32 TDO Pin
  4854. @item STM32 TDO Pin (output) -> Xilinx TDI Pin (input)
  4855. @item Xilinx TDO Pin -> OpenOCD TDO (input)
  4856. @end itemize
  4857. The ``jtag device'' commands would thus be in the order shown below. Note:
  4858. @itemize @bullet
  4859. @item jtag newtap Xilinx tap -irlen ...
  4860. @item jtag newtap stm32 cpu -irlen ...
  4861. @item jtag newtap stm32 bs -irlen ...
  4862. @item # Create the debug target and say where it is
  4863. @item target create stm32.cpu -chain-position stm32.cpu ...
  4864. @end itemize
  4865. @item @b{SYSCOMP} Sometimes my debugging session terminates with an error. When I look into the
  4866. log file, I can see these error messages: Error: arm7_9_common.c:561
  4867. arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP
  4868. TODO.
  4869. @end enumerate
  4870. @node Tcl Crash Course
  4871. @chapter Tcl Crash Course
  4872. @cindex Tcl
  4873. Not everyone knows Tcl - this is not intended to be a replacement for
  4874. learning Tcl, the intent of this chapter is to give you some idea of
  4875. how the Tcl scripts work.
  4876. This chapter is written with two audiences in mind. (1) OpenOCD users
  4877. who need to understand a bit more of how JIM-Tcl works so they can do
  4878. something useful, and (2) those that want to add a new command to
  4879. OpenOCD.
  4880. @section Tcl Rule #1
  4881. There is a famous joke, it goes like this:
  4882. @enumerate
  4883. @item Rule #1: The wife is always correct
  4884. @item Rule #2: If you think otherwise, See Rule #1
  4885. @end enumerate
  4886. The Tcl equal is this:
  4887. @enumerate
  4888. @item Rule #1: Everything is a string
  4889. @item Rule #2: If you think otherwise, See Rule #1
  4890. @end enumerate
  4891. As in the famous joke, the consequences of Rule #1 are profound. Once
  4892. you understand Rule #1, you will understand Tcl.
  4893. @section Tcl Rule #1b
  4894. There is a second pair of rules.
  4895. @enumerate
  4896. @item Rule #1: Control flow does not exist. Only commands
  4897. @* For example: the classic FOR loop or IF statement is not a control
  4898. flow item, they are commands, there is no such thing as control flow
  4899. in Tcl.
  4900. @item Rule #2: If you think otherwise, See Rule #1
  4901. @* Actually what happens is this: There are commands that by
  4902. convention, act like control flow key words in other languages. One of
  4903. those commands is the word ``for'', another command is ``if''.
  4904. @end enumerate
  4905. @section Per Rule #1 - All Results are strings
  4906. Every Tcl command results in a string. The word ``result'' is used
  4907. deliberatly. No result is just an empty string. Remember: @i{Rule #1 -
  4908. Everything is a string}
  4909. @section Tcl Quoting Operators
  4910. In life of a Tcl script, there are two important periods of time, the
  4911. difference is subtle.
  4912. @enumerate
  4913. @item Parse Time
  4914. @item Evaluation Time
  4915. @end enumerate
  4916. The two key items here are how ``quoted things'' work in Tcl. Tcl has
  4917. three primary quoting constructs, the [square-brackets] the
  4918. @{curly-braces@} and ``double-quotes''
  4919. By now you should know $VARIABLES always start with a $DOLLAR
  4920. sign. BTW: To set a variable, you actually use the command ``set'', as
  4921. in ``set VARNAME VALUE'' much like the ancient BASIC langauge ``let x
  4922. = 1'' statement, but without the equal sign.
  4923. @itemize @bullet
  4924. @item @b{[square-brackets]}
  4925. @* @b{[square-brackets]} are command substitutions. It operates much
  4926. like Unix Shell `back-ticks`. The result of a [square-bracket]
  4927. operation is exactly 1 string. @i{Remember Rule #1 - Everything is a
  4928. string}. These two statements are roughly identical:
  4929. @example
  4930. # bash example
  4931. X=`date`
  4932. echo "The Date is: $X"
  4933. # Tcl example
  4934. set X [date]
  4935. puts "The Date is: $X"
  4936. @end example
  4937. @item @b{``double-quoted-things''}
  4938. @* @b{``double-quoted-things''} are just simply quoted
  4939. text. $VARIABLES and [square-brackets] are expanded in place - the
  4940. result however is exactly 1 string. @i{Remember Rule #1 - Everything
  4941. is a string}
  4942. @example
  4943. set x "Dinner"
  4944. puts "It is now \"[date]\", $x is in 1 hour"
  4945. @end example
  4946. @item @b{@{Curly-Braces@}}
  4947. @*@b{@{Curly-Braces@}} are magic: $VARIABLES and [square-brackets] are
  4948. parsed, but are NOT expanded or executed. @{Curly-Braces@} are like
  4949. 'single-quote' operators in BASH shell scripts, with the added
  4950. feature: @{curly-braces@} can be nested, single quotes can not. @{@{@{this is
  4951. nested 3 times@}@}@} NOTE: [date] is a bad example;
  4952. at this writing, Jim/OpenOCD does not have a date command.
  4953. @end itemize
  4954. @section Consequences of Rule 1/2/3/4
  4955. The consequences of Rule 1 are profound.
  4956. @subsection Tokenisation & Execution.
  4957. Of course, whitespace, blank lines and #comment lines are handled in
  4958. the normal way.
  4959. As a script is parsed, each (multi) line in the script file is
  4960. tokenised and according to the quoting rules. After tokenisation, that
  4961. line is immedatly executed.
  4962. Multi line statements end with one or more ``still-open''
  4963. @{curly-braces@} which - eventually - closes a few lines later.
  4964. @subsection Command Execution
  4965. Remember earlier: There are no ``control flow''
  4966. statements in Tcl. Instead there are COMMANDS that simply act like
  4967. control flow operators.
  4968. Commands are executed like this:
  4969. @enumerate
  4970. @item Parse the next line into (argc) and (argv[]).
  4971. @item Look up (argv[0]) in a table and call its function.
  4972. @item Repeat until End Of File.
  4973. @end enumerate
  4974. It sort of works like this:
  4975. @example
  4976. for(;;)@{
  4977. ReadAndParse( &argc, &argv );
  4978. cmdPtr = LookupCommand( argv[0] );
  4979. (*cmdPtr->Execute)( argc, argv );
  4980. @}
  4981. @end example
  4982. When the command ``proc'' is parsed (which creates a procedure
  4983. function) it gets 3 parameters on the command line. @b{1} the name of
  4984. the proc (function), @b{2} the list of parameters, and @b{3} the body
  4985. of the function. Not the choice of words: LIST and BODY. The PROC
  4986. command stores these items in a table somewhere so it can be found by
  4987. ``LookupCommand()''
  4988. @subsection The FOR command
  4989. The most interesting command to look at is the FOR command. In Tcl,
  4990. the FOR command is normally implemented in C. Remember, FOR is a
  4991. command just like any other command.
  4992. When the ascii text containing the FOR command is parsed, the parser
  4993. produces 5 parameter strings, @i{(If in doubt: Refer to Rule #1)} they
  4994. are:
  4995. @enumerate 0
  4996. @item The ascii text 'for'
  4997. @item The start text
  4998. @item The test expression
  4999. @item The next text
  5000. @item The body text
  5001. @end enumerate
  5002. Sort of reminds you of ``main( int argc, char **argv )'' does it not?
  5003. Remember @i{Rule #1 - Everything is a string.} The key point is this:
  5004. Often many of those parameters are in @{curly-braces@} - thus the
  5005. variables inside are not expanded or replaced until later.
  5006. Remember that every Tcl command looks like the classic ``main( argc,
  5007. argv )'' function in C. In JimTCL - they actually look like this:
  5008. @example
  5009. int
  5010. MyCommand( Jim_Interp *interp,
  5011. int *argc,
  5012. Jim_Obj * const *argvs );
  5013. @end example
  5014. Real Tcl is nearly identical. Although the newer versions have
  5015. introduced a byte-code parser and intepreter, but at the core, it
  5016. still operates in the same basic way.
  5017. @subsection FOR command implementation
  5018. To understand Tcl it is perhaps most helpful to see the FOR
  5019. command. Remember, it is a COMMAND not a control flow structure.
  5020. In Tcl there are two underlying C helper functions.
  5021. Remember Rule #1 - You are a string.
  5022. The @b{first} helper parses and executes commands found in an ascii
  5023. string. Commands can be seperated by semicolons, or newlines. While
  5024. parsing, variables are expanded via the quoting rules.
  5025. The @b{second} helper evaluates an ascii string as a numerical
  5026. expression and returns a value.
  5027. Here is an example of how the @b{FOR} command could be
  5028. implemented. The pseudo code below does not show error handling.
  5029. @example
  5030. void Execute_AsciiString( void *interp, const char *string );
  5031. int Evaluate_AsciiExpression( void *interp, const char *string );
  5032. int
  5033. MyForCommand( void *interp,
  5034. int argc,
  5035. char **argv )
  5036. @{
  5037. if( argc != 5 )@{
  5038. SetResult( interp, "WRONG number of parameters");
  5039. return ERROR;
  5040. @}
  5041. // argv[0] = the ascii string just like C
  5042. // Execute the start statement.
  5043. Execute_AsciiString( interp, argv[1] );
  5044. // Top of loop test
  5045. for(;;)@{
  5046. i = Evaluate_AsciiExpression(interp, argv[2]);
  5047. if( i == 0 )
  5048. break;
  5049. // Execute the body
  5050. Execute_AsciiString( interp, argv[3] );
  5051. // Execute the LOOP part
  5052. Execute_AsciiString( interp, argv[4] );
  5053. @}
  5054. // Return no error
  5055. SetResult( interp, "" );
  5056. return SUCCESS;
  5057. @}
  5058. @end example
  5059. Every other command IF, WHILE, FORMAT, PUTS, EXPR, everything works
  5060. in the same basic way.
  5061. @section OpenOCD Tcl Usage
  5062. @subsection source and find commands
  5063. @b{Where:} In many configuration files
  5064. @* Example: @b{ source [find FILENAME] }
  5065. @*Remember the parsing rules
  5066. @enumerate
  5067. @item The FIND command is in square brackets.
  5068. @* The FIND command is executed with the parameter FILENAME. It should
  5069. find the full path to the named file. The RESULT is a string, which is
  5070. substituted on the orginal command line.
  5071. @item The command source is executed with the resulting filename.
  5072. @* SOURCE reads a file and executes as a script.
  5073. @end enumerate
  5074. @subsection format command
  5075. @b{Where:} Generally occurs in numerous places.
  5076. @* Tcl has no command like @b{printf()}, instead it has @b{format}, which is really more like
  5077. @b{sprintf()}.
  5078. @b{Example}
  5079. @example
  5080. set x 6
  5081. set y 7
  5082. puts [format "The answer: %d" [expr $x * $y]]
  5083. @end example
  5084. @enumerate
  5085. @item The SET command creates 2 variables, X and Y.
  5086. @item The double [nested] EXPR command performs math
  5087. @* The EXPR command produces numerical result as a string.
  5088. @* Refer to Rule #1
  5089. @item The format command is executed, producing a single string
  5090. @* Refer to Rule #1.
  5091. @item The PUTS command outputs the text.
  5092. @end enumerate
  5093. @subsection Body or Inlined Text
  5094. @b{Where:} Various TARGET scripts.
  5095. @example
  5096. #1 Good
  5097. proc someproc @{@} @{
  5098. ... multiple lines of stuff ...
  5099. @}
  5100. $_TARGETNAME configure -event FOO someproc
  5101. #2 Good - no variables
  5102. $_TARGETNAME confgure -event foo "this ; that;"
  5103. #3 Good Curly Braces
  5104. $_TARGETNAME configure -event FOO @{
  5105. puts "Time: [date]"
  5106. @}
  5108. $_TARGETNAME configure -event foo "puts \"Time: [date]\""
  5109. @end example
  5110. @enumerate
  5111. @item The $_TARGETNAME is an OpenOCD variable convention.
  5112. @*@b{$_TARGETNAME} represents the last target created, the value changes
  5113. each time a new target is created. Remember the parsing rules. When
  5114. the ascii text is parsed, the @b{$_TARGETNAME} becomes a simple string,
  5115. the name of the target which happens to be a TARGET (object)
  5116. command.
  5117. @item The 2nd parameter to the @option{-event} parameter is a TCBODY
  5118. @*There are 4 examples:
  5119. @enumerate
  5120. @item The TCLBODY is a simple string that happens to be a proc name
  5121. @item The TCLBODY is several simple commands seperated by semicolons
  5122. @item The TCLBODY is a multi-line @{curly-brace@} quoted string
  5123. @item The TCLBODY is a string with variables that get expanded.
  5124. @end enumerate
  5125. In the end, when the target event FOO occurs the TCLBODY is
  5126. evaluated. Method @b{#1} and @b{#2} are functionally identical. For
  5127. Method @b{#3} and @b{#4} it is more interesting. What is the TCLBODY?
  5128. Remember the parsing rules. In case #3, @{curly-braces@} mean the
  5129. $VARS and [square-brackets] are expanded later, when the EVENT occurs,
  5130. and the text is evaluated. In case #4, they are replaced before the
  5131. ``Target Object Command'' is executed. This occurs at the same time
  5132. $_TARGETNAME is replaced. In case #4 the date will never
  5133. change. @{BTW: [date] is a bad example; at this writing,
  5134. Jim/OpenOCD does not have a date command@}
  5135. @end enumerate
  5136. @subsection Global Variables
  5137. @b{Where:} You might discover this when writing your own procs @* In
  5138. simple terms: Inside a PROC, if you need to access a global variable
  5139. you must say so. See also ``upvar''. Example:
  5140. @example
  5141. proc myproc @{ @} @{
  5142. set y 0 #Local variable Y
  5143. global x #Global variable X
  5144. puts [format "X=%d, Y=%d" $x $y]
  5145. @}
  5146. @end example
  5147. @section Other Tcl Hacks
  5148. @b{Dynamic variable creation}
  5149. @example
  5150. # Dynamically create a bunch of variables.
  5151. for @{ set x 0 @} @{ $x < 32 @} @{ set x [expr $x + 1]@} @{
  5152. # Create var name
  5153. set vn [format "BIT%d" $x]
  5154. # Make it a global
  5155. global $vn
  5156. # Set it.
  5157. set $vn [expr (1 << $x)]
  5158. @}
  5159. @end example
  5160. @b{Dynamic proc/command creation}
  5161. @example
  5162. # One "X" function - 5 uart functions.
  5163. foreach who @{A B C D E@}
  5164. proc [format "show_uart%c" $who] @{ @} "show_UARTx $who"
  5165. @}
  5166. @end example
  5167. @node Target Library
  5168. @chapter Target Library
  5169. @cindex Target Library
  5170. OpenOCD comes with a target configuration script library. These scripts can be
  5171. used as-is or serve as a starting point.
  5172. The target library is published together with the OpenOCD executable and
  5173. the path to the target library is in the OpenOCD script search path.
  5174. Similarly there are example scripts for configuring the JTAG interface.
  5175. The command line below uses the example parport configuration script
  5176. that ship with OpenOCD, then configures the str710.cfg target and
  5177. finally issues the init and reset commands. The communication speed
  5178. is set to 10kHz for reset and 8MHz for post reset.
  5179. @example
  5180. openocd -f interface/parport.cfg -f target/str710.cfg \
  5181. -c "init" -c "reset"
  5182. @end example
  5183. To list the target scripts available:
  5184. @example
  5185. $ ls /usr/local/lib/openocd/target
  5186. arm7_fast.cfg lm3s6965.cfg pxa255.cfg stm32.cfg xba_revA3.cfg
  5187. at91eb40a.cfg lpc2148.cfg pxa255_sst.cfg str710.cfg zy1000.cfg
  5188. at91r40008.cfg lpc2294.cfg sam7s256.cfg str912.cfg
  5189. at91sam9260.cfg nslu2.cfg sam7x256.cfg wi-9c.cfg
  5190. @end example
  5191. @include fdl.texi
  5192. @node OpenOCD Concept Index
  5193. @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
  5194. @comment case issue with ``Index.html'' and ``index.html''
  5195. @comment Occurs when creating ``--html --no-split'' output
  5196. @comment This fix is based on:
  5197. @unnumbered OpenOCD Concept Index
  5198. @printindex cp
  5199. @node Command and Driver Index
  5200. @unnumbered Command and Driver Index
  5201. @printindex fn
  5202. @bye