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  1. /***************************************************************************
  2. * Copyright (C) 2008 digenius technology GmbH. *
  3. * Michael Bruck *
  4. * *
  5. * Copyright (C) 2008,2009 Oyvind Harboe oyvind.harboe@zylin.com *
  6. * *
  7. * Copyright (C) 2008 Georg Acher <acher@in.tum.de> *
  8. * *
  9. * This program is free software; you can redistribute it and/or modify *
  10. * it under the terms of the GNU General Public License as published by *
  11. * the Free Software Foundation; either version 2 of the License, or *
  12. * (at your option) any later version. *
  13. * *
  14. * This program is distributed in the hope that it will be useful, *
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  17. * GNU General Public License for more details. *
  18. * *
  19. * You should have received a copy of the GNU General Public License *
  20. * along with this program; if not, write to the *
  21. * Free Software Foundation, Inc., *
  22. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
  23. ***************************************************************************/
  24. #ifdef HAVE_CONFIG_H
  25. #include "config.h"
  26. #endif
  27. #include "arm11.h"
  28. #include "armv4_5.h"
  29. #include "arm_simulator.h"
  30. #include "time_support.h"
  31. #include "target_type.h"
  32. #if 0
  33. #define _DEBUG_INSTRUCTION_EXECUTION_
  34. #endif
  35. #if 0
  36. #define FNC_INFO LOG_DEBUG("-")
  37. #else
  38. #define FNC_INFO
  39. #endif
  40. #if 1
  41. #define FNC_INFO_NOTIMPLEMENTED do { LOG_DEBUG("NOT IMPLEMENTED"); /*exit(-1);*/ } while (0)
  42. #else
  43. #define FNC_INFO_NOTIMPLEMENTED
  44. #endif
  45. static int arm11_on_enter_debug_state(arm11_common_t * arm11);
  46. bool arm11_config_memwrite_burst = true;
  47. bool arm11_config_memwrite_error_fatal = true;
  48. uint32_t arm11_vcr = 0;
  49. bool arm11_config_step_irq_enable = false;
  50. bool arm11_config_hardware_step = false;
  51. #define ARM11_HANDLER(x) \
  52. .x = arm11_##x
  53. target_type_t arm11_target =
  54. {
  55. .name = "arm11",
  56. ARM11_HANDLER(poll),
  57. ARM11_HANDLER(arch_state),
  58. ARM11_HANDLER(target_request_data),
  59. ARM11_HANDLER(halt),
  60. ARM11_HANDLER(resume),
  61. ARM11_HANDLER(step),
  62. ARM11_HANDLER(assert_reset),
  63. ARM11_HANDLER(deassert_reset),
  64. ARM11_HANDLER(soft_reset_halt),
  65. ARM11_HANDLER(get_gdb_reg_list),
  66. ARM11_HANDLER(read_memory),
  67. ARM11_HANDLER(write_memory),
  68. ARM11_HANDLER(bulk_write_memory),
  69. ARM11_HANDLER(checksum_memory),
  70. ARM11_HANDLER(add_breakpoint),
  71. ARM11_HANDLER(remove_breakpoint),
  72. ARM11_HANDLER(add_watchpoint),
  73. ARM11_HANDLER(remove_watchpoint),
  74. ARM11_HANDLER(run_algorithm),
  75. ARM11_HANDLER(register_commands),
  76. ARM11_HANDLER(target_create),
  77. ARM11_HANDLER(init_target),
  78. ARM11_HANDLER(examine),
  79. ARM11_HANDLER(quit),
  80. };
  81. int arm11_regs_arch_type = -1;
  82. enum arm11_regtype
  83. {
  84. ARM11_REGISTER_CORE,
  85. ARM11_REGISTER_CPSR,
  86. ARM11_REGISTER_FX,
  87. ARM11_REGISTER_FPS,
  88. ARM11_REGISTER_FIQ,
  89. ARM11_REGISTER_SVC,
  90. ARM11_REGISTER_ABT,
  91. ARM11_REGISTER_IRQ,
  92. ARM11_REGISTER_UND,
  93. ARM11_REGISTER_MON,
  94. ARM11_REGISTER_SPSR_FIQ,
  95. ARM11_REGISTER_SPSR_SVC,
  96. ARM11_REGISTER_SPSR_ABT,
  97. ARM11_REGISTER_SPSR_IRQ,
  98. ARM11_REGISTER_SPSR_UND,
  99. ARM11_REGISTER_SPSR_MON,
  100. /* debug regs */
  101. ARM11_REGISTER_DSCR,
  102. ARM11_REGISTER_WDTR,
  103. ARM11_REGISTER_RDTR,
  104. };
  105. typedef struct arm11_reg_defs_s
  106. {
  107. char * name;
  108. uint32_t num;
  109. int gdb_num;
  110. enum arm11_regtype type;
  111. } arm11_reg_defs_t;
  112. /* update arm11_regcache_ids when changing this */
  113. static const arm11_reg_defs_t arm11_reg_defs[] =
  114. {
  115. {"r0", 0, 0, ARM11_REGISTER_CORE},
  116. {"r1", 1, 1, ARM11_REGISTER_CORE},
  117. {"r2", 2, 2, ARM11_REGISTER_CORE},
  118. {"r3", 3, 3, ARM11_REGISTER_CORE},
  119. {"r4", 4, 4, ARM11_REGISTER_CORE},
  120. {"r5", 5, 5, ARM11_REGISTER_CORE},
  121. {"r6", 6, 6, ARM11_REGISTER_CORE},
  122. {"r7", 7, 7, ARM11_REGISTER_CORE},
  123. {"r8", 8, 8, ARM11_REGISTER_CORE},
  124. {"r9", 9, 9, ARM11_REGISTER_CORE},
  125. {"r10", 10, 10, ARM11_REGISTER_CORE},
  126. {"r11", 11, 11, ARM11_REGISTER_CORE},
  127. {"r12", 12, 12, ARM11_REGISTER_CORE},
  128. {"sp", 13, 13, ARM11_REGISTER_CORE},
  129. {"lr", 14, 14, ARM11_REGISTER_CORE},
  130. {"pc", 15, 15, ARM11_REGISTER_CORE},
  131. #if ARM11_REGCACHE_FREGS
  132. {"f0", 0, 16, ARM11_REGISTER_FX},
  133. {"f1", 1, 17, ARM11_REGISTER_FX},
  134. {"f2", 2, 18, ARM11_REGISTER_FX},
  135. {"f3", 3, 19, ARM11_REGISTER_FX},
  136. {"f4", 4, 20, ARM11_REGISTER_FX},
  137. {"f5", 5, 21, ARM11_REGISTER_FX},
  138. {"f6", 6, 22, ARM11_REGISTER_FX},
  139. {"f7", 7, 23, ARM11_REGISTER_FX},
  140. {"fps", 0, 24, ARM11_REGISTER_FPS},
  141. #endif
  142. {"cpsr", 0, 25, ARM11_REGISTER_CPSR},
  143. #if ARM11_REGCACHE_MODEREGS
  144. {"r8_fiq", 8, -1, ARM11_REGISTER_FIQ},
  145. {"r9_fiq", 9, -1, ARM11_REGISTER_FIQ},
  146. {"r10_fiq", 10, -1, ARM11_REGISTER_FIQ},
  147. {"r11_fiq", 11, -1, ARM11_REGISTER_FIQ},
  148. {"r12_fiq", 12, -1, ARM11_REGISTER_FIQ},
  149. {"r13_fiq", 13, -1, ARM11_REGISTER_FIQ},
  150. {"r14_fiq", 14, -1, ARM11_REGISTER_FIQ},
  151. {"spsr_fiq", 0, -1, ARM11_REGISTER_SPSR_FIQ},
  152. {"r13_svc", 13, -1, ARM11_REGISTER_SVC},
  153. {"r14_svc", 14, -1, ARM11_REGISTER_SVC},
  154. {"spsr_svc", 0, -1, ARM11_REGISTER_SPSR_SVC},
  155. {"r13_abt", 13, -1, ARM11_REGISTER_ABT},
  156. {"r14_abt", 14, -1, ARM11_REGISTER_ABT},
  157. {"spsr_abt", 0, -1, ARM11_REGISTER_SPSR_ABT},
  158. {"r13_irq", 13, -1, ARM11_REGISTER_IRQ},
  159. {"r14_irq", 14, -1, ARM11_REGISTER_IRQ},
  160. {"spsr_irq", 0, -1, ARM11_REGISTER_SPSR_IRQ},
  161. {"r13_und", 13, -1, ARM11_REGISTER_UND},
  162. {"r14_und", 14, -1, ARM11_REGISTER_UND},
  163. {"spsr_und", 0, -1, ARM11_REGISTER_SPSR_UND},
  164. /* ARM1176 only */
  165. {"r13_mon", 13, -1, ARM11_REGISTER_MON},
  166. {"r14_mon", 14, -1, ARM11_REGISTER_MON},
  167. {"spsr_mon", 0, -1, ARM11_REGISTER_SPSR_MON},
  168. #endif
  169. /* Debug Registers */
  170. {"dscr", 0, -1, ARM11_REGISTER_DSCR},
  171. {"wdtr", 0, -1, ARM11_REGISTER_WDTR},
  172. {"rdtr", 0, -1, ARM11_REGISTER_RDTR},
  173. };
  174. enum arm11_regcache_ids
  175. {
  176. ARM11_RC_R0,
  177. ARM11_RC_RX = ARM11_RC_R0,
  178. ARM11_RC_R1,
  179. ARM11_RC_R2,
  180. ARM11_RC_R3,
  181. ARM11_RC_R4,
  182. ARM11_RC_R5,
  183. ARM11_RC_R6,
  184. ARM11_RC_R7,
  185. ARM11_RC_R8,
  186. ARM11_RC_R9,
  187. ARM11_RC_R10,
  188. ARM11_RC_R11,
  189. ARM11_RC_R12,
  190. ARM11_RC_R13,
  191. ARM11_RC_SP = ARM11_RC_R13,
  192. ARM11_RC_R14,
  193. ARM11_RC_LR = ARM11_RC_R14,
  194. ARM11_RC_R15,
  195. ARM11_RC_PC = ARM11_RC_R15,
  196. #if ARM11_REGCACHE_FREGS
  197. ARM11_RC_F0,
  198. ARM11_RC_FX = ARM11_RC_F0,
  199. ARM11_RC_F1,
  200. ARM11_RC_F2,
  201. ARM11_RC_F3,
  202. ARM11_RC_F4,
  203. ARM11_RC_F5,
  204. ARM11_RC_F6,
  205. ARM11_RC_F7,
  206. ARM11_RC_FPS,
  207. #endif
  208. ARM11_RC_CPSR,
  209. #if ARM11_REGCACHE_MODEREGS
  210. ARM11_RC_R8_FIQ,
  211. ARM11_RC_R9_FIQ,
  212. ARM11_RC_R10_FIQ,
  213. ARM11_RC_R11_FIQ,
  214. ARM11_RC_R12_FIQ,
  215. ARM11_RC_R13_FIQ,
  216. ARM11_RC_R14_FIQ,
  217. ARM11_RC_SPSR_FIQ,
  218. ARM11_RC_R13_SVC,
  219. ARM11_RC_R14_SVC,
  220. ARM11_RC_SPSR_SVC,
  221. ARM11_RC_R13_ABT,
  222. ARM11_RC_R14_ABT,
  223. ARM11_RC_SPSR_ABT,
  224. ARM11_RC_R13_IRQ,
  225. ARM11_RC_R14_IRQ,
  226. ARM11_RC_SPSR_IRQ,
  227. ARM11_RC_R13_UND,
  228. ARM11_RC_R14_UND,
  229. ARM11_RC_SPSR_UND,
  230. ARM11_RC_R13_MON,
  231. ARM11_RC_R14_MON,
  232. ARM11_RC_SPSR_MON,
  233. #endif
  234. ARM11_RC_DSCR,
  235. ARM11_RC_WDTR,
  236. ARM11_RC_RDTR,
  237. ARM11_RC_MAX,
  238. };
  239. #define ARM11_GDB_REGISTER_COUNT 26
  240. uint8_t arm11_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
  241. reg_t arm11_gdb_dummy_fp_reg =
  242. {
  243. "GDB dummy floating-point register", arm11_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
  244. };
  245. uint8_t arm11_gdb_dummy_fps_value[] = {0, 0, 0, 0};
  246. reg_t arm11_gdb_dummy_fps_reg =
  247. {
  248. "GDB dummy floating-point status register", arm11_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0
  249. };
  250. /** Check and if necessary take control of the system
  251. *
  252. * \param arm11 Target state variable.
  253. * \param dscr If the current DSCR content is
  254. * available a pointer to a word holding the
  255. * DSCR can be passed. Otherwise use NULL.
  256. */
  257. int arm11_check_init(arm11_common_t * arm11, uint32_t * dscr)
  258. {
  259. FNC_INFO;
  260. uint32_t dscr_local_tmp_copy;
  261. if (!dscr)
  262. {
  263. dscr = &dscr_local_tmp_copy;
  264. CHECK_RETVAL(arm11_read_DSCR(arm11, dscr));
  265. }
  266. if (!(*dscr & ARM11_DSCR_MODE_SELECT))
  267. {
  268. LOG_DEBUG("Bringing target into debug mode");
  269. *dscr |= ARM11_DSCR_MODE_SELECT; /* Halt debug-mode */
  270. arm11_write_DSCR(arm11, *dscr);
  271. /* add further reset initialization here */
  272. arm11->simulate_reset_on_next_halt = true;
  273. if (*dscr & ARM11_DSCR_CORE_HALTED)
  274. {
  275. /** \todo TODO: this needs further scrutiny because
  276. * arm11_on_enter_debug_state() never gets properly called.
  277. * As a result we don't read the actual register states from
  278. * the target.
  279. */
  280. arm11->target->state = TARGET_HALTED;
  281. arm11->target->debug_reason = arm11_get_DSCR_debug_reason(*dscr);
  282. }
  283. else
  284. {
  285. arm11->target->state = TARGET_RUNNING;
  286. arm11->target->debug_reason = DBG_REASON_NOTHALTED;
  287. }
  288. arm11_sc7_clear_vbw(arm11);
  289. }
  290. return ERROR_OK;
  291. }
  292. #define R(x) \
  293. (arm11->reg_values[ARM11_RC_##x])
  294. /** Save processor state.
  295. *
  296. * This is called when the HALT instruction has succeeded
  297. * or on other occasions that stop the processor.
  298. *
  299. */
  300. static int arm11_on_enter_debug_state(arm11_common_t * arm11)
  301. {
  302. int retval;
  303. FNC_INFO;
  304. for (size_t i = 0; i < asizeof(arm11->reg_values); i++)
  305. {
  306. arm11->reg_list[i].valid = 1;
  307. arm11->reg_list[i].dirty = 0;
  308. }
  309. /* Save DSCR */
  310. CHECK_RETVAL(arm11_read_DSCR(arm11, &R(DSCR)));
  311. /* Save wDTR */
  312. if (R(DSCR) & ARM11_DSCR_WDTR_FULL)
  313. {
  314. arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
  315. arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
  316. scan_field_t chain5_fields[3];
  317. arm11_setup_field(arm11, 32, NULL, &R(WDTR), chain5_fields + 0);
  318. arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 1);
  319. arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2);
  320. arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
  321. }
  322. else
  323. {
  324. arm11->reg_list[ARM11_RC_WDTR].valid = 0;
  325. }
  326. /* DSCR: set ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE */
  327. /* ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode", but not to issue ITRs
  328. ARM1136 seems to require this to issue ITR's as well */
  329. uint32_t new_dscr = R(DSCR) | ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE;
  330. /* this executes JTAG queue: */
  331. arm11_write_DSCR(arm11, new_dscr);
  332. /* From the spec:
  333. Before executing any instruction in debug state you have to drain the write buffer.
  334. This ensures that no imprecise Data Aborts can return at a later point:*/
  335. /** \todo TODO: Test drain write buffer. */
  336. #if 0
  337. while (1)
  338. {
  339. /* MRC p14,0,R0,c5,c10,0 */
  340. // arm11_run_instr_no_data1(arm11, /*0xee150e1a*/0xe320f000);
  341. /* mcr 15, 0, r0, cr7, cr10, {4} */
  342. arm11_run_instr_no_data1(arm11, 0xee070f9a);
  343. uint32_t dscr = arm11_read_DSCR(arm11);
  344. LOG_DEBUG("DRAIN, DSCR %08x", dscr);
  345. if (dscr & ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT)
  346. {
  347. arm11_run_instr_no_data1(arm11, 0xe320f000);
  348. dscr = arm11_read_DSCR(arm11);
  349. LOG_DEBUG("DRAIN, DSCR %08x (DONE)", dscr);
  350. break;
  351. }
  352. }
  353. #endif
  354. retval = arm11_run_instr_data_prepare(arm11);
  355. if (retval != ERROR_OK)
  356. return retval;
  357. /* save r0 - r14 */
  358. /** \todo TODO: handle other mode registers */
  359. for (size_t i = 0; i < 15; i++)
  360. {
  361. /* MCR p14,0,R?,c0,c5,0 */
  362. retval = arm11_run_instr_data_from_core(arm11, 0xEE000E15 | (i << 12), &R(RX + i), 1);
  363. if (retval != ERROR_OK)
  364. return retval;
  365. }
  366. /* save rDTR */
  367. /* check rDTRfull in DSCR */
  368. if (R(DSCR) & ARM11_DSCR_RDTR_FULL)
  369. {
  370. /* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */
  371. retval = arm11_run_instr_data_from_core_via_r0(arm11, 0xEE100E15, &R(RDTR));
  372. if (retval != ERROR_OK)
  373. return retval;
  374. }
  375. else
  376. {
  377. arm11->reg_list[ARM11_RC_RDTR].valid = 0;
  378. }
  379. /* save CPSR */
  380. /* MRS r0,CPSR (move CPSR -> r0 (-> wDTR -> local var)) */
  381. retval = arm11_run_instr_data_from_core_via_r0(arm11, 0xE10F0000, &R(CPSR));
  382. if (retval != ERROR_OK)
  383. return retval;
  384. /* save PC */
  385. /* MOV R0,PC (move PC -> r0 (-> wDTR -> local var)) */
  386. retval = arm11_run_instr_data_from_core_via_r0(arm11, 0xE1A0000F, &R(PC));
  387. if (retval != ERROR_OK)
  388. return retval;
  389. /* adjust PC depending on ARM state */
  390. if (R(CPSR) & ARM11_CPSR_J) /* Java state */
  391. {
  392. arm11->reg_values[ARM11_RC_PC] -= 0;
  393. }
  394. else if (R(CPSR) & ARM11_CPSR_T) /* Thumb state */
  395. {
  396. arm11->reg_values[ARM11_RC_PC] -= 4;
  397. }
  398. else /* ARM state */
  399. {
  400. arm11->reg_values[ARM11_RC_PC] -= 8;
  401. }
  402. if (arm11->simulate_reset_on_next_halt)
  403. {
  404. arm11->simulate_reset_on_next_halt = false;
  405. LOG_DEBUG("Reset c1 Control Register");
  406. /* Write 0 (reset value) to Control register 0 to disable MMU/Cache etc. */
  407. /* MCR p15,0,R0,c1,c0,0 */
  408. retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xee010f10, 0);
  409. if (retval != ERROR_OK)
  410. return retval;
  411. }
  412. retval = arm11_run_instr_data_finish(arm11);
  413. if (retval != ERROR_OK)
  414. return retval;
  415. arm11_dump_reg_changes(arm11);
  416. return ERROR_OK;
  417. }
  418. void arm11_dump_reg_changes(arm11_common_t * arm11)
  419. {
  420. if (!(debug_level >= LOG_LVL_DEBUG))
  421. {
  422. return;
  423. }
  424. for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
  425. {
  426. if (!arm11->reg_list[i].valid)
  427. {
  428. if (arm11->reg_history[i].valid)
  429. LOG_DEBUG("%8s INVALID (%08" PRIx32 ")", arm11_reg_defs[i].name, arm11->reg_history[i].value);
  430. }
  431. else
  432. {
  433. if (arm11->reg_history[i].valid)
  434. {
  435. if (arm11->reg_history[i].value != arm11->reg_values[i])
  436. LOG_DEBUG("%8s %08" PRIx32 " (%08" PRIx32 ")", arm11_reg_defs[i].name, arm11->reg_values[i], arm11->reg_history[i].value);
  437. }
  438. else
  439. {
  440. LOG_DEBUG("%8s %08" PRIx32 " (INVALID)", arm11_reg_defs[i].name, arm11->reg_values[i]);
  441. }
  442. }
  443. }
  444. }
  445. /** Restore processor state
  446. *
  447. * This is called in preparation for the RESTART function.
  448. *
  449. */
  450. int arm11_leave_debug_state(arm11_common_t * arm11)
  451. {
  452. FNC_INFO;
  453. int retval;
  454. retval = arm11_run_instr_data_prepare(arm11);
  455. if (retval != ERROR_OK)
  456. return retval;
  457. /** \todo TODO: handle other mode registers */
  458. /* restore R1 - R14 */
  459. for (size_t i = 1; i < 15; i++)
  460. {
  461. if (!arm11->reg_list[ARM11_RC_RX + i].dirty)
  462. continue;
  463. /* MRC p14,0,r?,c0,c5,0 */
  464. arm11_run_instr_data_to_core1(arm11, 0xee100e15 | (i << 12), R(RX + i));
  465. // LOG_DEBUG("RESTORE R" ZU " %08x", i, R(RX + i));
  466. }
  467. retval = arm11_run_instr_data_finish(arm11);
  468. if (retval != ERROR_OK)
  469. return retval;
  470. /* spec says clear wDTR and rDTR; we assume they are clear as
  471. otherwise our programming would be sloppy */
  472. {
  473. uint32_t DSCR;
  474. CHECK_RETVAL(arm11_read_DSCR(arm11, &DSCR));
  475. if (DSCR & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL))
  476. {
  477. /*
  478. The wDTR/rDTR two registers that are used to send/receive data to/from
  479. the core in tandem with corresponding instruction codes that are
  480. written into the core. The RDTR FULL/WDTR FULL flag indicates that the
  481. registers hold data that was written by one side (CPU or JTAG) and not
  482. read out by the other side.
  483. */
  484. LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08" PRIx32 ")", DSCR);
  485. return ERROR_FAIL;
  486. }
  487. }
  488. retval = arm11_run_instr_data_prepare(arm11);
  489. if (retval != ERROR_OK)
  490. return retval;
  491. /* restore original wDTR */
  492. if ((R(DSCR) & ARM11_DSCR_WDTR_FULL) || arm11->reg_list[ARM11_RC_WDTR].dirty)
  493. {
  494. /* MCR p14,0,R0,c0,c5,0 */
  495. retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xee000e15, R(WDTR));
  496. if (retval != ERROR_OK)
  497. return retval;
  498. }
  499. /* restore CPSR */
  500. /* MSR CPSR,R0*/
  501. retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xe129f000, R(CPSR));
  502. if (retval != ERROR_OK)
  503. return retval;
  504. /* restore PC */
  505. /* MOV PC,R0 */
  506. retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xe1a0f000, R(PC));
  507. if (retval != ERROR_OK)
  508. return retval;
  509. /* restore R0 */
  510. /* MRC p14,0,r0,c0,c5,0 */
  511. arm11_run_instr_data_to_core1(arm11, 0xee100e15, R(R0));
  512. retval = arm11_run_instr_data_finish(arm11);
  513. if (retval != ERROR_OK)
  514. return retval;
  515. /* restore DSCR */
  516. arm11_write_DSCR(arm11, R(DSCR));
  517. /* restore rDTR */
  518. if (R(DSCR) & ARM11_DSCR_RDTR_FULL || arm11->reg_list[ARM11_RC_RDTR].dirty)
  519. {
  520. arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
  521. arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
  522. scan_field_t chain5_fields[3];
  523. uint8_t Ready = 0; /* ignored */
  524. uint8_t Valid = 0; /* ignored */
  525. arm11_setup_field(arm11, 32, &R(RDTR), NULL, chain5_fields + 0);
  526. arm11_setup_field(arm11, 1, &Ready, NULL, chain5_fields + 1);
  527. arm11_setup_field(arm11, 1, &Valid, NULL, chain5_fields + 2);
  528. arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
  529. }
  530. arm11_record_register_history(arm11);
  531. return ERROR_OK;
  532. }
  533. void arm11_record_register_history(arm11_common_t * arm11)
  534. {
  535. for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
  536. {
  537. arm11->reg_history[i].value = arm11->reg_values[i];
  538. arm11->reg_history[i].valid = arm11->reg_list[i].valid;
  539. arm11->reg_list[i].valid = 0;
  540. arm11->reg_list[i].dirty = 0;
  541. }
  542. }
  543. /* poll current target status */
  544. int arm11_poll(struct target_s *target)
  545. {
  546. FNC_INFO;
  547. int retval;
  548. arm11_common_t * arm11 = target->arch_info;
  549. uint32_t dscr;
  550. CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
  551. LOG_DEBUG("DSCR %08" PRIx32 "", dscr);
  552. CHECK_RETVAL(arm11_check_init(arm11, &dscr));
  553. if (dscr & ARM11_DSCR_CORE_HALTED)
  554. {
  555. if (target->state != TARGET_HALTED)
  556. {
  557. enum target_state old_state = target->state;
  558. LOG_DEBUG("enter TARGET_HALTED");
  559. target->state = TARGET_HALTED;
  560. target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
  561. retval = arm11_on_enter_debug_state(arm11);
  562. if (retval != ERROR_OK)
  563. return retval;
  564. target_call_event_callbacks(target,
  565. old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED);
  566. }
  567. }
  568. else
  569. {
  570. if (target->state != TARGET_RUNNING && target->state != TARGET_DEBUG_RUNNING)
  571. {
  572. LOG_DEBUG("enter TARGET_RUNNING");
  573. target->state = TARGET_RUNNING;
  574. target->debug_reason = DBG_REASON_NOTHALTED;
  575. }
  576. }
  577. return ERROR_OK;
  578. }
  579. /* architecture specific status reply */
  580. int arm11_arch_state(struct target_s *target)
  581. {
  582. arm11_common_t * arm11 = target->arch_info;
  583. LOG_USER("target halted due to %s\ncpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "",
  584. Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name,
  585. R(CPSR),
  586. R(PC));
  587. return ERROR_OK;
  588. }
  589. /* target request support */
  590. int arm11_target_request_data(struct target_s *target, uint32_t size, uint8_t *buffer)
  591. {
  592. FNC_INFO_NOTIMPLEMENTED;
  593. return ERROR_OK;
  594. }
  595. /* target execution control */
  596. int arm11_halt(struct target_s *target)
  597. {
  598. FNC_INFO;
  599. arm11_common_t * arm11 = target->arch_info;
  600. LOG_DEBUG("target->state: %s",
  601. target_state_name(target));
  602. if (target->state == TARGET_UNKNOWN)
  603. {
  604. arm11->simulate_reset_on_next_halt = true;
  605. }
  606. if (target->state == TARGET_HALTED)
  607. {
  608. LOG_DEBUG("target was already halted");
  609. return ERROR_OK;
  610. }
  611. arm11_add_IR(arm11, ARM11_HALT, TAP_IDLE);
  612. CHECK_RETVAL(jtag_execute_queue());
  613. uint32_t dscr;
  614. int i = 0;
  615. while (1)
  616. {
  617. CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
  618. if (dscr & ARM11_DSCR_CORE_HALTED)
  619. break;
  620. long long then = 0;
  621. if (i == 1000)
  622. {
  623. then = timeval_ms();
  624. }
  625. if (i >= 1000)
  626. {
  627. if ((timeval_ms()-then) > 1000)
  628. {
  629. LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
  630. return ERROR_FAIL;
  631. }
  632. }
  633. i++;
  634. }
  635. arm11_on_enter_debug_state(arm11);
  636. enum target_state old_state = target->state;
  637. target->state = TARGET_HALTED;
  638. target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
  639. CHECK_RETVAL(
  640. target_call_event_callbacks(target,
  641. old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED));
  642. return ERROR_OK;
  643. }
  644. int arm11_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution)
  645. {
  646. FNC_INFO;
  647. // LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
  648. // current, address, handle_breakpoints, debug_execution);
  649. arm11_common_t * arm11 = target->arch_info;
  650. LOG_DEBUG("target->state: %s",
  651. target_state_name(target));
  652. if (target->state != TARGET_HALTED)
  653. {
  654. LOG_ERROR("Target not halted");
  655. return ERROR_TARGET_NOT_HALTED;
  656. }
  657. if (!current)
  658. R(PC) = address;
  659. LOG_DEBUG("RESUME PC %08" PRIx32 "%s", R(PC), !current ? "!" : "");
  660. /* clear breakpoints/watchpoints and VCR*/
  661. arm11_sc7_clear_vbw(arm11);
  662. /* Set up breakpoints */
  663. if (!debug_execution)
  664. {
  665. /* check if one matches PC and step over it if necessary */
  666. breakpoint_t * bp;
  667. for (bp = target->breakpoints; bp; bp = bp->next)
  668. {
  669. if (bp->address == R(PC))
  670. {
  671. LOG_DEBUG("must step over %08" PRIx32 "", bp->address);
  672. arm11_step(target, 1, 0, 0);
  673. break;
  674. }
  675. }
  676. /* set all breakpoints */
  677. size_t brp_num = 0;
  678. for (bp = target->breakpoints; bp; bp = bp->next)
  679. {
  680. arm11_sc7_action_t brp[2];
  681. brp[0].write = 1;
  682. brp[0].address = ARM11_SC7_BVR0 + brp_num;
  683. brp[0].value = bp->address;
  684. brp[1].write = 1;
  685. brp[1].address = ARM11_SC7_BCR0 + brp_num;
  686. brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
  687. arm11_sc7_run(arm11, brp, asizeof(brp));
  688. LOG_DEBUG("Add BP " ZU " at %08" PRIx32 "", brp_num, bp->address);
  689. brp_num++;
  690. }
  691. arm11_sc7_set_vcr(arm11, arm11_vcr);
  692. }
  693. arm11_leave_debug_state(arm11);
  694. arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
  695. CHECK_RETVAL(jtag_execute_queue());
  696. int i = 0;
  697. while (1)
  698. {
  699. uint32_t dscr;
  700. CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
  701. LOG_DEBUG("DSCR %08" PRIx32 "", dscr);
  702. if (dscr & ARM11_DSCR_CORE_RESTARTED)
  703. break;
  704. long long then = 0;
  705. if (i == 1000)
  706. {
  707. then = timeval_ms();
  708. }
  709. if (i >= 1000)
  710. {
  711. if ((timeval_ms()-then) > 1000)
  712. {
  713. LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
  714. return ERROR_FAIL;
  715. }
  716. }
  717. i++;
  718. }
  719. if (!debug_execution)
  720. {
  721. target->state = TARGET_RUNNING;
  722. target->debug_reason = DBG_REASON_NOTHALTED;
  723. CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
  724. }
  725. else
  726. {
  727. target->state = TARGET_DEBUG_RUNNING;
  728. target->debug_reason = DBG_REASON_NOTHALTED;
  729. CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
  730. }
  731. return ERROR_OK;
  732. }
  733. static int armv4_5_to_arm11(int reg)
  734. {
  735. if (reg < 16)
  736. return reg;
  737. switch (reg)
  738. {
  739. case ARMV4_5_CPSR:
  740. return ARM11_RC_CPSR;
  741. case 16:
  742. /* FIX!!! handle thumb better! */
  743. return ARM11_RC_CPSR;
  744. default:
  745. LOG_ERROR("BUG: register translation from armv4_5 to arm11 not supported %d", reg);
  746. exit(-1);
  747. }
  748. }
  749. static uint32_t arm11_sim_get_reg(struct arm_sim_interface *sim, int reg)
  750. {
  751. arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
  752. reg=armv4_5_to_arm11(reg);
  753. return buf_get_u32(arm11->reg_list[reg].value, 0, 32);
  754. }
  755. static void arm11_sim_set_reg(struct arm_sim_interface *sim, int reg, uint32_t value)
  756. {
  757. arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
  758. reg=armv4_5_to_arm11(reg);
  759. buf_set_u32(arm11->reg_list[reg].value, 0, 32, value);
  760. }
  761. static uint32_t arm11_sim_get_cpsr(struct arm_sim_interface *sim, int pos, int bits)
  762. {
  763. arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
  764. return buf_get_u32(arm11->reg_list[ARM11_RC_CPSR].value, pos, bits);
  765. }
  766. static enum armv4_5_state arm11_sim_get_state(struct arm_sim_interface *sim)
  767. {
  768. // arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
  769. /* FIX!!!! we should implement thumb for arm11 */
  770. return ARMV4_5_STATE_ARM;
  771. }
  772. static void arm11_sim_set_state(struct arm_sim_interface *sim, enum armv4_5_state mode)
  773. {
  774. // arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
  775. /* FIX!!!! we should implement thumb for arm11 */
  776. LOG_ERROR("Not implemetned!");
  777. }
  778. static enum armv4_5_mode arm11_sim_get_mode(struct arm_sim_interface *sim)
  779. {
  780. //arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
  781. /* FIX!!!! we should implement something that returns the current mode here!!! */
  782. return ARMV4_5_MODE_USR;
  783. }
  784. static int arm11_simulate_step(target_t *target, uint32_t *dry_run_pc)
  785. {
  786. struct arm_sim_interface sim;
  787. sim.user_data=target->arch_info;
  788. sim.get_reg=&arm11_sim_get_reg;
  789. sim.set_reg=&arm11_sim_set_reg;
  790. sim.get_reg_mode=&arm11_sim_get_reg;
  791. sim.set_reg_mode=&arm11_sim_set_reg;
  792. sim.get_cpsr=&arm11_sim_get_cpsr;
  793. sim.get_mode=&arm11_sim_get_mode;
  794. sim.get_state=&arm11_sim_get_state;
  795. sim.set_state=&arm11_sim_set_state;
  796. return arm_simulate_step_core(target, dry_run_pc, &sim);
  797. }
  798. int arm11_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints)
  799. {
  800. FNC_INFO;
  801. LOG_DEBUG("target->state: %s",
  802. target_state_name(target));
  803. if (target->state != TARGET_HALTED)
  804. {
  805. LOG_WARNING("target was not halted");
  806. return ERROR_TARGET_NOT_HALTED;
  807. }
  808. arm11_common_t * arm11 = target->arch_info;
  809. if (!current)
  810. R(PC) = address;
  811. LOG_DEBUG("STEP PC %08" PRIx32 "%s", R(PC), !current ? "!" : "");
  812. /** \todo TODO: Thumb not supported here */
  813. uint32_t next_instruction;
  814. CHECK_RETVAL(arm11_read_memory_word(arm11, R(PC), &next_instruction));
  815. /* skip over BKPT */
  816. if ((next_instruction & 0xFFF00070) == 0xe1200070)
  817. {
  818. R(PC) += 4;
  819. arm11->reg_list[ARM11_RC_PC].valid = 1;
  820. arm11->reg_list[ARM11_RC_PC].dirty = 0;
  821. LOG_DEBUG("Skipping BKPT");
  822. }
  823. /* skip over Wait for interrupt / Standby */
  824. /* mcr 15, 0, r?, cr7, cr0, {4} */
  825. else if ((next_instruction & 0xFFFF0FFF) == 0xee070f90)
  826. {
  827. R(PC) += 4;
  828. arm11->reg_list[ARM11_RC_PC].valid = 1;
  829. arm11->reg_list[ARM11_RC_PC].dirty = 0;
  830. LOG_DEBUG("Skipping WFI");
  831. }
  832. /* ignore B to self */
  833. else if ((next_instruction & 0xFEFFFFFF) == 0xeafffffe)
  834. {
  835. LOG_DEBUG("Not stepping jump to self");
  836. }
  837. else
  838. {
  839. /** \todo TODO: check if break-/watchpoints make any sense at all in combination
  840. * with this. */
  841. /** \todo TODO: check if disabling IRQs might be a good idea here. Alternatively
  842. * the VCR might be something worth looking into. */
  843. /* Set up breakpoint for stepping */
  844. arm11_sc7_action_t brp[2];
  845. brp[0].write = 1;
  846. brp[0].address = ARM11_SC7_BVR0;
  847. brp[1].write = 1;
  848. brp[1].address = ARM11_SC7_BCR0;
  849. if (arm11_config_hardware_step)
  850. {
  851. /* hardware single stepping be used if possible or is it better to
  852. * always use the same code path? Hardware single stepping is not supported
  853. * on all hardware
  854. */
  855. brp[0].value = R(PC);
  856. brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21);
  857. } else
  858. {
  859. /* sets a breakpoint on the next PC(calculated by simulation),
  860. */
  861. uint32_t next_pc;
  862. int retval;
  863. retval = arm11_simulate_step(target, &next_pc);
  864. if (retval != ERROR_OK)
  865. return retval;
  866. brp[0].value = next_pc;
  867. brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
  868. }
  869. CHECK_RETVAL(arm11_sc7_run(arm11, brp, asizeof(brp)));
  870. /* resume */
  871. if (arm11_config_step_irq_enable)
  872. R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE; /* should be redundant */
  873. else
  874. R(DSCR) |= ARM11_DSCR_INTERRUPTS_DISABLE;
  875. CHECK_RETVAL(arm11_leave_debug_state(arm11));
  876. arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
  877. CHECK_RETVAL(jtag_execute_queue());
  878. /* wait for halt */
  879. int i = 0;
  880. while (1)
  881. {
  882. uint32_t dscr;
  883. CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
  884. LOG_DEBUG("DSCR %08" PRIx32 "e", dscr);
  885. if ((dscr & (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED)) ==
  886. (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED))
  887. break;
  888. long long then = 0;
  889. if (i == 1000)
  890. {
  891. then = timeval_ms();
  892. }
  893. if (i >= 1000)
  894. {
  895. if ((timeval_ms()-then) > 1000)
  896. {
  897. LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
  898. return ERROR_FAIL;
  899. }
  900. }
  901. i++;
  902. }
  903. /* clear breakpoint */
  904. arm11_sc7_clear_vbw(arm11);
  905. /* save state */
  906. CHECK_RETVAL(arm11_on_enter_debug_state(arm11));
  907. /* restore default state */
  908. R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE;
  909. }
  910. // target->state = TARGET_HALTED;
  911. target->debug_reason = DBG_REASON_SINGLESTEP;
  912. CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED));
  913. return ERROR_OK;
  914. }
  915. int arm11_assert_reset(target_t *target)
  916. {
  917. FNC_INFO;
  918. /* FIX! we really should assert srst here, but
  919. * how do we reset the target into the halted state?
  920. *
  921. * Also arm11 behaves "funny" when srst is asserted
  922. * (as of writing the rules are not understood).
  923. */
  924. if (target->reset_halt)
  925. {
  926. CHECK_RETVAL(target_halt(target));
  927. }
  928. return ERROR_OK;
  929. }
  930. int arm11_deassert_reset(target_t *target)
  931. {
  932. return ERROR_OK;
  933. }
  934. int arm11_soft_reset_halt(struct target_s *target)
  935. {
  936. FNC_INFO_NOTIMPLEMENTED;
  937. return ERROR_OK;
  938. }
  939. /* target register access for gdb */
  940. int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], int *reg_list_size)
  941. {
  942. FNC_INFO;
  943. arm11_common_t * arm11 = target->arch_info;
  944. *reg_list_size = ARM11_GDB_REGISTER_COUNT;
  945. *reg_list = malloc(sizeof(reg_t*) * ARM11_GDB_REGISTER_COUNT);
  946. for (size_t i = 16; i < 24; i++)
  947. {
  948. (*reg_list)[i] = &arm11_gdb_dummy_fp_reg;
  949. }
  950. (*reg_list)[24] = &arm11_gdb_dummy_fps_reg;
  951. for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
  952. {
  953. if (arm11_reg_defs[i].gdb_num == -1)
  954. continue;
  955. (*reg_list)[arm11_reg_defs[i].gdb_num] = arm11->reg_list + i;
  956. }
  957. return ERROR_OK;
  958. }
  959. /* target memory access
  960. * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
  961. * count: number of items of <size>
  962. *
  963. * arm11_config_memrw_no_increment - in the future we may want to be able
  964. * to read/write a range of data to a "port". a "port" is an action on
  965. * read memory address for some peripheral.
  966. */
  967. int arm11_read_memory_inner(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer,
  968. bool arm11_config_memrw_no_increment)
  969. {
  970. /** \todo TODO: check if buffer cast to uint32_t* and uint16_t* might cause alignment problems */
  971. int retval;
  972. FNC_INFO;
  973. if (target->state != TARGET_HALTED)
  974. {
  975. LOG_WARNING("target was not halted");
  976. return ERROR_TARGET_NOT_HALTED;
  977. }
  978. LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32 "", address, size, count);
  979. arm11_common_t * arm11 = target->arch_info;
  980. retval = arm11_run_instr_data_prepare(arm11);
  981. if (retval != ERROR_OK)
  982. return retval;
  983. /* MRC p14,0,r0,c0,c5,0 */
  984. retval = arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
  985. if (retval != ERROR_OK)
  986. return retval;
  987. switch (size)
  988. {
  989. case 1:
  990. /** \todo TODO: check if dirty is the right choice to force a rewrite on arm11_resume() */
  991. arm11->reg_list[ARM11_RC_R1].dirty = 1;
  992. for (size_t i = 0; i < count; i++)
  993. {
  994. /* ldrb r1, [r0], #1 */
  995. /* ldrb r1, [r0] */
  996. arm11_run_instr_no_data1(arm11,
  997. !arm11_config_memrw_no_increment ? 0xe4d01001 : 0xe5d01000);
  998. uint32_t res;
  999. /* MCR p14,0,R1,c0,c5,0 */
  1000. arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
  1001. *buffer++ = res;
  1002. }
  1003. break;
  1004. case 2:
  1005. {
  1006. arm11->reg_list[ARM11_RC_R1].dirty = 1;
  1007. for (size_t i = 0; i < count; i++)
  1008. {
  1009. /* ldrh r1, [r0], #2 */
  1010. arm11_run_instr_no_data1(arm11,
  1011. !arm11_config_memrw_no_increment ? 0xe0d010b2 : 0xe1d010b0);
  1012. uint32_t res;
  1013. /* MCR p14,0,R1,c0,c5,0 */
  1014. arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
  1015. uint16_t svalue = res;
  1016. memcpy(buffer + i * sizeof(uint16_t), &svalue, sizeof(uint16_t));
  1017. }
  1018. break;
  1019. }
  1020. case 4:
  1021. {
  1022. uint32_t instr = !arm11_config_memrw_no_increment ? 0xecb05e01 : 0xed905e00;
  1023. /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
  1024. uint32_t *words = (uint32_t *)buffer;
  1025. /* LDC p14,c5,[R0],#4 */
  1026. /* LDC p14,c5,[R0] */
  1027. arm11_run_instr_data_from_core(arm11, instr, words, count);
  1028. break;
  1029. }
  1030. }
  1031. return arm11_run_instr_data_finish(arm11);
  1032. }
  1033. int arm11_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
  1034. {
  1035. return arm11_read_memory_inner(target, address, size, count, buffer, false);
  1036. }
  1037. /*
  1038. * arm11_config_memrw_no_increment - in the future we may want to be able
  1039. * to read/write a range of data to a "port". a "port" is an action on
  1040. * read memory address for some peripheral.
  1041. */
  1042. int arm11_write_memory_inner(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer,
  1043. bool arm11_config_memrw_no_increment)
  1044. {
  1045. int retval;
  1046. FNC_INFO;
  1047. if (target->state != TARGET_HALTED)
  1048. {
  1049. LOG_WARNING("target was not halted");
  1050. return ERROR_TARGET_NOT_HALTED;
  1051. }
  1052. LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32 "", address, size, count);
  1053. arm11_common_t * arm11 = target->arch_info;
  1054. retval = arm11_run_instr_data_prepare(arm11);
  1055. if (retval != ERROR_OK)
  1056. return retval;
  1057. /* MRC p14,0,r0,c0,c5,0 */
  1058. retval = arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
  1059. if (retval != ERROR_OK)
  1060. return retval;
  1061. /* burst writes are not used for single words as those may well be
  1062. * reset init script writes.
  1063. *
  1064. * The other advantage is that as burst writes are default, we'll
  1065. * now exercise both burst and non-burst code paths with the
  1066. * default settings, increasing code coverage.
  1067. */
  1068. bool burst = arm11_config_memwrite_burst && (count > 1);
  1069. switch (size)
  1070. {
  1071. case 1:
  1072. {
  1073. arm11->reg_list[ARM11_RC_R1].dirty = 1;
  1074. for (size_t i = 0; i < count; i++)
  1075. {
  1076. /* MRC p14,0,r1,c0,c5,0 */
  1077. retval = arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buffer++);
  1078. if (retval != ERROR_OK)
  1079. return retval;
  1080. /* strb r1, [r0], #1 */
  1081. /* strb r1, [r0] */
  1082. retval = arm11_run_instr_no_data1(arm11,
  1083. !arm11_config_memrw_no_increment ? 0xe4c01001 : 0xe5c01000);
  1084. if (retval != ERROR_OK)
  1085. return retval;
  1086. }
  1087. break;
  1088. }
  1089. case 2:
  1090. {
  1091. arm11->reg_list[ARM11_RC_R1].dirty = 1;
  1092. for (size_t i = 0; i < count; i++)
  1093. {
  1094. uint16_t value;
  1095. memcpy(&value, buffer + i * sizeof(uint16_t), sizeof(uint16_t));
  1096. /* MRC p14,0,r1,c0,c5,0 */
  1097. retval = arm11_run_instr_data_to_core1(arm11, 0xee101e15, value);
  1098. if (retval != ERROR_OK)
  1099. return retval;
  1100. /* strh r1, [r0], #2 */
  1101. /* strh r1, [r0] */
  1102. retval = arm11_run_instr_no_data1(arm11,
  1103. !arm11_config_memrw_no_increment ? 0xe0c010b2 : 0xe1c010b0);
  1104. if (retval != ERROR_OK)
  1105. return retval;
  1106. }
  1107. break;
  1108. }
  1109. case 4: {
  1110. uint32_t instr = !arm11_config_memrw_no_increment ? 0xeca05e01 : 0xed805e00;
  1111. /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
  1112. uint32_t *words = (uint32_t*)buffer;
  1113. if (!burst)
  1114. {
  1115. /* STC p14,c5,[R0],#4 */
  1116. /* STC p14,c5,[R0]*/
  1117. retval = arm11_run_instr_data_to_core(arm11, instr, words, count);
  1118. if (retval != ERROR_OK)
  1119. return retval;
  1120. }
  1121. else
  1122. {
  1123. /* STC p14,c5,[R0],#4 */
  1124. /* STC p14,c5,[R0]*/
  1125. retval = arm11_run_instr_data_to_core_noack(arm11, instr, words, count);
  1126. if (retval != ERROR_OK)
  1127. return retval;
  1128. }
  1129. break;
  1130. }
  1131. }
  1132. /* r0 verification */
  1133. if (!arm11_config_memrw_no_increment)
  1134. {
  1135. uint32_t r0;
  1136. /* MCR p14,0,R0,c0,c5,0 */
  1137. retval = arm11_run_instr_data_from_core(arm11, 0xEE000E15, &r0, 1);
  1138. if (retval != ERROR_OK)
  1139. return retval;
  1140. if (address + size * count != r0)
  1141. {
  1142. LOG_ERROR("Data transfer failed. Expected end "
  1143. "address 0x%08x, got 0x%08x",
  1144. (unsigned) (address + size * count),
  1145. (unsigned) r0);
  1146. if (burst)
  1147. LOG_ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode");
  1148. if (arm11_config_memwrite_error_fatal)
  1149. return ERROR_FAIL;
  1150. }
  1151. }
  1152. return arm11_run_instr_data_finish(arm11);
  1153. }
  1154. int arm11_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
  1155. {
  1156. return arm11_write_memory_inner(target, address, size, count, buffer, false);
  1157. }
  1158. /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
  1159. int arm11_bulk_write_memory(struct target_s *target, uint32_t address, uint32_t count, uint8_t *buffer)
  1160. {
  1161. FNC_INFO;
  1162. if (target->state != TARGET_HALTED)
  1163. {
  1164. LOG_WARNING("target was not halted");
  1165. return ERROR_TARGET_NOT_HALTED;
  1166. }
  1167. return arm11_write_memory(target, address, 4, count, buffer);
  1168. }
  1169. /* here we have nothing target specific to contribute, so we fail and then the
  1170. * fallback code will read data from the target and calculate the CRC on the
  1171. * host.
  1172. */
  1173. int arm11_checksum_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* checksum)
  1174. {
  1175. return ERROR_FAIL;
  1176. }
  1177. /* target break-/watchpoint control
  1178. * rw: 0 = write, 1 = read, 2 = access
  1179. */
  1180. int arm11_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
  1181. {
  1182. FNC_INFO;
  1183. arm11_common_t * arm11 = target->arch_info;
  1184. #if 0
  1185. if (breakpoint->type == BKPT_SOFT)
  1186. {
  1187. LOG_INFO("sw breakpoint requested, but software breakpoints not enabled");
  1188. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  1189. }
  1190. #endif
  1191. if (!arm11->free_brps)
  1192. {
  1193. LOG_DEBUG("no breakpoint unit available for hardware breakpoint");
  1194. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  1195. }
  1196. if (breakpoint->length != 4)
  1197. {
  1198. LOG_DEBUG("only breakpoints of four bytes length supported");
  1199. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  1200. }
  1201. arm11->free_brps--;
  1202. return ERROR_OK;
  1203. }
  1204. int arm11_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
  1205. {
  1206. FNC_INFO;
  1207. arm11_common_t * arm11 = target->arch_info;
  1208. arm11->free_brps++;
  1209. return ERROR_OK;
  1210. }
  1211. int arm11_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
  1212. {
  1213. FNC_INFO_NOTIMPLEMENTED;
  1214. return ERROR_OK;
  1215. }
  1216. int arm11_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
  1217. {
  1218. FNC_INFO_NOTIMPLEMENTED;
  1219. return ERROR_OK;
  1220. }
  1221. // HACKHACKHACK - FIXME mode/state
  1222. /* target algorithm support */
  1223. int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params,
  1224. int num_reg_params, reg_param_t *reg_params, uint32_t entry_point, uint32_t exit_point,
  1225. int timeout_ms, void *arch_info)
  1226. {
  1227. arm11_common_t *arm11 = target->arch_info;
  1228. // enum armv4_5_state core_state = arm11->core_state;
  1229. // enum armv4_5_mode core_mode = arm11->core_mode;
  1230. uint32_t context[16];
  1231. uint32_t cpsr;
  1232. int exit_breakpoint_size = 0;
  1233. int retval = ERROR_OK;
  1234. LOG_DEBUG("Running algorithm");
  1235. if (target->state != TARGET_HALTED)
  1236. {
  1237. LOG_WARNING("target not halted");
  1238. return ERROR_TARGET_NOT_HALTED;
  1239. }
  1240. // FIXME
  1241. // if (armv4_5_mode_to_number(arm11->core_mode)==-1)
  1242. // return ERROR_FAIL;
  1243. // Save regs
  1244. for (size_t i = 0; i < 16; i++)
  1245. {
  1246. context[i] = buf_get_u32((uint8_t*)(&arm11->reg_values[i]),0,32);
  1247. LOG_DEBUG("Save %zi: 0x%" PRIx32 "",i,context[i]);
  1248. }
  1249. cpsr = buf_get_u32((uint8_t*)(arm11->reg_values + ARM11_RC_CPSR),0,32);
  1250. LOG_DEBUG("Save CPSR: 0x%" PRIx32 "", cpsr);
  1251. for (int i = 0; i < num_mem_params; i++)
  1252. {
  1253. target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
  1254. }
  1255. // Set register parameters
  1256. for (int i = 0; i < num_reg_params; i++)
  1257. {
  1258. reg_t *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
  1259. if (!reg)
  1260. {
  1261. LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
  1262. exit(-1);
  1263. }
  1264. if (reg->size != reg_params[i].size)
  1265. {
  1266. LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
  1267. exit(-1);
  1268. }
  1269. arm11_set_reg(reg,reg_params[i].value);
  1270. // printf("%i: Set %s =%08x\n", i, reg_params[i].reg_name,val);
  1271. }
  1272. exit_breakpoint_size = 4;
  1273. /* arm11->core_state = arm11_algorithm_info->core_state;
  1274. if (arm11->core_state == ARMV4_5_STATE_ARM)
  1275. exit_breakpoint_size = 4;
  1276. else if (arm11->core_state == ARMV4_5_STATE_THUMB)
  1277. exit_breakpoint_size = 2;
  1278. else
  1279. {
  1280. LOG_ERROR("BUG: can't execute algorithms when not in ARM or Thumb state");
  1281. exit(-1);
  1282. }
  1283. */
  1284. /* arm11 at this point only supports ARM not THUMB mode
  1285. however if this test needs to be reactivated the current state can be read back
  1286. from CPSR */
  1287. #if 0
  1288. if (arm11_algorithm_info->core_mode != ARMV4_5_MODE_ANY)
  1289. {
  1290. LOG_DEBUG("setting core_mode: 0x%2.2x", arm11_algorithm_info->core_mode);
  1291. buf_set_u32(arm11->reg_list[ARM11_RC_CPSR].value, 0, 5, arm11_algorithm_info->core_mode);
  1292. arm11->reg_list[ARM11_RC_CPSR].dirty = 1;
  1293. arm11->reg_list[ARM11_RC_CPSR].valid = 1;
  1294. }
  1295. #endif
  1296. if ((retval = breakpoint_add(target, exit_point, exit_breakpoint_size, BKPT_HARD)) != ERROR_OK)
  1297. {
  1298. LOG_ERROR("can't add breakpoint to finish algorithm execution");
  1299. retval = ERROR_TARGET_FAILURE;
  1300. goto restore;
  1301. }
  1302. // no debug, otherwise breakpoint is not set
  1303. CHECK_RETVAL(target_resume(target, 0, entry_point, 1, 0));
  1304. CHECK_RETVAL(target_wait_state(target, TARGET_HALTED, timeout_ms));
  1305. if (target->state != TARGET_HALTED)
  1306. {
  1307. CHECK_RETVAL(target_halt(target));
  1308. CHECK_RETVAL(target_wait_state(target, TARGET_HALTED, 500));
  1309. retval = ERROR_TARGET_TIMEOUT;
  1310. goto del_breakpoint;
  1311. }
  1312. if (buf_get_u32(arm11->reg_list[15].value, 0, 32) != exit_point)
  1313. {
  1314. LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32 "",
  1315. buf_get_u32(arm11->reg_list[15].value, 0, 32));
  1316. retval = ERROR_TARGET_TIMEOUT;
  1317. goto del_breakpoint;
  1318. }
  1319. for (int i = 0; i < num_mem_params; i++)
  1320. {
  1321. if (mem_params[i].direction != PARAM_OUT)
  1322. target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
  1323. }
  1324. for (int i = 0; i < num_reg_params; i++)
  1325. {
  1326. if (reg_params[i].direction != PARAM_OUT)
  1327. {
  1328. reg_t *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
  1329. if (!reg)
  1330. {
  1331. LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
  1332. exit(-1);
  1333. }
  1334. if (reg->size != reg_params[i].size)
  1335. {
  1336. LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
  1337. exit(-1);
  1338. }
  1339. buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
  1340. }
  1341. }
  1342. del_breakpoint:
  1343. breakpoint_remove(target, exit_point);
  1344. restore:
  1345. // Restore context
  1346. for (size_t i = 0; i < 16; i++)
  1347. {
  1348. LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32 "",
  1349. arm11->reg_list[i].name, context[i]);
  1350. arm11_set_reg(&arm11->reg_list[i], (uint8_t*)&context[i]);
  1351. }
  1352. LOG_DEBUG("restoring CPSR with value 0x%8.8" PRIx32 "", cpsr);
  1353. arm11_set_reg(&arm11->reg_list[ARM11_RC_CPSR], (uint8_t*)&cpsr);
  1354. // arm11->core_state = core_state;
  1355. // arm11->core_mode = core_mode;
  1356. return retval;
  1357. }
  1358. int arm11_target_create(struct target_s *target, Jim_Interp *interp)
  1359. {
  1360. FNC_INFO;
  1361. NEW(arm11_common_t, arm11, 1);
  1362. arm11->target = target;
  1363. if (target->tap == NULL)
  1364. return ERROR_FAIL;
  1365. if (target->tap->ir_length != 5)
  1366. {
  1367. LOG_ERROR("'target arm11' expects IR LENGTH = 5");
  1368. return ERROR_COMMAND_SYNTAX_ERROR;
  1369. }
  1370. target->arch_info = arm11;
  1371. return ERROR_OK;
  1372. }
  1373. int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
  1374. {
  1375. /* Initialize anything we can set up without talking to the target */
  1376. return arm11_build_reg_cache(target);
  1377. }
  1378. /* talk to the target and set things up */
  1379. int arm11_examine(struct target_s *target)
  1380. {
  1381. int retval;
  1382. FNC_INFO;
  1383. arm11_common_t * arm11 = target->arch_info;
  1384. /* check IDCODE */
  1385. arm11_add_IR(arm11, ARM11_IDCODE, ARM11_TAP_DEFAULT);
  1386. scan_field_t idcode_field;
  1387. arm11_setup_field(arm11, 32, NULL, &arm11->device_id, &idcode_field);
  1388. arm11_add_dr_scan_vc(1, &idcode_field, TAP_DRPAUSE);
  1389. /* check DIDR */
  1390. arm11_add_debug_SCAN_N(arm11, 0x00, ARM11_TAP_DEFAULT);
  1391. arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
  1392. scan_field_t chain0_fields[2];
  1393. arm11_setup_field(arm11, 32, NULL, &arm11->didr, chain0_fields + 0);
  1394. arm11_setup_field(arm11, 8, NULL, &arm11->implementor, chain0_fields + 1);
  1395. arm11_add_dr_scan_vc(asizeof(chain0_fields), chain0_fields, TAP_IDLE);
  1396. CHECK_RETVAL(jtag_execute_queue());
  1397. switch (arm11->device_id & 0x0FFFF000)
  1398. {
  1399. case 0x07B36000: LOG_INFO("found ARM1136"); break;
  1400. case 0x07B56000: LOG_INFO("found ARM1156"); break;
  1401. case 0x07B76000: LOG_INFO("found ARM1176"); break;
  1402. default:
  1403. {
  1404. LOG_ERROR("'target arm11' expects IDCODE 0x*7B*7****");
  1405. return ERROR_FAIL;
  1406. }
  1407. }
  1408. arm11->debug_version = (arm11->didr >> 16) & 0x0F;
  1409. if (arm11->debug_version != ARM11_DEBUG_V6 &&
  1410. arm11->debug_version != ARM11_DEBUG_V61)
  1411. {
  1412. LOG_ERROR("Only ARMv6 v6 and v6.1 architectures supported.");
  1413. return ERROR_FAIL;
  1414. }
  1415. arm11->brp = ((arm11->didr >> 24) & 0x0F) + 1;
  1416. arm11->wrp = ((arm11->didr >> 28) & 0x0F) + 1;
  1417. /** \todo TODO: reserve one brp slot if we allow breakpoints during step */
  1418. arm11->free_brps = arm11->brp;
  1419. arm11->free_wrps = arm11->wrp;
  1420. LOG_DEBUG("IDCODE %08" PRIx32 " IMPLEMENTOR %02x DIDR %08" PRIx32 "",
  1421. arm11->device_id,
  1422. (int)(arm11->implementor),
  1423. arm11->didr);
  1424. /* as a side-effect this reads DSCR and thus
  1425. * clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag
  1426. * as suggested by the spec.
  1427. */
  1428. retval = arm11_check_init(arm11, NULL);
  1429. if (retval != ERROR_OK)
  1430. return retval;
  1431. target_set_examined(target);
  1432. return ERROR_OK;
  1433. }
  1434. int arm11_quit(void)
  1435. {
  1436. FNC_INFO_NOTIMPLEMENTED;
  1437. return ERROR_OK;
  1438. }
  1439. /** Load a register that is marked !valid in the register cache */
  1440. int arm11_get_reg(reg_t *reg)
  1441. {
  1442. FNC_INFO;
  1443. target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
  1444. if (target->state != TARGET_HALTED)
  1445. {
  1446. LOG_WARNING("target was not halted");
  1447. return ERROR_TARGET_NOT_HALTED;
  1448. }
  1449. /** \todo TODO: Check this. We assume that all registers are fetched at debug entry. */
  1450. #if 0
  1451. arm11_common_t *arm11 = target->arch_info;
  1452. const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
  1453. #endif
  1454. return ERROR_OK;
  1455. }
  1456. /** Change a value in the register cache */
  1457. int arm11_set_reg(reg_t *reg, uint8_t *buf)
  1458. {
  1459. FNC_INFO;
  1460. target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
  1461. arm11_common_t *arm11 = target->arch_info;
  1462. // const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
  1463. arm11->reg_values[((arm11_reg_state_t *)reg->arch_info)->def_index] = buf_get_u32(buf, 0, 32);
  1464. reg->valid = 1;
  1465. reg->dirty = 1;
  1466. return ERROR_OK;
  1467. }
  1468. int arm11_build_reg_cache(target_t *target)
  1469. {
  1470. arm11_common_t *arm11 = target->arch_info;
  1471. NEW(reg_cache_t, cache, 1);
  1472. NEW(reg_t, reg_list, ARM11_REGCACHE_COUNT);
  1473. NEW(arm11_reg_state_t, arm11_reg_states, ARM11_REGCACHE_COUNT);
  1474. if (arm11_regs_arch_type == -1)
  1475. arm11_regs_arch_type = register_reg_arch_type(arm11_get_reg, arm11_set_reg);
  1476. register_init_dummy(&arm11_gdb_dummy_fp_reg);
  1477. register_init_dummy(&arm11_gdb_dummy_fps_reg);
  1478. arm11->reg_list = reg_list;
  1479. /* Build the process context cache */
  1480. cache->name = "arm11 registers";
  1481. cache->next = NULL;
  1482. cache->reg_list = reg_list;
  1483. cache->num_regs = ARM11_REGCACHE_COUNT;
  1484. reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
  1485. (*cache_p) = cache;
  1486. arm11->core_cache = cache;
  1487. // armv7m->process_context = cache;
  1488. size_t i;
  1489. /* Not very elegant assertion */
  1490. if (ARM11_REGCACHE_COUNT != asizeof(arm11->reg_values) ||
  1491. ARM11_REGCACHE_COUNT != asizeof(arm11_reg_defs) ||
  1492. ARM11_REGCACHE_COUNT != ARM11_RC_MAX)
  1493. {
  1494. LOG_ERROR("BUG: arm11->reg_values inconsistent (%d " ZU " " ZU " %d)", ARM11_REGCACHE_COUNT, asizeof(arm11->reg_values), asizeof(arm11_reg_defs), ARM11_RC_MAX);
  1495. exit(-1);
  1496. }
  1497. for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
  1498. {
  1499. reg_t * r = reg_list + i;
  1500. const arm11_reg_defs_t * rd = arm11_reg_defs + i;
  1501. arm11_reg_state_t * rs = arm11_reg_states + i;
  1502. r->name = rd->name;
  1503. r->size = 32;
  1504. r->value = (uint8_t *)(arm11->reg_values + i);
  1505. r->dirty = 0;
  1506. r->valid = 0;
  1507. r->bitfield_desc = NULL;
  1508. r->num_bitfields = 0;
  1509. r->arch_type = arm11_regs_arch_type;
  1510. r->arch_info = rs;
  1511. rs->def_index = i;
  1512. rs->target = target;
  1513. }
  1514. return ERROR_OK;
  1515. }
  1516. int arm11_handle_bool(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool * var, char * name)
  1517. {
  1518. if (argc == 0)
  1519. {
  1520. LOG_INFO("%s is %s.", name, *var ? "enabled" : "disabled");
  1521. return ERROR_OK;
  1522. }
  1523. if (argc != 1)
  1524. return ERROR_COMMAND_SYNTAX_ERROR;
  1525. switch (args[0][0])
  1526. {
  1527. case '0': /* 0 */
  1528. case 'f': /* false */
  1529. case 'F':
  1530. case 'd': /* disable */
  1531. case 'D':
  1532. *var = false;
  1533. break;
  1534. case '1': /* 1 */
  1535. case 't': /* true */
  1536. case 'T':
  1537. case 'e': /* enable */
  1538. case 'E':
  1539. *var = true;
  1540. break;
  1541. }
  1542. LOG_INFO("%s %s.", *var ? "Enabled" : "Disabled", name);
  1543. return ERROR_OK;
  1544. }
  1545. #define BOOL_WRAPPER(name, print_name) \
  1546. int arm11_handle_bool_##name(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) \
  1547. { \
  1548. return arm11_handle_bool(cmd_ctx, cmd, args, argc, &arm11_config_##name, print_name); \
  1549. }
  1550. BOOL_WRAPPER(memwrite_burst, "memory write burst mode")
  1551. BOOL_WRAPPER(memwrite_error_fatal, "fatal error mode for memory writes")
  1552. BOOL_WRAPPER(step_irq_enable, "IRQs while stepping")
  1553. BOOL_WRAPPER(hardware_step, "hardware single step")
  1554. int arm11_handle_vcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
  1555. {
  1556. if (argc == 1)
  1557. {
  1558. arm11_vcr = strtoul(args[0], NULL, 0);
  1559. }
  1560. else if (argc != 0)
  1561. {
  1562. return ERROR_COMMAND_SYNTAX_ERROR;
  1563. }
  1564. LOG_INFO("VCR 0x%08" PRIx32 "", arm11_vcr);
  1565. return ERROR_OK;
  1566. }
  1567. const uint32_t arm11_coproc_instruction_limits[] =
  1568. {
  1569. 15, /* coprocessor */
  1570. 7, /* opcode 1 */
  1571. 15, /* CRn */
  1572. 15, /* CRm */
  1573. 7, /* opcode 2 */
  1574. 0xFFFFFFFF, /* value */
  1575. };
  1576. arm11_common_t * arm11_find_target(const char * arg)
  1577. {
  1578. jtag_tap_t * tap;
  1579. target_t * t;
  1580. tap = jtag_tap_by_string(arg);
  1581. if (!tap)
  1582. return 0;
  1583. for (t = all_targets; t; t = t->next)
  1584. {
  1585. if (t->tap != tap)
  1586. continue;
  1587. /* if (t->type == arm11_target) */
  1588. if (0 == strcmp(target_get_name(t), "arm11"))
  1589. return t->arch_info;
  1590. }
  1591. return 0;
  1592. }
  1593. int arm11_handle_mrc_mcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool read)
  1594. {
  1595. int retval;
  1596. if (argc != (read ? 6 : 7))
  1597. {
  1598. LOG_ERROR("Invalid number of arguments.");
  1599. return ERROR_COMMAND_SYNTAX_ERROR;
  1600. }
  1601. arm11_common_t * arm11 = arm11_find_target(args[0]);
  1602. if (!arm11)
  1603. {
  1604. LOG_ERROR("Parameter 1 is not a the JTAG chain position of an ARM11 device.");
  1605. return ERROR_COMMAND_SYNTAX_ERROR;
  1606. }
  1607. if (arm11->target->state != TARGET_HALTED)
  1608. {
  1609. LOG_WARNING("target was not halted");
  1610. return ERROR_TARGET_NOT_HALTED;
  1611. }
  1612. uint32_t values[6];
  1613. for (size_t i = 0; i < (read ? 5 : 6); i++)
  1614. {
  1615. values[i] = strtoul(args[i + 1], NULL, 0);
  1616. if (values[i] > arm11_coproc_instruction_limits[i])
  1617. {
  1618. LOG_ERROR("Parameter %ld out of bounds (%" PRId32 " max).",
  1619. (long)(i + 2),
  1620. arm11_coproc_instruction_limits[i]);
  1621. return ERROR_COMMAND_SYNTAX_ERROR;
  1622. }
  1623. }
  1624. uint32_t instr = 0xEE000010 |
  1625. (values[0] << 8) |
  1626. (values[1] << 21) |
  1627. (values[2] << 16) |
  1628. (values[3] << 0) |
  1629. (values[4] << 5);
  1630. if (read)
  1631. instr |= 0x00100000;
  1632. retval = arm11_run_instr_data_prepare(arm11);
  1633. if (retval != ERROR_OK)
  1634. return retval;
  1635. if (read)
  1636. {
  1637. uint32_t result;
  1638. retval = arm11_run_instr_data_from_core_via_r0(arm11, instr, &result);
  1639. if (retval != ERROR_OK)
  1640. return retval;
  1641. LOG_INFO("MRC p%d, %d, R0, c%d, c%d, %d = 0x%08" PRIx32 " (%" PRId32 ")",
  1642. (int)(values[0]),
  1643. (int)(values[1]),
  1644. (int)(values[2]),
  1645. (int)(values[3]),
  1646. (int)(values[4]), result, result);
  1647. }
  1648. else
  1649. {
  1650. retval = arm11_run_instr_data_to_core_via_r0(arm11, instr, values[5]);
  1651. if (retval != ERROR_OK)
  1652. return retval;
  1653. LOG_INFO("MRC p%d, %d, R0 (#0x%08" PRIx32 "), c%d, c%d, %d",
  1654. (int)(values[0]), (int)(values[1]),
  1655. values[5],
  1656. (int)(values[2]), (int)(values[3]), (int)(values[4]));
  1657. }
  1658. return arm11_run_instr_data_finish(arm11);
  1659. }
  1660. int arm11_handle_mrc(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
  1661. {
  1662. return arm11_handle_mrc_mcr(cmd_ctx, cmd, args, argc, true);
  1663. }
  1664. int arm11_handle_mcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
  1665. {
  1666. return arm11_handle_mrc_mcr(cmd_ctx, cmd, args, argc, false);
  1667. }
  1668. int arm11_register_commands(struct command_context_s *cmd_ctx)
  1669. {
  1670. FNC_INFO;
  1671. command_t *top_cmd, *mw_cmd;
  1672. top_cmd = register_command(cmd_ctx, NULL, "arm11",
  1673. NULL, COMMAND_ANY, NULL);
  1674. /* "hardware_step" is only here to check if the default
  1675. * simulate + breakpoint implementation is broken.
  1676. * TEMPORARY! NOT DOCUMENTED!
  1677. */
  1678. register_command(cmd_ctx, top_cmd, "hardware_step",
  1679. arm11_handle_bool_hardware_step, COMMAND_ANY,
  1680. "DEBUG ONLY - Hardware single stepping"
  1681. " (default: disabled)");
  1682. register_command(cmd_ctx, top_cmd, "mcr",
  1683. arm11_handle_mcr, COMMAND_ANY,
  1684. "Write Coprocessor register. mcr <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2> <32bit value to write>. All parameters are numbers only.");
  1685. mw_cmd = register_command(cmd_ctx, top_cmd, "memwrite",
  1686. NULL, COMMAND_ANY, NULL);
  1687. register_command(cmd_ctx, mw_cmd, "burst",
  1688. arm11_handle_bool_memwrite_burst, COMMAND_ANY,
  1689. "Enable/Disable non-standard but fast burst mode"
  1690. " (default: enabled)");
  1691. register_command(cmd_ctx, mw_cmd, "error_fatal",
  1692. arm11_handle_bool_memwrite_error_fatal, COMMAND_ANY,
  1693. "Terminate program if transfer error was found"
  1694. " (default: enabled)");
  1695. register_command(cmd_ctx, top_cmd, "mrc",
  1696. arm11_handle_mrc, COMMAND_ANY,
  1697. "Read Coprocessor register. mrc <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2>. All parameters are numbers only.");
  1698. register_command(cmd_ctx, top_cmd, "step_irq_enable",
  1699. arm11_handle_bool_step_irq_enable, COMMAND_ANY,
  1700. "Enable interrupts while stepping"
  1701. " (default: disabled)");
  1702. register_command(cmd_ctx, top_cmd, "vcr",
  1703. arm11_handle_vcr, COMMAND_ANY,
  1704. "Control (Interrupt) Vector Catch Register");
  1705. return ERROR_OK;
  1706. }