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  1. /***************************************************************************
  2. * Copyright (C) 2007, 2008 by Ben Dooks *
  3. * ben@fluff.org *
  4. * *
  5. * This program is free software; you can redistribute it and/or modify *
  6. * it under the terms of the GNU General Public License as published by *
  7. * the Free Software Foundation; either version 2 of the License, or *
  8. * (at your option) any later version. *
  9. * *
  10. * This program is distributed in the hope that it will be useful, *
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  13. * GNU General Public License for more details. *
  14. * *
  15. * You should have received a copy of the GNU General Public License *
  16. * along with this program; if not, write to the *
  17. * Free Software Foundation, Inc., *
  18. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
  19. ***************************************************************************/
  20. /*
  21. * S3C2443 OpenOCD NAND Flash controller support.
  22. *
  23. * Many thanks to Simtec Electronics for sponsoring this work.
  24. */
  25. #ifdef HAVE_CONFIG_H
  26. #include "config.h"
  27. #endif
  28. #include "replacements.h"
  29. #include "log.h"
  30. #include <stdlib.h>
  31. #include <string.h>
  32. #include "nand.h"
  33. #include "s3c24xx_nand.h"
  34. #include "target.h"
  35. int s3c2443_nand_device_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct nand_device_s *device);
  36. int s3c2443_init(struct nand_device_s *device);
  37. int s3c2443_nand_ready(struct nand_device_s *device, int timeout);
  38. nand_flash_controller_t s3c2443_nand_controller =
  39. {
  40. .name = "s3c2443",
  41. .nand_device_command = s3c2443_nand_device_command,
  42. .register_commands = s3c24xx_register_commands,
  43. .init = s3c2443_init,
  44. .reset = s3c24xx_reset,
  45. .command = s3c24xx_command,
  46. .address = s3c24xx_address,
  47. .write_data = s3c24xx_write_data,
  48. .read_data = s3c24xx_read_data,
  49. .write_page = s3c24xx_write_page,
  50. .read_page = s3c24xx_read_page,
  51. .write_block_data = s3c2440_write_block_data,
  52. .read_block_data = s3c2440_read_block_data,
  53. .controller_ready = s3c24xx_controller_ready,
  54. .nand_ready = s3c2440_nand_ready,
  55. };
  56. int s3c2443_nand_device_command(struct command_context_s *cmd_ctx, char *cmd,
  57. char **args, int argc,
  58. struct nand_device_s *device)
  59. {
  60. s3c24xx_nand_controller_t *info;
  61. info = s3c24xx_nand_device_command(cmd_ctx, cmd, args, argc, device);
  62. if (info == NULL) {
  63. return ERROR_NAND_DEVICE_INVALID;
  64. }
  65. /* fill in the address fields for the core device */
  66. info->cmd = S3C2440_NFCMD;
  67. info->addr = S3C2440_NFADDR;
  68. info->data = S3C2440_NFDATA;
  69. info->nfstat = S3C2412_NFSTAT;
  70. return ERROR_OK;
  71. }
  72. int s3c2443_init(struct nand_device_s *device)
  73. {
  74. s3c24xx_nand_controller_t *s3c24xx_info = device->controller_priv;
  75. target_t *target = s3c24xx_info->target;
  76. target_write_u32(target, S3C2410_NFCONF,
  77. S3C2440_NFCONF_TACLS(3) |
  78. S3C2440_NFCONF_TWRPH0(7) |
  79. S3C2440_NFCONF_TWRPH1(7));
  80. target_write_u32(target, S3C2440_NFCONT,
  81. S3C2412_NFCONT_INIT_MAIN_ECC |
  82. S3C2440_NFCONT_ENABLE);
  83. return ERROR_OK;
  84. }