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  1. /***************************************************************************
  2. * Copyright (C) 2007,2008 by Christopher Kilgour *
  3. * techie |_at_| whiterocker |_dot_| com *
  4. * *
  5. * This program is free software; you can redistribute it and/or modify *
  6. * it under the terms of the GNU General Public License as published by *
  7. * the Free Software Foundation; either version 2 of the License, or *
  8. * (at your option) any later version. *
  9. * *
  10. * This program is distributed in the hope that it will be useful, *
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  13. * GNU General Public License for more details. *
  14. * *
  15. * You should have received a copy of the GNU General Public License *
  16. * along with this program; if not, write to the *
  17. * Free Software Foundation, Inc., *
  18. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
  19. ***************************************************************************/
  20. #ifdef HAVE_CONFIG_H
  21. #include "config.h"
  22. #endif
  23. #include "log.h"
  24. #include "tms470.h"
  25. #include <string.h>
  26. #include <unistd.h>
  27. int tms470_register_commands(struct command_context_s *cmd_ctx);
  28. int tms470_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
  29. int tms470_erase(struct flash_bank_s *bank, int first, int last);
  30. int tms470_protect(struct flash_bank_s *bank, int set, int first, int last);
  31. int tms470_write(struct flash_bank_s *bank, u8 * buffer, u32 offset, u32 count);
  32. int tms470_probe(struct flash_bank_s *bank);
  33. int tms470_auto_probe(struct flash_bank_s *bank);
  34. int tms470_erase_check(struct flash_bank_s *bank);
  35. int tms470_protect_check(struct flash_bank_s *bank);
  36. int tms470_info(struct flash_bank_s *bank, char *buf, int buf_size);
  37. flash_driver_t tms470_flash = {
  38. .name = "tms470",
  39. .register_commands = tms470_register_commands,
  40. .flash_bank_command = tms470_flash_bank_command,
  41. .erase = tms470_erase,
  42. .protect = tms470_protect,
  43. .write = tms470_write,
  44. .probe = tms470_probe,
  45. .auto_probe = tms470_auto_probe,
  46. .erase_check = tms470_erase_check,
  47. .protect_check = tms470_protect_check,
  48. .info = tms470_info
  49. };
  50. /* ----------------------------------------------------------------------
  51. Internal Support, Helpers
  52. ---------------------------------------------------------------------- */
  53. const flash_sector_t TMS470R1A256_SECTORS[] = {
  54. {0x00000000, 0x00002000, -1, -1},
  55. {0x00002000, 0x00002000, -1, -1},
  56. {0x00004000, 0x00002000, -1, -1},
  57. {0x00006000, 0x00002000, -1, -1},
  58. {0x00008000, 0x00008000, -1, -1},
  59. {0x00010000, 0x00008000, -1, -1},
  60. {0x00018000, 0x00008000, -1, -1},
  61. {0x00020000, 0x00008000, -1, -1},
  62. {0x00028000, 0x00008000, -1, -1},
  63. {0x00030000, 0x00008000, -1, -1},
  64. {0x00038000, 0x00002000, -1, -1},
  65. {0x0003A000, 0x00002000, -1, -1},
  66. {0x0003C000, 0x00002000, -1, -1},
  67. {0x0003E000, 0x00002000, -1, -1},
  68. };
  69. #define TMS470R1A256_NUM_SECTORS \
  70. (sizeof(TMS470R1A256_SECTORS)/sizeof(TMS470R1A256_SECTORS[0]))
  71. const flash_sector_t TMS470R1A288_BANK0_SECTORS[] = {
  72. {0x00000000, 0x00002000, -1, -1},
  73. {0x00002000, 0x00002000, -1, -1},
  74. {0x00004000, 0x00002000, -1, -1},
  75. {0x00006000, 0x00002000, -1, -1},
  76. };
  77. #define TMS470R1A288_BANK0_NUM_SECTORS \
  78. (sizeof(TMS470R1A288_BANK0_SECTORS)/sizeof(TMS470R1A288_BANK0_SECTORS[0]))
  79. const flash_sector_t TMS470R1A288_BANK1_SECTORS[] = {
  80. {0x00040000, 0x00010000, -1, -1},
  81. {0x00050000, 0x00010000, -1, -1},
  82. {0x00060000, 0x00010000, -1, -1},
  83. {0x00070000, 0x00010000, -1, -1},
  84. };
  85. #define TMS470R1A288_BANK1_NUM_SECTORS \
  86. (sizeof(TMS470R1A288_BANK1_SECTORS)/sizeof(TMS470R1A288_BANK1_SECTORS[0]))
  87. /* ---------------------------------------------------------------------- */
  88. int tms470_read_part_info(struct flash_bank_s *bank)
  89. {
  90. tms470_flash_bank_t *tms470_info = bank->driver_priv;
  91. target_t *target = bank->target;
  92. u32 device_ident_reg;
  93. u32 silicon_version;
  94. u32 technology_family;
  95. u32 rom_flash;
  96. u32 part_number;
  97. char *part_name;
  98. /* we shall not rely on the caller in this test, this function allocates memory,
  99. thus and executing the code more than once may cause memory leak */
  100. if (tms470_info->device_ident_reg)
  101. return ERROR_OK;
  102. /* read and parse the device identification register */
  103. target_read_u32(target, 0xFFFFFFF0, &device_ident_reg);
  104. INFO("device_ident_reg=0x%08x", device_ident_reg);
  105. if ((device_ident_reg & 7) == 0)
  106. {
  107. WARNING("Cannot identify target as a TMS470 family.");
  108. return ERROR_FLASH_OPERATION_FAILED;
  109. }
  110. silicon_version = (device_ident_reg >> 12) & 0xF;
  111. technology_family = (device_ident_reg >> 11) & 1;
  112. rom_flash = (device_ident_reg >> 10) & 1;
  113. part_number = (device_ident_reg >> 3) & 0x7f;
  114. /*
  115. * If the part number is known, determine if the flash bank is valid
  116. * based on the base address being within the known flash bank
  117. * ranges. Then fixup/complete the remaining fields of the flash
  118. * bank structure.
  119. */
  120. switch (part_number)
  121. {
  122. case 0x0a:
  123. part_name = "TMS470R1A256";
  124. if (bank->base >= 0x00040000)
  125. {
  126. ERROR("No %s flash bank contains base address 0x%08x.", part_name, bank->base);
  127. return ERROR_FLASH_OPERATION_FAILED;
  128. }
  129. tms470_info->ordinal = 0;
  130. bank->base = 0x00000000;
  131. bank->size = 256 * 1024;
  132. bank->num_sectors = TMS470R1A256_NUM_SECTORS;
  133. bank->sectors = malloc(sizeof(TMS470R1A256_SECTORS));
  134. if (!bank->sectors)
  135. {
  136. return ERROR_FLASH_OPERATION_FAILED;
  137. }
  138. (void)memcpy(bank->sectors, TMS470R1A256_SECTORS, sizeof(TMS470R1A256_SECTORS));
  139. break;
  140. case 0x2b:
  141. part_name = "TMS470R1A288";
  142. if ((bank->base >= 0x00000000) && (bank->base < 0x00008000))
  143. {
  144. tms470_info->ordinal = 0;
  145. bank->base = 0x00000000;
  146. bank->size = 32 * 1024;
  147. bank->num_sectors = TMS470R1A288_BANK0_NUM_SECTORS;
  148. bank->sectors = malloc(sizeof(TMS470R1A288_BANK0_SECTORS));
  149. if (!bank->sectors)
  150. {
  151. return ERROR_FLASH_OPERATION_FAILED;
  152. }
  153. (void)memcpy(bank->sectors, TMS470R1A288_BANK0_SECTORS, sizeof(TMS470R1A288_BANK0_SECTORS));
  154. }
  155. else if ((bank->base >= 0x00040000) && (bank->base < 0x00080000))
  156. {
  157. tms470_info->ordinal = 1;
  158. bank->base = 0x00040000;
  159. bank->size = 256 * 1024;
  160. bank->num_sectors = TMS470R1A288_BANK1_NUM_SECTORS;
  161. bank->sectors = malloc(sizeof(TMS470R1A288_BANK1_SECTORS));
  162. if (!bank->sectors)
  163. {
  164. return ERROR_FLASH_OPERATION_FAILED;
  165. }
  166. (void)memcpy(bank->sectors, TMS470R1A288_BANK1_SECTORS, sizeof(TMS470R1A288_BANK1_SECTORS));
  167. }
  168. else
  169. {
  170. ERROR("No %s flash bank contains base address 0x%08x.", part_name, bank->base);
  171. return ERROR_FLASH_OPERATION_FAILED;
  172. }
  173. break;
  174. default:
  175. WARNING("Could not identify part 0x%02x as a member of the TMS470 family.", part_number);
  176. return ERROR_FLASH_OPERATION_FAILED;
  177. }
  178. /* turn off memory selects */
  179. target_write_u32(target, 0xFFFFFFE4, 0x00000000);
  180. target_write_u32(target, 0xFFFFFFE0, 0x00000000);
  181. bank->chip_width = 32;
  182. bank->bus_width = 32;
  183. INFO("Identified %s, ver=%d, core=%s, nvmem=%s.", part_name, silicon_version, (technology_family ? "1.8v" : "3.3v"), (rom_flash ? "rom" : "flash"));
  184. tms470_info->device_ident_reg = device_ident_reg;
  185. tms470_info->silicon_version = silicon_version;
  186. tms470_info->technology_family = technology_family;
  187. tms470_info->rom_flash = rom_flash;
  188. tms470_info->part_number = part_number;
  189. tms470_info->part_name = part_name;
  190. /*
  191. * Disable reset on address access violation.
  192. */
  193. target_write_u32(target, 0xFFFFFFE0, 0x00004007);
  194. return ERROR_OK;
  195. }
  196. /* ---------------------------------------------------------------------- */
  197. u32 keysSet = 0;
  198. u32 flashKeys[4];
  199. int tms470_handle_flash_keyset_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
  200. {
  201. if (argc > 4)
  202. {
  203. command_print(cmd_ctx, "tms470 flash_keyset <key0> <key1> <key2> <key3>");
  204. return ERROR_INVALID_ARGUMENTS;
  205. }
  206. else if (argc == 4)
  207. {
  208. int i;
  209. for (i = 0; i < 4; i++)
  210. {
  211. int start = (0 == strncmp(args[i], "0x", 2)) ? 2 : 0;
  212. if (1 != sscanf(&args[i][start], "%x", &flashKeys[i]))
  213. {
  214. command_print(cmd_ctx, "could not process flash key %s", args[i]);
  215. ERROR("could not process flash key %s", args[i]);
  216. return ERROR_INVALID_ARGUMENTS;
  217. }
  218. }
  219. keysSet = 1;
  220. }
  221. else if (argc != 0)
  222. {
  223. command_print(cmd_ctx, "tms470 flash_keyset <key0> <key1> <key2> <key3>");
  224. return ERROR_INVALID_ARGUMENTS;
  225. }
  226. if (keysSet)
  227. {
  228. command_print(cmd_ctx, "using flash keys 0x%08x, 0x%08x, 0x%08x, 0x%08x", flashKeys[0], flashKeys[1], flashKeys[2], flashKeys[3]);
  229. }
  230. else
  231. {
  232. command_print(cmd_ctx, "flash keys not set");
  233. }
  234. return ERROR_OK;
  235. }
  236. const u32 FLASH_KEYS_ALL_ONES[] = { 0xFFFFFFFF, 0xFFFFFFFF,
  237. 0xFFFFFFFF, 0xFFFFFFFF,
  238. };
  239. const u32 FLASH_KEYS_ALL_ZEROS[] = { 0x00000000, 0x00000000,
  240. 0x00000000, 0x00000000,
  241. };
  242. const u32 FLASH_KEYS_MIX1[] = { 0xf0fff0ff, 0xf0fff0ff,
  243. 0xf0fff0ff, 0xf0fff0ff
  244. };
  245. const u32 FLASH_KEYS_MIX2[] = { 0x0000ffff, 0x0000ffff,
  246. 0x0000ffff, 0x0000ffff
  247. };
  248. /* ---------------------------------------------------------------------- */
  249. int oscMHz = 12;
  250. int tms470_handle_osc_megahertz_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
  251. {
  252. if (argc > 1)
  253. {
  254. command_print(cmd_ctx, "tms470 osc_megahertz <MHz>");
  255. return ERROR_INVALID_ARGUMENTS;
  256. }
  257. else if (argc == 1)
  258. {
  259. sscanf(args[0], "%d", &oscMHz);
  260. }
  261. if (oscMHz <= 0)
  262. {
  263. ERROR("osc_megahertz must be positive and non-zero!");
  264. command_print(cmd_ctx, "osc_megahertz must be positive and non-zero!");
  265. oscMHz = 12;
  266. return ERROR_INVALID_ARGUMENTS;
  267. }
  268. command_print(cmd_ctx, "osc_megahertz=%d", oscMHz);
  269. return ERROR_OK;
  270. }
  271. /* ---------------------------------------------------------------------- */
  272. int plldis = 0;
  273. int tms470_handle_plldis_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
  274. {
  275. if (argc > 1)
  276. {
  277. command_print(cmd_ctx, "tms470 plldis <0|1>");
  278. return ERROR_INVALID_ARGUMENTS;
  279. }
  280. else if (argc == 1)
  281. {
  282. sscanf(args[0], "%d", &plldis);
  283. plldis = plldis ? 1 : 0;
  284. }
  285. command_print(cmd_ctx, "plldis=%d", plldis);
  286. return ERROR_OK;
  287. }
  288. /* ---------------------------------------------------------------------- */
  289. int tms470_check_flash_unlocked(target_t * target)
  290. {
  291. u32 fmbbusy;
  292. target_read_u32(target, 0xFFE89C08, &fmbbusy);
  293. INFO("tms470 fmbbusy=0x%08x -> %s", fmbbusy, fmbbusy & 0x8000 ? "unlocked" : "LOCKED");
  294. return fmbbusy & 0x8000 ? ERROR_OK : ERROR_FLASH_OPERATION_FAILED;
  295. }
  296. /* ---------------------------------------------------------------------- */
  297. int tms470_try_flash_keys(target_t * target, const u32 * key_set)
  298. {
  299. u32 glbctrl, fmmstat;
  300. int retval = ERROR_FLASH_OPERATION_FAILED;
  301. /* set GLBCTRL.4 */
  302. target_read_u32(target, 0xFFFFFFDC, &glbctrl);
  303. target_write_u32(target, 0xFFFFFFDC, glbctrl | 0x10);
  304. /* only perform the key match when 3VSTAT is clear */
  305. target_read_u32(target, 0xFFE8BC0C, &fmmstat);
  306. if (!(fmmstat & 0x08))
  307. {
  308. unsigned i;
  309. u32 fmbptr, fmbac2, orig_fmregopt;
  310. target_write_u32(target, 0xFFE8BC04, fmmstat & ~0x07);
  311. /* wait for pump ready */
  312. do
  313. {
  314. target_read_u32(target, 0xFFE8A814, &fmbptr);
  315. usleep(1000);
  316. }
  317. while (!(fmbptr & 0x0200));
  318. /* force max wait states */
  319. target_read_u32(target, 0xFFE88004, &fmbac2);
  320. target_write_u32(target, 0xFFE88004, fmbac2 | 0xff);
  321. /* save current access mode, force normal read mode */
  322. target_read_u32(target, 0xFFE89C00, &orig_fmregopt);
  323. target_write_u32(target, 0xFFE89C00, 0x00);
  324. for (i = 0; i < 4; i++)
  325. {
  326. u32 tmp;
  327. /* There is no point displaying the value of tmp, it is
  328. * filtered by the chip. The purpose of this read is to
  329. * prime the unlocking logic rather than read out the value.
  330. */
  331. target_read_u32(target, 0x00001FF0 + 4 * i, &tmp);
  332. INFO("tms470 writing fmpkey=0x%08x", key_set[i]);
  333. target_write_u32(target, 0xFFE89C0C, key_set[i]);
  334. }
  335. if (ERROR_OK == tms470_check_flash_unlocked(target))
  336. {
  337. /*
  338. * There seems to be a side-effect of reading the FMPKEY
  339. * register in that it re-enables the protection. So we
  340. * re-enable it.
  341. */
  342. for (i = 0; i < 4; i++)
  343. {
  344. u32 tmp;
  345. target_read_u32(target, 0x00001FF0 + 4 * i, &tmp);
  346. target_write_u32(target, 0xFFE89C0C, key_set[i]);
  347. }
  348. retval = ERROR_OK;
  349. }
  350. /* restore settings */
  351. target_write_u32(target, 0xFFE89C00, orig_fmregopt);
  352. target_write_u32(target, 0xFFE88004, fmbac2);
  353. }
  354. /* clear config bit */
  355. target_write_u32(target, 0xFFFFFFDC, glbctrl);
  356. return retval;
  357. }
  358. /* ---------------------------------------------------------------------- */
  359. int tms470_unlock_flash(struct flash_bank_s *bank)
  360. {
  361. target_t *target = bank->target;
  362. const u32 *p_key_sets[5];
  363. unsigned i, key_set_count;
  364. if (keysSet)
  365. {
  366. p_key_sets[0] = flashKeys;
  367. p_key_sets[1] = FLASH_KEYS_ALL_ONES;
  368. p_key_sets[2] = FLASH_KEYS_ALL_ZEROS;
  369. p_key_sets[3] = FLASH_KEYS_MIX1;
  370. p_key_sets[4] = FLASH_KEYS_MIX2;
  371. }
  372. else
  373. {
  374. key_set_count = 4;
  375. p_key_sets[0] = FLASH_KEYS_ALL_ONES;
  376. p_key_sets[1] = FLASH_KEYS_ALL_ZEROS;
  377. p_key_sets[2] = FLASH_KEYS_MIX1;
  378. p_key_sets[3] = FLASH_KEYS_MIX2;
  379. }
  380. for (i = 0; i < key_set_count; i++)
  381. {
  382. if (tms470_try_flash_keys(target, p_key_sets[i]) == ERROR_OK)
  383. {
  384. INFO("tms470 flash is unlocked");
  385. return ERROR_OK;
  386. }
  387. }
  388. WARNING("tms470 could not unlock flash memory protection level 2");
  389. return ERROR_FLASH_OPERATION_FAILED;
  390. }
  391. /* ---------------------------------------------------------------------- */
  392. int tms470_flash_initialize_internal_state_machine(struct flash_bank_s *bank)
  393. {
  394. u32 fmmac2, fmmac1, fmmaxep, k, delay, glbctrl, sysclk;
  395. target_t *target = bank->target;
  396. tms470_flash_bank_t *tms470_info = bank->driver_priv;
  397. int result = ERROR_OK;
  398. /*
  399. * Select the desired bank to be programmed by writing BANK[2:0] of
  400. * FMMAC2.
  401. */
  402. target_read_u32(target, 0xFFE8BC04, &fmmac2);
  403. fmmac2 &= ~0x0007;
  404. fmmac2 |= (tms470_info->ordinal & 7);
  405. target_write_u32(target, 0xFFE8BC04, fmmac2);
  406. DEBUG("set fmmac2=0x%04x", fmmac2);
  407. /*
  408. * Disable level 1 sector protection by setting bit 15 of FMMAC1.
  409. */
  410. target_read_u32(target, 0xFFE8BC00, &fmmac1);
  411. fmmac1 |= 0x8000;
  412. target_write_u32(target, 0xFFE8BC00, fmmac1);
  413. DEBUG("set fmmac1=0x%04x", fmmac1);
  414. /*
  415. * FMTCREG=0x2fc0;
  416. */
  417. target_write_u32(target, 0xFFE8BC10, 0x2fc0);
  418. DEBUG("set fmtcreg=0x2fc0");
  419. /*
  420. * MAXPP=50
  421. */
  422. target_write_u32(target, 0xFFE8A07C, 50);
  423. DEBUG("set fmmaxpp=50");
  424. /*
  425. * MAXCP=0xf000+2000
  426. */
  427. target_write_u32(target, 0xFFE8A084, 0xf000 + 2000);
  428. DEBUG("set fmmaxcp=0x%04x", 0xf000 + 2000);
  429. /*
  430. * configure VHV
  431. */
  432. target_read_u32(target, 0xFFE8A080, &fmmaxep);
  433. if (fmmaxep == 0xf000)
  434. {
  435. fmmaxep = 0xf000 + 4095;
  436. target_write_u32(target, 0xFFE8A80C, 0x9964);
  437. DEBUG("set fmptr3=0x9964");
  438. }
  439. else
  440. {
  441. fmmaxep = 0xa000 + 4095;
  442. target_write_u32(target, 0xFFE8A80C, 0x9b64);
  443. DEBUG("set fmptr3=0x9b64");
  444. }
  445. target_write_u32(target, 0xFFE8A080, fmmaxep);
  446. DEBUG("set fmmaxep=0x%04x", fmmaxep);
  447. /*
  448. * FMPTR4=0xa000
  449. */
  450. target_write_u32(target, 0xFFE8A810, 0xa000);
  451. DEBUG("set fmptr4=0xa000");
  452. /*
  453. * FMPESETUP, delay parameter selected based on clock frequency.
  454. *
  455. * According to the TI App Note SPNU257 and flashing code, delay is
  456. * int((sysclk(MHz) + 1) / 2), with a minimum of 5. The system
  457. * clock is usually derived from the ZPLL module, and selected by
  458. * the plldis global.
  459. */
  460. target_read_u32(target, 0xFFFFFFDC, &glbctrl);
  461. sysclk = (plldis ? 1 : (glbctrl & 0x08) ? 4 : 8) * oscMHz / (1 + (glbctrl & 7));
  462. delay = (sysclk > 10) ? (sysclk + 1) / 2 : 5;
  463. target_write_u32(target, 0xFFE8A018, (delay << 4) | (delay << 8));
  464. DEBUG("set fmpsetup=0x%04x", (delay << 4) | (delay << 8));
  465. /*
  466. * FMPVEVACCESS, based on delay.
  467. */
  468. k = delay | (delay << 8);
  469. target_write_u32(target, 0xFFE8A05C, k);
  470. DEBUG("set fmpvevaccess=0x%04x", k);
  471. /*
  472. * FMPCHOLD, FMPVEVHOLD, FMPVEVSETUP, based on delay.
  473. */
  474. k <<= 1;
  475. target_write_u32(target, 0xFFE8A034, k);
  476. DEBUG("set fmpchold=0x%04x", k);
  477. target_write_u32(target, 0xFFE8A040, k);
  478. DEBUG("set fmpvevhold=0x%04x", k);
  479. target_write_u32(target, 0xFFE8A024, k);
  480. DEBUG("set fmpvevsetup=0x%04x", k);
  481. /*
  482. * FMCVACCESS, based on delay.
  483. */
  484. k = delay * 16;
  485. target_write_u32(target, 0xFFE8A060, k);
  486. DEBUG("set fmcvaccess=0x%04x", k);
  487. /*
  488. * FMCSETUP, based on delay.
  489. */
  490. k = 0x3000 | delay * 20;
  491. target_write_u32(target, 0xFFE8A020, k);
  492. DEBUG("set fmcsetup=0x%04x", k);
  493. /*
  494. * FMEHOLD, based on delay.
  495. */
  496. k = (delay * 20) << 2;
  497. target_write_u32(target, 0xFFE8A038, k);
  498. DEBUG("set fmehold=0x%04x", k);
  499. /*
  500. * PWIDTH, CWIDTH, EWIDTH, based on delay.
  501. */
  502. target_write_u32(target, 0xFFE8A050, delay * 8);
  503. DEBUG("set fmpwidth=0x%04x", delay * 8);
  504. target_write_u32(target, 0xFFE8A058, delay * 1000);
  505. DEBUG("set fmcwidth=0x%04x", delay * 1000);
  506. target_write_u32(target, 0xFFE8A054, delay * 5400);
  507. DEBUG("set fmewidth=0x%04x", delay * 5400);
  508. return result;
  509. }
  510. /* ---------------------------------------------------------------------- */
  511. int tms470_flash_status(struct flash_bank_s *bank)
  512. {
  513. target_t *target = bank->target;
  514. int result = ERROR_OK;
  515. u32 fmmstat;
  516. target_read_u32(target, 0xFFE8BC0C, &fmmstat);
  517. DEBUG("set fmmstat=0x%04x", fmmstat);
  518. if (fmmstat & 0x0080)
  519. {
  520. WARNING("tms470 flash command: erase still active after busy clear.");
  521. result = ERROR_FLASH_OPERATION_FAILED;
  522. }
  523. if (fmmstat & 0x0040)
  524. {
  525. WARNING("tms470 flash command: program still active after busy clear.");
  526. result = ERROR_FLASH_OPERATION_FAILED;
  527. }
  528. if (fmmstat & 0x0020)
  529. {
  530. WARNING("tms470 flash command: invalid data command.");
  531. result = ERROR_FLASH_OPERATION_FAILED;
  532. }
  533. if (fmmstat & 0x0010)
  534. {
  535. WARNING("tms470 flash command: program, erase or validate sector failed.");
  536. result = ERROR_FLASH_OPERATION_FAILED;
  537. }
  538. if (fmmstat & 0x0008)
  539. {
  540. WARNING("tms470 flash command: voltage instability detected.");
  541. result = ERROR_FLASH_OPERATION_FAILED;
  542. }
  543. if (fmmstat & 0x0006)
  544. {
  545. WARNING("tms470 flash command: command suspend detected.");
  546. result = ERROR_FLASH_OPERATION_FAILED;
  547. }
  548. if (fmmstat & 0x0001)
  549. {
  550. WARNING("tms470 flash command: sector was locked.");
  551. result = ERROR_FLASH_OPERATION_FAILED;
  552. }
  553. return result;
  554. }
  555. /* ---------------------------------------------------------------------- */
  556. int tms470_erase_sector(struct flash_bank_s *bank, int sector)
  557. {
  558. u32 glbctrl, orig_fmregopt, fmbsea, fmbseb, fmmstat;
  559. target_t *target = bank->target;
  560. u32 flashAddr = bank->base + bank->sectors[sector].offset;
  561. int result = ERROR_OK;
  562. /*
  563. * Set the bit GLBCTRL4 of the GLBCTRL register (in the System
  564. * module) to enable writing to the flash registers }.
  565. */
  566. target_read_u32(target, 0xFFFFFFDC, &glbctrl);
  567. target_write_u32(target, 0xFFFFFFDC, glbctrl | 0x10);
  568. DEBUG("set glbctrl=0x%08x", glbctrl | 0x10);
  569. /* Force normal read mode. */
  570. target_read_u32(target, 0xFFE89C00, &orig_fmregopt);
  571. target_write_u32(target, 0xFFE89C00, 0);
  572. DEBUG("set fmregopt=0x%08x", 0);
  573. (void)tms470_flash_initialize_internal_state_machine(bank);
  574. /*
  575. * Select one or more bits in FMBSEA or FMBSEB to disable Level 1
  576. * protection for the particular sector to be erased/written.
  577. */
  578. if (sector < 16)
  579. {
  580. target_read_u32(target, 0xFFE88008, &fmbsea);
  581. target_write_u32(target, 0xFFE88008, fmbsea | (1 << sector));
  582. DEBUG("set fmbsea=0x%04x", fmbsea | (1 << sector));
  583. }
  584. else
  585. {
  586. target_read_u32(target, 0xFFE8800C, &fmbseb);
  587. target_write_u32(target, 0xFFE8800C, fmbseb | (1 << (sector - 16)));
  588. DEBUG("set fmbseb=0x%04x", fmbseb | (1 << (sector - 16)));
  589. }
  590. bank->sectors[sector].is_protected = 0;
  591. /*
  592. * clear status regiser, sent erase command, kickoff erase
  593. */
  594. target_write_u16(target, flashAddr, 0x0040);
  595. DEBUG("write *(u16 *)0x%08x=0x0040", flashAddr);
  596. target_write_u16(target, flashAddr, 0x0020);
  597. DEBUG("write *(u16 *)0x%08x=0x0020", flashAddr);
  598. target_write_u16(target, flashAddr, 0xffff);
  599. DEBUG("write *(u16 *)0x%08x=0xffff", flashAddr);
  600. /*
  601. * Monitor FMMSTAT, busy until clear, then check and other flags for
  602. * ultimate result of the operation.
  603. */
  604. do
  605. {
  606. target_read_u32(target, 0xFFE8BC0C, &fmmstat);
  607. if (fmmstat & 0x0100)
  608. {
  609. usleep(1000);
  610. }
  611. }
  612. while (fmmstat & 0x0100);
  613. result = tms470_flash_status(bank);
  614. if (sector < 16)
  615. {
  616. target_write_u32(target, 0xFFE88008, fmbsea);
  617. DEBUG("set fmbsea=0x%04x", fmbsea);
  618. bank->sectors[sector].is_protected = fmbsea & (1 << sector) ? 0 : 1;
  619. }
  620. else
  621. {
  622. target_write_u32(target, 0xFFE8800C, fmbseb);
  623. DEBUG("set fmbseb=0x%04x", fmbseb);
  624. bank->sectors[sector].is_protected = fmbseb & (1 << (sector - 16)) ? 0 : 1;
  625. }
  626. target_write_u32(target, 0xFFE89C00, orig_fmregopt);
  627. DEBUG("set fmregopt=0x%08x", orig_fmregopt);
  628. target_write_u32(target, 0xFFFFFFDC, glbctrl);
  629. DEBUG("set glbctrl=0x%08x", glbctrl);
  630. if (result == ERROR_OK)
  631. {
  632. bank->sectors[sector].is_erased = 1;
  633. }
  634. return result;
  635. }
  636. /* ----------------------------------------------------------------------
  637. Implementation of Flash Driver Interfaces
  638. ---------------------------------------------------------------------- */
  639. int tms470_register_commands(struct command_context_s *cmd_ctx)
  640. {
  641. command_t *tms470_cmd = register_command(cmd_ctx, NULL, "tms470", NULL, COMMAND_ANY, "applies to TI tms470 family");
  642. register_command(cmd_ctx, tms470_cmd, "flash_keyset", tms470_handle_flash_keyset_command, COMMAND_ANY, "tms470 flash_keyset <key0> <key1> <key2> <key3>");
  643. register_command(cmd_ctx, tms470_cmd, "osc_megahertz", tms470_handle_osc_megahertz_command, COMMAND_ANY, "tms470 osc_megahertz <MHz>");
  644. register_command(cmd_ctx, tms470_cmd, "plldis", tms470_handle_plldis_command, COMMAND_ANY, "tms470 plldis <0/1>");
  645. return ERROR_OK;
  646. }
  647. /* ---------------------------------------------------------------------- */
  648. int tms470_erase(struct flash_bank_s *bank, int first, int last)
  649. {
  650. tms470_flash_bank_t *tms470_info = bank->driver_priv;
  651. int sector, result = ERROR_OK;
  652. if (bank->target->state != TARGET_HALTED)
  653. {
  654. return ERROR_TARGET_NOT_HALTED;
  655. }
  656. tms470_read_part_info(bank);
  657. if ((first < 0) || (first >= bank->num_sectors) || (last < 0) || (last >= bank->num_sectors) || (first > last))
  658. {
  659. ERROR("Sector range %d to %d invalid.", first, last);
  660. return ERROR_FLASH_SECTOR_INVALID;
  661. }
  662. result = tms470_unlock_flash(bank);
  663. if (result != ERROR_OK)
  664. {
  665. return result;
  666. }
  667. for (sector = first; sector <= last; sector++)
  668. {
  669. INFO("Erasing tms470 bank %d sector %d...", tms470_info->ordinal, sector);
  670. result = tms470_erase_sector(bank, sector);
  671. if (result != ERROR_OK)
  672. {
  673. ERROR("tms470 could not erase flash sector.");
  674. break;
  675. }
  676. else
  677. {
  678. INFO("sector erased successfully.");
  679. }
  680. }
  681. return result;
  682. }
  683. /* ---------------------------------------------------------------------- */
  684. int tms470_protect(struct flash_bank_s *bank, int set, int first, int last)
  685. {
  686. tms470_flash_bank_t *tms470_info = bank->driver_priv;
  687. target_t *target = bank->target;
  688. u32 fmmac2, fmbsea, fmbseb;
  689. int sector;
  690. if (target->state != TARGET_HALTED)
  691. {
  692. return ERROR_TARGET_NOT_HALTED;
  693. }
  694. tms470_read_part_info(bank);
  695. if ((first < 0) || (first >= bank->num_sectors) || (last < 0) || (last >= bank->num_sectors) || (first > last))
  696. {
  697. ERROR("Sector range %d to %d invalid.", first, last);
  698. return ERROR_FLASH_SECTOR_INVALID;
  699. }
  700. /* enable the appropriate bank */
  701. target_read_u32(target, 0xFFE8BC04, &fmmac2);
  702. target_write_u32(target, 0xFFE8BC04, (fmmac2 & ~7) | tms470_info->ordinal);
  703. /* get the original sector proection flags for this bank */
  704. target_read_u32(target, 0xFFE88008, &fmbsea);
  705. target_read_u32(target, 0xFFE8800C, &fmbseb);
  706. for (sector = 0; sector < bank->num_sectors; sector++)
  707. {
  708. if (sector < 16)
  709. {
  710. fmbsea = set ? fmbsea & ~(1 << sector) : fmbsea | (1 << sector);
  711. bank->sectors[sector].is_protected = set ? 1 : 0;
  712. }
  713. else
  714. {
  715. fmbseb = set ? fmbseb & ~(1 << (sector - 16)) : fmbseb | (1 << (sector - 16));
  716. bank->sectors[sector].is_protected = set ? 1 : 0;
  717. }
  718. }
  719. /* update the protection bits */
  720. target_write_u32(target, 0xFFE88008, fmbsea);
  721. target_write_u32(target, 0xFFE8800C, fmbseb);
  722. return ERROR_OK;
  723. }
  724. /* ---------------------------------------------------------------------- */
  725. int tms470_write(struct flash_bank_s *bank, u8 * buffer, u32 offset, u32 count)
  726. {
  727. target_t *target = bank->target;
  728. tms470_flash_bank_t *tms470_info = bank->driver_priv;
  729. u32 glbctrl, fmbac2, orig_fmregopt, fmbsea, fmbseb, fmmaxpp, fmmstat;
  730. int i, result = ERROR_OK;
  731. if (target->state != TARGET_HALTED)
  732. {
  733. return ERROR_TARGET_NOT_HALTED;
  734. }
  735. tms470_read_part_info(bank);
  736. INFO("Writing %d bytes starting at 0x%08x", count, bank->base + offset);
  737. /* set GLBCTRL.4 */
  738. target_read_u32(target, 0xFFFFFFDC, &glbctrl);
  739. target_write_u32(target, 0xFFFFFFDC, glbctrl | 0x10);
  740. (void)tms470_flash_initialize_internal_state_machine(bank);
  741. /* force max wait states */
  742. target_read_u32(target, 0xFFE88004, &fmbac2);
  743. target_write_u32(target, 0xFFE88004, fmbac2 | 0xff);
  744. /* save current access mode, force normal read mode */
  745. target_read_u32(target, 0xFFE89C00, &orig_fmregopt);
  746. target_write_u32(target, 0xFFE89C00, 0x00);
  747. /*
  748. * Disable Level 1 protection for all sectors to be erased/written.
  749. */
  750. target_read_u32(target, 0xFFE88008, &fmbsea);
  751. target_write_u32(target, 0xFFE88008, 0xffff);
  752. target_read_u32(target, 0xFFE8800C, &fmbseb);
  753. target_write_u32(target, 0xFFE8800C, 0xffff);
  754. /* read MAXPP */
  755. target_read_u32(target, 0xFFE8A07C, &fmmaxpp);
  756. for (i = 0; i < count; i += 2)
  757. {
  758. u32 addr = bank->base + offset + i;
  759. u16 word = (((u16) buffer[i]) << 8) | (u16) buffer[i + 1];
  760. if (word != 0xffff)
  761. {
  762. INFO("writing 0x%04x at 0x%08x", word, addr);
  763. /* clear status register */
  764. target_write_u16(target, addr, 0x0040);
  765. /* program flash command */
  766. target_write_u16(target, addr, 0x0010);
  767. /* burn the 16-bit word (big-endian) */
  768. target_write_u16(target, addr, word);
  769. /*
  770. * Monitor FMMSTAT, busy until clear, then check and other flags
  771. * for ultimate result of the operation.
  772. */
  773. do
  774. {
  775. target_read_u32(target, 0xFFE8BC0C, &fmmstat);
  776. if (fmmstat & 0x0100)
  777. {
  778. usleep(1000);
  779. }
  780. }
  781. while (fmmstat & 0x0100);
  782. if (fmmstat & 0x3ff)
  783. {
  784. ERROR("fmstat=0x%04x", fmmstat);
  785. ERROR("Could not program word 0x%04x at address 0x%08x.", word, addr);
  786. result = ERROR_FLASH_OPERATION_FAILED;
  787. break;
  788. }
  789. }
  790. else
  791. {
  792. INFO("skipping 0xffff at 0x%08x", addr);
  793. }
  794. }
  795. /* restore */
  796. target_write_u32(target, 0xFFE88008, fmbsea);
  797. target_write_u32(target, 0xFFE8800C, fmbseb);
  798. target_write_u32(target, 0xFFE88004, fmbac2);
  799. target_write_u32(target, 0xFFE89C00, orig_fmregopt);
  800. target_write_u32(target, 0xFFFFFFDC, glbctrl);
  801. return result;
  802. }
  803. /* ---------------------------------------------------------------------- */
  804. int tms470_probe(struct flash_bank_s *bank)
  805. {
  806. if (bank->target->state != TARGET_HALTED)
  807. {
  808. WARNING("Cannot communicate... target not halted.");
  809. return ERROR_TARGET_NOT_HALTED;
  810. }
  811. return tms470_read_part_info(bank);
  812. }
  813. int tms470_auto_probe(struct flash_bank_s *bank)
  814. {
  815. tms470_flash_bank_t *tms470_info = bank->driver_priv;
  816. if (tms470_info->device_ident_reg)
  817. return ERROR_OK;
  818. return tms470_probe(bank);
  819. }
  820. /* ---------------------------------------------------------------------- */
  821. int tms470_erase_check(struct flash_bank_s *bank)
  822. {
  823. target_t *target = bank->target;
  824. tms470_flash_bank_t *tms470_info = bank->driver_priv;
  825. int sector, result = ERROR_OK;
  826. u32 fmmac2, fmbac2, glbctrl, orig_fmregopt;
  827. static u8 buffer[64 * 1024];
  828. if (target->state != TARGET_HALTED)
  829. {
  830. return ERROR_TARGET_NOT_HALTED;
  831. }
  832. if (!tms470_info->device_ident_reg)
  833. {
  834. tms470_read_part_info(bank);
  835. }
  836. /* set GLBCTRL.4 */
  837. target_read_u32(target, 0xFFFFFFDC, &glbctrl);
  838. target_write_u32(target, 0xFFFFFFDC, glbctrl | 0x10);
  839. /* save current access mode, force normal read mode */
  840. target_read_u32(target, 0xFFE89C00, &orig_fmregopt);
  841. target_write_u32(target, 0xFFE89C00, 0x00);
  842. /* enable the appropriate bank */
  843. target_read_u32(target, 0xFFE8BC04, &fmmac2);
  844. target_write_u32(target, 0xFFE8BC04, (fmmac2 & ~7) | tms470_info->ordinal);
  845. /* TCR=0 */
  846. target_write_u32(target, 0xFFE8BC10, 0x2fc0);
  847. /* clear TEZ in fmbrdy */
  848. target_write_u32(target, 0xFFE88010, 0x0b);
  849. /* save current wait states, force max */
  850. target_read_u32(target, 0xFFE88004, &fmbac2);
  851. target_write_u32(target, 0xFFE88004, fmbac2 | 0xff);
  852. /*
  853. * The TI primitives inspect the flash memory by reading one 32-bit
  854. * word at a time. Here we read an entire sector and inspect it in
  855. * an attempt to reduce the JTAG overhead.
  856. */
  857. for (sector = 0; sector < bank->num_sectors; sector++)
  858. {
  859. if (bank->sectors[sector].is_erased != 1)
  860. {
  861. u32 i, addr = bank->base + bank->sectors[sector].offset;
  862. INFO("checking flash bank %d sector %d", tms470_info->ordinal, sector);
  863. target_read_buffer(target, addr, bank->sectors[sector].size, buffer);
  864. bank->sectors[sector].is_erased = 1;
  865. for (i = 0; i < bank->sectors[sector].size; i++)
  866. {
  867. if (buffer[i] != 0xff)
  868. {
  869. WARNING("tms470 bank %d, sector %d, not erased.", tms470_info->ordinal, sector);
  870. WARNING("at location 0x%08x: flash data is 0x%02x.", addr + i, buffer[i]);
  871. bank->sectors[sector].is_erased = 0;
  872. break;
  873. }
  874. }
  875. }
  876. if (bank->sectors[sector].is_erased != 1)
  877. {
  878. result = ERROR_FLASH_SECTOR_NOT_ERASED;
  879. break;
  880. }
  881. else
  882. {
  883. INFO("sector erased");
  884. }
  885. }
  886. /* reset TEZ, wait states, read mode, GLBCTRL.4 */
  887. target_write_u32(target, 0xFFE88010, 0x0f);
  888. target_write_u32(target, 0xFFE88004, fmbac2);
  889. target_write_u32(target, 0xFFE89C00, orig_fmregopt);
  890. target_write_u32(target, 0xFFFFFFDC, glbctrl);
  891. return result;
  892. }
  893. /* ---------------------------------------------------------------------- */
  894. int tms470_protect_check(struct flash_bank_s *bank)
  895. {
  896. target_t *target = bank->target;
  897. tms470_flash_bank_t *tms470_info = bank->driver_priv;
  898. int sector, result = ERROR_OK;
  899. u32 fmmac2, fmbsea, fmbseb;
  900. if (target->state != TARGET_HALTED)
  901. {
  902. return ERROR_TARGET_NOT_HALTED;
  903. }
  904. if (!tms470_info->device_ident_reg)
  905. {
  906. tms470_read_part_info(bank);
  907. }
  908. /* enable the appropriate bank */
  909. target_read_u32(target, 0xFFE8BC04, &fmmac2);
  910. target_write_u32(target, 0xFFE8BC04, (fmmac2 & ~7) | tms470_info->ordinal);
  911. target_read_u32(target, 0xFFE88008, &fmbsea);
  912. target_read_u32(target, 0xFFE8800C, &fmbseb);
  913. for (sector = 0; sector < bank->num_sectors; sector++)
  914. {
  915. int protected;
  916. if (sector < 16)
  917. {
  918. protected = fmbsea & (1 << sector) ? 0 : 1;
  919. bank->sectors[sector].is_protected = protected;
  920. }
  921. else
  922. {
  923. protected = fmbseb & (1 << (sector - 16)) ? 0 : 1;
  924. bank->sectors[sector].is_protected = protected;
  925. }
  926. DEBUG("bank %d sector %d is %s", tms470_info->ordinal, sector, protected ? "protected" : "not protected");
  927. }
  928. return result;
  929. }
  930. /* ---------------------------------------------------------------------- */
  931. int tms470_info(struct flash_bank_s *bank, char *buf, int buf_size)
  932. {
  933. int used = 0;
  934. tms470_flash_bank_t *tms470_info = bank->driver_priv;
  935. if (!tms470_info->device_ident_reg)
  936. {
  937. tms470_read_part_info(bank);
  938. }
  939. if (!tms470_info->device_ident_reg)
  940. {
  941. (void)snprintf(buf, buf_size, "Cannot identify target as a TMS470\n");
  942. return ERROR_FLASH_OPERATION_FAILED;
  943. }
  944. used += snprintf(buf, buf_size, "\ntms470 information: Chip is %s\n", tms470_info->part_name);
  945. buf += used;
  946. buf_size -= used;
  947. used += snprintf(buf, buf_size, "Flash protection level 2 is %s\n", tms470_check_flash_unlocked(bank->target) == ERROR_OK ? "disabled" : "enabled");
  948. buf += used;
  949. buf_size -= used;
  950. return ERROR_OK;
  951. }
  952. /* ---------------------------------------------------------------------- */
  953. /*
  954. * flash bank tms470 <base> <size> <chip_width> <bus_width> <target>
  955. * [options...]
  956. */
  957. int tms470_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
  958. {
  959. bank->driver_priv = malloc(sizeof(tms470_flash_bank_t));
  960. if (!bank->driver_priv)
  961. {
  962. return ERROR_FLASH_OPERATION_FAILED;
  963. }
  964. (void)memset(bank->driver_priv, 0, sizeof(tms470_flash_bank_t));
  965. return ERROR_OK;
  966. }