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  1. /***************************************************************************
  2. * Copyright (C) 2006 by Magnus Lundin
  3. * lundin@mlu.mine.nu
  4. *
  5. * Copyright (C) 2008 by Spencer Oliver
  6. * spen@spen-soft.co.uk
  7. *
  8. * Copyright (C) 2009 by Oyvind Harboe
  9. * oyvind.harboe@zylin.com
  10. *
  11. * Copyright (C) 2009-2010 by David Brownell
  12. *
  13. * This program is free software; you can redistribute it and/or modify
  14. * it under the terms of the GNU General Public License as published by
  15. * the Free Software Foundation; either version 2 of the License, or
  16. * (at your option) any later version.
  17. *
  18. * This program is distributed in the hope that it will be useful,
  19. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21. * GNU General Public License for more details.
  22. *
  23. * You should have received a copy of the GNU General Public License
  24. * along with this program; if not, write to the
  25. * Free Software Foundation, Inc.,
  26. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  27. ***************************************************************************/
  28. /**
  29. * @file
  30. * This file implements JTAG transport support for cores implementing
  31. the ARM Debug Interface version 5 (ADIv5).
  32. */
  33. #ifdef HAVE_CONFIG_H
  34. #include "config.h"
  35. #endif
  36. #include "arm.h"
  37. #include "arm_adi_v5.h"
  38. #include <helper/time_support.h>
  39. /* JTAG instructions/registers for JTAG-DP and SWJ-DP */
  40. #define JTAG_DP_ABORT 0x8
  41. #define JTAG_DP_DPACC 0xA
  42. #define JTAG_DP_APACC 0xB
  43. #define JTAG_DP_IDCODE 0xE
  44. /* three-bit ACK values for DPACC and APACC reads */
  45. #define JTAG_ACK_OK_FAULT 0x2
  46. #define JTAG_ACK_WAIT 0x1
  47. static int jtag_ap_q_abort(struct adiv5_dap *dap, uint8_t *ack);
  48. /***************************************************************************
  49. *
  50. * DPACC and APACC scanchain access through JTAG-DP (or SWJ-DP)
  51. *
  52. ***************************************************************************/
  53. /**
  54. * Scan DPACC or APACC using target ordered uint8_t buffers. No endianness
  55. * conversions are performed. See section 4.4.3 of the ADIv5 spec, which
  56. * discusses operations which access these registers.
  57. *
  58. * Note that only one scan is performed. If RnW is set, a separate scan
  59. * will be needed to collect the data which was read; the "invalue" collects
  60. * the posted result of a preceding operation, not the current one.
  61. *
  62. * @param dap the DAP
  63. * @param instr JTAG_DP_APACC (AP access) or JTAG_DP_DPACC (DP access)
  64. * @param reg_addr two significant bits; A[3:2]; for APACC access, the
  65. * SELECT register has more addressing bits.
  66. * @param RnW false iff outvalue will be written to the DP or AP
  67. * @param outvalue points to a 32-bit (little-endian) integer
  68. * @param invalue NULL, or points to a 32-bit (little-endian) integer
  69. * @param ack points to where the three bit JTAG_ACK_* code will be stored
  70. */
  71. static int adi_jtag_dp_scan(struct adiv5_dap *dap,
  72. uint8_t instr, uint8_t reg_addr, uint8_t RnW,
  73. uint8_t *outvalue, uint8_t *invalue, uint8_t *ack)
  74. {
  75. struct arm_jtag *jtag_info = dap->jtag_info;
  76. struct scan_field fields[2];
  77. uint8_t out_addr_buf;
  78. int retval;
  79. retval = arm_jtag_set_instr(jtag_info, instr, NULL, TAP_IDLE);
  80. if (retval != ERROR_OK)
  81. return retval;
  82. /* Scan out a read or write operation using some DP or AP register.
  83. * For APACC access with any sticky error flag set, this is discarded.
  84. */
  85. fields[0].num_bits = 3;
  86. buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
  87. fields[0].out_value = &out_addr_buf;
  88. fields[0].in_value = ack;
  89. /* NOTE: if we receive JTAG_ACK_WAIT, the previous operation did not
  90. * complete; data we write is discarded, data we read is unpredictable.
  91. * When overrun detect is active, STICKYORUN is set.
  92. */
  93. fields[1].num_bits = 32;
  94. fields[1].out_value = outvalue;
  95. fields[1].in_value = invalue;
  96. jtag_add_dr_scan(jtag_info->tap, 2, fields, TAP_IDLE);
  97. /* Add specified number of tck clocks after starting memory bus
  98. * access, giving the hardware time to complete the access.
  99. * They provide more time for the (MEM) AP to complete the read ...
  100. * See "Minimum Response Time" for JTAG-DP, in the ADIv5 spec.
  101. */
  102. if ((instr == JTAG_DP_APACC)
  103. && ((reg_addr == AP_REG_DRW)
  104. || ((reg_addr & 0xF0) == AP_REG_BD0))
  105. && (dap->memaccess_tck != 0))
  106. jtag_add_runtest(dap->memaccess_tck,
  107. TAP_IDLE);
  108. return ERROR_OK;
  109. }
  110. /**
  111. * Scan DPACC or APACC out and in from host ordered uint32_t buffers.
  112. * This is exactly like adi_jtag_dp_scan(), except that endianness
  113. * conversions are performed (so the types of invalue and outvalue
  114. * must be different).
  115. */
  116. static int adi_jtag_dp_scan_u32(struct adiv5_dap *dap,
  117. uint8_t instr, uint8_t reg_addr, uint8_t RnW,
  118. uint32_t outvalue, uint32_t *invalue, uint8_t *ack)
  119. {
  120. uint8_t out_value_buf[4];
  121. int retval;
  122. buf_set_u32(out_value_buf, 0, 32, outvalue);
  123. retval = adi_jtag_dp_scan(dap, instr, reg_addr, RnW,
  124. out_value_buf, (uint8_t *)invalue, ack);
  125. if (retval != ERROR_OK)
  126. return retval;
  127. if (invalue)
  128. jtag_add_callback(arm_le_to_h_u32,
  129. (jtag_callback_data_t) invalue);
  130. return retval;
  131. }
  132. /**
  133. * Utility to write AP registers.
  134. */
  135. static inline int adi_jtag_ap_write_check(struct adiv5_dap *dap,
  136. uint8_t reg_addr, uint8_t *outvalue)
  137. {
  138. return adi_jtag_dp_scan(dap, JTAG_DP_APACC, reg_addr, DPAP_WRITE,
  139. outvalue, NULL, NULL);
  140. }
  141. static int adi_jtag_scan_inout_check_u32(struct adiv5_dap *dap,
  142. uint8_t instr, uint8_t reg_addr, uint8_t RnW,
  143. uint32_t outvalue, uint32_t *invalue)
  144. {
  145. int retval;
  146. /* Issue the read or write */
  147. retval = adi_jtag_dp_scan_u32(dap, instr, reg_addr,
  148. RnW, outvalue, NULL, NULL);
  149. if (retval != ERROR_OK)
  150. return retval;
  151. /* For reads, collect posted value; RDBUFF has no other effect.
  152. * Assumes read gets acked with OK/FAULT, and CTRL_STAT says "OK".
  153. */
  154. if ((RnW == DPAP_READ) && (invalue != NULL))
  155. retval = adi_jtag_dp_scan_u32(dap, JTAG_DP_DPACC,
  156. DP_RDBUFF, DPAP_READ, 0, invalue, &dap->ack);
  157. return retval;
  158. }
  159. static int jtagdp_transaction_endcheck(struct adiv5_dap *dap)
  160. {
  161. int retval;
  162. uint32_t ctrlstat;
  163. /* too expensive to call keep_alive() here */
  164. /* Here be dragons!
  165. *
  166. * It is easy to be in a JTAG clock range where the target
  167. * is not operating in a stable fashion. This happens
  168. * for a few reasons:
  169. *
  170. * - the user may construct a simple test case to try to see
  171. * if a higher JTAG clock works to eke out more performance.
  172. * This simple case may pass, but more complex situations can
  173. * fail.
  174. *
  175. * - The mostly works JTAG clock rate and the complete failure
  176. * JTAG clock rate may be as much as 2-4x apart. This seems
  177. * to be especially true on RC oscillator driven parts.
  178. *
  179. * So: even if calling adi_jtag_scan_inout_check_u32() multiple
  180. * times here seems to "make things better here", it is just
  181. * hiding problems with too high a JTAG clock.
  182. *
  183. * Note that even if some parts have RCLK/RTCK, that doesn't
  184. * mean that RCLK/RTCK is the *correct* rate to run the JTAG
  185. * interface at, i.e. RCLK/RTCK rates can be "too high", especially
  186. * before the RC oscillator phase is not yet complete.
  187. */
  188. /* Post CTRL/STAT read; discard any previous posted read value
  189. * but collect its ACK status.
  190. */
  191. retval = adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
  192. DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
  193. if (retval != ERROR_OK)
  194. return retval;
  195. retval = jtag_execute_queue();
  196. if (retval != ERROR_OK)
  197. return retval;
  198. dap->ack = dap->ack & 0x7;
  199. /* common code path avoids calling timeval_ms() */
  200. if (dap->ack != JTAG_ACK_OK_FAULT) {
  201. long long then = timeval_ms();
  202. while (dap->ack != JTAG_ACK_OK_FAULT) {
  203. if (dap->ack == JTAG_ACK_WAIT) {
  204. if ((timeval_ms()-then) > 1000) {
  205. LOG_WARNING("Timeout (1000ms) waiting "
  206. "for ACK=OK/FAULT "
  207. "in JTAG-DP transaction - aborting");
  208. uint8_t ack;
  209. int abort_ret = jtag_ap_q_abort(dap, &ack);
  210. if (abort_ret != 0)
  211. LOG_WARNING("Abort failed : return=%d ack=%d", abort_ret, ack);
  212. return ERROR_JTAG_DEVICE_ERROR;
  213. }
  214. } else {
  215. LOG_WARNING("Invalid ACK %#x "
  216. "in JTAG-DP transaction",
  217. dap->ack);
  218. return ERROR_JTAG_DEVICE_ERROR;
  219. }
  220. retval = adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
  221. DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
  222. if (retval != ERROR_OK)
  223. return retval;
  224. retval = jtag_execute_queue();
  225. if (retval != ERROR_OK)
  226. return retval;
  227. dap->ack = dap->ack & 0x7;
  228. }
  229. }
  230. /* REVISIT also STICKYCMP, for pushed comparisons (nyet used) */
  231. /* Check for STICKYERR and STICKYORUN */
  232. if (ctrlstat & (SSTICKYORUN | SSTICKYERR)) {
  233. LOG_DEBUG("jtag-dp: CTRL/STAT error, 0x%" PRIx32, ctrlstat);
  234. /* Check power to debug regions */
  235. if ((ctrlstat & 0xf0000000) != 0xf0000000) {
  236. retval = ahbap_debugport_init(dap);
  237. if (retval != ERROR_OK)
  238. return retval;
  239. } else {
  240. uint32_t mem_ap_csw, mem_ap_tar;
  241. /* Maybe print information about last intended
  242. * MEM-AP access; but not if autoincrementing.
  243. * *Real* CSW and TAR values are always shown.
  244. */
  245. if (dap->ap_tar_value != (uint32_t) -1)
  246. LOG_DEBUG("MEM-AP Cached values: "
  247. "ap_bank 0x%" PRIx32
  248. ", ap_csw 0x%" PRIx32
  249. ", ap_tar 0x%" PRIx32,
  250. dap->ap_bank_value,
  251. dap->ap_csw_value,
  252. dap->ap_tar_value);
  253. if (ctrlstat & SSTICKYORUN)
  254. LOG_ERROR("JTAG-DP OVERRUN - check clock, "
  255. "memaccess, or reduce jtag speed");
  256. if (ctrlstat & SSTICKYERR)
  257. LOG_ERROR("JTAG-DP STICKY ERROR");
  258. /* Clear Sticky Error Bits */
  259. retval = adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
  260. DP_CTRL_STAT, DPAP_WRITE,
  261. dap->dp_ctrl_stat | SSTICKYORUN
  262. | SSTICKYERR, NULL);
  263. if (retval != ERROR_OK)
  264. return retval;
  265. retval = adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
  266. DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
  267. if (retval != ERROR_OK)
  268. return retval;
  269. retval = jtag_execute_queue();
  270. if (retval != ERROR_OK)
  271. return retval;
  272. LOG_DEBUG("jtag-dp: CTRL/STAT 0x%" PRIx32, ctrlstat);
  273. retval = dap_queue_ap_read(dap,
  274. AP_REG_CSW, &mem_ap_csw);
  275. if (retval != ERROR_OK)
  276. return retval;
  277. retval = dap_queue_ap_read(dap,
  278. AP_REG_TAR, &mem_ap_tar);
  279. if (retval != ERROR_OK)
  280. return retval;
  281. retval = jtag_execute_queue();
  282. if (retval != ERROR_OK)
  283. return retval;
  284. LOG_ERROR("MEM_AP_CSW 0x%" PRIx32 ", MEM_AP_TAR 0x%"
  285. PRIx32, mem_ap_csw, mem_ap_tar);
  286. }
  287. retval = jtag_execute_queue();
  288. if (retval != ERROR_OK)
  289. return retval;
  290. return ERROR_JTAG_DEVICE_ERROR;
  291. }
  292. return ERROR_OK;
  293. }
  294. /*--------------------------------------------------------------------------*/
  295. static int jtag_idcode_q_read(struct adiv5_dap *dap,
  296. uint8_t *ack, uint32_t *data)
  297. {
  298. struct arm_jtag *jtag_info = dap->jtag_info;
  299. int retval;
  300. struct scan_field fields[1];
  301. /* This is a standard JTAG operation -- no DAP tweakage */
  302. retval = arm_jtag_set_instr(jtag_info, JTAG_DP_IDCODE, NULL, TAP_IDLE);
  303. if (retval != ERROR_OK)
  304. return retval;
  305. fields[0].num_bits = 32;
  306. fields[0].out_value = NULL;
  307. fields[0].in_value = (void *) data;
  308. jtag_add_dr_scan(jtag_info->tap, 1, fields, TAP_IDLE);
  309. jtag_add_callback(arm_le_to_h_u32,
  310. (jtag_callback_data_t) data);
  311. return ERROR_OK;
  312. }
  313. static int jtag_dp_q_read(struct adiv5_dap *dap, unsigned reg,
  314. uint32_t *data)
  315. {
  316. return adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
  317. reg, DPAP_READ, 0, data);
  318. }
  319. static int jtag_dp_q_write(struct adiv5_dap *dap, unsigned reg,
  320. uint32_t data)
  321. {
  322. return adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
  323. reg, DPAP_WRITE, data, NULL);
  324. }
  325. /** Select the AP register bank matching bits 7:4 of reg. */
  326. static int jtag_ap_q_bankselect(struct adiv5_dap *dap, unsigned reg)
  327. {
  328. uint32_t select_ap_bank = reg & 0x000000F0;
  329. if (select_ap_bank == dap->ap_bank_value)
  330. return ERROR_OK;
  331. dap->ap_bank_value = select_ap_bank;
  332. select_ap_bank |= dap->ap_current;
  333. return jtag_dp_q_write(dap, DP_SELECT, select_ap_bank);
  334. }
  335. static int jtag_ap_q_read(struct adiv5_dap *dap, unsigned reg,
  336. uint32_t *data)
  337. {
  338. int retval = jtag_ap_q_bankselect(dap, reg);
  339. if (retval != ERROR_OK)
  340. return retval;
  341. return adi_jtag_scan_inout_check_u32(dap, JTAG_DP_APACC, reg,
  342. DPAP_READ, 0, data);
  343. }
  344. static int jtag_ap_q_write(struct adiv5_dap *dap, unsigned reg,
  345. uint32_t data)
  346. {
  347. uint8_t out_value_buf[4];
  348. int retval = jtag_ap_q_bankselect(dap, reg);
  349. if (retval != ERROR_OK)
  350. return retval;
  351. buf_set_u32(out_value_buf, 0, 32, data);
  352. return adi_jtag_ap_write_check(dap, reg, out_value_buf);
  353. }
  354. static int jtag_ap_q_read_block(struct adiv5_dap *dap, unsigned reg,
  355. uint32_t blocksize, uint8_t *buffer)
  356. {
  357. uint32_t readcount;
  358. int retval = ERROR_OK;
  359. /* Scan out first read */
  360. retval = adi_jtag_dp_scan(dap, JTAG_DP_APACC, reg,
  361. DPAP_READ, 0, NULL, NULL);
  362. if (retval != ERROR_OK)
  363. return retval;
  364. for (readcount = 0; readcount < blocksize - 1; readcount++) {
  365. /* Scan out next read; scan in posted value for the
  366. * previous one. Assumes read is acked "OK/FAULT",
  367. * and CTRL_STAT says that meant "OK".
  368. */
  369. retval = adi_jtag_dp_scan(dap, JTAG_DP_APACC, reg,
  370. DPAP_READ, 0, buffer + 4 * readcount,
  371. &dap->ack);
  372. if (retval != ERROR_OK)
  373. return retval;
  374. }
  375. /* Scan in last posted value; RDBUFF has no other effect,
  376. * assuming ack is OK/FAULT and CTRL_STAT says "OK".
  377. */
  378. retval = adi_jtag_dp_scan(dap, JTAG_DP_DPACC, DP_RDBUFF,
  379. DPAP_READ, 0, buffer + 4 * readcount,
  380. &dap->ack);
  381. return retval;
  382. }
  383. static int jtag_ap_q_abort(struct adiv5_dap *dap, uint8_t *ack)
  384. {
  385. /* for JTAG, this is the only valid ABORT register operation */
  386. return adi_jtag_dp_scan_u32(dap, JTAG_DP_ABORT,
  387. 0, DPAP_WRITE, 1, NULL, ack);
  388. }
  389. static int jtag_dp_run(struct adiv5_dap *dap)
  390. {
  391. return jtagdp_transaction_endcheck(dap);
  392. }
  393. /* FIXME don't export ... just initialize as
  394. * part of DAP setup
  395. */
  396. const struct dap_ops jtag_dp_ops = {
  397. .queue_idcode_read = jtag_idcode_q_read,
  398. .queue_dp_read = jtag_dp_q_read,
  399. .queue_dp_write = jtag_dp_q_write,
  400. .queue_ap_read = jtag_ap_q_read,
  401. .queue_ap_write = jtag_ap_q_write,
  402. .queue_ap_read_block = jtag_ap_q_read_block,
  403. .queue_ap_abort = jtag_ap_q_abort,
  404. .run = jtag_dp_run,
  405. };
  406. static const uint8_t swd2jtag_bitseq[] = {
  407. /* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
  408. * putting both JTAG and SWD logic into reset state.
  409. */
  410. 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
  411. /* Switching equence disables SWD and enables JTAG
  412. * NOTE: bits in the DP's IDCODE can expose the need for
  413. * the old/deprecated sequence (0xae 0xde).
  414. */
  415. 0x3c, 0xe7,
  416. /* At least 50 TCK/SWCLK cycles with TMS/SWDIO high,
  417. * putting both JTAG and SWD logic into reset state.
  418. * NOTE: some docs say "at least 5".
  419. */
  420. 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
  421. };
  422. /** Put the debug link into JTAG mode, if the target supports it.
  423. * The link's initial mode may be either SWD or JTAG.
  424. *
  425. * @param target Enters JTAG mode (if possible).
  426. *
  427. * Note that targets implemented with SW-DP do not support JTAG, and
  428. * that some targets which could otherwise support it may have been
  429. * configured to disable JTAG signaling
  430. *
  431. * @return ERROR_OK or else a fault code.
  432. */
  433. int dap_to_jtag(struct target *target)
  434. {
  435. int retval;
  436. LOG_DEBUG("Enter JTAG mode");
  437. /* REVISIT it's nasty to need to make calls to a "jtag"
  438. * subsystem if the link isn't in JTAG mode...
  439. */
  440. retval = jtag_add_tms_seq(8 * sizeof(swd2jtag_bitseq),
  441. swd2jtag_bitseq, TAP_RESET);
  442. if (retval == ERROR_OK)
  443. retval = jtag_execute_queue();
  444. /* REVISIT set up the DAP's ops vector for JTAG mode. */
  445. return retval;
  446. }