On XScale architecture, to write debug control register DCSR
and activate JTAG debug (ie. to choose Halt Mode), the
enabling can only be done while the board is held in reset
state (ie. PXAxx #RST line held low).
The current implementation writes to the register before
asserting the SRST line. Swap the order to activate the SRST
line before writing to DCSR.
Signed-off-by: Robert Jarzmik <firstname.lastname@example.org>
Reviewed-by: Marek Vasut <email@example.com>
Reviewed-by: Spencer Oliver <firstname.lastname@example.org>