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  1. /***************************************************************************
  2. * Copyright (C) 2008 by Spencer Oliver *
  3. * spen@spen-soft.co.uk *
  4. * *
  5. * Copyright (C) 2008 by David T.L. Wong *
  6. * *
  7. * This program is free software; you can redistribute it and/or modify *
  8. * it under the terms of the GNU General Public License as published by *
  9. * the Free Software Foundation; either version 2 of the License, or *
  10. * (at your option) any later version. *
  11. * *
  12. * This program is distributed in the hope that it will be useful, *
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  15. * GNU General Public License for more details. *
  16. * *
  17. * You should have received a copy of the GNU General Public License *
  18. * along with this program; if not, write to the *
  19. * Free Software Foundation, Inc., *
  20. * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
  21. ***************************************************************************/
  22. #ifndef MIPS_EJTAG
  23. #define MIPS_EJTAG
  24. #include <jtag/jtag.h>
  25. /* tap instructions */
  26. #define EJTAG_INST_IDCODE 0x01
  27. #define EJTAG_INST_IMPCODE 0x03
  28. #define EJTAG_INST_ADDRESS 0x08
  29. #define EJTAG_INST_DATA 0x09
  30. #define EJTAG_INST_CONTROL 0x0A
  31. #define EJTAG_INST_ALL 0x0B
  32. #define EJTAG_INST_EJTAGBOOT 0x0C
  33. #define EJTAG_INST_NORMALBOOT 0x0D
  34. #define EJTAG_INST_FASTDATA 0x0E
  35. #define EJTAG_INST_TCBCONTROLA 0x10
  36. #define EJTAG_INST_TCBCONTROLB 0x11
  37. #define EJTAG_INST_TCBDATA 0x12
  38. #define EJTAG_INST_BYPASS 0xFF
  39. /* microchip PIC32MX specific instructions */
  40. #define MTAP_SW_MTAP 0x04
  41. #define MTAP_SW_ETAP 0x05
  42. #define MTAP_COMMAND 0x07
  43. /* microchip specific cmds */
  44. #define MCHP_ASERT_RST 0xd1
  45. #define MCHP_DE_ASSERT_RST 0xd0
  46. #define MCHP_ERASE 0xfc
  47. #define MCHP_STATUS 0x00
  48. /* ejtag control register bits ECR */
  49. #define EJTAG_CTRL_TOF (1 << 1)
  50. #define EJTAG_CTRL_TIF (1 << 2)
  51. #define EJTAG_CTRL_BRKST (1 << 3)
  52. #define EJTAG_CTRL_DLOCK (1 << 5)
  53. #define EJTAG_CTRL_DRWN (1 << 9)
  54. #define EJTAG_CTRL_DERR (1 << 10)
  55. #define EJTAG_CTRL_DSTRT (1 << 11)
  56. #define EJTAG_CTRL_JTAGBRK (1 << 12)
  57. #define EJTAG_CTRL_SETDEV (1 << 14)
  58. #define EJTAG_CTRL_PROBEN (1 << 15)
  59. #define EJTAG_CTRL_PRRST (1 << 16)
  60. #define EJTAG_CTRL_DMAACC (1 << 17)
  61. #define EJTAG_CTRL_PRACC (1 << 18)
  62. #define EJTAG_CTRL_PRNW (1 << 19)
  63. #define EJTAG_CTRL_PERRST (1 << 20)
  64. #define EJTAG_CTRL_SYNC (1 << 23)
  65. #define EJTAG_CTRL_DNM (1 << 28)
  66. #define EJTAG_CTRL_ROCC (1 << 31)
  67. /* Debug Register (CP0 Register 23, Select 0) */
  68. #define EJTAG_DEBUG_DSS (1 << 0)
  69. #define EJTAG_DEBUG_DBP (1 << 1)
  70. #define EJTAG_DEBUG_DDBL (1 << 2)
  71. #define EJTAG_DEBUG_DDBS (1 << 3)
  72. #define EJTAG_DEBUG_DIB (1 << 4)
  73. #define EJTAG_DEBUG_DINT (1 << 5)
  74. #define EJTAG_DEBUG_OFFLINE (1 << 7)
  75. #define EJTAG_DEBUG_SST (1 << 8)
  76. #define EJTAG_DEBUG_NOSST (1 << 9)
  77. #define EJTAG_DEBUG_DDBLIMPR (1 << 18)
  78. #define EJTAG_DEBUG_DDBSIMPR (1 << 19)
  79. #define EJTAG_DEBUG_IEXI (1 << 20)
  80. #define EJTAG_DEBUG_DBUSEP (1 << 21)
  81. #define EJTAG_DEBUG_CACHEEP (1 << 22)
  82. #define EJTAG_DEBUG_MCHECKP (1 << 23)
  83. #define EJTAG_DEBUG_IBUSEP (1 << 24)
  84. #define EJTAG_DEBUG_COUNTDM (1 << 25)
  85. #define EJTAG_DEBUG_HALT (1 << 26)
  86. #define EJTAG_DEBUG_DOZE (1 << 27)
  87. #define EJTAG_DEBUG_LSNM (1 << 28)
  88. #define EJTAG_DEBUG_NODCR (1 << 29)
  89. #define EJTAG_DEBUG_DM (1 << 30)
  90. #define EJTAG_DEBUG_DBD (1 << 31)
  91. /* implementation MIPS register bits.
  92. * Bits marked with V20 or v2.0 mean that, this registers supported only
  93. * by EJTAG v2.0. Bits marked with Lexra or BMIPS are different from the
  94. * official EJATG.
  95. * NOTE: Lexra or BMIPS use EJTAG v2.0 */
  96. #define EJTAG_IMP_HAS(x) (ejtag_info->impcode & (x))
  97. /* v2.0(Lexra) 29 - 1’b1 - Lexra Internal Trace Buffer implemented. This bit
  98. * overlaps with version bit of MIPS EJTAG specification. */
  99. #define EJTAG_V26_IMP_R3K (1 << 28)
  100. /* v2.0 - 24:25 - 2’b00- No profiling support */
  101. #define EJTAG_V26_IMP_DINT (1 << 24)
  102. #define EJTAG_V20_IMP_SDBBP (1 << 23) /* 1’b1 - sdbbp is Special2 Opcode */
  103. #define EJTAG_IMP_ASID8 (1 << 22)
  104. #define EJTAG_IMP_ASID6 (1 << 21)
  105. #define EJTAG_V20_IMP_COMPLEX_BREAK (1 << 20) /* Complex Breaks supported*/
  106. #define EJTAG_V20_IMP_EADDR_NO32BIT (1 << 19) /* EJTAG_ADDR > 32 bits wide */
  107. #define EJTAG_V20_IMP_DCACHE_COH (1 << 18) /* DCache does keep DMA coherent */
  108. #define EJTAG_V20_IMP_ICACHE_COH (1 << 17) /* DCache does keep DMA coherent */
  109. #define EJTAG_IMP_MIPS16 (1 << 16)
  110. #define EJTAG_IMP_NODMA (1 << 14)
  111. /* v2.0 - 11:13 external PC trace. Trace PC Width. */
  112. /* v2.0 - 8:10 external PC trace. PCST Width and DCLK Division Factor */
  113. #define EJTAG_V20_IMP_NOPB (1 << 7) /* no processor breaks */
  114. #define EJTAG_V20_IMP_NODB (1 << 6) /* no data breaks */
  115. #define EJTAG_V20_IMP_NOIB (1 << 5) /* no instruction breaks implemented */
  116. /* v2.0 - 1:4 Number of Break Channels. */
  117. #define EJTAG_V20_IMP_BCHANNELS_MASK 0xf
  118. #define EJTAG_V20_IMP_BCHANNELS_SHIFT 1
  119. #define EJTAG_DCR_MIPS64 (1 << 0)
  120. /* Debug Control Register DCR */
  121. #define EJTAG_DCR 0xFF300000
  122. #define EJTAG_DCR_ENM (1 << 29)
  123. #define EJTAG_DCR_DB (1 << 17)
  124. #define EJTAG_DCR_IB (1 << 16)
  125. #define EJTAG_DCR_INTE (1 << 4)
  126. #define EJTAG_DCR_MP (1 << 2)
  127. /* breakpoint support */
  128. /* EJTAG_V20_* was tested on Broadcom BCM7401
  129. * and may or will differ with other hardware. For example EZ4021-FC. */
  130. #define EJTAG_V20_IBS 0xFF300004
  131. #define EJTAG_V20_IBA0 0xFF300100
  132. #define EJTAG_V20_IBC_OFFS 0x4 /* IBC Offset */
  133. #define EJTAG_V20_IBM_OFFS 0x8
  134. #define EJTAG_V20_IBAn_STEP 0x10 /* Offset for next channel */
  135. #define EJTAG_V20_DBS 0xFF300008
  136. #define EJTAG_V20_DBA0 0xFF300200
  137. #define EJTAG_V20_DBC_OFFS 0x4
  138. #define EJTAG_V20_DBM_OFFS 0x8
  139. #define EJTAG_V20_DBV_OFFS 0xc
  140. #define EJTAG_V20_DBAn_STEP 0x10
  141. #define EJTAG_V25_IBS 0xFF301000
  142. #define EJTAG_V25_IBA0 0xFF301100
  143. #define EJTAG_V25_IBM_OFFS 0x8
  144. #define EJTAG_V25_IBASID_OFFS 0x10
  145. #define EJTAG_V25_IBC_OFFS 0x18
  146. #define EJTAG_V25_IBAn_STEP 0x100
  147. #define EJTAG_V25_DBS 0xFF302000
  148. #define EJTAG_V25_DBA0 0xFF302100
  149. #define EJTAG_V25_DBM_OFFS 0x8
  150. #define EJTAG_V25_DBASID_OFFS 0x10
  151. #define EJTAG_V25_DBC_OFFS 0x18
  152. #define EJTAG_V25_DBV_OFFS 0x20
  153. #define EJTAG_V25_DBAn_STEP 0x100
  154. #define EJTAG_DBCn_NOSB (1 << 13)
  155. #define EJTAG_DBCn_NOLB (1 << 12)
  156. #define EJTAG_DBCn_BLM_MASK 0xff
  157. #define EJTAG_DBCn_BLM_SHIFT 4
  158. #define EJTAG_DBCn_BE (1 << 0)
  159. #define EJTAG_VERSION_20 0
  160. #define EJTAG_VERSION_25 1
  161. #define EJTAG_VERSION_26 2
  162. #define EJTAG_VERSION_31 3
  163. #define EJTAG_VERSION_41 4
  164. #define EJTAG_VERSION_51 5
  165. struct mips_ejtag {
  166. struct jtag_tap *tap;
  167. uint32_t impcode;
  168. uint32_t idcode;
  169. uint32_t ejtag_ctrl;
  170. int fast_access_save;
  171. uint32_t reg8;
  172. uint32_t reg9;
  173. unsigned scan_delay;
  174. int mode;
  175. uint32_t pa_ctrl;
  176. uint32_t pa_addr;
  177. unsigned int ejtag_version;
  178. /* Memory-Mapped Registers. This addresses are not same on different
  179. * EJTAG versions. */
  180. uint32_t debug_caps;
  181. uint32_t ejtag_ibs_addr; /* Instruction Address Break Status */
  182. uint32_t ejtag_iba0_addr; /* IAB channel 0 */
  183. uint32_t ejtag_ibc_offs; /* IAB Control offset */
  184. uint32_t ejtag_ibm_offs; /* IAB Mask offset */
  185. uint32_t ejtag_ibasid_offs; /* IAB ASID (4Kc) */
  186. uint32_t ejtag_dbs_addr; /* Data Address Break Status Register */
  187. uint32_t ejtag_dba0_addr; /* DAB channel 0 */
  188. uint32_t ejtag_dbc_offs; /* DAB Control offset */
  189. uint32_t ejtag_dbm_offs; /* DAB Mask offset */
  190. uint32_t ejtag_dbv_offs; /* DAB Value offset */
  191. uint32_t ejtag_dbasid_offs; /* DAB ASID (4Kc) */
  192. uint32_t ejtag_iba_step_size;
  193. uint32_t ejtag_dba_step_size; /* size of step till next *DBAn register. */
  194. };
  195. void mips_ejtag_set_instr(struct mips_ejtag *ejtag_info,
  196. int new_instr);
  197. int mips_ejtag_enter_debug(struct mips_ejtag *ejtag_info);
  198. int mips_ejtag_exit_debug(struct mips_ejtag *ejtag_info);
  199. int mips_ejtag_get_idcode(struct mips_ejtag *ejtag_info, uint32_t *idcode);
  200. void mips_ejtag_add_scan_96(struct mips_ejtag *ejtag_info,
  201. uint32_t ctrl, uint32_t data, uint8_t *in_scan_buf);
  202. void mips_ejtag_drscan_32_out(struct mips_ejtag *ejtag_info, uint32_t data);
  203. int mips_ejtag_drscan_32(struct mips_ejtag *ejtag_info, uint32_t *data);
  204. void mips_ejtag_drscan_8_out(struct mips_ejtag *ejtag_info, uint8_t data);
  205. int mips_ejtag_drscan_8(struct mips_ejtag *ejtag_info, uint32_t *data);
  206. int mips_ejtag_fastdata_scan(struct mips_ejtag *ejtag_info, int write_t, uint32_t *data);
  207. int mips_ejtag_init(struct mips_ejtag *ejtag_info);
  208. int mips_ejtag_config_step(struct mips_ejtag *ejtag_info, int enable_step);
  209. static inline void mips_le_to_h_u32(jtag_callback_data_t arg)
  210. {
  211. uint8_t *in = (uint8_t *)arg;
  212. *((uint32_t *)arg) = le_to_h_u32(in);
  213. }
  214. #endif /* MIPS_EJTAG */