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  1. /***************************************************************************
  2. * Copyright (C) 2008 by Spencer Oliver *
  3. * spen@spen-soft.co.uk *
  4. * *
  5. * Copyright (C) 2008 by David T.L. Wong *
  6. * *
  7. * Copyright (C) 2009 by David N. Claffey <dnclaffey@gmail.com> *
  8. * *
  9. * Copyright (C) 2011 by Drasko DRASKOVIC *
  10. * drasko.draskovic@gmail.com *
  11. * *
  12. * This program is free software; you can redistribute it and/or modify *
  13. * it under the terms of the GNU General Public License as published by *
  14. * the Free Software Foundation; either version 2 of the License, or *
  15. * (at your option) any later version. *
  16. * *
  17. * This program is distributed in the hope that it will be useful, *
  18. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  19. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  20. * GNU General Public License for more details. *
  21. * *
  22. * You should have received a copy of the GNU General Public License *
  23. * along with this program; if not, write to the *
  24. * Free Software Foundation, Inc., *
  25. * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
  26. ***************************************************************************/
  27. #ifdef HAVE_CONFIG_H
  28. #include "config.h"
  29. #endif
  30. #include "breakpoints.h"
  31. #include "mips32.h"
  32. #include "mips_m4k.h"
  33. #include "mips32_dmaacc.h"
  34. #include "target_type.h"
  35. #include "register.h"
  36. static void mips_m4k_enable_breakpoints(struct target *target);
  37. static void mips_m4k_enable_watchpoints(struct target *target);
  38. static int mips_m4k_set_breakpoint(struct target *target,
  39. struct breakpoint *breakpoint);
  40. static int mips_m4k_unset_breakpoint(struct target *target,
  41. struct breakpoint *breakpoint);
  42. static int mips_m4k_internal_restore(struct target *target, int current,
  43. uint32_t address, int handle_breakpoints,
  44. int debug_execution);
  45. static int mips_m4k_halt(struct target *target);
  46. static int mips_m4k_bulk_write_memory(struct target *target, uint32_t address,
  47. uint32_t count, const uint8_t *buffer);
  48. static int mips_m4k_examine_debug_reason(struct target *target)
  49. {
  50. struct mips32_common *mips32 = target_to_mips32(target);
  51. struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
  52. uint32_t break_status;
  53. int retval;
  54. if ((target->debug_reason != DBG_REASON_DBGRQ)
  55. && (target->debug_reason != DBG_REASON_SINGLESTEP)) {
  56. if (ejtag_info->debug_caps & EJTAG_DCR_IB) {
  57. /* get info about inst breakpoint support */
  58. retval = target_read_u32(target,
  59. ejtag_info->ejtag_ibs_addr, &break_status);
  60. if (retval != ERROR_OK)
  61. return retval;
  62. if (break_status & 0x1f) {
  63. /* we have halted on a breakpoint */
  64. retval = target_write_u32(target,
  65. ejtag_info->ejtag_ibs_addr, 0);
  66. if (retval != ERROR_OK)
  67. return retval;
  68. target->debug_reason = DBG_REASON_BREAKPOINT;
  69. }
  70. }
  71. if (ejtag_info->debug_caps & EJTAG_DCR_DB) {
  72. /* get info about data breakpoint support */
  73. retval = target_read_u32(target,
  74. ejtag_info->ejtag_dbs_addr, &break_status);
  75. if (retval != ERROR_OK)
  76. return retval;
  77. if (break_status & 0x1f) {
  78. /* we have halted on a breakpoint */
  79. retval = target_write_u32(target,
  80. ejtag_info->ejtag_dbs_addr, 0);
  81. if (retval != ERROR_OK)
  82. return retval;
  83. target->debug_reason = DBG_REASON_WATCHPOINT;
  84. }
  85. }
  86. }
  87. return ERROR_OK;
  88. }
  89. static int mips_m4k_debug_entry(struct target *target)
  90. {
  91. struct mips32_common *mips32 = target_to_mips32(target);
  92. struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
  93. mips32_save_context(target);
  94. /* make sure stepping disabled, SSt bit in CP0 debug register cleared */
  95. mips_ejtag_config_step(ejtag_info, 0);
  96. /* make sure break unit configured */
  97. mips32_configure_break_unit(target);
  98. /* attempt to find halt reason */
  99. mips_m4k_examine_debug_reason(target);
  100. /* default to mips32 isa, it will be changed below if required */
  101. mips32->isa_mode = MIPS32_ISA_MIPS32;
  102. if (ejtag_info->impcode & EJTAG_IMP_MIPS16)
  103. mips32->isa_mode = buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 1);
  104. LOG_DEBUG("entered debug state at PC 0x%" PRIx32 ", target->state: %s",
  105. buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32),
  106. target_state_name(target));
  107. return ERROR_OK;
  108. }
  109. static struct target *get_mips_m4k(struct target *target, int32_t coreid)
  110. {
  111. struct target_list *head;
  112. struct target *curr;
  113. head = target->head;
  114. while (head != (struct target_list *)NULL) {
  115. curr = head->target;
  116. if ((curr->coreid == coreid) && (curr->state == TARGET_HALTED))
  117. return curr;
  118. head = head->next;
  119. }
  120. return target;
  121. }
  122. static int mips_m4k_halt_smp(struct target *target)
  123. {
  124. int retval = ERROR_OK;
  125. struct target_list *head;
  126. struct target *curr;
  127. head = target->head;
  128. while (head != (struct target_list *)NULL) {
  129. int ret = ERROR_OK;
  130. curr = head->target;
  131. if ((curr != target) && (curr->state != TARGET_HALTED))
  132. ret = mips_m4k_halt(curr);
  133. if (ret != ERROR_OK) {
  134. LOG_ERROR("halt failed target->coreid: %" PRId32, curr->coreid);
  135. retval = ret;
  136. }
  137. head = head->next;
  138. }
  139. return retval;
  140. }
  141. static int update_halt_gdb(struct target *target)
  142. {
  143. int retval = ERROR_OK;
  144. if (target->gdb_service->core[0] == -1) {
  145. target->gdb_service->target = target;
  146. target->gdb_service->core[0] = target->coreid;
  147. retval = mips_m4k_halt_smp(target);
  148. }
  149. return retval;
  150. }
  151. static int mips_m4k_poll(struct target *target)
  152. {
  153. int retval = ERROR_OK;
  154. struct mips32_common *mips32 = target_to_mips32(target);
  155. struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
  156. uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl;
  157. enum target_state prev_target_state = target->state;
  158. /* toggle to another core is done by gdb as follow */
  159. /* maint packet J core_id */
  160. /* continue */
  161. /* the next polling trigger an halt event sent to gdb */
  162. if ((target->state == TARGET_HALTED) && (target->smp) &&
  163. (target->gdb_service) &&
  164. (target->gdb_service->target == NULL)) {
  165. target->gdb_service->target =
  166. get_mips_m4k(target, target->gdb_service->core[1]);
  167. target_call_event_callbacks(target, TARGET_EVENT_HALTED);
  168. return retval;
  169. }
  170. /* read ejtag control reg */
  171. mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
  172. retval = mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
  173. if (retval != ERROR_OK)
  174. return retval;
  175. /* clear this bit before handling polling
  176. * as after reset registers will read zero */
  177. if (ejtag_ctrl & EJTAG_CTRL_ROCC) {
  178. /* we have detected a reset, clear flag
  179. * otherwise ejtag will not work */
  180. ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_ROCC;
  181. mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
  182. retval = mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
  183. if (retval != ERROR_OK)
  184. return retval;
  185. LOG_DEBUG("Reset Detected");
  186. }
  187. /* check for processor halted */
  188. if (ejtag_ctrl & EJTAG_CTRL_BRKST) {
  189. if ((target->state != TARGET_HALTED)
  190. && (target->state != TARGET_DEBUG_RUNNING)) {
  191. if (target->state == TARGET_UNKNOWN)
  192. LOG_DEBUG("EJTAG_CTRL_BRKST already set during server startup.");
  193. /* OpenOCD was was probably started on the board with EJTAG_CTRL_BRKST already set
  194. * (maybe put on by HALT-ing the board in the previous session).
  195. *
  196. * Force enable debug entry for this session.
  197. */
  198. mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT);
  199. target->state = TARGET_HALTED;
  200. retval = mips_m4k_debug_entry(target);
  201. if (retval != ERROR_OK)
  202. return retval;
  203. if (target->smp &&
  204. ((prev_target_state == TARGET_RUNNING)
  205. || (prev_target_state == TARGET_RESET))) {
  206. retval = update_halt_gdb(target);
  207. if (retval != ERROR_OK)
  208. return retval;
  209. }
  210. target_call_event_callbacks(target, TARGET_EVENT_HALTED);
  211. } else if (target->state == TARGET_DEBUG_RUNNING) {
  212. target->state = TARGET_HALTED;
  213. retval = mips_m4k_debug_entry(target);
  214. if (retval != ERROR_OK)
  215. return retval;
  216. if (target->smp) {
  217. retval = update_halt_gdb(target);
  218. if (retval != ERROR_OK)
  219. return retval;
  220. }
  221. target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
  222. }
  223. } else
  224. target->state = TARGET_RUNNING;
  225. /* LOG_DEBUG("ctrl = 0x%08X", ejtag_ctrl); */
  226. return ERROR_OK;
  227. }
  228. static int mips_m4k_halt(struct target *target)
  229. {
  230. struct mips32_common *mips32 = target_to_mips32(target);
  231. struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
  232. LOG_DEBUG("target->state: %s", target_state_name(target));
  233. if (target->state == TARGET_HALTED) {
  234. LOG_DEBUG("target was already halted");
  235. return ERROR_OK;
  236. }
  237. if (target->state == TARGET_UNKNOWN)
  238. LOG_WARNING("target was in unknown state when halt was requested");
  239. if (target->state == TARGET_RESET) {
  240. if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst()) {
  241. LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
  242. return ERROR_TARGET_FAILURE;
  243. } else {
  244. /* we came here in a reset_halt or reset_init sequence
  245. * debug entry was already prepared in mips_m4k_assert_reset()
  246. */
  247. target->debug_reason = DBG_REASON_DBGRQ;
  248. return ERROR_OK;
  249. }
  250. }
  251. /* break processor */
  252. mips_ejtag_enter_debug(ejtag_info);
  253. target->debug_reason = DBG_REASON_DBGRQ;
  254. return ERROR_OK;
  255. }
  256. static int mips_m4k_assert_reset(struct target *target)
  257. {
  258. struct mips_m4k_common *mips_m4k = target_to_m4k(target);
  259. struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;
  260. /* TODO: apply hw reset signal in not examined state */
  261. if (!(target_was_examined(target))) {
  262. LOG_WARNING("Reset is not asserted because the target is not examined.");
  263. LOG_WARNING("Use a reset button or power cycle the target.");
  264. return ERROR_TARGET_NOT_EXAMINED;
  265. }
  266. LOG_DEBUG("target->state: %s",
  267. target_state_name(target));
  268. enum reset_types jtag_reset_config = jtag_get_reset_config();
  269. /* some cores support connecting while srst is asserted
  270. * use that mode is it has been configured */
  271. bool srst_asserted = false;
  272. if (!(jtag_reset_config & RESET_SRST_PULLS_TRST) &&
  273. (jtag_reset_config & RESET_SRST_NO_GATING)) {
  274. jtag_add_reset(0, 1);
  275. srst_asserted = true;
  276. }
  277. /* EJTAG before v2.5/2.6 does not support EJTAGBOOT or NORMALBOOT */
  278. if (ejtag_info->ejtag_version != EJTAG_VERSION_20) {
  279. if (target->reset_halt) {
  280. /* use hardware to catch reset */
  281. mips_ejtag_set_instr(ejtag_info, EJTAG_INST_EJTAGBOOT);
  282. } else
  283. mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT);
  284. }
  285. if (jtag_reset_config & RESET_HAS_SRST) {
  286. /* here we should issue a srst only, but we may have to assert trst as well */
  287. if (jtag_reset_config & RESET_SRST_PULLS_TRST)
  288. jtag_add_reset(1, 1);
  289. else if (!srst_asserted)
  290. jtag_add_reset(0, 1);
  291. } else {
  292. if (mips_m4k->is_pic32mx) {
  293. LOG_DEBUG("Using MTAP reset to reset processor...");
  294. /* use microchip specific MTAP reset */
  295. mips_ejtag_set_instr(ejtag_info, MTAP_SW_MTAP);
  296. mips_ejtag_set_instr(ejtag_info, MTAP_COMMAND);
  297. mips_ejtag_drscan_8_out(ejtag_info, MCHP_ASERT_RST);
  298. mips_ejtag_drscan_8_out(ejtag_info, MCHP_DE_ASSERT_RST);
  299. mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP);
  300. } else {
  301. /* use ejtag reset - not supported by all cores */
  302. uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_PRRST | EJTAG_CTRL_PERRST;
  303. LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor...");
  304. mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
  305. mips_ejtag_drscan_32_out(ejtag_info, ejtag_ctrl);
  306. }
  307. }
  308. target->state = TARGET_RESET;
  309. jtag_add_sleep(50000);
  310. register_cache_invalidate(mips_m4k->mips32.core_cache);
  311. if (target->reset_halt) {
  312. int retval = target_halt(target);
  313. if (retval != ERROR_OK)
  314. return retval;
  315. }
  316. return ERROR_OK;
  317. }
  318. static int mips_m4k_deassert_reset(struct target *target)
  319. {
  320. LOG_DEBUG("target->state: %s", target_state_name(target));
  321. /* deassert reset lines */
  322. jtag_add_reset(0, 0);
  323. return ERROR_OK;
  324. }
  325. static int mips_m4k_single_step_core(struct target *target)
  326. {
  327. struct mips32_common *mips32 = target_to_mips32(target);
  328. struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
  329. /* configure single step mode */
  330. mips_ejtag_config_step(ejtag_info, 1);
  331. /* disable interrupts while stepping */
  332. mips32_enable_interrupts(target, 0);
  333. /* exit debug mode */
  334. mips_ejtag_exit_debug(ejtag_info);
  335. mips_m4k_debug_entry(target);
  336. return ERROR_OK;
  337. }
  338. static int mips_m4k_restore_smp(struct target *target, uint32_t address, int handle_breakpoints)
  339. {
  340. int retval = ERROR_OK;
  341. struct target_list *head;
  342. struct target *curr;
  343. head = target->head;
  344. while (head != (struct target_list *)NULL) {
  345. int ret = ERROR_OK;
  346. curr = head->target;
  347. if ((curr != target) && (curr->state != TARGET_RUNNING)) {
  348. /* resume current address , not in step mode */
  349. ret = mips_m4k_internal_restore(curr, 1, address,
  350. handle_breakpoints, 0);
  351. if (ret != ERROR_OK) {
  352. LOG_ERROR("target->coreid :%" PRId32 " failed to resume at address :0x%" PRIx32,
  353. curr->coreid, address);
  354. retval = ret;
  355. }
  356. }
  357. head = head->next;
  358. }
  359. return retval;
  360. }
  361. static int mips_m4k_internal_restore(struct target *target, int current,
  362. uint32_t address, int handle_breakpoints, int debug_execution)
  363. {
  364. struct mips32_common *mips32 = target_to_mips32(target);
  365. struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
  366. struct breakpoint *breakpoint = NULL;
  367. uint32_t resume_pc;
  368. if (target->state != TARGET_HALTED) {
  369. LOG_WARNING("target not halted");
  370. return ERROR_TARGET_NOT_HALTED;
  371. }
  372. if (!debug_execution) {
  373. target_free_all_working_areas(target);
  374. mips_m4k_enable_breakpoints(target);
  375. mips_m4k_enable_watchpoints(target);
  376. }
  377. /* current = 1: continue on current pc, otherwise continue at <address> */
  378. if (!current) {
  379. buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);
  380. mips32->core_cache->reg_list[MIPS32_PC].dirty = 1;
  381. mips32->core_cache->reg_list[MIPS32_PC].valid = 1;
  382. }
  383. if (ejtag_info->impcode & EJTAG_IMP_MIPS16)
  384. buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 1, mips32->isa_mode);
  385. if (!current)
  386. resume_pc = address;
  387. else
  388. resume_pc = buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32);
  389. mips32_restore_context(target);
  390. /* the front-end may request us not to handle breakpoints */
  391. if (handle_breakpoints) {
  392. /* Single step past breakpoint at current address */
  393. breakpoint = breakpoint_find(target, resume_pc);
  394. if (breakpoint) {
  395. LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 "", breakpoint->address);
  396. mips_m4k_unset_breakpoint(target, breakpoint);
  397. mips_m4k_single_step_core(target);
  398. mips_m4k_set_breakpoint(target, breakpoint);
  399. }
  400. }
  401. /* enable interrupts if we are running */
  402. mips32_enable_interrupts(target, !debug_execution);
  403. /* exit debug mode */
  404. mips_ejtag_exit_debug(ejtag_info);
  405. target->debug_reason = DBG_REASON_NOTHALTED;
  406. /* registers are now invalid */
  407. register_cache_invalidate(mips32->core_cache);
  408. if (!debug_execution) {
  409. target->state = TARGET_RUNNING;
  410. target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
  411. LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
  412. } else {
  413. target->state = TARGET_DEBUG_RUNNING;
  414. target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
  415. LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
  416. }
  417. return ERROR_OK;
  418. }
  419. static int mips_m4k_resume(struct target *target, int current,
  420. uint32_t address, int handle_breakpoints, int debug_execution)
  421. {
  422. int retval = ERROR_OK;
  423. /* dummy resume for smp toggle in order to reduce gdb impact */
  424. if ((target->smp) && (target->gdb_service->core[1] != -1)) {
  425. /* simulate a start and halt of target */
  426. target->gdb_service->target = NULL;
  427. target->gdb_service->core[0] = target->gdb_service->core[1];
  428. /* fake resume at next poll we play the target core[1], see poll*/
  429. target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
  430. return retval;
  431. }
  432. retval = mips_m4k_internal_restore(target, current, address,
  433. handle_breakpoints,
  434. debug_execution);
  435. if (retval == ERROR_OK && target->smp) {
  436. target->gdb_service->core[0] = -1;
  437. retval = mips_m4k_restore_smp(target, address, handle_breakpoints);
  438. }
  439. return retval;
  440. }
  441. static int mips_m4k_step(struct target *target, int current,
  442. uint32_t address, int handle_breakpoints)
  443. {
  444. /* get pointers to arch-specific information */
  445. struct mips32_common *mips32 = target_to_mips32(target);
  446. struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
  447. struct breakpoint *breakpoint = NULL;
  448. if (target->state != TARGET_HALTED) {
  449. LOG_WARNING("target not halted");
  450. return ERROR_TARGET_NOT_HALTED;
  451. }
  452. /* current = 1: continue on current pc, otherwise continue at <address> */
  453. if (!current) {
  454. buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);
  455. mips32->core_cache->reg_list[MIPS32_PC].dirty = 1;
  456. mips32->core_cache->reg_list[MIPS32_PC].valid = 1;
  457. }
  458. /* the front-end may request us not to handle breakpoints */
  459. if (handle_breakpoints) {
  460. breakpoint = breakpoint_find(target,
  461. buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32));
  462. if (breakpoint)
  463. mips_m4k_unset_breakpoint(target, breakpoint);
  464. }
  465. /* restore context */
  466. mips32_restore_context(target);
  467. /* configure single step mode */
  468. mips_ejtag_config_step(ejtag_info, 1);
  469. target->debug_reason = DBG_REASON_SINGLESTEP;
  470. target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
  471. /* disable interrupts while stepping */
  472. mips32_enable_interrupts(target, 0);
  473. /* exit debug mode */
  474. mips_ejtag_exit_debug(ejtag_info);
  475. /* registers are now invalid */
  476. register_cache_invalidate(mips32->core_cache);
  477. LOG_DEBUG("target stepped ");
  478. mips_m4k_debug_entry(target);
  479. if (breakpoint)
  480. mips_m4k_set_breakpoint(target, breakpoint);
  481. target_call_event_callbacks(target, TARGET_EVENT_HALTED);
  482. return ERROR_OK;
  483. }
  484. static void mips_m4k_enable_breakpoints(struct target *target)
  485. {
  486. struct breakpoint *breakpoint = target->breakpoints;
  487. /* set any pending breakpoints */
  488. while (breakpoint) {
  489. if (breakpoint->set == 0)
  490. mips_m4k_set_breakpoint(target, breakpoint);
  491. breakpoint = breakpoint->next;
  492. }
  493. }
  494. static int mips_m4k_set_breakpoint(struct target *target,
  495. struct breakpoint *breakpoint)
  496. {
  497. struct mips32_common *mips32 = target_to_mips32(target);
  498. struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
  499. struct mips32_comparator *comparator_list = mips32->inst_break_list;
  500. int retval;
  501. if (breakpoint->set) {
  502. LOG_WARNING("breakpoint already set");
  503. return ERROR_OK;
  504. }
  505. if (breakpoint->type == BKPT_HARD) {
  506. int bp_num = 0;
  507. while (comparator_list[bp_num].used && (bp_num < mips32->num_inst_bpoints))
  508. bp_num++;
  509. if (bp_num >= mips32->num_inst_bpoints) {
  510. LOG_ERROR("Can not find free FP Comparator(bpid: %" PRIu32 ")",
  511. breakpoint->unique_id);
  512. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  513. }
  514. breakpoint->set = bp_num + 1;
  515. comparator_list[bp_num].used = 1;
  516. comparator_list[bp_num].bp_value = breakpoint->address;
  517. /* EJTAG 2.0 uses 30bit IBA. First 2 bits are reserved.
  518. * Warning: there is no IB ASID registers in 2.0.
  519. * Do not set it! :) */
  520. if (ejtag_info->ejtag_version == EJTAG_VERSION_20)
  521. comparator_list[bp_num].bp_value &= 0xFFFFFFFC;
  522. target_write_u32(target, comparator_list[bp_num].reg_address,
  523. comparator_list[bp_num].bp_value);
  524. target_write_u32(target, comparator_list[bp_num].reg_address +
  525. ejtag_info->ejtag_ibm_offs, 0x00000000);
  526. target_write_u32(target, comparator_list[bp_num].reg_address +
  527. ejtag_info->ejtag_ibc_offs, 1);
  528. LOG_DEBUG("bpid: %" PRIu32 ", bp_num %i bp_value 0x%" PRIx32 "",
  529. breakpoint->unique_id,
  530. bp_num, comparator_list[bp_num].bp_value);
  531. } else if (breakpoint->type == BKPT_SOFT) {
  532. LOG_DEBUG("bpid: %" PRIu32, breakpoint->unique_id);
  533. if (breakpoint->length == 4) {
  534. uint32_t verify = 0xffffffff;
  535. retval = target_read_memory(target, breakpoint->address, breakpoint->length, 1,
  536. breakpoint->orig_instr);
  537. if (retval != ERROR_OK)
  538. return retval;
  539. retval = target_write_u32(target, breakpoint->address, MIPS32_SDBBP);
  540. if (retval != ERROR_OK)
  541. return retval;
  542. retval = target_read_u32(target, breakpoint->address, &verify);
  543. if (retval != ERROR_OK)
  544. return retval;
  545. if (verify != MIPS32_SDBBP) {
  546. LOG_ERROR("Unable to set 32bit breakpoint at address %08" PRIx32
  547. " - check that memory is read/writable", breakpoint->address);
  548. return ERROR_OK;
  549. }
  550. } else {
  551. uint16_t verify = 0xffff;
  552. retval = target_read_memory(target, breakpoint->address, breakpoint->length, 1,
  553. breakpoint->orig_instr);
  554. if (retval != ERROR_OK)
  555. return retval;
  556. retval = target_write_u16(target, breakpoint->address, MIPS16_SDBBP);
  557. if (retval != ERROR_OK)
  558. return retval;
  559. retval = target_read_u16(target, breakpoint->address, &verify);
  560. if (retval != ERROR_OK)
  561. return retval;
  562. if (verify != MIPS16_SDBBP) {
  563. LOG_ERROR("Unable to set 16bit breakpoint at address %08" PRIx32
  564. " - check that memory is read/writable", breakpoint->address);
  565. return ERROR_OK;
  566. }
  567. }
  568. breakpoint->set = 20; /* Any nice value but 0 */
  569. }
  570. return ERROR_OK;
  571. }
  572. static int mips_m4k_unset_breakpoint(struct target *target,
  573. struct breakpoint *breakpoint)
  574. {
  575. /* get pointers to arch-specific information */
  576. struct mips32_common *mips32 = target_to_mips32(target);
  577. struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
  578. struct mips32_comparator *comparator_list = mips32->inst_break_list;
  579. int retval;
  580. if (!breakpoint->set) {
  581. LOG_WARNING("breakpoint not set");
  582. return ERROR_OK;
  583. }
  584. if (breakpoint->type == BKPT_HARD) {
  585. int bp_num = breakpoint->set - 1;
  586. if ((bp_num < 0) || (bp_num >= mips32->num_inst_bpoints)) {
  587. LOG_DEBUG("Invalid FP Comparator number in breakpoint (bpid: %" PRIu32 ")",
  588. breakpoint->unique_id);
  589. return ERROR_OK;
  590. }
  591. LOG_DEBUG("bpid: %" PRIu32 " - releasing hw: %d",
  592. breakpoint->unique_id,
  593. bp_num);
  594. comparator_list[bp_num].used = 0;
  595. comparator_list[bp_num].bp_value = 0;
  596. target_write_u32(target, comparator_list[bp_num].reg_address +
  597. ejtag_info->ejtag_ibc_offs, 0);
  598. } else {
  599. /* restore original instruction (kept in target endianness) */
  600. LOG_DEBUG("bpid: %" PRIu32, breakpoint->unique_id);
  601. if (breakpoint->length == 4) {
  602. uint32_t current_instr;
  603. /* check that user program has not modified breakpoint instruction */
  604. retval = target_read_memory(target, breakpoint->address, 4, 1,
  605. (uint8_t *)&current_instr);
  606. if (retval != ERROR_OK)
  607. return retval;
  608. /**
  609. * target_read_memory() gets us data in _target_ endianess.
  610. * If we want to use this data on the host for comparisons with some macros
  611. * we must first transform it to _host_ endianess using target_buffer_get_u32().
  612. */
  613. current_instr = target_buffer_get_u32(target, (uint8_t *)&current_instr);
  614. if (current_instr == MIPS32_SDBBP) {
  615. retval = target_write_memory(target, breakpoint->address, 4, 1,
  616. breakpoint->orig_instr);
  617. if (retval != ERROR_OK)
  618. return retval;
  619. }
  620. } else {
  621. uint16_t current_instr;
  622. /* check that user program has not modified breakpoint instruction */
  623. retval = target_read_memory(target, breakpoint->address, 2, 1,
  624. (uint8_t *)&current_instr);
  625. if (retval != ERROR_OK)
  626. return retval;
  627. current_instr = target_buffer_get_u16(target, (uint8_t *)&current_instr);
  628. if (current_instr == MIPS16_SDBBP) {
  629. retval = target_write_memory(target, breakpoint->address, 2, 1,
  630. breakpoint->orig_instr);
  631. if (retval != ERROR_OK)
  632. return retval;
  633. }
  634. }
  635. }
  636. breakpoint->set = 0;
  637. return ERROR_OK;
  638. }
  639. static int mips_m4k_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
  640. {
  641. struct mips32_common *mips32 = target_to_mips32(target);
  642. if (breakpoint->type == BKPT_HARD) {
  643. if (mips32->num_inst_bpoints_avail < 1) {
  644. LOG_INFO("no hardware breakpoint available");
  645. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  646. }
  647. mips32->num_inst_bpoints_avail--;
  648. }
  649. return mips_m4k_set_breakpoint(target, breakpoint);
  650. }
  651. static int mips_m4k_remove_breakpoint(struct target *target,
  652. struct breakpoint *breakpoint)
  653. {
  654. /* get pointers to arch-specific information */
  655. struct mips32_common *mips32 = target_to_mips32(target);
  656. if (target->state != TARGET_HALTED) {
  657. LOG_WARNING("target not halted");
  658. return ERROR_TARGET_NOT_HALTED;
  659. }
  660. if (breakpoint->set)
  661. mips_m4k_unset_breakpoint(target, breakpoint);
  662. if (breakpoint->type == BKPT_HARD)
  663. mips32->num_inst_bpoints_avail++;
  664. return ERROR_OK;
  665. }
  666. static int mips_m4k_set_watchpoint(struct target *target,
  667. struct watchpoint *watchpoint)
  668. {
  669. struct mips32_common *mips32 = target_to_mips32(target);
  670. struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
  671. struct mips32_comparator *comparator_list = mips32->data_break_list;
  672. int wp_num = 0;
  673. /*
  674. * watchpoint enabled, ignore all byte lanes in value register
  675. * and exclude both load and store accesses from watchpoint
  676. * condition evaluation
  677. */
  678. int enable = EJTAG_DBCn_NOSB | EJTAG_DBCn_NOLB | EJTAG_DBCn_BE |
  679. (0xff << EJTAG_DBCn_BLM_SHIFT);
  680. if (watchpoint->set) {
  681. LOG_WARNING("watchpoint already set");
  682. return ERROR_OK;
  683. }
  684. while (comparator_list[wp_num].used && (wp_num < mips32->num_data_bpoints))
  685. wp_num++;
  686. if (wp_num >= mips32->num_data_bpoints) {
  687. LOG_ERROR("Can not find free FP Comparator");
  688. return ERROR_FAIL;
  689. }
  690. if (watchpoint->length != 4) {
  691. LOG_ERROR("Only watchpoints of length 4 are supported");
  692. return ERROR_TARGET_UNALIGNED_ACCESS;
  693. }
  694. if (watchpoint->address % 4) {
  695. LOG_ERROR("Watchpoints address should be word aligned");
  696. return ERROR_TARGET_UNALIGNED_ACCESS;
  697. }
  698. switch (watchpoint->rw) {
  699. case WPT_READ:
  700. enable &= ~EJTAG_DBCn_NOLB;
  701. break;
  702. case WPT_WRITE:
  703. enable &= ~EJTAG_DBCn_NOSB;
  704. break;
  705. case WPT_ACCESS:
  706. enable &= ~(EJTAG_DBCn_NOLB | EJTAG_DBCn_NOSB);
  707. break;
  708. default:
  709. LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");
  710. }
  711. watchpoint->set = wp_num + 1;
  712. comparator_list[wp_num].used = 1;
  713. comparator_list[wp_num].bp_value = watchpoint->address;
  714. /* EJTAG 2.0 uses 29bit DBA. First 3 bits are reserved.
  715. * There is as well no ASID register support. */
  716. if (ejtag_info->ejtag_version == EJTAG_VERSION_20)
  717. comparator_list[wp_num].bp_value &= 0xFFFFFFF8;
  718. else
  719. target_write_u32(target, comparator_list[wp_num].reg_address +
  720. ejtag_info->ejtag_dbasid_offs, 0x00000000);
  721. target_write_u32(target, comparator_list[wp_num].reg_address,
  722. comparator_list[wp_num].bp_value);
  723. target_write_u32(target, comparator_list[wp_num].reg_address +
  724. ejtag_info->ejtag_dbm_offs, 0x00000000);
  725. target_write_u32(target, comparator_list[wp_num].reg_address +
  726. ejtag_info->ejtag_dbc_offs, enable);
  727. /* TODO: probably this value is ignored on 2.0 */
  728. target_write_u32(target, comparator_list[wp_num].reg_address +
  729. ejtag_info->ejtag_dbv_offs, 0);
  730. LOG_DEBUG("wp_num %i bp_value 0x%" PRIx32 "", wp_num, comparator_list[wp_num].bp_value);
  731. return ERROR_OK;
  732. }
  733. static int mips_m4k_unset_watchpoint(struct target *target,
  734. struct watchpoint *watchpoint)
  735. {
  736. /* get pointers to arch-specific information */
  737. struct mips32_common *mips32 = target_to_mips32(target);
  738. struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
  739. struct mips32_comparator *comparator_list = mips32->data_break_list;
  740. if (!watchpoint->set) {
  741. LOG_WARNING("watchpoint not set");
  742. return ERROR_OK;
  743. }
  744. int wp_num = watchpoint->set - 1;
  745. if ((wp_num < 0) || (wp_num >= mips32->num_data_bpoints)) {
  746. LOG_DEBUG("Invalid FP Comparator number in watchpoint");
  747. return ERROR_OK;
  748. }
  749. comparator_list[wp_num].used = 0;
  750. comparator_list[wp_num].bp_value = 0;
  751. target_write_u32(target, comparator_list[wp_num].reg_address +
  752. ejtag_info->ejtag_dbc_offs, 0);
  753. watchpoint->set = 0;
  754. return ERROR_OK;
  755. }
  756. static int mips_m4k_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
  757. {
  758. struct mips32_common *mips32 = target_to_mips32(target);
  759. if (mips32->num_data_bpoints_avail < 1) {
  760. LOG_INFO("no hardware watchpoints available");
  761. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  762. }
  763. mips32->num_data_bpoints_avail--;
  764. mips_m4k_set_watchpoint(target, watchpoint);
  765. return ERROR_OK;
  766. }
  767. static int mips_m4k_remove_watchpoint(struct target *target,
  768. struct watchpoint *watchpoint)
  769. {
  770. /* get pointers to arch-specific information */
  771. struct mips32_common *mips32 = target_to_mips32(target);
  772. if (target->state != TARGET_HALTED) {
  773. LOG_WARNING("target not halted");
  774. return ERROR_TARGET_NOT_HALTED;
  775. }
  776. if (watchpoint->set)
  777. mips_m4k_unset_watchpoint(target, watchpoint);
  778. mips32->num_data_bpoints_avail++;
  779. return ERROR_OK;
  780. }
  781. static void mips_m4k_enable_watchpoints(struct target *target)
  782. {
  783. struct watchpoint *watchpoint = target->watchpoints;
  784. /* set any pending watchpoints */
  785. while (watchpoint) {
  786. if (watchpoint->set == 0)
  787. mips_m4k_set_watchpoint(target, watchpoint);
  788. watchpoint = watchpoint->next;
  789. }
  790. }
  791. static int mips_m4k_read_memory(struct target *target, uint32_t address,
  792. uint32_t size, uint32_t count, uint8_t *buffer)
  793. {
  794. struct mips32_common *mips32 = target_to_mips32(target);
  795. struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
  796. LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",
  797. address, size, count);
  798. if (target->state != TARGET_HALTED) {
  799. LOG_WARNING("target not halted");
  800. return ERROR_TARGET_NOT_HALTED;
  801. }
  802. /* sanitize arguments */
  803. if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
  804. return ERROR_COMMAND_SYNTAX_ERROR;
  805. if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
  806. return ERROR_TARGET_UNALIGNED_ACCESS;
  807. /* since we don't know if buffer is aligned, we allocate new mem that is always aligned */
  808. void *t = NULL;
  809. if (size > 1) {
  810. t = malloc(count * size * sizeof(uint8_t));
  811. if (t == NULL) {
  812. LOG_ERROR("Out of memory");
  813. return ERROR_FAIL;
  814. }
  815. } else
  816. t = buffer;
  817. /* if noDMA off, use DMAACC mode for memory read */
  818. int retval;
  819. if (ejtag_info->impcode & EJTAG_IMP_NODMA)
  820. retval = mips32_pracc_read_mem(ejtag_info, address, size, count, t);
  821. else
  822. retval = mips32_dmaacc_read_mem(ejtag_info, address, size, count, t);
  823. /* mips32_..._read_mem with size 4/2 returns uint32_t/uint16_t in host */
  824. /* endianness, but byte array should represent target endianness */
  825. if (ERROR_OK == retval) {
  826. switch (size) {
  827. case 4:
  828. target_buffer_set_u32_array(target, buffer, count, t);
  829. break;
  830. case 2:
  831. target_buffer_set_u16_array(target, buffer, count, t);
  832. break;
  833. }
  834. }
  835. if ((size > 1) && (t != NULL))
  836. free(t);
  837. return retval;
  838. }
  839. static int mips_m4k_write_memory(struct target *target, uint32_t address,
  840. uint32_t size, uint32_t count, const uint8_t *buffer)
  841. {
  842. struct mips32_common *mips32 = target_to_mips32(target);
  843. struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
  844. LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",
  845. address, size, count);
  846. if (target->state != TARGET_HALTED) {
  847. LOG_WARNING("target not halted");
  848. return ERROR_TARGET_NOT_HALTED;
  849. }
  850. if (size == 4 && count > 32) {
  851. int retval = mips_m4k_bulk_write_memory(target, address, count, buffer);
  852. if (retval == ERROR_OK)
  853. return ERROR_OK;
  854. LOG_WARNING("Falling back to non-bulk write");
  855. }
  856. /* sanitize arguments */
  857. if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
  858. return ERROR_COMMAND_SYNTAX_ERROR;
  859. if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
  860. return ERROR_TARGET_UNALIGNED_ACCESS;
  861. /** correct endianess if we have word or hword access */
  862. void *t = NULL;
  863. if (size > 1) {
  864. /* mips32_..._write_mem with size 4/2 requires uint32_t/uint16_t in host */
  865. /* endianness, but byte array represents target endianness */
  866. t = malloc(count * size * sizeof(uint8_t));
  867. if (t == NULL) {
  868. LOG_ERROR("Out of memory");
  869. return ERROR_FAIL;
  870. }
  871. switch (size) {
  872. case 4:
  873. target_buffer_get_u32_array(target, buffer, count, (uint32_t *)t);
  874. break;
  875. case 2:
  876. target_buffer_get_u16_array(target, buffer, count, (uint16_t *)t);
  877. break;
  878. }
  879. buffer = t;
  880. }
  881. /* if noDMA off, use DMAACC mode for memory write */
  882. int retval;
  883. if (ejtag_info->impcode & EJTAG_IMP_NODMA)
  884. retval = mips32_pracc_write_mem(ejtag_info, address, size, count, buffer);
  885. else
  886. retval = mips32_dmaacc_write_mem(ejtag_info, address, size, count, buffer);
  887. if (t != NULL)
  888. free(t);
  889. if (ERROR_OK != retval)
  890. return retval;
  891. return ERROR_OK;
  892. }
  893. static int mips_m4k_init_target(struct command_context *cmd_ctx,
  894. struct target *target)
  895. {
  896. mips32_build_reg_cache(target);
  897. return ERROR_OK;
  898. }
  899. static int mips_m4k_init_arch_info(struct target *target,
  900. struct mips_m4k_common *mips_m4k, struct jtag_tap *tap)
  901. {
  902. struct mips32_common *mips32 = &mips_m4k->mips32;
  903. mips_m4k->common_magic = MIPSM4K_COMMON_MAGIC;
  904. /* initialize mips4k specific info */
  905. mips32_init_arch_info(target, mips32, tap);
  906. mips32->arch_info = mips_m4k;
  907. return ERROR_OK;
  908. }
  909. static int mips_m4k_target_create(struct target *target, Jim_Interp *interp)
  910. {
  911. struct mips_m4k_common *mips_m4k = calloc(1, sizeof(struct mips_m4k_common));
  912. mips_m4k_init_arch_info(target, mips_m4k, target->tap);
  913. return ERROR_OK;
  914. }
  915. static int mips_m4k_examine(struct target *target)
  916. {
  917. int retval;
  918. struct mips_m4k_common *mips_m4k = target_to_m4k(target);
  919. struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;
  920. uint32_t idcode = 0;
  921. if (!target_was_examined(target)) {
  922. retval = mips_ejtag_get_idcode(ejtag_info, &idcode);
  923. if (retval != ERROR_OK)
  924. return retval;
  925. ejtag_info->idcode = idcode;
  926. if (((idcode >> 1) & 0x7FF) == 0x29) {
  927. /* we are using a pic32mx so select ejtag port
  928. * as it is not selected by default */
  929. mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP);
  930. LOG_DEBUG("PIC32MX Detected - using EJTAG Interface");
  931. mips_m4k->is_pic32mx = true;
  932. }
  933. }
  934. /* init rest of ejtag interface */
  935. retval = mips_ejtag_init(ejtag_info);
  936. if (retval != ERROR_OK)
  937. return retval;
  938. retval = mips32_examine(target);
  939. if (retval != ERROR_OK)
  940. return retval;
  941. return ERROR_OK;
  942. }
  943. static int mips_m4k_bulk_write_memory(struct target *target, uint32_t address,
  944. uint32_t count, const uint8_t *buffer)
  945. {
  946. struct mips32_common *mips32 = target_to_mips32(target);
  947. struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
  948. struct working_area *fast_data_area;
  949. int retval;
  950. int write_t = 1;
  951. LOG_DEBUG("address: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", address, count);
  952. /* check alignment */
  953. if (address & 0x3u)
  954. return ERROR_TARGET_UNALIGNED_ACCESS;
  955. if (mips32->fast_data_area == NULL) {
  956. /* Get memory for block write handler
  957. * we preserve this area between calls and gain a speed increase
  958. * of about 3kb/sec when writing flash
  959. * this will be released/nulled by the system when the target is resumed or reset */
  960. retval = target_alloc_working_area(target,
  961. MIPS32_FASTDATA_HANDLER_SIZE,
  962. &mips32->fast_data_area);
  963. if (retval != ERROR_OK) {
  964. LOG_ERROR("No working area available");
  965. return retval;
  966. }
  967. /* reset fastadata state so the algo get reloaded */
  968. ejtag_info->fast_access_save = -1;
  969. }
  970. fast_data_area = mips32->fast_data_area;
  971. if (address <= fast_data_area->address + fast_data_area->size &&
  972. fast_data_area->address <= address + count) {
  973. LOG_ERROR("fast_data (0x%8.8" PRIx32 ") is within write area "
  974. "(0x%8.8" PRIx32 "-0x%8.8" PRIx32 ").",
  975. fast_data_area->address, address, address + count);
  976. LOG_ERROR("Change work-area-phys or load_image address!");
  977. return ERROR_FAIL;
  978. }
  979. /* mips32_pracc_fastdata_xfer requires uint32_t in host endianness, */
  980. /* but byte array represents target endianness */
  981. uint32_t *t = NULL;
  982. t = malloc(count * sizeof(uint32_t));
  983. if (t == NULL) {
  984. LOG_ERROR("Out of memory");
  985. return ERROR_FAIL;
  986. }
  987. target_buffer_get_u32_array(target, buffer, count, t);
  988. retval = mips32_pracc_fastdata_xfer(ejtag_info, mips32->fast_data_area, write_t, address,
  989. count, t);
  990. if (t != NULL)
  991. free(t);
  992. if (retval != ERROR_OK)
  993. LOG_ERROR("Fastdata access Failed");
  994. return retval;
  995. }
  996. static int mips_m4k_verify_pointer(struct command_context *cmd_ctx,
  997. struct mips_m4k_common *mips_m4k)
  998. {
  999. if (mips_m4k->common_magic != MIPSM4K_COMMON_MAGIC) {
  1000. command_print(cmd_ctx, "target is not an MIPS_M4K");
  1001. return ERROR_TARGET_INVALID;
  1002. }
  1003. return ERROR_OK;
  1004. }
  1005. COMMAND_HANDLER(mips_m4k_handle_cp0_command)
  1006. {
  1007. int retval;
  1008. struct target *target = get_current_target(CMD_CTX);
  1009. struct mips_m4k_common *mips_m4k = target_to_m4k(target);
  1010. struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;
  1011. retval = mips_m4k_verify_pointer(CMD_CTX, mips_m4k);
  1012. if (retval != ERROR_OK)
  1013. return retval;
  1014. if (target->state != TARGET_HALTED) {
  1015. command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
  1016. return ERROR_OK;
  1017. }
  1018. /* two or more argument, access a single register/select (write if third argument is given) */
  1019. if (CMD_ARGC < 2)
  1020. return ERROR_COMMAND_SYNTAX_ERROR;
  1021. else {
  1022. uint32_t cp0_reg, cp0_sel;
  1023. COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], cp0_reg);
  1024. COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], cp0_sel);
  1025. if (CMD_ARGC == 2) {
  1026. uint32_t value;
  1027. retval = mips32_cp0_read(ejtag_info, &value, cp0_reg, cp0_sel);
  1028. if (retval != ERROR_OK) {
  1029. command_print(CMD_CTX,
  1030. "couldn't access reg %" PRIi32,
  1031. cp0_reg);
  1032. return ERROR_OK;
  1033. }
  1034. command_print(CMD_CTX, "cp0 reg %" PRIi32 ", select %" PRIi32 ": %8.8" PRIx32,
  1035. cp0_reg, cp0_sel, value);
  1036. } else if (CMD_ARGC == 3) {
  1037. uint32_t value;
  1038. COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value);
  1039. retval = mips32_cp0_write(ejtag_info, value, cp0_reg, cp0_sel);
  1040. if (retval != ERROR_OK) {
  1041. command_print(CMD_CTX,
  1042. "couldn't access cp0 reg %" PRIi32 ", select %" PRIi32,
  1043. cp0_reg, cp0_sel);
  1044. return ERROR_OK;
  1045. }
  1046. command_print(CMD_CTX, "cp0 reg %" PRIi32 ", select %" PRIi32 ": %8.8" PRIx32,
  1047. cp0_reg, cp0_sel, value);
  1048. }
  1049. }
  1050. return ERROR_OK;
  1051. }
  1052. COMMAND_HANDLER(mips_m4k_handle_smp_off_command)
  1053. {
  1054. struct target *target = get_current_target(CMD_CTX);
  1055. /* check target is an smp target */
  1056. struct target_list *head;
  1057. struct target *curr;
  1058. head = target->head;
  1059. target->smp = 0;
  1060. if (head != (struct target_list *)NULL) {
  1061. while (head != (struct target_list *)NULL) {
  1062. curr = head->target;
  1063. curr->smp = 0;
  1064. head = head->next;
  1065. }
  1066. /* fixes the target display to the debugger */
  1067. target->gdb_service->target = target;
  1068. }
  1069. return ERROR_OK;
  1070. }
  1071. COMMAND_HANDLER(mips_m4k_handle_smp_on_command)
  1072. {
  1073. struct target *target = get_current_target(CMD_CTX);
  1074. struct target_list *head;
  1075. struct target *curr;
  1076. head = target->head;
  1077. if (head != (struct target_list *)NULL) {
  1078. target->smp = 1;
  1079. while (head != (struct target_list *)NULL) {
  1080. curr = head->target;
  1081. curr->smp = 1;
  1082. head = head->next;
  1083. }
  1084. }
  1085. return ERROR_OK;
  1086. }
  1087. COMMAND_HANDLER(mips_m4k_handle_smp_gdb_command)
  1088. {
  1089. struct target *target = get_current_target(CMD_CTX);
  1090. int retval = ERROR_OK;
  1091. struct target_list *head;
  1092. head = target->head;
  1093. if (head != (struct target_list *)NULL) {
  1094. if (CMD_ARGC == 1) {
  1095. int coreid = 0;
  1096. COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], coreid);
  1097. if (ERROR_OK != retval)
  1098. return retval;
  1099. target->gdb_service->core[1] = coreid;
  1100. }
  1101. command_print(CMD_CTX, "gdb coreid %" PRId32 " -> %" PRId32, target->gdb_service->core[0]
  1102. , target->gdb_service->core[1]);
  1103. }
  1104. return ERROR_OK;
  1105. }
  1106. COMMAND_HANDLER(mips_m4k_handle_scan_delay_command)
  1107. {
  1108. struct target *target = get_current_target(CMD_CTX);
  1109. struct mips_m4k_common *mips_m4k = target_to_m4k(target);
  1110. struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;
  1111. if (CMD_ARGC == 1)
  1112. COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], ejtag_info->scan_delay);
  1113. else if (CMD_ARGC > 1)
  1114. return ERROR_COMMAND_SYNTAX_ERROR;
  1115. command_print(CMD_CTX, "scan delay: %d nsec", ejtag_info->scan_delay);
  1116. if (ejtag_info->scan_delay >= 2000000) {
  1117. ejtag_info->mode = 0;
  1118. command_print(CMD_CTX, "running in legacy mode");
  1119. } else {
  1120. ejtag_info->mode = 1;
  1121. command_print(CMD_CTX, "running in fast queued mode");
  1122. }
  1123. return ERROR_OK;
  1124. }
  1125. static const struct command_registration mips_m4k_exec_command_handlers[] = {
  1126. {
  1127. .name = "cp0",
  1128. .handler = mips_m4k_handle_cp0_command,
  1129. .mode = COMMAND_EXEC,
  1130. .usage = "regnum [value]",
  1131. .help = "display/modify cp0 register",
  1132. },
  1133. {
  1134. .name = "smp_off",
  1135. .handler = mips_m4k_handle_smp_off_command,
  1136. .mode = COMMAND_EXEC,
  1137. .help = "Stop smp handling",
  1138. .usage = "",},
  1139. {
  1140. .name = "smp_on",
  1141. .handler = mips_m4k_handle_smp_on_command,
  1142. .mode = COMMAND_EXEC,
  1143. .help = "Restart smp handling",
  1144. .usage = "",
  1145. },
  1146. {
  1147. .name = "smp_gdb",
  1148. .handler = mips_m4k_handle_smp_gdb_command,
  1149. .mode = COMMAND_EXEC,
  1150. .help = "display/fix current core played to gdb",
  1151. .usage = "",
  1152. },
  1153. {
  1154. .name = "scan_delay",
  1155. .handler = mips_m4k_handle_scan_delay_command,
  1156. .mode = COMMAND_ANY,
  1157. .help = "display/set scan delay in nano seconds",
  1158. .usage = "[value]",
  1159. },
  1160. COMMAND_REGISTRATION_DONE
  1161. };
  1162. const struct command_registration mips_m4k_command_handlers[] = {
  1163. {
  1164. .chain = mips32_command_handlers,
  1165. },
  1166. {
  1167. .name = "mips_m4k",
  1168. .mode = COMMAND_ANY,
  1169. .help = "mips_m4k command group",
  1170. .usage = "",
  1171. .chain = mips_m4k_exec_command_handlers,
  1172. },
  1173. COMMAND_REGISTRATION_DONE
  1174. };
  1175. struct target_type mips_m4k_target = {
  1176. .name = "mips_m4k",
  1177. .poll = mips_m4k_poll,
  1178. .arch_state = mips32_arch_state,
  1179. .halt = mips_m4k_halt,
  1180. .resume = mips_m4k_resume,
  1181. .step = mips_m4k_step,
  1182. .assert_reset = mips_m4k_assert_reset,
  1183. .deassert_reset = mips_m4k_deassert_reset,
  1184. .get_gdb_reg_list = mips32_get_gdb_reg_list,
  1185. .read_memory = mips_m4k_read_memory,
  1186. .write_memory = mips_m4k_write_memory,
  1187. .checksum_memory = mips32_checksum_memory,
  1188. .blank_check_memory = mips32_blank_check_memory,
  1189. .run_algorithm = mips32_run_algorithm,
  1190. .add_breakpoint = mips_m4k_add_breakpoint,
  1191. .remove_breakpoint = mips_m4k_remove_breakpoint,
  1192. .add_watchpoint = mips_m4k_add_watchpoint,
  1193. .remove_watchpoint = mips_m4k_remove_watchpoint,
  1194. .commands = mips_m4k_command_handlers,
  1195. .target_create = mips_m4k_target_create,
  1196. .init_target = mips_m4k_init_target,
  1197. .examine = mips_m4k_examine,
  1198. };