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90 lines
3.1 KiB

  1. ################################################################################
  2. # Olimex SAM9-L9260 Development Board
  3. #
  4. # http://www.olimex.com/dev/sam9-L9260.html
  5. #
  6. # Atmel AT91SAM9260 : PLLA = 198.656 MHz, MCK = 99.328 MHz
  7. # PMC configured for external 18.432 MHz crystal
  8. #
  9. # 32-bit SDRAM : 2 x Samsung K4S561632J-UC75, 4M x 16Bit x 4 Banks
  10. # 8-bit NAND Flash : 1 x Samsung K9F4G08U0M, 512M x 8Bit
  11. # Dataflash : 1 x Atmel AT45DB161D, 16Mbit
  12. #
  13. ################################################################################
  14. source [find target/at91sam9260.cfg]
  15. # NTRST_E jumper is enabled by default, so we don't need to override the reset
  16. # config.
  17. #reset_config srst_only
  18. $_TARGETNAME configure -event reset-start {
  19. # At reset, CPU runs at 32.768 kHz. JTAG frequency must be 6 times slower if
  20. # RCLK is not supported.
  21. jtag_rclk 5
  22. halt
  23. # RSTC_MR : enable user reset, reset length is 64 slow clock cycles. MMU may
  24. # be enabled... use physical address.
  25. arm926ejs mww_phys 0xfffffd08 0xa5000501
  26. }
  27. $_TARGETNAME configure -event reset-init {
  28. mww 0xfffffd44 0x00008000 # WDT_MR : disable watchdog
  29. ##
  30. # Clock configuration for 99.328 MHz main clock.
  31. ##
  32. mww 0xfffffc20 0x00004001 # CKGR_MOR : enable main oscillator, 512 slow clock startup
  33. sleep 20 # wait 20 ms (need 15.6 ms for startup)
  34. mww 0xfffffc30 0x00000001 # PMC_MCKR : switch to main oscillator (18.432 MHz)
  35. sleep 10 # wait 10 ms
  36. mww 0xfffffc28 0x2060bf09 # CKGR_PLLAR : 18.432 MHz / 9 * 97 = 198.656 MHz, 63 slow clock startup
  37. sleep 20 # wait 20 ms (need 1.9 ms for startup)
  38. mww 0xfffffc30 0x00000101 # PMC_MCKR : no scale on proc clock, master is proc / 2
  39. sleep 10 # wait 10 ms
  40. mww 0xfffffc30 0x00000102 # PMC_MCKR : switch to PLLA (99.328 MHz)
  41. # Increase JTAG speed to 6 MHz if RCLK is not supported.
  42. jtag_rclk 6000
  43. arm7_9 dcc_downloads enable # Enable faster DCC downloads.
  44. ##
  45. # SDRAM configuration for 2 x Samsung K4S561632J-UC75, 4M x 16Bit x 4 Banks.
  46. ##
  47. mww 0xfffff870 0xffff0000 # PIOC_ASR : select peripheral function for D15..D31
  48. mww 0xfffff804 0xffff0000 # PIOC_PDR : disable PIO function for D15..D31
  49. mww 0xffffef1c 0x00010002 # EBI_CSA : assign EBI CS1 to SDRAM, VDDIOMSEL set for +3V3 memory
  50. mww 0xffffea08 0x85237259 # SDRAMC_CR : configure SDRAM for Samsung chips
  51. mww 0xffffea00 0x1 # SDRAMC_MR : issue NOP command
  52. mww 0x20000000 0
  53. mww 0xffffea00 0x2 # SDRAMC_MR : issue an 'All Banks Precharge' command
  54. mww 0x20000000 0
  55. mww 0xffffea00 0x4 # SDRAMC_MR : issue 8 x 'Auto-Refresh' command
  56. mww 0x20000000 0
  57. mww 0xffffea00 0x4
  58. mww 0x20000000 0
  59. mww 0xffffea00 0x4
  60. mww 0x20000000 0
  61. mww 0xffffea00 0x4
  62. mww 0x20000000 0
  63. mww 0xffffea00 0x4
  64. mww 0x20000000 0
  65. mww 0xffffea00 0x4
  66. mww 0x20000000 0
  67. mww 0xffffea00 0x4
  68. mww 0x20000000 0
  69. mww 0xffffea00 0x4
  70. mww 0x20000000 0
  71. mww 0xffffea00 0x3 # SDRAMC_MR : issue a 'Load Mode Register' command
  72. mww 0x20000000 0
  73. mww 0xffffea00 0x0 # SDRAMC_MR : normal mode
  74. mww 0x20000000 0
  75. mww 0xffffea04 0x2b6 # SDRAMC_TR : set refresh timer count to 7 us
  76. }