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  1. /**************************************************************************
  2. * Copyright (C) 2015 Jeff Ciesielski <jeffciesielski@gmail.com> *
  3. * *
  4. * This program is free software; you can redistribute it and/or modify *
  5. * it under the terms of the GNU General Public License as published by *
  6. * the Free Software Foundation; either version 2 of the License, or *
  7. * (at your option) any later version. *
  8. * *
  9. * This program is distributed in the hope that it will be useful, *
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  12. * GNU General Public License for more details. *
  13. * *
  14. ***************************************************************************/
  15. #ifdef HAVE_CONFIG_H
  16. #include "config.h"
  17. #endif
  18. #include "imp.h"
  19. #include <helper/binarybuffer.h>
  20. #include <target/algorithm.h>
  21. #include <target/armv7m.h>
  22. /* Maximum number of sectors */
  23. #define MAX_XMC_SECTORS 12
  24. /* System control unit registers */
  25. #define SCU_REG_BASE 0x50004000
  26. #define SCU_ID_CHIP 0x04
  27. /* Base of the non-cached flash memory */
  28. #define PFLASH_BASE 0x0C000000
  29. /* User configuration block offsets */
  30. #define UCB0_BASE 0x00000000
  31. #define UCB1_BASE 0x00000400
  32. #define UCB2_BASE 0x00000800
  33. /* Flash register base */
  34. #define FLASH_REG_BASE 0x58000000
  35. /* PMU ID Registers */
  36. #define FLASH_REG_PMU_ID (FLASH_REG_BASE | 0x0508)
  37. /* PMU Fields */
  38. #define PMU_MOD_REV_MASK 0xFF
  39. #define PMU_MOD_TYPE_MASK 0xFF00
  40. #define PMU_MOD_NO_MASK 0xFFFF0000
  41. /* Prefetch Config */
  42. #define FLASH_REG_PREF_PCON (FLASH_REG_BASE | 0x4000)
  43. /* Prefetch Fields */
  44. #define PCON_IBYP (1 << 0)
  45. #define PCON_IINV (1 << 1)
  46. /* Flash ID Register */
  47. #define FLASH_REG_FLASH0_ID (FLASH_REG_BASE | 0x2008)
  48. /* Flash Status Register */
  49. #define FLASH_REG_FLASH0_FSR (FLASH_REG_BASE | 0x2010)
  50. #define FSR_PBUSY (0)
  51. #define FSR_FABUSY (1)
  52. #define FSR_PROG (4)
  53. #define FSR_ERASE (5)
  54. #define FSR_PFPAGE (6)
  55. #define FSR_PFOPER (8)
  56. #define FSR_SQER (10)
  57. #define FSR_PROER (11)
  58. #define FSR_PFSBER (12)
  59. #define FSR_PFDBER (14)
  60. #define FSR_PROIN (16)
  61. #define FSR_RPROIN (18)
  62. #define FSR_RPRODIS (19)
  63. #define FSR_WPROIN0 (21)
  64. #define FSR_WPROIN1 (22)
  65. #define FSR_WPROIN2 (23)
  66. #define FSR_WPRODIS0 (25)
  67. #define FSR_WPRODIS1 (26)
  68. #define FSR_SLM (28)
  69. #define FSR_VER (31)
  70. #define FSR_PBUSY_MASK (0x01 << FSR_PBUSY)
  71. #define FSR_FABUSY_MASK (0x01 << FSR_FABUSY)
  72. #define FSR_PROG_MASK (0x01 << FSR_PROG)
  73. #define FSR_ERASE_MASK (0x01 << FSR_ERASE)
  74. #define FSR_PFPAGE_MASK (0x01 << FSR_PFPAGE)
  75. #define FSR_PFOPER_MASK (0x01 << FSR_PFOPER)
  76. #define FSR_SQER_MASK (0x01 << FSR_SQER)
  77. #define FSR_PROER_MASK (0x01 << FSR_PROER)
  78. #define FSR_PFSBER_MASK (0x01 << FSR_PFSBER)
  79. #define FSR_PFDBER_MASK (0x01 << FSR_PFDBER)
  80. #define FSR_PROIN_MASK (0x01 << FSR_PROIN)
  81. #define FSR_RPROIN_MASK (0x01 << FSR_RPROIN)
  82. #define FSR_RPRODIS_MASK (0x01 << FSR_RPRODIS)
  83. #define FSR_WPROIN0_MASK (0x01 << FSR_WPROIN0)
  84. #define FSR_WPROIN1_MASK (0x01 << FSR_WPROIN1)
  85. #define FSR_WPROIN2_MASK (0x01 << FSR_WPROIN2)
  86. #define FSR_WPRODIS0_MASK (0x01 << FSR_WPRODIS0)
  87. #define FSR_WPRODIS1_MASK (0x01 << FSR_WPRODIS1)
  88. #define FSR_SLM_MASK (0x01 << FSR_SLM)
  89. #define FSR_VER_MASK (0x01 << FSR_VER)
  90. /* Flash Config Register */
  91. #define FLASH_REG_FLASH0_FCON (FLASH_REG_BASE | 0x2014)
  92. #define FCON_WSPFLASH (0)
  93. #define FCON_WSECPF (4)
  94. #define FCON_IDLE (13)
  95. #define FCON_ESLDIS (14)
  96. #define FCON_SLEEP (15)
  97. #define FCON_RPA (16)
  98. #define FCON_DCF (17)
  99. #define FCON_DDF (18)
  100. #define FCON_VOPERM (24)
  101. #define FCON_SQERM (25)
  102. #define FCON_PROERM (26)
  103. #define FCON_PFSBERM (27)
  104. #define FCON_PFDBERM (29)
  105. #define FCON_EOBM (31)
  106. #define FCON_WSPFLASH_MASK (0x0f << FCON_WSPFLASH)
  107. #define FCON_WSECPF_MASK (0x01 << FCON_WSECPF)
  108. #define FCON_IDLE_MASK (0x01 << FCON_IDLE)
  109. #define FCON_ESLDIS_MASK (0x01 << FCON_ESLDIS)
  110. #define FCON_SLEEP_MASK (0x01 << FCON_SLEEP)
  111. #define FCON_RPA_MASK (0x01 << FCON_RPA)
  112. #define FCON_DCF_MASK (0x01 << FCON_DCF)
  113. #define FCON_DDF_MASK (0x01 << FCON_DDF)
  114. #define FCON_VOPERM_MASK (0x01 << FCON_VOPERM)
  115. #define FCON_SQERM_MASK (0x01 << FCON_SQERM)
  116. #define FCON_PROERM_MASK (0x01 << FCON_PROERM)
  117. #define FCON_PFSBERM_MASK (0x01 << FCON_PFSBERM)
  118. #define FCON_PFDBERM_MASK (0x01 << FCON_PFDBERM)
  119. #define FCON_EOBM_MASK (0x01 << FCON_EOBM)
  120. /* Flash Margin Control Register */
  121. #define FLASH_REG_FLASH0_MARP (FLASH_REG_BASE | 0x2018)
  122. #define MARP_MARGIN (0)
  123. #define MARP_TRAPDIS (15)
  124. #define MARP_MARGIN_MASK (0x0f << MARP_MARGIN)
  125. #define MARP_TRAPDIS_MASK (0x01 << MARP_TRAPDIS)
  126. /* Flash Protection Registers */
  127. #define FLASH_REG_FLASH0_PROCON0 (FLASH_REG_BASE | 0x2020)
  128. #define FLASH_REG_FLASH0_PROCON1 (FLASH_REG_BASE | 0x2024)
  129. #define FLASH_REG_FLASH0_PROCON2 (FLASH_REG_BASE | 0x2028)
  130. #define PROCON_S0L (0)
  131. #define PROCON_S1L (1)
  132. #define PROCON_S2L (2)
  133. #define PROCON_S3L (3)
  134. #define PROCON_S4L (4)
  135. #define PROCON_S5L (5)
  136. #define PROCON_S6L (6)
  137. #define PROCON_S7L (7)
  138. #define PROCON_S8L (8)
  139. #define PROCON_S9L (9)
  140. #define PROCON_S10_S11L (10)
  141. #define PROCON_RPRO (15)
  142. #define PROCON_S0L_MASK (0x01 << PROCON_S0L)
  143. #define PROCON_S1L_MASK (0x01 << PROCON_S1L)
  144. #define PROCON_S2L_MASK (0x01 << PROCON_S2L)
  145. #define PROCON_S3L_MASK (0x01 << PROCON_S3L)
  146. #define PROCON_S4L_MASK (0x01 << PROCON_S4L)
  147. #define PROCON_S5L_MASK (0x01 << PROCON_S5L)
  148. #define PROCON_S6L_MASK (0x01 << PROCON_S6L)
  149. #define PROCON_S7L_MASK (0x01 << PROCON_S7L)
  150. #define PROCON_S8L_MASK (0x01 << PROCON_S8L)
  151. #define PROCON_S9L_MASK (0x01 << PROCON_S9L)
  152. #define PROCON_S10_S11L_MASK (0x01 << PROCON_S10_S11L)
  153. #define PROCON_RPRO_MASK (0x01 << PROCON_RPRO)
  154. #define FLASH_PROTECT_CONFIRMATION_CODE 0x8AFE15C3
  155. /* Flash controller configuration values */
  156. #define FLASH_ID_XMC4500 0xA2
  157. #define FLASH_ID_XMC4700_4800 0x92
  158. #define FLASH_ID_XMC4100_4200 0x9C
  159. #define FLASH_ID_XMC4400 0x9F
  160. /* Timeouts */
  161. #define FLASH_OP_TIMEOUT 5000
  162. /* Flash commands (write/erase/protect) are performed using special
  163. * command sequences that are written to magic addresses in the flash controller */
  164. /* Command sequence addresses. See reference manual, section 8: Flash Command Sequences */
  165. #define FLASH_CMD_ERASE_1 0x0C005554
  166. #define FLASH_CMD_ERASE_2 0x0C00AAA8
  167. #define FLASH_CMD_ERASE_3 FLASH_CMD_ERASE_1
  168. #define FLASH_CMD_ERASE_4 FLASH_CMD_ERASE_1
  169. #define FLASH_CMD_ERASE_5 FLASH_CMD_ERASE_2
  170. /* ERASE_6 is the sector base address */
  171. #define FLASH_CMD_CLEAR_STATUS FLASH_CMD_ERASE_1
  172. #define FLASH_CMD_ENTER_PAGEMODE FLASH_CMD_ERASE_1
  173. #define FLASH_CMD_LOAD_PAGE_1 0x0C0055F0
  174. #define FLASH_CMD_LOAD_PAGE_2 0x0C0055F4
  175. #define FLASH_CMD_WRITE_PAGE_1 FLASH_CMD_ERASE_1
  176. #define FLASH_CMD_WRITE_PAGE_2 FLASH_CMD_ERASE_2
  177. #define FLASH_CMD_WRITE_PAGE_3 FLASH_CMD_ERASE_1
  178. /* WRITE_PAGE_4 is the page base address */
  179. #define FLASH_CMD_TEMP_UNPROT_1 FLASH_CMD_ERASE_1
  180. #define FLASH_CMD_TEMP_UNPROT_2 FLASH_CMD_ERASE_2
  181. #define FLASH_CMD_TEMP_UNPROT_3 0x0C00553C
  182. #define FLASH_CMD_TEMP_UNPROT_4 FLASH_CMD_ERASE_2
  183. #define FLASH_CMD_TEMP_UNPROT_5 FLASH_CMD_ERASE_2
  184. #define FLASH_CMD_TEMP_UNPROT_6 0x0C005558
  185. struct xmc4xxx_flash_bank {
  186. bool probed;
  187. /* We need the flash controller ID to choose the sector layout */
  188. uint32_t fcon_id;
  189. /* Passwords used for protection operations */
  190. uint32_t pw1;
  191. uint32_t pw2;
  192. bool pw_set;
  193. /* Protection flags */
  194. bool read_protected;
  195. bool write_prot_otp[MAX_XMC_SECTORS];
  196. };
  197. struct xmc4xxx_command_seq {
  198. uint32_t address;
  199. uint32_t magic;
  200. };
  201. /* Sector capacities. See section 8 of xmc4x00_rm */
  202. static const unsigned int sector_capacity_8[8] = {
  203. 16, 16, 16, 16, 16, 16, 16, 128
  204. };
  205. static const unsigned int sector_capacity_9[9] = {
  206. 16, 16, 16, 16, 16, 16, 16, 128, 256
  207. };
  208. static const unsigned int sector_capacity_12[12] = {
  209. 16, 16, 16, 16, 16, 16, 16, 16, 128, 256, 256, 256
  210. };
  211. static const unsigned int sector_capacity_16[16] = {
  212. 16, 16, 16, 16, 16, 16, 16, 16, 128, 256, 256, 256, 256, 256, 256, 256
  213. };
  214. static int xmc4xxx_write_command_sequence(struct flash_bank *bank,
  215. struct xmc4xxx_command_seq *seq,
  216. int seq_len)
  217. {
  218. int res = ERROR_OK;
  219. for (int i = 0; i < seq_len; i++) {
  220. res = target_write_u32(bank->target, seq[i].address,
  221. seq[i].magic);
  222. if (res != ERROR_OK)
  223. return res;
  224. }
  225. return ERROR_OK;
  226. }
  227. static int xmc4xxx_load_bank_layout(struct flash_bank *bank)
  228. {
  229. const unsigned int *capacity = NULL;
  230. /* At this point, we know which flash controller ID we're
  231. * talking to and simply need to fill out the bank structure accordingly */
  232. LOG_DEBUG("%d sectors", bank->num_sectors);
  233. switch (bank->num_sectors) {
  234. case 8:
  235. capacity = sector_capacity_8;
  236. break;
  237. case 9:
  238. capacity = sector_capacity_9;
  239. break;
  240. case 12:
  241. capacity = sector_capacity_12;
  242. break;
  243. case 16:
  244. capacity = sector_capacity_16;
  245. break;
  246. default:
  247. LOG_ERROR("Unexpected number of sectors, %d\n",
  248. bank->num_sectors);
  249. return ERROR_FAIL;
  250. }
  251. /* This looks like a bank that we understand, now we know the
  252. * corresponding sector capacities and we can add those up into the
  253. * bank size. */
  254. uint32_t total_offset = 0;
  255. bank->sectors = calloc(bank->num_sectors,
  256. sizeof(struct flash_sector));
  257. for (int i = 0; i < bank->num_sectors; i++) {
  258. bank->sectors[i].size = capacity[i] * 1024;
  259. bank->sectors[i].offset = total_offset;
  260. bank->sectors[i].is_erased = -1;
  261. bank->sectors[i].is_protected = -1;
  262. bank->size += bank->sectors[i].size;
  263. LOG_DEBUG("\t%d: %uk", i, capacity[i]);
  264. total_offset += bank->sectors[i].size;
  265. }
  266. /* This part doesn't follow the typical standard of 0xff
  267. * being the default padding value.*/
  268. bank->default_padded_value = 0x00;
  269. return ERROR_OK;
  270. }
  271. static int xmc4xxx_probe(struct flash_bank *bank)
  272. {
  273. int res;
  274. uint32_t devid, config;
  275. struct xmc4xxx_flash_bank *fb = bank->driver_priv;
  276. uint8_t flash_id;
  277. if (fb->probed)
  278. return ERROR_OK;
  279. /* It's not possible for the DAP to access the OTP locations needed for
  280. * probing the part info and Flash geometry so we require that the target
  281. * be halted before proceeding. */
  282. if (bank->target->state != TARGET_HALTED) {
  283. LOG_WARNING("Cannot communicate... target not halted.");
  284. return ERROR_TARGET_NOT_HALTED;
  285. }
  286. /* The SCU registers contain the ID of the chip */
  287. res = target_read_u32(bank->target, SCU_REG_BASE + SCU_ID_CHIP, &devid);
  288. if (res != ERROR_OK) {
  289. LOG_ERROR("Cannot read device identification register.");
  290. return res;
  291. }
  292. /* Make sure this is a XMC4000 family device */
  293. if ((devid & 0xF0000) != 0x40000 && devid != 0) {
  294. LOG_ERROR("Platform ID doesn't match XMC4xxx: 0x%08" PRIx32, devid);
  295. return ERROR_FAIL;
  296. }
  297. LOG_DEBUG("Found XMC4xxx with devid: 0x%08" PRIx32, devid);
  298. /* Now sanity-check the Flash controller itself. */
  299. res = target_read_u32(bank->target, FLASH_REG_FLASH0_ID,
  300. &config);
  301. if (res != ERROR_OK) {
  302. LOG_ERROR("Cannot read Flash bank configuration.");
  303. return res;
  304. }
  305. flash_id = (config & 0xff0000) >> 16;
  306. /* The Flash configuration register is our only means of
  307. * determining the sector layout. We need to make sure that
  308. * we understand the type of controller we're dealing with */
  309. switch (flash_id) {
  310. case FLASH_ID_XMC4100_4200:
  311. bank->num_sectors = 8;
  312. LOG_DEBUG("XMC4xxx: XMC4100/4200 detected.");
  313. break;
  314. case FLASH_ID_XMC4400:
  315. bank->num_sectors = 9;
  316. LOG_DEBUG("XMC4xxx: XMC4400 detected.");
  317. break;
  318. case FLASH_ID_XMC4500:
  319. bank->num_sectors = 12;
  320. LOG_DEBUG("XMC4xxx: XMC4500 detected.");
  321. break;
  322. case FLASH_ID_XMC4700_4800:
  323. bank->num_sectors = 16;
  324. LOG_DEBUG("XMC4xxx: XMC4700/4800 detected.");
  325. break;
  326. default:
  327. LOG_ERROR("XMC4xxx: Unexpected flash ID. got %02" PRIx8,
  328. flash_id);
  329. return ERROR_FAIL;
  330. }
  331. /* Retrieve information about the particular bank we're probing and fill in
  332. * the bank structure accordingly. */
  333. res = xmc4xxx_load_bank_layout(bank);
  334. if (res == ERROR_OK) {
  335. /* We're done */
  336. fb->probed = true;
  337. } else {
  338. LOG_ERROR("Unable to load bank information.");
  339. return ERROR_FAIL;
  340. }
  341. return ERROR_OK;
  342. }
  343. static int xmc4xxx_get_sector_start_addr(struct flash_bank *bank,
  344. int sector, uint32_t *ret_addr)
  345. {
  346. /* Make sure we understand this sector */
  347. if (sector > bank->num_sectors)
  348. return ERROR_FAIL;
  349. *ret_addr = bank->base + bank->sectors[sector].offset;
  350. return ERROR_OK;
  351. }
  352. static int xmc4xxx_clear_flash_status(struct flash_bank *bank)
  353. {
  354. int res;
  355. /* TODO: Do we need to check for sequence error? */
  356. LOG_INFO("Clearing flash status");
  357. res = target_write_u32(bank->target, FLASH_CMD_CLEAR_STATUS,
  358. 0xF5);
  359. if (res != ERROR_OK) {
  360. LOG_ERROR("Unable to write erase command sequence");
  361. return res;
  362. }
  363. return ERROR_OK;
  364. }
  365. static int xmc4xxx_get_flash_status(struct flash_bank *bank, uint32_t *status)
  366. {
  367. int res;
  368. res = target_read_u32(bank->target, FLASH_REG_FLASH0_FSR, status);
  369. if (res != ERROR_OK)
  370. LOG_ERROR("Cannot read flash status register.");
  371. return res;
  372. }
  373. static int xmc4xxx_wait_status_busy(struct flash_bank *bank, int timeout)
  374. {
  375. int res;
  376. uint32_t status;
  377. res = xmc4xxx_get_flash_status(bank, &status);
  378. if (res != ERROR_OK)
  379. return res;
  380. /* While the flash controller is busy, wait */
  381. while (status & FSR_PBUSY_MASK) {
  382. res = xmc4xxx_get_flash_status(bank, &status);
  383. if (res != ERROR_OK)
  384. return res;
  385. if (timeout-- <= 0) {
  386. LOG_ERROR("Timed out waiting for flash");
  387. return ERROR_FAIL;
  388. }
  389. alive_sleep(1);
  390. keep_alive();
  391. }
  392. if (status & FSR_PROER_MASK) {
  393. LOG_ERROR("XMC4xxx flash protected");
  394. res = ERROR_FAIL;
  395. }
  396. return res;
  397. }
  398. static int xmc4xxx_erase_sector(struct flash_bank *bank, uint32_t address,
  399. bool user_config)
  400. {
  401. int res;
  402. uint32_t status;
  403. /* See reference manual table 8.4: Command Sequences for Flash Control */
  404. struct xmc4xxx_command_seq erase_cmd_seq[6] = {
  405. {FLASH_CMD_ERASE_1, 0xAA},
  406. {FLASH_CMD_ERASE_2, 0x55},
  407. {FLASH_CMD_ERASE_3, 0x80},
  408. {FLASH_CMD_ERASE_4, 0xAA},
  409. {FLASH_CMD_ERASE_5, 0x55},
  410. {0xFF, 0xFF} /* Needs filled in */
  411. };
  412. /* We need to fill in the base address of the sector we'll be
  413. * erasing, as well as the magic code that determines whether
  414. * this is a standard flash sector or a user configuration block */
  415. erase_cmd_seq[5].address = address;
  416. if (user_config) {
  417. /* Removing flash protection requires the addition of
  418. * the base address */
  419. erase_cmd_seq[5].address += bank->base;
  420. erase_cmd_seq[5].magic = 0xC0;
  421. } else {
  422. erase_cmd_seq[5].magic = 0x30;
  423. }
  424. res = xmc4xxx_write_command_sequence(bank, erase_cmd_seq,
  425. ARRAY_SIZE(erase_cmd_seq));
  426. if (res != ERROR_OK)
  427. return res;
  428. /* Read the flash status register */
  429. res = target_read_u32(bank->target, FLASH_REG_FLASH0_FSR, &status);
  430. if (res != ERROR_OK) {
  431. LOG_ERROR("Cannot read flash status register.");
  432. return res;
  433. }
  434. /* Check for a sequence error */
  435. if (status & FSR_SQER_MASK) {
  436. LOG_ERROR("Error with flash erase sequence");
  437. return ERROR_FAIL;
  438. }
  439. /* Make sure a flash erase was triggered */
  440. if (!(status & FSR_ERASE_MASK)) {
  441. LOG_ERROR("Flash failed to erase");
  442. return ERROR_FAIL;
  443. }
  444. /* Now we must wait for the erase operation to end */
  445. res = xmc4xxx_wait_status_busy(bank, FLASH_OP_TIMEOUT);
  446. return res;
  447. }
  448. static int xmc4xxx_erase(struct flash_bank *bank, int first, int last)
  449. {
  450. struct xmc4xxx_flash_bank *fb = bank->driver_priv;
  451. int res;
  452. if (bank->target->state != TARGET_HALTED) {
  453. LOG_ERROR("Unable to erase, target is not halted");
  454. return ERROR_TARGET_NOT_HALTED;
  455. }
  456. if (!fb->probed) {
  457. res = xmc4xxx_probe(bank);
  458. if (res != ERROR_OK)
  459. return res;
  460. }
  461. uint32_t tmp_addr;
  462. /* Loop through the sectors and erase each one */
  463. for (int i = first; i <= last; i++) {
  464. res = xmc4xxx_get_sector_start_addr(bank, i, &tmp_addr);
  465. if (res != ERROR_OK) {
  466. LOG_ERROR("Invalid sector %d", i);
  467. return res;
  468. }
  469. LOG_DEBUG("Erasing sector %d @ 0x%08"PRIx32, i, tmp_addr);
  470. res = xmc4xxx_erase_sector(bank, tmp_addr, false);
  471. if (res != ERROR_OK) {
  472. LOG_ERROR("Unable to write erase command sequence");
  473. goto clear_status_and_exit;
  474. }
  475. /* Now we must wait for the erase operation to end */
  476. res = xmc4xxx_wait_status_busy(bank, FLASH_OP_TIMEOUT);
  477. if (res != ERROR_OK)
  478. goto clear_status_and_exit;
  479. bank->sectors[i].is_erased = 1;
  480. }
  481. clear_status_and_exit:
  482. res = xmc4xxx_clear_flash_status(bank);
  483. return res;
  484. }
  485. static int xmc4xxx_enter_page_mode(struct flash_bank *bank)
  486. {
  487. int res;
  488. uint32_t status;
  489. res = target_write_u32(bank->target, FLASH_CMD_ENTER_PAGEMODE, 0x50);
  490. if (res != ERROR_OK) {
  491. LOG_ERROR("Unable to write enter page mode command");
  492. return ERROR_FAIL;
  493. }
  494. res = xmc4xxx_get_flash_status(bank, &status);
  495. if (res != ERROR_OK)
  496. return res;
  497. /* Make sure we're in page mode */
  498. if (!(status & FSR_PFPAGE_MASK)) {
  499. LOG_ERROR("Unable to enter page mode");
  500. return ERROR_FAIL;
  501. }
  502. /* Make sure we didn't encounter a sequence error */
  503. if (status & FSR_SQER_MASK) {
  504. LOG_ERROR("Sequence error while entering page mode");
  505. return ERROR_FAIL;
  506. }
  507. return res;
  508. }
  509. /* The logical erase value of an xmc4xxx memory cell is 0x00,
  510. * therefore, we cannot use the built in flash blank check and must
  511. * implement our own */
  512. /** Checks whether a memory region is zeroed. */
  513. int xmc4xxx_blank_check_memory(struct target *target,
  514. uint32_t address, uint32_t count, uint32_t *blank)
  515. {
  516. struct working_area *erase_check_algorithm;
  517. struct reg_param reg_params[3];
  518. struct armv7m_algorithm armv7m_info;
  519. int retval;
  520. static const uint8_t erase_check_code[] = {
  521. #include "../../../contrib/loaders/erase_check/armv7m_0_erase_check.inc"
  522. };
  523. /* make sure we have a working area */
  524. if (target_alloc_working_area(target, sizeof(erase_check_code),
  525. &erase_check_algorithm) != ERROR_OK)
  526. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  527. retval = target_write_buffer(target, erase_check_algorithm->address,
  528. sizeof(erase_check_code), (uint8_t *)erase_check_code);
  529. if (retval != ERROR_OK)
  530. return retval;
  531. armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
  532. armv7m_info.core_mode = ARM_MODE_THREAD;
  533. init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
  534. buf_set_u32(reg_params[0].value, 0, 32, address);
  535. init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
  536. buf_set_u32(reg_params[1].value, 0, 32, count);
  537. init_reg_param(&reg_params[2], "r2", 32, PARAM_IN_OUT);
  538. buf_set_u32(reg_params[2].value, 0, 32, 0x00);
  539. retval = target_run_algorithm(target,
  540. 0,
  541. NULL,
  542. 3,
  543. reg_params,
  544. erase_check_algorithm->address,
  545. erase_check_algorithm->address + (sizeof(erase_check_code) - 2),
  546. 10000,
  547. &armv7m_info);
  548. if (retval == ERROR_OK)
  549. *blank = buf_get_u32(reg_params[2].value, 0, 32);
  550. destroy_reg_param(&reg_params[0]);
  551. destroy_reg_param(&reg_params[1]);
  552. destroy_reg_param(&reg_params[2]);
  553. target_free_working_area(target, erase_check_algorithm);
  554. return retval;
  555. }
  556. static int xmc4xxx_flash_blank_check(struct flash_bank *bank)
  557. {
  558. struct target *target = bank->target;
  559. int i;
  560. int retval;
  561. uint32_t blank;
  562. if (bank->target->state != TARGET_HALTED) {
  563. LOG_ERROR("Target not halted");
  564. return ERROR_TARGET_NOT_HALTED;
  565. }
  566. for (i = 0; i < bank->num_sectors; i++) {
  567. uint32_t address = bank->base + bank->sectors[i].offset;
  568. uint32_t size = bank->sectors[i].size;
  569. LOG_DEBUG("Erase checking 0x%08"PRIx32, address);
  570. retval = xmc4xxx_blank_check_memory(target, address, size, &blank);
  571. if (retval != ERROR_OK)
  572. break;
  573. if (blank == 0x00)
  574. bank->sectors[i].is_erased = 1;
  575. else
  576. bank->sectors[i].is_erased = 0;
  577. }
  578. return ERROR_OK;
  579. }
  580. static int xmc4xxx_write_page(struct flash_bank *bank, const uint8_t *pg_buf,
  581. uint32_t offset, bool user_config)
  582. {
  583. int res;
  584. uint32_t status;
  585. /* Base of the flash write command */
  586. struct xmc4xxx_command_seq write_cmd_seq[4] = {
  587. {FLASH_CMD_WRITE_PAGE_1, 0xAA},
  588. {FLASH_CMD_WRITE_PAGE_2, 0x55},
  589. {FLASH_CMD_WRITE_PAGE_3, 0xFF}, /* Needs filled in */
  590. {0xFF, 0xFF} /* Needs filled in */
  591. };
  592. /* The command sequence differs depending on whether this is
  593. * being written to standard flash or the user configuration
  594. * area */
  595. if (user_config)
  596. write_cmd_seq[2].magic = 0xC0;
  597. else
  598. write_cmd_seq[2].magic = 0xA0;
  599. /* Finally, we need to add the address that this page will be
  600. * written to */
  601. write_cmd_seq[3].address = bank->base + offset;
  602. write_cmd_seq[3].magic = 0xAA;
  603. /* Flash pages are written 256 bytes at a time. For each 256
  604. * byte chunk, we need to:
  605. * 1. Enter page mode. This activates the flash write buffer
  606. * 2. Load the page buffer with data (2x 32 bit words at a time)
  607. * 3. Burn the page buffer into its intended location
  608. * If the starting offset is not on a 256 byte boundary, we
  609. * will need to pad the beginning of the write buffer
  610. * accordingly. Likewise, if the last page does not fill the
  611. * buffer, we should pad it to avoid leftover data from being
  612. * written to flash
  613. */
  614. res = xmc4xxx_enter_page_mode(bank);
  615. if (res != ERROR_OK)
  616. return res;
  617. /* Copy the data into the page buffer*/
  618. for (int i = 0; i < 256; i += 8) {
  619. uint32_t w_lo = target_buffer_get_u32(bank->target, &pg_buf[i]);
  620. uint32_t w_hi = target_buffer_get_u32(bank->target, &pg_buf[i + 4]);
  621. LOG_DEBUG("WLO: %08"PRIx32, w_lo);
  622. LOG_DEBUG("WHI: %08"PRIx32, w_hi);
  623. /* Data is loaded 2x 32 bit words at a time */
  624. res = target_write_u32(bank->target, FLASH_CMD_LOAD_PAGE_1, w_lo);
  625. if (res != ERROR_OK)
  626. return res;
  627. res = target_write_u32(bank->target, FLASH_CMD_LOAD_PAGE_2, w_hi);
  628. if (res != ERROR_OK)
  629. return res;
  630. /* Check for an error */
  631. res = xmc4xxx_get_flash_status(bank, &status);
  632. if (res != ERROR_OK)
  633. return res;
  634. if (status & FSR_SQER_MASK) {
  635. LOG_ERROR("Error loading page buffer");
  636. return ERROR_FAIL;
  637. }
  638. }
  639. /* The page buffer is now full, time to commit it to flash */
  640. res = xmc4xxx_write_command_sequence(bank, write_cmd_seq, ARRAY_SIZE(write_cmd_seq));
  641. if (res != ERROR_OK) {
  642. LOG_ERROR("Unable to enter write command sequence");
  643. return res;
  644. }
  645. /* Read the flash status register */
  646. res = xmc4xxx_get_flash_status(bank, &status);
  647. if (res != ERROR_OK)
  648. return res;
  649. /* Check for a sequence error */
  650. if (status & FSR_SQER_MASK) {
  651. LOG_ERROR("Error with flash write sequence");
  652. return ERROR_FAIL;
  653. }
  654. /* Make sure a flash write was triggered */
  655. if (!(status & FSR_PROG_MASK)) {
  656. LOG_ERROR("Failed to write flash page");
  657. return ERROR_FAIL;
  658. }
  659. /* Wait for the write operation to end */
  660. res = xmc4xxx_wait_status_busy(bank, FLASH_OP_TIMEOUT);
  661. if (res != ERROR_OK)
  662. return res;
  663. /* TODO: Verify that page was written without error */
  664. return res;
  665. }
  666. static int xmc4xxx_write(struct flash_bank *bank, const uint8_t *buffer,
  667. uint32_t offset, uint32_t count)
  668. {
  669. struct xmc4xxx_flash_bank *fb = bank->driver_priv;
  670. int res = ERROR_OK;
  671. if (bank->target->state != TARGET_HALTED) {
  672. LOG_ERROR("Unable to erase, target is not halted");
  673. return ERROR_TARGET_NOT_HALTED;
  674. }
  675. if (!fb->probed) {
  676. res = xmc4xxx_probe(bank);
  677. if (res != ERROR_OK)
  678. return res;
  679. }
  680. /* Make sure we won't run off the end of the flash bank */
  681. if ((offset + count) > (bank->size)) {
  682. LOG_ERROR("Attempting to write past the end of flash");
  683. return ERROR_FAIL;
  684. }
  685. /* Attempt to write the passed in buffer to flash */
  686. /* Pages are written 256 bytes at a time, we need to handle
  687. * scenarios where padding is required at the beginning and
  688. * end of a page */
  689. while (count) {
  690. /* page working area */
  691. uint8_t tmp_buf[256] = {0};
  692. /* Amount of data we'll be writing to this page */
  693. int remaining;
  694. int end_pad;
  695. remaining = MIN(count, sizeof(tmp_buf));
  696. end_pad = sizeof(tmp_buf) - remaining;
  697. /* Make sure we're starting on a page boundary */
  698. int start_pad = offset % 256;
  699. if (start_pad) {
  700. LOG_INFO("Write does not start on a 256 byte boundary. "
  701. "Padding by %d bytes", start_pad);
  702. memset(tmp_buf, 0xff, start_pad);
  703. /* Subtract the amount of start offset from
  704. * the amount of data we'll need to write */
  705. remaining -= start_pad;
  706. }
  707. /* Remove the amount we'll be writing from the total count */
  708. count -= remaining;
  709. /* Now copy in the remaining data */
  710. memcpy(&tmp_buf[start_pad], buffer, remaining);
  711. if (end_pad) {
  712. LOG_INFO("Padding end of page @%08"PRIx32" by %d bytes",
  713. bank->base + offset, end_pad);
  714. memset(&tmp_buf[256 - end_pad], 0xff, end_pad);
  715. }
  716. /* Now commit this page to flash, if there was start
  717. * padding, we should subtract that from the target offset */
  718. res = xmc4xxx_write_page(bank, tmp_buf, (offset - start_pad), false);
  719. if (res != ERROR_OK) {
  720. LOG_ERROR("Unable to write flash page");
  721. goto abort_write_and_exit;
  722. }
  723. /* Advance the buffer pointer */
  724. buffer += remaining;
  725. /* Advance the offset */
  726. offset += remaining;
  727. }
  728. abort_write_and_exit:
  729. xmc4xxx_clear_flash_status(bank);
  730. return res;
  731. }
  732. static int xmc4xxx_get_info_command(struct flash_bank *bank, char *buf, int buf_size)
  733. {
  734. struct xmc4xxx_flash_bank *fb = bank->driver_priv;
  735. uint32_t scu_idcode;
  736. if (bank->target->state != TARGET_HALTED) {
  737. LOG_WARNING("Cannot communicate... target not halted.");
  738. return ERROR_TARGET_NOT_HALTED;
  739. }
  740. /* The SCU registers contain the ID of the chip */
  741. int res = target_read_u32(bank->target, SCU_REG_BASE + SCU_ID_CHIP, &scu_idcode);
  742. if (res != ERROR_OK) {
  743. LOG_ERROR("Cannot read device identification register.");
  744. return res;
  745. }
  746. uint16_t dev_id = (scu_idcode & 0xfff0) >> 4;
  747. uint16_t rev_id = scu_idcode & 0xf;
  748. const char *dev_str;
  749. const char *rev_str = NULL;
  750. switch (dev_id) {
  751. case 0x100:
  752. dev_str = "XMC4100";
  753. switch (rev_id) {
  754. case 0x1:
  755. rev_str = "AA";
  756. break;
  757. case 0x2:
  758. rev_str = "AB";
  759. break;
  760. }
  761. break;
  762. case 0x200:
  763. dev_str = "XMC4200";
  764. switch (rev_id) {
  765. case 0x1:
  766. rev_str = "AA";
  767. break;
  768. case 0x2:
  769. rev_str = "AB";
  770. break;
  771. }
  772. break;
  773. case 0x400:
  774. dev_str = "XMC4400";
  775. switch (rev_id) {
  776. case 0x1:
  777. rev_str = "AA";
  778. break;
  779. case 0x2:
  780. rev_str = "AB";
  781. break;
  782. }
  783. break;
  784. case 0:
  785. /* XMC4500 EES AA13 with date codes before GE212
  786. * had zero SCU_IDCHIP
  787. */
  788. dev_str = "XMC4500 EES";
  789. rev_str = "AA13";
  790. break;
  791. case 0x500:
  792. dev_str = "XMC4500";
  793. switch (rev_id) {
  794. case 0x2:
  795. rev_str = "AA";
  796. break;
  797. case 0x3:
  798. rev_str = "AB";
  799. break;
  800. case 0x4:
  801. rev_str = "AC";
  802. break;
  803. }
  804. break;
  805. case 0x700:
  806. dev_str = "XMC4700";
  807. switch (rev_id) {
  808. case 0x1:
  809. rev_str = "EES-AA";
  810. break;
  811. }
  812. break;
  813. case 0x800:
  814. dev_str = "XMC4800";
  815. switch (rev_id) {
  816. case 0x1:
  817. rev_str = "EES-AA";
  818. break;
  819. }
  820. break;
  821. default:
  822. snprintf(buf, buf_size,
  823. "Cannot identify target as an XMC4xxx. SCU_ID: %"PRIx32"\n",
  824. scu_idcode);
  825. return ERROR_OK;
  826. }
  827. /* String to declare protection data held in the private driver */
  828. char prot_str[512] = {0};
  829. if (fb->read_protected)
  830. snprintf(prot_str, sizeof(prot_str), "\nFlash is read protected");
  831. bool otp_enabled = false;
  832. for (int i = 0; i < bank->num_sectors; i++)
  833. if (fb->write_prot_otp[i])
  834. otp_enabled = true;
  835. /* If OTP Write protection is enabled (User 2), list each
  836. * sector that has it enabled */
  837. char otp_str[8];
  838. if (otp_enabled) {
  839. strcat(prot_str, "\nOTP Protection is enabled for sectors:\n");
  840. for (int i = 0; i < bank->num_sectors; i++) {
  841. if (fb->write_prot_otp[i]) {
  842. snprintf(otp_str, sizeof(otp_str), "- %d\n", i);
  843. strncat(prot_str, otp_str, ARRAY_SIZE(otp_str));
  844. }
  845. }
  846. }
  847. if (rev_str != NULL)
  848. snprintf(buf, buf_size, "%s - Rev: %s%s",
  849. dev_str, rev_str, prot_str);
  850. else
  851. snprintf(buf, buf_size, "%s - Rev: unknown (0x%01x)%s",
  852. dev_str, rev_id, prot_str);
  853. return ERROR_OK;
  854. }
  855. static int xmc4xxx_temp_unprotect(struct flash_bank *bank, int user_level)
  856. {
  857. struct xmc4xxx_flash_bank *fb;
  858. int res = ERROR_OK;
  859. uint32_t status = 0;
  860. struct xmc4xxx_command_seq temp_unprot_seq[6] = {
  861. {FLASH_CMD_TEMP_UNPROT_1, 0xAA},
  862. {FLASH_CMD_TEMP_UNPROT_2, 0x55},
  863. {FLASH_CMD_TEMP_UNPROT_3, 0xFF}, /* Needs filled in */
  864. {FLASH_CMD_TEMP_UNPROT_4, 0xFF}, /* Needs filled in */
  865. {FLASH_CMD_TEMP_UNPROT_5, 0xFF}, /* Needs filled in */
  866. {FLASH_CMD_TEMP_UNPROT_6, 0x05}
  867. };
  868. if (user_level < 0 || user_level > 2) {
  869. LOG_ERROR("Invalid user level, must be 0-2");
  870. return ERROR_FAIL;
  871. }
  872. fb = bank->driver_priv;
  873. /* Fill in the user level and passwords */
  874. temp_unprot_seq[2].magic = user_level;
  875. temp_unprot_seq[3].magic = fb->pw1;
  876. temp_unprot_seq[4].magic = fb->pw2;
  877. res = xmc4xxx_write_command_sequence(bank, temp_unprot_seq,
  878. ARRAY_SIZE(temp_unprot_seq));
  879. if (res != ERROR_OK) {
  880. LOG_ERROR("Unable to write temp unprotect sequence");
  881. return res;
  882. }
  883. res = xmc4xxx_get_flash_status(bank, &status);
  884. if (res != ERROR_OK)
  885. return res;
  886. if (status & FSR_WPRODIS0) {
  887. LOG_INFO("Flash is temporarily unprotected");
  888. } else {
  889. LOG_INFO("Unable to disable flash protection");
  890. res = ERROR_FAIL;
  891. }
  892. return res;
  893. }
  894. static int xmc4xxx_flash_unprotect(struct flash_bank *bank, int32_t level)
  895. {
  896. uint32_t addr;
  897. int res;
  898. if ((level < 0) || (level > 1)) {
  899. LOG_ERROR("Invalid user level. Must be 0-1");
  900. return ERROR_FAIL;
  901. }
  902. switch (level) {
  903. case 0:
  904. addr = UCB0_BASE;
  905. break;
  906. case 1:
  907. addr = UCB1_BASE;
  908. break;
  909. }
  910. res = xmc4xxx_erase_sector(bank, addr, true);
  911. if (res != ERROR_OK)
  912. LOG_ERROR("Error erasing user configuration block");
  913. return res;
  914. }
  915. /* Reference: "XMC4500 Flash Protection.pptx" app note */
  916. static int xmc4xxx_flash_protect(struct flash_bank *bank, int level, bool read_protect,
  917. int first, int last)
  918. {
  919. /* User configuration block buffers */
  920. uint8_t ucp0_buf[8 * sizeof(uint32_t)] = {0};
  921. uint32_t ucb_base = 0;
  922. uint32_t procon = 0;
  923. int res = ERROR_OK;
  924. uint32_t status = 0;
  925. bool proin = false;
  926. struct xmc4xxx_flash_bank *fb = bank->driver_priv;
  927. /* Read protect only works for user 0, make sure we don't try
  928. * to do something silly */
  929. if (level != 0 && read_protect) {
  930. LOG_ERROR("Read protection is for user level 0 only!");
  931. return ERROR_FAIL;
  932. }
  933. /* Check to see if protection is already installed for the
  934. * specified user level. If it is, the user configuration
  935. * block will need to be erased before we can continue */
  936. /* Grab the flash status register*/
  937. res = xmc4xxx_get_flash_status(bank, &status);
  938. if (res != ERROR_OK)
  939. return res;
  940. switch (level) {
  941. case 0:
  942. if ((status & FSR_RPROIN_MASK) || (status & FSR_WPROIN0_MASK))
  943. proin = true;
  944. break;
  945. case 1:
  946. if (status & FSR_WPROIN1_MASK)
  947. proin = true;
  948. break;
  949. case 2:
  950. if (status & FSR_WPROIN2_MASK)
  951. proin = true;
  952. break;
  953. }
  954. if (proin) {
  955. LOG_ERROR("Flash protection is installed for user %d"
  956. " and must be removed before continuing", level);
  957. return ERROR_FAIL;
  958. }
  959. /* If this device has 12 flash sectors, protection for
  960. * sectors 10 & 11 are handled jointly. If we are trying to
  961. * write all sectors, we should decrement
  962. * last to ensure we don't write to a register bit that
  963. * doesn't exist*/
  964. if ((bank->num_sectors == 12) && (last == 12))
  965. last--;
  966. /* We need to fill out the procon register representation
  967. * that we will be writing to the device */
  968. for (int i = first; i <= last; i++)
  969. procon |= 1 << i;
  970. /* If read protection is requested, set the appropriate bit
  971. * (we checked that this is allowed above) */
  972. if (read_protect)
  973. procon |= PROCON_RPRO_MASK;
  974. LOG_DEBUG("Setting flash protection with procon:");
  975. LOG_DEBUG("PROCON: %"PRIx32, procon);
  976. /* First we need to copy in the procon register to the buffer
  977. * we're going to attempt to write. This is written twice */
  978. target_buffer_set_u32(bank->target, &ucp0_buf[0 * 4], procon);
  979. target_buffer_set_u32(bank->target, &ucp0_buf[2 * 4], procon);
  980. /* Now we must copy in both flash passwords. As with the
  981. * procon data, this must be written twice (4 total words
  982. * worth of data) */
  983. target_buffer_set_u32(bank->target, &ucp0_buf[4 * 4], fb->pw1);
  984. target_buffer_set_u32(bank->target, &ucp0_buf[5 * 4], fb->pw2);
  985. target_buffer_set_u32(bank->target, &ucp0_buf[6 * 4], fb->pw1);
  986. target_buffer_set_u32(bank->target, &ucp0_buf[7 * 4], fb->pw2);
  987. /* Finally, (if requested) we copy in the confirmation
  988. * code so that the protection is permanent and will
  989. * require a password to undo. */
  990. target_buffer_set_u32(bank->target, &ucp0_buf[0 * 4], FLASH_PROTECT_CONFIRMATION_CODE);
  991. target_buffer_set_u32(bank->target, &ucp0_buf[2 * 4], FLASH_PROTECT_CONFIRMATION_CODE);
  992. /* Now that the data is copied into place, we must write
  993. * these pages into flash */
  994. /* The user configuration block base depends on what level of
  995. * protection we're trying to install, select the proper one */
  996. switch (level) {
  997. case 0:
  998. ucb_base = UCB0_BASE;
  999. break;
  1000. case 1:
  1001. ucb_base = UCB1_BASE;
  1002. break;
  1003. case 2:
  1004. ucb_base = UCB2_BASE;
  1005. break;
  1006. }
  1007. /* Write the user config pages */
  1008. res = xmc4xxx_write_page(bank, ucp0_buf, ucb_base, true);
  1009. if (res != ERROR_OK) {
  1010. LOG_ERROR("Error writing user configuration block 0");
  1011. return res;
  1012. }
  1013. return ERROR_OK;
  1014. }
  1015. static int xmc4xxx_protect(struct flash_bank *bank, int set, int first, int last)
  1016. {
  1017. int ret;
  1018. struct xmc4xxx_flash_bank *fb = bank->driver_priv;
  1019. /* Check for flash passwords */
  1020. if (!fb->pw_set) {
  1021. LOG_ERROR("Flash passwords not set, use xmc4xxx flash_password to set them");
  1022. return ERROR_FAIL;
  1023. }
  1024. /* We want to clear flash protection temporarily*/
  1025. if (set == 0) {
  1026. LOG_WARNING("Flash protection will be temporarily disabled"
  1027. " for all pages (User 0 only)!");
  1028. ret = xmc4xxx_temp_unprotect(bank, 0);
  1029. return ret;
  1030. }
  1031. /* Install write protection for user 0 on the specified pages */
  1032. ret = xmc4xxx_flash_protect(bank, 0, false, first, last);
  1033. return ret;
  1034. }
  1035. static int xmc4xxx_protect_check(struct flash_bank *bank)
  1036. {
  1037. int ret;
  1038. uint32_t protection[3] = {0};
  1039. struct xmc4xxx_flash_bank *fb = bank->driver_priv;
  1040. ret = target_read_u32(bank->target, FLASH_REG_FLASH0_PROCON0, &protection[0]);
  1041. if (ret != ERROR_OK) {
  1042. LOG_ERROR("Unable to read flash User0 protection register");
  1043. return ret;
  1044. }
  1045. ret = target_read_u32(bank->target, FLASH_REG_FLASH0_PROCON1, &protection[1]);
  1046. if (ret != ERROR_OK) {
  1047. LOG_ERROR("Unable to read flash User1 protection register");
  1048. return ret;
  1049. }
  1050. ret = target_read_u32(bank->target, FLASH_REG_FLASH0_PROCON2, &protection[2]);
  1051. if (ret != ERROR_OK) {
  1052. LOG_ERROR("Unable to read flash User2 protection register");
  1053. return ret;
  1054. }
  1055. int sectors = bank->num_sectors;
  1056. /* On devices with 12 sectors, sectors 10 & 11 are ptected
  1057. * together instead of individually */
  1058. if (sectors == 12)
  1059. sectors--;
  1060. /* Clear the protection status */
  1061. for (int i = 0; i < bank->num_sectors; i++) {
  1062. bank->sectors[i].is_protected = 0;
  1063. fb->write_prot_otp[i] = false;
  1064. }
  1065. fb->read_protected = false;
  1066. /* The xmc4xxx series supports 3 levels of user protection
  1067. * (User0, User1 (low priority), and User 2(OTP), we need to
  1068. * check all 3 */
  1069. for (unsigned int i = 0; i < ARRAY_SIZE(protection); i++) {
  1070. /* Check for write protection on every available
  1071. * sector */
  1072. for (int j = 0; j < sectors; j++) {
  1073. int set = (protection[i] & (1 << j)) ? 1 : 0;
  1074. bank->sectors[j].is_protected |= set;
  1075. /* Handle sector 11 */
  1076. if (j == 10)
  1077. bank->sectors[j + 1].is_protected |= set;
  1078. /* User 2 indicates this protection is
  1079. * permanent, make note in the private driver structure */
  1080. if (i == 2 && set) {
  1081. fb->write_prot_otp[j] = true;
  1082. /* Handle sector 11 */
  1083. if (j == 10)
  1084. fb->write_prot_otp[j + 1] = true;
  1085. }
  1086. }
  1087. }
  1088. /* XMC4xxx also supports read proptection, make a note
  1089. * in the private driver structure */
  1090. if (protection[0] & PROCON_RPRO_MASK)
  1091. fb->read_protected = true;
  1092. return ERROR_OK;
  1093. }
  1094. FLASH_BANK_COMMAND_HANDLER(xmc4xxx_flash_bank_command)
  1095. {
  1096. bank->driver_priv = malloc(sizeof(struct xmc4xxx_flash_bank));
  1097. if (!bank->driver_priv)
  1098. return ERROR_FLASH_OPERATION_FAILED;
  1099. (void)memset(bank->driver_priv, 0, sizeof(struct xmc4xxx_flash_bank));
  1100. return ERROR_OK;
  1101. }
  1102. COMMAND_HANDLER(xmc4xxx_handle_flash_password_command)
  1103. {
  1104. int res;
  1105. struct flash_bank *bank;
  1106. if (CMD_ARGC < 3)
  1107. return ERROR_COMMAND_SYNTAX_ERROR;
  1108. res = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
  1109. if (res != ERROR_OK)
  1110. return res;
  1111. struct xmc4xxx_flash_bank *fb = bank->driver_priv;
  1112. errno = 0;
  1113. /* We skip over the flash bank */
  1114. fb->pw1 = strtol(CMD_ARGV[1], NULL, 16);
  1115. if (errno)
  1116. return ERROR_COMMAND_SYNTAX_ERROR;
  1117. fb->pw2 = strtol(CMD_ARGV[2], NULL, 16);
  1118. if (errno)
  1119. return ERROR_COMMAND_SYNTAX_ERROR;
  1120. fb->pw_set = true;
  1121. command_print(CMD_CTX, "XMC4xxx flash passwords set to:\n");
  1122. command_print(CMD_CTX, "-0x%08"PRIx32"\n", fb->pw1);
  1123. command_print(CMD_CTX, "-0x%08"PRIx32"\n", fb->pw2);
  1124. return ERROR_OK;
  1125. }
  1126. COMMAND_HANDLER(xmc4xxx_handle_flash_unprotect_command)
  1127. {
  1128. struct flash_bank *bank;
  1129. int res;
  1130. int32_t level;
  1131. if (CMD_ARGC < 2)
  1132. return ERROR_COMMAND_SYNTAX_ERROR;
  1133. res = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
  1134. if (res != ERROR_OK)
  1135. return res;
  1136. COMMAND_PARSE_NUMBER(s32, CMD_ARGV[1], level);
  1137. res = xmc4xxx_flash_unprotect(bank, level);
  1138. return res;
  1139. }
  1140. static const struct command_registration xmc4xxx_exec_command_handlers[] = {
  1141. {
  1142. .name = "flash_password",
  1143. .handler = xmc4xxx_handle_flash_password_command,
  1144. .mode = COMMAND_EXEC,
  1145. .usage = "bank_id password1 password2",
  1146. .help = "Set the flash passwords used for protect operations. "
  1147. "Passwords should be in standard hex form (0x00000000). "
  1148. "(You must call this before any other protect commands) "
  1149. "NOTE: The xmc4xxx's UCB area only allows for FOUR cycles. "
  1150. "Please use protection carefully!",
  1151. },
  1152. {
  1153. .name = "flash_unprotect",
  1154. .handler = xmc4xxx_handle_flash_unprotect_command,
  1155. .mode = COMMAND_EXEC,
  1156. .usage = "bank_id user_level[0-1]",
  1157. .help = "Permanently Removes flash protection (read and write) "
  1158. "for the specified user level",
  1159. }, COMMAND_REGISTRATION_DONE
  1160. };
  1161. static const struct command_registration xmc4xxx_command_handlers[] = {
  1162. {
  1163. .name = "xmc4xxx",
  1164. .mode = COMMAND_ANY,
  1165. .help = "xmc4xxx flash command group",
  1166. .usage = "",
  1167. .chain = xmc4xxx_exec_command_handlers,
  1168. },
  1169. COMMAND_REGISTRATION_DONE
  1170. };
  1171. struct flash_driver xmc4xxx_flash = {
  1172. .name = "xmc4xxx",
  1173. .commands = xmc4xxx_command_handlers,
  1174. .flash_bank_command = xmc4xxx_flash_bank_command,
  1175. .erase = xmc4xxx_erase,
  1176. .write = xmc4xxx_write,
  1177. .read = default_flash_read,
  1178. .probe = xmc4xxx_probe,
  1179. .auto_probe = xmc4xxx_probe,
  1180. .erase_check = xmc4xxx_flash_blank_check,
  1181. .info = xmc4xxx_get_info_command,
  1182. .protect_check = xmc4xxx_protect_check,
  1183. .protect = xmc4xxx_protect,
  1184. };