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  1. /***************************************************************************
  2. * Copyright (C) 2007 by Dominic Rath *
  3. * Dominic.Rath@gmx.de *
  4. * *
  5. * Copyright (C) 2009 by √ėyvind Harboe *
  6. * oyvind.harboe@zylin.com *
  7. * *
  8. * This program is free software; you can redistribute it and/or modify *
  9. * it under the terms of the GNU General Public License as published by *
  10. * the Free Software Foundation; either version 2 of the License, or *
  11. * (at your option) any later version. *
  12. * *
  13. * This program is distributed in the hope that it will be useful, *
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  16. * GNU General Public License for more details. *
  17. * *
  18. * You should have received a copy of the GNU General Public License *
  19. * along with this program; if not, write to the *
  20. * Free Software Foundation, Inc., *
  21. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
  22. ***************************************************************************/
  23. #ifdef HAVE_CONFIG_H
  24. #include "config.h"
  25. #endif
  26. #include "arm926ejs.h"
  27. #include "time_support.h"
  28. #include "target_type.h"
  29. #if 0
  30. #define _DEBUG_INSTRUCTION_EXECUTION_
  31. #endif
  32. /* cli handling */
  33. int arm926ejs_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  34. int arm926ejs_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  35. int arm926ejs_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  36. int arm926ejs_handle_md_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  37. int arm926ejs_handle_mw_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  38. int arm926ejs_handle_read_cache_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  39. int arm926ejs_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  40. /* forward declarations */
  41. int arm926ejs_target_create(struct target_s *target, Jim_Interp *interp);
  42. int arm926ejs_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
  43. int arm926ejs_quit(void);
  44. int arm926ejs_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
  45. static int arm926ejs_virt2phys(struct target_s *target, uint32_t virtual, uint32_t *physical);
  46. static int arm926ejs_mmu(struct target_s *target, int *enabled);
  47. target_type_t arm926ejs_target =
  48. {
  49. .name = "arm926ejs",
  50. .poll = arm7_9_poll,
  51. .arch_state = arm926ejs_arch_state,
  52. .target_request_data = arm7_9_target_request_data,
  53. .halt = arm7_9_halt,
  54. .resume = arm7_9_resume,
  55. .step = arm7_9_step,
  56. .assert_reset = arm7_9_assert_reset,
  57. .deassert_reset = arm7_9_deassert_reset,
  58. .soft_reset_halt = arm926ejs_soft_reset_halt,
  59. .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
  60. .read_memory = arm7_9_read_memory,
  61. .write_memory = arm926ejs_write_memory,
  62. .bulk_write_memory = arm7_9_bulk_write_memory,
  63. .checksum_memory = arm7_9_checksum_memory,
  64. .blank_check_memory = arm7_9_blank_check_memory,
  65. .run_algorithm = armv4_5_run_algorithm,
  66. .add_breakpoint = arm7_9_add_breakpoint,
  67. .remove_breakpoint = arm7_9_remove_breakpoint,
  68. .add_watchpoint = arm7_9_add_watchpoint,
  69. .remove_watchpoint = arm7_9_remove_watchpoint,
  70. .register_commands = arm926ejs_register_commands,
  71. .target_create = arm926ejs_target_create,
  72. .init_target = arm926ejs_init_target,
  73. .examine = arm9tdmi_examine,
  74. .quit = arm926ejs_quit,
  75. .virt2phys = arm926ejs_virt2phys,
  76. .mmu = arm926ejs_mmu
  77. };
  78. int arm926ejs_catch_broken_irscan(uint8_t *captured, void *priv, scan_field_t *field)
  79. {
  80. /* FIX!!!! this code should be reenabled. For now it does not check
  81. * the queue...*/
  82. return 0;
  83. #if 0
  84. /* The ARM926EJ-S' instruction register is 4 bits wide */
  85. uint8_t t = *captured & 0xf;
  86. uint8_t t2 = *field->in_check_value & 0xf;
  87. if (t == t2)
  88. {
  89. return ERROR_OK;
  90. }
  91. else if ((t == 0x0f) || (t == 0x00))
  92. {
  93. LOG_DEBUG("caught ARM926EJ-S invalid Capture-IR result after CP15 access");
  94. return ERROR_OK;
  95. }
  96. return ERROR_JTAG_QUEUE_FAILED;;
  97. #endif
  98. }
  99. #define ARM926EJS_CP15_ADDR(opcode_1, opcode_2, CRn, CRm) ((opcode_1 << 11) | (opcode_2 << 8) | (CRn << 4) | (CRm << 0))
  100. int arm926ejs_cp15_read(target_t *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
  101. {
  102. int retval = ERROR_OK;
  103. armv4_5_common_t *armv4_5 = target->arch_info;
  104. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  105. arm_jtag_t *jtag_info = &arm7_9->jtag_info;
  106. uint32_t address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm);
  107. scan_field_t fields[4];
  108. uint8_t address_buf[2];
  109. uint8_t nr_w_buf = 0;
  110. uint8_t access = 1;
  111. buf_set_u32(address_buf, 0, 14, address);
  112. jtag_set_end_state(TAP_IDLE);
  113. if ((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
  114. {
  115. return retval;
  116. }
  117. arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
  118. fields[0].tap = jtag_info->tap;
  119. fields[0].num_bits = 32;
  120. fields[0].out_value = NULL;
  121. fields[0].in_value = (uint8_t *)value;
  122. fields[1].tap = jtag_info->tap;
  123. fields[1].num_bits = 1;
  124. fields[1].out_value = &access;
  125. fields[1].in_value = &access;
  126. fields[2].tap = jtag_info->tap;
  127. fields[2].num_bits = 14;
  128. fields[2].out_value = address_buf;
  129. fields[2].in_value = NULL;
  130. fields[3].tap = jtag_info->tap;
  131. fields[3].num_bits = 1;
  132. fields[3].out_value = &nr_w_buf;
  133. fields[3].in_value = NULL;
  134. jtag_add_dr_scan(4, fields, jtag_get_end_state());
  135. long long then = timeval_ms();
  136. for (;;)
  137. {
  138. /* rescan with NOP, to wait for the access to complete */
  139. access = 0;
  140. nr_w_buf = 0;
  141. jtag_add_dr_scan(4, fields, jtag_get_end_state());
  142. jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t)value);
  143. if ((retval = jtag_execute_queue()) != ERROR_OK)
  144. {
  145. return retval;
  146. }
  147. if (buf_get_u32(&access, 0, 1) == 1)
  148. {
  149. break;
  150. }
  151. /* 10ms timeout */
  152. if ((timeval_ms()-then)>10)
  153. {
  154. LOG_ERROR("cp15 read operation timed out");
  155. return ERROR_FAIL;
  156. }
  157. }
  158. #ifdef _DEBUG_INSTRUCTION_EXECUTION_
  159. LOG_DEBUG("addr: 0x%x value: %8.8x", address, *value);
  160. #endif
  161. arm_jtag_set_instr(jtag_info, 0xc, &arm926ejs_catch_broken_irscan);
  162. return ERROR_OK;
  163. }
  164. int arm926ejs_cp15_write(target_t *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
  165. {
  166. int retval = ERROR_OK;
  167. armv4_5_common_t *armv4_5 = target->arch_info;
  168. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  169. arm_jtag_t *jtag_info = &arm7_9->jtag_info;
  170. uint32_t address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm);
  171. scan_field_t fields[4];
  172. uint8_t value_buf[4];
  173. uint8_t address_buf[2];
  174. uint8_t nr_w_buf = 1;
  175. uint8_t access = 1;
  176. buf_set_u32(address_buf, 0, 14, address);
  177. buf_set_u32(value_buf, 0, 32, value);
  178. jtag_set_end_state(TAP_IDLE);
  179. if ((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
  180. {
  181. return retval;
  182. }
  183. arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
  184. fields[0].tap = jtag_info->tap;
  185. fields[0].num_bits = 32;
  186. fields[0].out_value = value_buf;
  187. fields[0].in_value = NULL;
  188. fields[1].tap = jtag_info->tap;
  189. fields[1].num_bits = 1;
  190. fields[1].out_value = &access;
  191. fields[1].in_value = &access;
  192. fields[2].tap = jtag_info->tap;
  193. fields[2].num_bits = 14;
  194. fields[2].out_value = address_buf;
  195. fields[2].in_value = NULL;
  196. fields[3].tap = jtag_info->tap;
  197. fields[3].num_bits = 1;
  198. fields[3].out_value = &nr_w_buf;
  199. fields[3].in_value = NULL;
  200. jtag_add_dr_scan(4, fields, jtag_get_end_state());
  201. long long then = timeval_ms();
  202. for (;;)
  203. {
  204. /* rescan with NOP, to wait for the access to complete */
  205. access = 0;
  206. nr_w_buf = 0;
  207. jtag_add_dr_scan(4, fields, jtag_get_end_state());
  208. if ((retval = jtag_execute_queue()) != ERROR_OK)
  209. {
  210. return retval;
  211. }
  212. if (buf_get_u32(&access, 0, 1) == 1)
  213. {
  214. break;
  215. }
  216. /* 10ms timeout */
  217. if ((timeval_ms()-then)>10)
  218. {
  219. LOG_ERROR("cp15 write operation timed out");
  220. return ERROR_FAIL;
  221. }
  222. }
  223. #ifdef _DEBUG_INSTRUCTION_EXECUTION_
  224. LOG_DEBUG("addr: 0x%x value: %8.8x", address, value);
  225. #endif
  226. arm_jtag_set_instr(jtag_info, 0xf, &arm926ejs_catch_broken_irscan);
  227. return ERROR_OK;
  228. }
  229. static int arm926ejs_examine_debug_reason(target_t *target)
  230. {
  231. armv4_5_common_t *armv4_5 = target->arch_info;
  232. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  233. reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
  234. int debug_reason;
  235. int retval;
  236. embeddedice_read_reg(dbg_stat);
  237. if ((retval = jtag_execute_queue()) != ERROR_OK)
  238. return retval;
  239. /* Method-Of-Entry (MOE) field */
  240. debug_reason = buf_get_u32(dbg_stat->value, 6, 4);
  241. switch (debug_reason)
  242. {
  243. case 0:
  244. LOG_DEBUG("no *NEW* debug entry (?missed one?)");
  245. /* ... since last restart or debug reset ... */
  246. target->debug_reason = DBG_REASON_DBGRQ;
  247. break;
  248. case 1:
  249. LOG_DEBUG("breakpoint from EICE unit 0");
  250. target->debug_reason = DBG_REASON_BREAKPOINT;
  251. break;
  252. case 2:
  253. LOG_DEBUG("breakpoint from EICE unit 1");
  254. target->debug_reason = DBG_REASON_BREAKPOINT;
  255. break;
  256. case 3:
  257. LOG_DEBUG("soft breakpoint (BKPT instruction)");
  258. target->debug_reason = DBG_REASON_BREAKPOINT;
  259. break;
  260. case 4:
  261. LOG_DEBUG("vector catch breakpoint");
  262. target->debug_reason = DBG_REASON_BREAKPOINT;
  263. break;
  264. case 5:
  265. LOG_DEBUG("external breakpoint");
  266. target->debug_reason = DBG_REASON_BREAKPOINT;
  267. break;
  268. case 6:
  269. LOG_DEBUG("watchpoint from EICE unit 0");
  270. target->debug_reason = DBG_REASON_WATCHPOINT;
  271. break;
  272. case 7:
  273. LOG_DEBUG("watchpoint from EICE unit 1");
  274. target->debug_reason = DBG_REASON_WATCHPOINT;
  275. break;
  276. case 8:
  277. LOG_DEBUG("external watchpoint");
  278. target->debug_reason = DBG_REASON_WATCHPOINT;
  279. break;
  280. case 9:
  281. LOG_DEBUG("internal debug request");
  282. target->debug_reason = DBG_REASON_DBGRQ;
  283. break;
  284. case 10:
  285. LOG_DEBUG("external debug request");
  286. target->debug_reason = DBG_REASON_DBGRQ;
  287. break;
  288. case 11:
  289. LOG_DEBUG("debug re-entry from system speed access");
  290. /* This is normal when connecting to something that's
  291. * already halted, or in some related code paths, but
  292. * otherwise is surprising (and presumably wrong).
  293. */
  294. switch (target->debug_reason) {
  295. case DBG_REASON_DBGRQ:
  296. break;
  297. default:
  298. LOG_ERROR("unexpected -- debug re-entry");
  299. /* FALLTHROUGH */
  300. case DBG_REASON_UNDEFINED:
  301. target->debug_reason = DBG_REASON_DBGRQ;
  302. break;
  303. }
  304. break;
  305. case 12:
  306. /* FIX!!!! here be dragons!!! We need to fail here so
  307. * the target will interpreted as halted but we won't
  308. * try to talk to it right now... a resume + halt seems
  309. * to sync things up again. Please send an email to
  310. * openocd development mailing list if you have hardware
  311. * to donate to look into this problem....
  312. */
  313. LOG_WARNING("WARNING: mystery debug reason MOE = 0xc. Try issuing a resume + halt.");
  314. target->debug_reason = DBG_REASON_DBGRQ;
  315. break;
  316. default:
  317. LOG_WARNING("WARNING: unknown debug reason: 0x%x", debug_reason);
  318. /* Oh agony! should we interpret this as a halt request or
  319. * that the target stopped on it's own accord?
  320. */
  321. target->debug_reason = DBG_REASON_DBGRQ;
  322. /* if we fail here, we won't talk to the target and it will
  323. * be reported to be in the halted state */
  324. break;
  325. }
  326. return ERROR_OK;
  327. }
  328. uint32_t arm926ejs_get_ttb(target_t *target)
  329. {
  330. armv4_5_common_t *armv4_5 = target->arch_info;
  331. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  332. arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
  333. arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
  334. int retval;
  335. uint32_t ttb = 0x0;
  336. if ((retval = arm926ejs->read_cp15(target, 0, 0, 2, 0, &ttb)) != ERROR_OK)
  337. return retval;
  338. return ttb;
  339. }
  340. void arm926ejs_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
  341. {
  342. armv4_5_common_t *armv4_5 = target->arch_info;
  343. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  344. arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
  345. arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
  346. uint32_t cp15_control;
  347. /* read cp15 control register */
  348. arm926ejs->read_cp15(target, 0, 0, 1, 0, &cp15_control);
  349. jtag_execute_queue();
  350. if (mmu)
  351. {
  352. /* invalidate TLB */
  353. arm926ejs->write_cp15(target, 0, 0, 8, 7, 0x0);
  354. cp15_control &= ~0x1U;
  355. }
  356. if (d_u_cache)
  357. {
  358. uint32_t debug_override;
  359. /* read-modify-write CP15 debug override register
  360. * to enable "test and clean all" */
  361. arm926ejs->read_cp15(target, 0, 0, 15, 0, &debug_override);
  362. debug_override |= 0x80000;
  363. arm926ejs->write_cp15(target, 0, 0, 15, 0, debug_override);
  364. /* clean and invalidate DCache */
  365. arm926ejs->write_cp15(target, 0, 0, 7, 5, 0x0);
  366. /* write CP15 debug override register
  367. * to disable "test and clean all" */
  368. debug_override &= ~0x80000;
  369. arm926ejs->write_cp15(target, 0, 0, 15, 0, debug_override);
  370. cp15_control &= ~0x4U;
  371. }
  372. if (i_cache)
  373. {
  374. /* invalidate ICache */
  375. arm926ejs->write_cp15(target, 0, 0, 7, 5, 0x0);
  376. cp15_control &= ~0x1000U;
  377. }
  378. arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control);
  379. }
  380. void arm926ejs_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
  381. {
  382. armv4_5_common_t *armv4_5 = target->arch_info;
  383. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  384. arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
  385. arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
  386. uint32_t cp15_control;
  387. /* read cp15 control register */
  388. arm926ejs->read_cp15(target, 0, 0, 1, 0, &cp15_control);
  389. jtag_execute_queue();
  390. if (mmu)
  391. cp15_control |= 0x1U;
  392. if (d_u_cache)
  393. cp15_control |= 0x4U;
  394. if (i_cache)
  395. cp15_control |= 0x1000U;
  396. arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control);
  397. }
  398. void arm926ejs_post_debug_entry(target_t *target)
  399. {
  400. armv4_5_common_t *armv4_5 = target->arch_info;
  401. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  402. arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
  403. arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
  404. /* examine cp15 control reg */
  405. arm926ejs->read_cp15(target, 0, 0, 1, 0, &arm926ejs->cp15_control_reg);
  406. jtag_execute_queue();
  407. LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm926ejs->cp15_control_reg);
  408. if (arm926ejs->armv4_5_mmu.armv4_5_cache.ctype == -1)
  409. {
  410. uint32_t cache_type_reg;
  411. /* identify caches */
  412. arm926ejs->read_cp15(target, 0, 1, 0, 0, &cache_type_reg);
  413. jtag_execute_queue();
  414. armv4_5_identify_cache(cache_type_reg, &arm926ejs->armv4_5_mmu.armv4_5_cache);
  415. }
  416. arm926ejs->armv4_5_mmu.mmu_enabled = (arm926ejs->cp15_control_reg & 0x1U) ? 1 : 0;
  417. arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm926ejs->cp15_control_reg & 0x4U) ? 1 : 0;
  418. arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = (arm926ejs->cp15_control_reg & 0x1000U) ? 1 : 0;
  419. /* save i/d fault status and address register */
  420. arm926ejs->read_cp15(target, 0, 0, 5, 0, &arm926ejs->d_fsr);
  421. arm926ejs->read_cp15(target, 0, 1, 5, 0, &arm926ejs->i_fsr);
  422. arm926ejs->read_cp15(target, 0, 0, 6, 0, &arm926ejs->d_far);
  423. LOG_DEBUG("D FSR: 0x%8.8" PRIx32 ", D FAR: 0x%8.8" PRIx32 ", I FSR: 0x%8.8" PRIx32 "",
  424. arm926ejs->d_fsr, arm926ejs->d_far, arm926ejs->i_fsr);
  425. uint32_t cache_dbg_ctrl;
  426. /* read-modify-write CP15 cache debug control register
  427. * to disable I/D-cache linefills and force WT */
  428. arm926ejs->read_cp15(target, 7, 0, 15, 0, &cache_dbg_ctrl);
  429. cache_dbg_ctrl |= 0x7;
  430. arm926ejs->write_cp15(target, 7, 0, 15, 0, cache_dbg_ctrl);
  431. }
  432. void arm926ejs_pre_restore_context(target_t *target)
  433. {
  434. armv4_5_common_t *armv4_5 = target->arch_info;
  435. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  436. arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
  437. arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
  438. /* restore i/d fault status and address register */
  439. arm926ejs->write_cp15(target, 0, 0, 5, 0, arm926ejs->d_fsr);
  440. arm926ejs->write_cp15(target, 0, 1, 5, 0, arm926ejs->i_fsr);
  441. arm926ejs->write_cp15(target, 0, 0, 6, 0, arm926ejs->d_far);
  442. uint32_t cache_dbg_ctrl;
  443. /* read-modify-write CP15 cache debug control register
  444. * to reenable I/D-cache linefills and disable WT */
  445. arm926ejs->read_cp15(target, 7, 0, 15, 0, &cache_dbg_ctrl);
  446. cache_dbg_ctrl &= ~0x7;
  447. arm926ejs->write_cp15(target, 7, 0, 15, 0, cache_dbg_ctrl);
  448. }
  449. int arm926ejs_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm9tdmi_common_t **arm9tdmi_p, arm926ejs_common_t **arm926ejs_p)
  450. {
  451. armv4_5_common_t *armv4_5 = target->arch_info;
  452. arm7_9_common_t *arm7_9;
  453. arm9tdmi_common_t *arm9tdmi;
  454. arm926ejs_common_t *arm926ejs;
  455. if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
  456. {
  457. return -1;
  458. }
  459. arm7_9 = armv4_5->arch_info;
  460. if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
  461. {
  462. return -1;
  463. }
  464. arm9tdmi = arm7_9->arch_info;
  465. if (arm9tdmi->common_magic != ARM9TDMI_COMMON_MAGIC)
  466. {
  467. return -1;
  468. }
  469. arm926ejs = arm9tdmi->arch_info;
  470. if (arm926ejs->common_magic != ARM926EJS_COMMON_MAGIC)
  471. {
  472. return -1;
  473. }
  474. *armv4_5_p = armv4_5;
  475. *arm7_9_p = arm7_9;
  476. *arm9tdmi_p = arm9tdmi;
  477. *arm926ejs_p = arm926ejs;
  478. return ERROR_OK;
  479. }
  480. int arm926ejs_arch_state(struct target_s *target)
  481. {
  482. armv4_5_common_t *armv4_5 = target->arch_info;
  483. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  484. arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
  485. arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
  486. char *state[] =
  487. {
  488. "disabled", "enabled"
  489. };
  490. if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
  491. {
  492. LOG_ERROR("BUG: called for a non-ARMv4/5 target");
  493. exit(-1);
  494. }
  495. LOG_USER(
  496. "target halted in %s state due to %s, current mode: %s\n"
  497. "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
  498. "MMU: %s, D-Cache: %s, I-Cache: %s",
  499. armv4_5_state_strings[armv4_5->core_state],
  500. Jim_Nvp_value2name_simple(nvp_target_debug_reason,target->debug_reason)->name,
  501. armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
  502. buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
  503. buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
  504. state[arm926ejs->armv4_5_mmu.mmu_enabled],
  505. state[arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
  506. state[arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled]);
  507. return ERROR_OK;
  508. }
  509. int arm926ejs_soft_reset_halt(struct target_s *target)
  510. {
  511. int retval = ERROR_OK;
  512. armv4_5_common_t *armv4_5 = target->arch_info;
  513. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  514. arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
  515. arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
  516. reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
  517. if ((retval = target_halt(target)) != ERROR_OK)
  518. {
  519. return retval;
  520. }
  521. long long then = timeval_ms();
  522. int timeout;
  523. while (!(timeout = ((timeval_ms()-then) > 1000)))
  524. {
  525. if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
  526. {
  527. embeddedice_read_reg(dbg_stat);
  528. if ((retval = jtag_execute_queue()) != ERROR_OK)
  529. {
  530. return retval;
  531. }
  532. } else
  533. {
  534. break;
  535. }
  536. if (debug_level >= 1)
  537. {
  538. /* do not eat all CPU, time out after 1 se*/
  539. alive_sleep(100);
  540. } else
  541. {
  542. keep_alive();
  543. }
  544. }
  545. if (timeout)
  546. {
  547. LOG_ERROR("Failed to halt CPU after 1 sec");
  548. return ERROR_TARGET_TIMEOUT;
  549. }
  550. target->state = TARGET_HALTED;
  551. /* SVC, ARM state, IRQ and FIQ disabled */
  552. buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
  553. armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
  554. armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
  555. /* start fetching from 0x0 */
  556. buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
  557. armv4_5->core_cache->reg_list[15].dirty = 1;
  558. armv4_5->core_cache->reg_list[15].valid = 1;
  559. armv4_5->core_mode = ARMV4_5_MODE_SVC;
  560. armv4_5->core_state = ARMV4_5_STATE_ARM;
  561. arm926ejs_disable_mmu_caches(target, 1, 1, 1);
  562. arm926ejs->armv4_5_mmu.mmu_enabled = 0;
  563. arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
  564. arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
  565. return target_call_event_callbacks(target, TARGET_EVENT_HALTED);
  566. }
  567. int arm926ejs_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
  568. {
  569. int retval;
  570. armv4_5_common_t *armv4_5 = target->arch_info;
  571. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  572. arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
  573. arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
  574. /* FIX!!!! this should be cleaned up and made much more general. The
  575. * plan is to write up and test on arm926ejs specifically and
  576. * then generalize and clean up afterwards. */
  577. if ((count == 1) && ((size==2) || (size==4)))
  578. {
  579. /* special case the handling of single word writes to bypass MMU
  580. * to allow implementation of breakpoints in memory marked read only
  581. * by MMU */
  582. if (arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
  583. {
  584. /* flush and invalidate data cache
  585. *
  586. * MCR p15,0,p,c7,c10,1 - clean cache line using virtual address
  587. *
  588. */
  589. retval = arm926ejs->write_cp15(target, 0, 1, 7, 10, address&~0x3);
  590. if (retval != ERROR_OK)
  591. return retval;
  592. }
  593. uint32_t pa;
  594. retval = target->type->virt2phys(target, address, &pa);
  595. if (retval != ERROR_OK)
  596. return retval;
  597. /* write directly to physical memory bypassing any read only MMU bits, etc. */
  598. retval = armv4_5_mmu_write_physical(target, &arm926ejs->armv4_5_mmu, pa, size, count, buffer);
  599. if (retval != ERROR_OK)
  600. return retval;
  601. } else
  602. {
  603. if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK)
  604. return retval;
  605. }
  606. /* If ICache is enabled, we have to invalidate affected ICache lines
  607. * the DCache is forced to write-through, so we don't have to clean it here
  608. */
  609. if (arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
  610. {
  611. if (count <= 1)
  612. {
  613. /* invalidate ICache single entry with MVA */
  614. arm926ejs->write_cp15(target, 0, 1, 7, 5, address);
  615. }
  616. else
  617. {
  618. /* invalidate ICache */
  619. arm926ejs->write_cp15(target, 0, 0, 7, 5, address);
  620. }
  621. }
  622. return retval;
  623. }
  624. int arm926ejs_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
  625. {
  626. arm9tdmi_init_target(cmd_ctx, target);
  627. return ERROR_OK;
  628. }
  629. int arm926ejs_quit(void)
  630. {
  631. return ERROR_OK;
  632. }
  633. int arm926ejs_init_arch_info(target_t *target, arm926ejs_common_t *arm926ejs, jtag_tap_t *tap)
  634. {
  635. arm9tdmi_common_t *arm9tdmi = &arm926ejs->arm9tdmi_common;
  636. arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common;
  637. /* initialize arm9tdmi specific info (including arm7_9 and armv4_5)
  638. */
  639. arm9tdmi_init_arch_info(target, arm9tdmi, tap);
  640. arm9tdmi->arch_info = arm926ejs;
  641. arm926ejs->common_magic = ARM926EJS_COMMON_MAGIC;
  642. arm7_9->post_debug_entry = arm926ejs_post_debug_entry;
  643. arm7_9->pre_restore_context = arm926ejs_pre_restore_context;
  644. arm926ejs->read_cp15 = arm926ejs_cp15_read;
  645. arm926ejs->write_cp15 = arm926ejs_cp15_write;
  646. arm926ejs->armv4_5_mmu.armv4_5_cache.ctype = -1;
  647. arm926ejs->armv4_5_mmu.get_ttb = arm926ejs_get_ttb;
  648. arm926ejs->armv4_5_mmu.read_memory = arm7_9_read_memory;
  649. arm926ejs->armv4_5_mmu.write_memory = arm7_9_write_memory;
  650. arm926ejs->armv4_5_mmu.disable_mmu_caches = arm926ejs_disable_mmu_caches;
  651. arm926ejs->armv4_5_mmu.enable_mmu_caches = arm926ejs_enable_mmu_caches;
  652. arm926ejs->armv4_5_mmu.has_tiny_pages = 1;
  653. arm926ejs->armv4_5_mmu.mmu_enabled = 0;
  654. arm7_9->examine_debug_reason = arm926ejs_examine_debug_reason;
  655. /* The ARM926EJ-S implements the ARMv5TE architecture which
  656. * has the BKPT instruction, so we don't have to use a watchpoint comparator
  657. */
  658. arm7_9->arm_bkpt = ARMV5_BKPT(0x0);
  659. arm7_9->thumb_bkpt = ARMV5_T_BKPT(0x0) & 0xffff;
  660. return ERROR_OK;
  661. }
  662. int arm926ejs_target_create(struct target_s *target, Jim_Interp *interp)
  663. {
  664. arm926ejs_common_t *arm926ejs = calloc(1,sizeof(arm926ejs_common_t));
  665. arm926ejs_init_arch_info(target, arm926ejs, target->tap);
  666. return ERROR_OK;
  667. }
  668. int arm926ejs_register_commands(struct command_context_s *cmd_ctx)
  669. {
  670. int retval;
  671. command_t *arm926ejs_cmd;
  672. retval = arm9tdmi_register_commands(cmd_ctx);
  673. arm926ejs_cmd = register_command(cmd_ctx, NULL, "arm926ejs", NULL, COMMAND_ANY, "arm926ejs specific commands");
  674. register_command(cmd_ctx, arm926ejs_cmd, "cp15", arm926ejs_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register <opcode_1> <opcode_2> <CRn> <CRm> [value]");
  675. register_command(cmd_ctx, arm926ejs_cmd, "cache_info", arm926ejs_handle_cache_info_command, COMMAND_EXEC, "display information about target caches");
  676. register_command(cmd_ctx, arm926ejs_cmd, "mdw_phys", arm926ejs_handle_md_phys_command, COMMAND_EXEC, "display memory words <physical addr> [count]");
  677. register_command(cmd_ctx, arm926ejs_cmd, "mdh_phys", arm926ejs_handle_md_phys_command, COMMAND_EXEC, "display memory half-words <physical addr> [count]");
  678. register_command(cmd_ctx, arm926ejs_cmd, "mdb_phys", arm926ejs_handle_md_phys_command, COMMAND_EXEC, "display memory bytes <physical addr> [count]");
  679. register_command(cmd_ctx, arm926ejs_cmd, "mww_phys", arm926ejs_handle_mw_phys_command, COMMAND_EXEC, "write memory word <physical addr> <value>");
  680. register_command(cmd_ctx, arm926ejs_cmd, "mwh_phys", arm926ejs_handle_mw_phys_command, COMMAND_EXEC, "write memory half-word <physical addr> <value>");
  681. register_command(cmd_ctx, arm926ejs_cmd, "mwb_phys", arm926ejs_handle_mw_phys_command, COMMAND_EXEC, "write memory byte <physical addr> <value>");
  682. return retval;
  683. }
  684. int arm926ejs_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
  685. {
  686. int retval;
  687. target_t *target = get_current_target(cmd_ctx);
  688. armv4_5_common_t *armv4_5;
  689. arm7_9_common_t *arm7_9;
  690. arm9tdmi_common_t *arm9tdmi;
  691. arm926ejs_common_t *arm926ejs;
  692. int opcode_1;
  693. int opcode_2;
  694. int CRn;
  695. int CRm;
  696. if ((argc < 4) || (argc > 5))
  697. {
  698. command_print(cmd_ctx, "usage: arm926ejs cp15 <opcode_1> <opcode_2> <CRn> <CRm> [value]");
  699. return ERROR_OK;
  700. }
  701. opcode_1 = strtoul(args[0], NULL, 0);
  702. opcode_2 = strtoul(args[1], NULL, 0);
  703. CRn = strtoul(args[2], NULL, 0);
  704. CRm = strtoul(args[3], NULL, 0);
  705. if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
  706. {
  707. command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
  708. return ERROR_OK;
  709. }
  710. if (target->state != TARGET_HALTED)
  711. {
  712. command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
  713. return ERROR_OK;
  714. }
  715. if (argc == 4)
  716. {
  717. uint32_t value;
  718. if ((retval = arm926ejs->read_cp15(target, opcode_1, opcode_2, CRn, CRm, &value)) != ERROR_OK)
  719. {
  720. command_print(cmd_ctx, "couldn't access register");
  721. return ERROR_OK;
  722. }
  723. if ((retval = jtag_execute_queue()) != ERROR_OK)
  724. {
  725. return retval;
  726. }
  727. command_print(cmd_ctx, "%i %i %i %i: %8.8" PRIx32 "", opcode_1, opcode_2, CRn, CRm, value);
  728. }
  729. else
  730. {
  731. uint32_t value = strtoul(args[4], NULL, 0);
  732. if ((retval = arm926ejs->write_cp15(target, opcode_1, opcode_2, CRn, CRm, value)) != ERROR_OK)
  733. {
  734. command_print(cmd_ctx, "couldn't access register");
  735. return ERROR_OK;
  736. }
  737. command_print(cmd_ctx, "%i %i %i %i: %8.8" PRIx32 "", opcode_1, opcode_2, CRn, CRm, value);
  738. }
  739. return ERROR_OK;
  740. }
  741. int arm926ejs_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
  742. {
  743. target_t *target = get_current_target(cmd_ctx);
  744. armv4_5_common_t *armv4_5;
  745. arm7_9_common_t *arm7_9;
  746. arm9tdmi_common_t *arm9tdmi;
  747. arm926ejs_common_t *arm926ejs;
  748. if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
  749. {
  750. command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
  751. return ERROR_OK;
  752. }
  753. return armv4_5_handle_cache_info_command(cmd_ctx, &arm926ejs->armv4_5_mmu.armv4_5_cache);
  754. }
  755. int arm926ejs_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
  756. {
  757. target_t *target = get_current_target(cmd_ctx);
  758. armv4_5_common_t *armv4_5;
  759. arm7_9_common_t *arm7_9;
  760. arm9tdmi_common_t *arm9tdmi;
  761. arm926ejs_common_t *arm926ejs;
  762. arm_jtag_t *jtag_info;
  763. if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
  764. {
  765. command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
  766. return ERROR_OK;
  767. }
  768. jtag_info = &arm7_9->jtag_info;
  769. if (target->state != TARGET_HALTED)
  770. {
  771. command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
  772. return ERROR_OK;
  773. }
  774. return armv4_5_mmu_handle_md_phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu);
  775. }
  776. int arm926ejs_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
  777. {
  778. target_t *target = get_current_target(cmd_ctx);
  779. armv4_5_common_t *armv4_5;
  780. arm7_9_common_t *arm7_9;
  781. arm9tdmi_common_t *arm9tdmi;
  782. arm926ejs_common_t *arm926ejs;
  783. arm_jtag_t *jtag_info;
  784. if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
  785. {
  786. command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
  787. return ERROR_OK;
  788. }
  789. jtag_info = &arm7_9->jtag_info;
  790. if (target->state != TARGET_HALTED)
  791. {
  792. command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
  793. return ERROR_OK;
  794. }
  795. return armv4_5_mmu_handle_mw_phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu);
  796. }
  797. static int arm926ejs_virt2phys(struct target_s *target, uint32_t virtual, uint32_t *physical)
  798. {
  799. int retval;
  800. int type;
  801. uint32_t cb;
  802. int domain;
  803. uint32_t ap;
  804. armv4_5_common_t *armv4_5;
  805. arm7_9_common_t *arm7_9;
  806. arm9tdmi_common_t *arm9tdmi;
  807. arm926ejs_common_t *arm926ejs;
  808. retval= arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs);
  809. if (retval != ERROR_OK)
  810. {
  811. return retval;
  812. }
  813. uint32_t ret = armv4_5_mmu_translate_va(target, &arm926ejs->armv4_5_mmu, virtual, &type, &cb, &domain, &ap);
  814. if (type == -1)
  815. {
  816. return ret;
  817. }
  818. *physical = ret;
  819. return ERROR_OK;
  820. }
  821. static int arm926ejs_mmu(struct target_s *target, int *enabled)
  822. {
  823. armv4_5_common_t *armv4_5 = target->arch_info;
  824. arm926ejs_common_t *arm926ejs = armv4_5->arch_info;
  825. if (target->state != TARGET_HALTED)
  826. {
  827. LOG_ERROR("Target not halted");
  828. return ERROR_TARGET_INVALID;
  829. }
  830. *enabled = arm926ejs->armv4_5_mmu.mmu_enabled;
  831. return ERROR_OK;
  832. }