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  1. /***************************************************************************
  2. * Copyright (C) 2017 by STMicroelectronics *
  3. * *
  4. * This program is free software; you can redistribute it and/or modify *
  5. * it under the terms of the GNU General Public License as published by *
  6. * the Free Software Foundation; either version 2 of the License, or *
  7. * (at your option) any later version. *
  8. * *
  9. * This program is distributed in the hope that it will be useful, *
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  12. * GNU General Public License for more details. *
  13. * *
  14. * You should have received a copy of the GNU General Public License *
  15. * along with this program; if not, write to the *
  16. * Free Software Foundation, Inc. *
  17. ***************************************************************************/
  18. .text
  19. .syntax unified
  20. .cpu cortex-m4
  21. .thumb
  22. /*
  23. * Code limitations:
  24. * The workarea must have size multiple of 4 bytes, since R/W
  25. * operations are all at 32 bits.
  26. * The workarea must be big enough to contain rp, wp and data, thus the minumum
  27. * workarea size is: min_wa_size = sizeof(rp, wp, data) = 4 + 4 + sizeof(data).
  28. * - for 0x450 devices: sizeof(data) = 32 bytes, thus min_wa_size = 40 bytes.
  29. * - for 0x480 devices: sizeof(data) = 16 bytes, thus min_wa_size = 24 bytes.
  30. * To benefit from concurrent host write-to-buffer and target
  31. * write-to-flash, the workarea must be way bigger than the minimum.
  32. *
  33. * To avoid confusions the write word size is got from .block_size member of
  34. * struct stm32h7x_part_info defined in stm32h7x.c
  35. */
  36. /*
  37. * Params :
  38. * r0 = workarea start, status (out)
  39. * r1 = workarea end
  40. * r2 = target address
  41. * r3 = count (of write words)
  42. * r4 = size of write word
  43. * r5 = flash reg base
  44. *
  45. * Clobbered:
  46. * r6 - rp
  47. * r7 - wp, status, tmp
  48. * r8 - loop index, tmp
  49. */
  50. #define STM32_FLASH_CR_OFFSET 0x0C /* offset of CR register in FLASH struct */
  51. #define STM32_FLASH_SR_OFFSET 0x10 /* offset of SR register in FLASH struct */
  52. #define STM32_CR_PROG 0x00000002 /* PG */
  53. #define STM32_SR_QW_MASK 0x00000004 /* QW */
  54. #define STM32_SR_ERROR_MASK 0x07ee0000 /* DBECCERR | SNECCERR | RDSERR | RDPERR | OPERR
  55. | INCERR | STRBERR | PGSERR | WRPERR */
  56. .thumb_func
  57. .global _start
  58. _start:
  59. ldr r6, [r0, #4] /* read rp */
  60. wait_fifo:
  61. ldr r7, [r0, #0] /* read wp */
  62. cbz r7, exit /* abort if wp == 0, status = 0 */
  63. subs r7, r7, r6 /* number of bytes available for read in r7 */
  64. ittt mi /* if wrapped around */
  65. addmi r7, r1 /* add size of buffer */
  66. submi r7, r0
  67. submi r7, #8
  68. cmp r7, r4 /* wait until data buffer is full */
  69. bcc wait_fifo
  70. mov r7, #STM32_CR_PROG
  71. str r7, [r5, #STM32_FLASH_CR_OFFSET]
  72. mov r8, #4
  73. udiv r8, r4, r8 /* number of words is size of write word devided by 4*/
  74. write_flash:
  75. dsb
  76. ldr r7, [r6], #0x04 /* read one word from src, increment ptr */
  77. str r7, [r2], #0x04 /* write one word to dst, increment ptr */
  78. dsb
  79. cmp r6, r1 /* if rp >= end of buffer ... */
  80. it cs
  81. addcs r6, r0, #8 /* ... then wrap at buffer start */
  82. subs r8, r8, #1 /* decrement loop index */
  83. bne write_flash /* loop if not done */
  84. busy:
  85. ldr r7, [r5, #STM32_FLASH_SR_OFFSET]
  86. tst r7, #STM32_SR_QW_MASK
  87. bne busy /* operation in progress, wait ... */
  88. ldr r8, =STM32_SR_ERROR_MASK
  89. tst r7, r8
  90. bne error /* fail... */
  91. str r6, [r0, #4] /* store rp */
  92. subs r3, r3, #1 /* decrement count */
  93. bne wait_fifo /* loop if not done */
  94. b exit
  95. error:
  96. movs r8, #0
  97. str r8, [r0, #4] /* set rp = 0 on error */
  98. exit:
  99. mov r0, r7 /* return status in r0 */
  100. bkpt #0x00
  101. .pool