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  1. \input texinfo @c -*-texinfo-*-
  2. @c %**start of header
  3. @setfilename
  4. @settitle OpenOCD User's Guide
  5. @dircategory Development
  6. @direntry
  7. * OpenOCD: (openocd). OpenOCD User's Guide
  8. @end direntry
  9. @paragraphindent 0
  10. @c %**end of header
  11. @include version.texi
  12. @copying
  13. This User's Guide documents
  14. release @value{VERSION},
  15. dated @value{UPDATED},
  16. of the Open On-Chip Debugger (OpenOCD).
  17. @itemize @bullet
  18. @item Copyright @copyright{} 2008 The OpenOCD Project
  19. @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{}
  20. @item Copyright @copyright{} 2008-2010 Oyvind Harboe @email{}
  21. @item Copyright @copyright{} 2008 Duane Ellis @email{}
  22. @item Copyright @copyright{} 2009-2010 David Brownell
  23. @end itemize
  24. @quotation
  25. Permission is granted to copy, distribute and/or modify this document
  26. under the terms of the GNU Free Documentation License, Version 1.2 or
  27. any later version published by the Free Software Foundation; with no
  28. Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A
  29. copy of the license is included in the section entitled ``GNU Free
  30. Documentation License''.
  31. @end quotation
  32. @end copying
  33. @titlepage
  34. @titlefont{@emph{Open On-Chip Debugger:}}
  35. @sp 1
  36. @title OpenOCD User's Guide
  37. @subtitle for release @value{VERSION}
  38. @subtitle @value{UPDATED}
  39. @page
  40. @vskip 0pt plus 1filll
  41. @insertcopying
  42. @end titlepage
  43. @summarycontents
  44. @contents
  45. @ifnottex
  46. @node Top
  47. @top OpenOCD User's Guide
  48. @insertcopying
  49. @end ifnottex
  50. @menu
  51. * About:: About OpenOCD
  52. * Developers:: OpenOCD Developer Resources
  53. * Debug Adapter Hardware:: Debug Adapter Hardware
  54. * About Jim-Tcl:: About Jim-Tcl
  55. * Running:: Running OpenOCD
  56. * OpenOCD Project Setup:: OpenOCD Project Setup
  57. * Config File Guidelines:: Config File Guidelines
  58. * Server Configuration:: Server Configuration
  59. * Debug Adapter Configuration:: Debug Adapter Configuration
  60. * Reset Configuration:: Reset Configuration
  61. * TAP Declaration:: TAP Declaration
  62. * CPU Configuration:: CPU Configuration
  63. * Flash Commands:: Flash Commands
  64. * Flash Programming:: Flash Programming
  65. * PLD/FPGA Commands:: PLD/FPGA Commands
  66. * General Commands:: General Commands
  67. * Architecture and Core Commands:: Architecture and Core Commands
  68. * JTAG Commands:: JTAG Commands
  69. * Boundary Scan Commands:: Boundary Scan Commands
  70. * Utility Commands:: Utility Commands
  71. * GDB and OpenOCD:: Using GDB and OpenOCD
  72. * Tcl Scripting API:: Tcl Scripting API
  73. * FAQ:: Frequently Asked Questions
  74. * Tcl Crash Course:: Tcl Crash Course
  75. * License:: GNU Free Documentation License
  76. @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
  77. @comment case issue with ``Index.html'' and ``index.html''
  78. @comment Occurs when creating ``--html --no-split'' output
  79. @comment This fix is based on:
  80. * OpenOCD Concept Index:: Concept Index
  81. * Command and Driver Index:: Command and Driver Index
  82. @end menu
  83. @node About
  84. @unnumbered About
  85. @cindex about
  86. OpenOCD was created by Dominic Rath as part of a 2005 diploma thesis written
  87. at the University of Applied Sciences Augsburg (@uref{}).
  88. Since that time, the project has grown into an active open-source project,
  89. supported by a diverse community of software and hardware developers from
  90. around the world.
  91. @section What is OpenOCD?
  92. @cindex TAP
  93. @cindex JTAG
  94. The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
  95. in-system programming and boundary-scan testing for embedded target
  96. devices.
  97. It does so with the assistance of a @dfn{debug adapter}, which is
  98. a small hardware module which helps provide the right kind of
  99. electrical signaling to the target being debugged. These are
  100. required since the debug host (on which OpenOCD runs) won't
  101. usually have native support for such signaling, or the connector
  102. needed to hook up to the target.
  103. Such debug adapters support one or more @dfn{transport} protocols,
  104. each of which involves different electrical signaling (and uses
  105. different messaging protocols on top of that signaling). There
  106. are many types of debug adapter, and little uniformity in what
  107. they are called. (There are also product naming differences.)
  108. These adapters are sometimes packaged as discrete dongles, which
  109. may generically be called @dfn{hardware interface dongles}.
  110. Some development boards also integrate them directly, which may
  111. let the development board connect directly to the debug
  112. host over USB (and sometimes also to power it over USB).
  113. For example, a @dfn{JTAG Adapter} supports JTAG
  114. signaling, and is used to communicate
  115. with JTAG (IEEE 1149.1) compliant TAPs on your target board.
  116. A @dfn{TAP} is a ``Test Access Port'', a module which processes
  117. special instructions and data. TAPs are daisy-chained within and
  118. between chips and boards. JTAG supports debugging and boundary
  119. scan operations.
  120. There are also @dfn{SWD Adapters} that support Serial Wire Debug (SWD)
  121. signaling to communicate with some newer ARM cores, as well as debug
  122. adapters which support both JTAG and SWD transports. SWD supports only
  123. debugging, whereas JTAG also supports boundary scan operations.
  124. For some chips, there are also @dfn{Programming Adapters} supporting
  125. special transports used only to write code to flash memory, without
  126. support for on-chip debugging or boundary scan.
  127. (At this writing, OpenOCD does not support such non-debug adapters.)
  128. @b{Dongles:} OpenOCD currently supports many types of hardware dongles:
  129. USB-based, parallel port-based, and other standalone boxes that run
  130. OpenOCD internally. @xref{Debug Adapter Hardware}.
  131. @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
  132. ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x), Cortex-M3
  133. (Stellaris LM3, STMicroelectronics STM32 and Energy Micro EFM32) and
  134. Intel Quark (x10xx) based cores to be debugged via the GDB protocol.
  135. @b{Flash Programming:} Flash writing is supported for external
  136. CFI-compatible NOR flashes (Intel and AMD/Spansion command set) and several
  137. internal flashes (LPC1700, LPC1800, LPC2000, LPC4300, AT91SAM7, AT91SAM3U,
  138. STR7x, STR9x, LM3, STM32x and EFM32). Preliminary support for various NAND flash
  139. controllers (LPC3180, Orion, S3C24xx, more) is included.
  140. @section OpenOCD Web Site
  141. The OpenOCD web site provides the latest public news from the community:
  142. @uref{}
  143. @section Latest User's Guide:
  144. The user's guide you are now reading may not be the latest one
  145. available. A version for more recent code may be available.
  146. Its HTML form is published regularly at:
  147. @uref{}
  148. PDF form is likewise published at:
  149. @uref{}
  150. @section OpenOCD User's Forum
  151. There is an OpenOCD forum (phpBB) hosted by SparkFun,
  152. which might be helpful to you. Note that if you want
  153. anything to come to the attention of developers, you
  154. should post it to the OpenOCD Developer Mailing List
  155. instead of this forum.
  156. @uref{}
  157. @section OpenOCD User's Mailing List
  158. The OpenOCD User Mailing List provides the primary means of
  159. communication between users:
  160. @uref{}
  161. @section OpenOCD IRC
  162. Support can also be found on irc:
  163. @uref{irc://}
  164. @node Developers
  165. @chapter OpenOCD Developer Resources
  166. @cindex developers
  167. If you are interested in improving the state of OpenOCD's debugging and
  168. testing support, new contributions will be welcome. Motivated developers
  169. can produce new target, flash or interface drivers, improve the
  170. documentation, as well as more conventional bug fixes and enhancements.
  171. The resources in this chapter are available for developers wishing to explore
  172. or expand the OpenOCD source code.
  173. @section OpenOCD Git Repository
  174. During the 0.3.x release cycle, OpenOCD switched from Subversion to
  175. a Git repository hosted at SourceForge. The repository URL is:
  176. @uref{git://}
  177. or via http
  178. @uref{}
  179. You may prefer to use a mirror and the HTTP protocol:
  180. @uref{}
  181. With standard Git tools, use @command{git clone} to initialize
  182. a local repository, and @command{git pull} to update it.
  183. There are also gitweb pages letting you browse the repository
  184. with a web browser, or download arbitrary snapshots without
  185. needing a Git client:
  186. @uref{}
  187. The @file{README} file contains the instructions for building the project
  188. from the repository or a snapshot.
  189. Developers that want to contribute patches to the OpenOCD system are
  190. @b{strongly} encouraged to work against mainline.
  191. Patches created against older versions may require additional
  192. work from their submitter in order to be updated for newer releases.
  193. @section Doxygen Developer Manual
  194. During the 0.2.x release cycle, the OpenOCD project began
  195. providing a Doxygen reference manual. This document contains more
  196. technical information about the software internals, development
  197. processes, and similar documentation:
  198. @uref{}
  199. This document is a work-in-progress, but contributions would be welcome
  200. to fill in the gaps. All of the source files are provided in-tree,
  201. listed in the Doxyfile configuration at the top of the source tree.
  202. @section Gerrit Review System
  203. All changes in the OpenOCD Git repository go through the web-based Gerrit
  204. Code Review System:
  205. @uref{}
  206. After a one-time registration and repository setup, anyone can push commits
  207. from their local Git repository directly into Gerrit.
  208. All users and developers are encouraged to review, test, discuss and vote
  209. for changes in Gerrit. The feedback provides the basis for a maintainer to
  210. eventually submit the change to the main Git repository.
  211. The @file{HACKING} file, also available as the Patch Guide in the Doxygen
  212. Developer Manual, contains basic information about how to connect a
  213. repository to Gerrit, prepare and push patches. Patch authors are expected to
  214. maintain their changes while they're in Gerrit, respond to feedback and if
  215. necessary rework and push improved versions of the change.
  216. @section OpenOCD Developer Mailing List
  217. The OpenOCD Developer Mailing List provides the primary means of
  218. communication between developers:
  219. @uref{}
  220. @section OpenOCD Bug Tracker
  221. The OpenOCD Bug Tracker is hosted on SourceForge:
  222. @uref{}
  223. @node Debug Adapter Hardware
  224. @chapter Debug Adapter Hardware
  225. @cindex dongles
  226. @cindex FTDI
  227. @cindex wiggler
  228. @cindex printer port
  229. @cindex USB Adapter
  230. @cindex RTCK
  231. Defined: @b{dongle}: A small device that plugs into a computer and serves as
  232. an adapter .... [snip]
  233. In the OpenOCD case, this generally refers to @b{a small adapter} that
  234. attaches to your computer via USB or the parallel port.
  235. @section Choosing a Dongle
  236. There are several things you should keep in mind when choosing a dongle.
  237. @enumerate
  238. @item @b{Transport} Does it support the kind of communication that you need?
  239. OpenOCD focuses mostly on JTAG. Your version may also support
  240. other ways to communicate with target devices.
  241. @item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
  242. Does your dongle support it? You might need a level converter.
  243. @item @b{Pinout} What pinout does your target board use?
  244. Does your dongle support it? You may be able to use jumper
  245. wires, or an "octopus" connector, to convert pinouts.
  246. @item @b{Connection} Does your computer have the USB, parallel, or
  247. Ethernet port needed?
  248. @item @b{RTCK} Do you expect to use it with ARM chips and boards with
  249. RTCK support (also known as ``adaptive clocking'')?
  250. @end enumerate
  251. @section USB FT2232 Based
  252. There are many USB JTAG dongles on the market, many of them based
  253. on a chip from ``Future Technology Devices International'' (FTDI)
  254. known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
  255. See: @url{} for more information.
  256. In summer 2009, USB high speed (480 Mbps) versions of these FTDI
  257. chips started to become available in JTAG adapters. Around 2012, a new
  258. variant appeared - FT232H - this is a single-channel version of FT2232H.
  259. (Adapters using those high speed FT2232H or FT232H chips may support adaptive
  260. clocking.)
  261. The FT2232 chips are flexible enough to support some other
  262. transport options, such as SWD or the SPI variants used to
  263. program some chips. They have two communications channels,
  264. and one can be used for a UART adapter at the same time the
  265. other one is used to provide a debug adapter.
  266. Also, some development boards integrate an FT2232 chip to serve as
  267. a built-in low-cost debug adapter and USB-to-serial solution.
  268. @itemize @bullet
  269. @item @b{usbjtag}
  270. @* Link @url{}
  271. @item @b{jtagkey}
  272. @* See: @url{}
  273. @item @b{jtagkey2}
  274. @* See: @url{}
  275. @item @b{oocdlink}
  276. @* See: @url{} By Joern Kaipf
  277. @item @b{signalyzer}
  278. @* See: @url{}
  279. @item @b{Stellaris Eval Boards}
  280. @* See: @url{} - The Stellaris eval boards
  281. bundle FT2232-based JTAG and SWD support, which can be used to debug
  282. the Stellaris chips. Using separate JTAG adapters is optional.
  283. These boards can also be used in a "pass through" mode as JTAG adapters
  284. to other target boards, disabling the Stellaris chip.
  285. @item @b{TI/Luminary ICDI}
  286. @* See: @url{} - TI/Luminary In-Circuit Debug
  287. Interface (ICDI) Boards are included in Stellaris LM3S9B9x
  288. Evaluation Kits. Like the non-detachable FT2232 support on the other
  289. Stellaris eval boards, they can be used to debug other target boards.
  290. @item @b{olimex-jtag}
  291. @* See: @url{}
  292. @item @b{Flyswatter/Flyswatter2}
  293. @* See: @url{}
  294. @item @b{turtelizer2}
  295. @* See:
  296. @uref{, Turtelizer 2}, or
  297. @url{}
  298. @item @b{comstick}
  299. @* Link: @url{}
  300. @item @b{stm32stick}
  301. @* Link @url{}
  302. @item @b{axm0432_jtag}
  303. @* Axiom AXM-0432 Link @url{} - NOTE: This JTAG does not appear
  304. to be available anymore as of April 2012.
  305. @item @b{cortino}
  306. @* Link @url{}
  307. @item @b{dlp-usb1232h}
  308. @* Link @url{}
  309. @item @b{digilent-hs1}
  310. @* Link @url{}
  311. @item @b{opendous}
  312. @* Link @url{} FT2232H-based
  313. (OpenHardware).
  314. @item @b{JTAG-lock-pick Tiny 2}
  315. @* Link @url{} FT232H-based
  316. @item @b{GW16042}
  317. @* Link: @url{}
  318. FT2232H-based
  319. @end itemize
  320. @section USB-JTAG / Altera USB-Blaster compatibles
  321. These devices also show up as FTDI devices, but are not
  322. protocol-compatible with the FT2232 devices. They are, however,
  323. protocol-compatible among themselves. USB-JTAG devices typically consist
  324. of a FT245 followed by a CPLD that understands a particular protocol,
  325. or emulates this protocol using some other hardware.
  326. They may appear under different USB VID/PID depending on the particular
  327. product. The driver can be configured to search for any VID/PID pair
  328. (see the section on driver commands).
  329. @itemize
  330. @item @b{USB-JTAG} Kolja Waschk's USB Blaster-compatible adapter
  331. @* Link: @url{}
  332. @item @b{Altera USB-Blaster}
  333. @* Link: @url{}
  334. @end itemize
  335. @section USB J-Link based
  336. There are several OEM versions of the SEGGER @b{J-Link} adapter. It is
  337. an example of a microcontroller based JTAG adapter, it uses an
  338. AT91SAM764 internally.
  339. @itemize @bullet
  340. @item @b{SEGGER J-Link}
  341. @* Link: @url{}
  342. @item @b{Atmel SAM-ICE} (Only works with Atmel chips!)
  343. @* Link: @url{}
  344. @item @b{IAR J-Link}
  345. @end itemize
  346. @section USB RLINK based
  347. Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer,
  348. permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for
  349. SWD and not JTAG, thus not supported.
  350. @itemize @bullet
  351. @item @b{Raisonance RLink}
  352. @* Link: @url{}
  353. @item @b{STM32 Primer}
  354. @* Link: @url{}
  355. @item @b{STM32 Primer2}
  356. @* Link: @url{}
  357. @end itemize
  358. @section USB ST-LINK based
  359. STMicroelectronics has an adapter called @b{ST-LINK}.
  360. They only work with STMicroelectronics chips, notably STM32 and STM8.
  361. @itemize @bullet
  362. @item @b{ST-LINK}
  363. @* This is available standalone and as part of some kits, eg. STM32VLDISCOVERY.
  364. @* Link: @url{}
  365. @item @b{ST-LINK/V2}
  366. @* This is available standalone and as part of some kits, eg. STM32F4DISCOVERY.
  367. @* Link: @url{}
  368. @item @b{STLINK-V3}
  369. @* This is available standalone and as part of some kits.
  370. @* Link: @url{}
  371. @end itemize
  372. For info the original ST-LINK enumerates using the mass storage usb class; however,
  373. its implementation is completely broken. The result is this causes issues under Linux.
  374. The simplest solution is to get Linux to ignore the ST-LINK using one of the following methods:
  375. @itemize @bullet
  376. @item modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i
  377. @item add "options usb-storage quirks=483:3744:i" to /etc/modprobe.conf
  378. @end itemize
  379. @section USB TI/Stellaris ICDI based
  380. Texas Instruments has an adapter called @b{ICDI}.
  381. It is not to be confused with the FTDI based adapters that were originally fitted to their
  382. evaluation boards. This is the adapter fitted to the Stellaris LaunchPad.
  383. @section USB Nuvoton Nu-Link
  384. Nuvoton has an adapter called @b{Nu-Link}.
  385. It is available either as stand-alone dongle and embedded on development boards.
  386. It supports SWD, serial port bridge and mass storage for firmware update.
  387. Both Nu-Link v1 and v2 are supported.
  388. @section USB CMSIS-DAP based
  389. ARM has released a interface standard called CMSIS-DAP that simplifies connecting
  390. debuggers to ARM Cortex based targets @url{}.
  391. @section USB Other
  392. @itemize @bullet
  393. @item @b{USBprog}
  394. @* Link: @url{} - which uses an Atmel MEGA32 and a UBN9604
  395. @item @b{USB - Presto}
  396. @* Link: @url{}
  397. @item @b{Versaloon-Link}
  398. @* Link: @url{}
  399. @item @b{ARM-JTAG-EW}
  400. @* Link: @url{}
  401. @item @b{Buspirate}
  402. @* Link: @url{}
  403. @item @b{opendous}
  404. @* Link: @url{} - which uses an AT90USB162
  405. @item @b{estick}
  406. @* Link: @url{}
  407. @item @b{Keil ULINK v1}
  408. @* Link: @url{}
  409. @item @b{TI XDS110 Debug Probe}
  410. @* Link: @url{}
  411. @* Link: @url{}
  412. @end itemize
  413. @section IBM PC Parallel Printer Port Based
  414. The two well-known ``JTAG Parallel Ports'' cables are the Xilinx DLC5
  415. and the Macraigor Wiggler. There are many clones and variations of
  416. these on the market.
  417. Note that parallel ports are becoming much less common, so if you
  418. have the choice you should probably avoid these adapters in favor
  419. of USB-based ones.
  420. @itemize @bullet
  421. @item @b{Wiggler} - There are many clones of this.
  422. @* Link: @url{}
  423. @item @b{DLC5} - From XILINX - There are many clones of this
  424. @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
  425. produced, PDF schematics are easily found and it is easy to make.
  426. @item @b{Amontec - JTAG Accelerator}
  427. @* Link: @url{}
  428. @item @b{Wiggler2}
  429. @* Link: @url{}
  430. @item @b{Wiggler_ntrst_inverted}
  431. @* Yet another variation - See the source code, src/jtag/parport.c
  432. @item @b{old_amt_wiggler}
  433. @* Unknown - probably not on the market today
  434. @item @b{arm-jtag}
  435. @* Link: Most likely @url{} [another wiggler clone]
  436. @item @b{chameleon}
  437. @* Link: @url{}
  438. @item @b{Triton}
  439. @* Unknown.
  440. @item @b{Lattice}
  441. @* ispDownload from Lattice Semiconductor
  442. @url{}
  443. @item @b{flashlink}
  444. @* From STMicroelectronics;
  445. @* Link: @url{}
  446. @end itemize
  447. @section Other...
  448. @itemize @bullet
  449. @item @b{ep93xx}
  450. @* An EP93xx based Linux machine using the GPIO pins directly.
  451. @item @b{at91rm9200}
  452. @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
  453. @item @b{bcm2835gpio}
  454. @* A BCM2835-based board (e.g. Raspberry Pi) using the GPIO pins of the expansion header.
  455. @item @b{imx_gpio}
  456. @* A NXP i.MX-based board (e.g. Wandboard) using the GPIO pins (should work on any i.MX processor).
  457. @item @b{jtag_vpi}
  458. @* A JTAG driver acting as a client for the JTAG VPI server interface.
  459. @* Link: @url{}
  460. @item @b{jtag_dpi}
  461. @* A JTAG driver acting as a client for the SystemVerilog Direct Programming
  462. Interface (DPI) for JTAG devices. DPI allows OpenOCD to connect to the JTAG
  463. interface of a hardware model written in SystemVerilog, for example, on an
  464. emulation model of target hardware.
  465. @item @b{xlnx_pcie_xvc}
  466. @* A JTAG driver exposing Xilinx Virtual Cable over PCI Express to OpenOCD as JTAG/SWD interface.
  467. @item @b{linuxgpiod}
  468. @* A bitbang JTAG driver using Linux GPIO through library libgpiod.
  469. @item @b{sysfsgpio}
  470. @* A bitbang JTAG driver using Linux legacy sysfs GPIO.
  471. This is deprecated from Linux v5.3; prefer using @b{linuxgpiod}.
  472. @end itemize
  473. @node About Jim-Tcl
  474. @chapter About Jim-Tcl
  475. @cindex Jim-Tcl
  476. @cindex tcl
  477. OpenOCD uses a small ``Tcl Interpreter'' known as Jim-Tcl.
  478. This programming language provides a simple and extensible
  479. command interpreter.
  480. All commands presented in this Guide are extensions to Jim-Tcl.
  481. You can use them as simple commands, without needing to learn
  482. much of anything about Tcl.
  483. Alternatively, you can write Tcl programs with them.
  484. You can learn more about Jim at its website, @url{}.
  485. There is an active and responsive community, get on the mailing list
  486. if you have any questions. Jim-Tcl maintainers also lurk on the
  487. OpenOCD mailing list.
  488. @itemize @bullet
  489. @item @b{Jim vs. Tcl}
  490. @* Jim-Tcl is a stripped down version of the well known Tcl language,
  491. which can be found here: @url{}. Jim-Tcl has far
  492. fewer features. Jim-Tcl is several dozens of .C files and .H files and
  493. implements the basic Tcl command set. In contrast: Tcl 8.6 is a
  494. 4.2 MB .zip file containing 1540 files.
  495. @item @b{Missing Features}
  496. @* Our practice has been: Add/clone the real Tcl feature if/when
  497. needed. We welcome Jim-Tcl improvements, not bloat. Also there
  498. are a large number of optional Jim-Tcl features that are not
  499. enabled in OpenOCD.
  500. @item @b{Scripts}
  501. @* OpenOCD configuration scripts are Jim-Tcl Scripts. OpenOCD's
  502. command interpreter today is a mixture of (newer)
  503. Jim-Tcl commands, and the (older) original command interpreter.
  504. @item @b{Commands}
  505. @* At the OpenOCD telnet command line (or via the GDB monitor command) one
  506. can type a Tcl for() loop, set variables, etc.
  507. Some of the commands documented in this guide are implemented
  508. as Tcl scripts, from a @file{startup.tcl} file internal to the server.
  509. @item @b{Historical Note}
  510. @* Jim-Tcl was introduced to OpenOCD in spring 2008. Fall 2010,
  511. before OpenOCD 0.5 release, OpenOCD switched to using Jim-Tcl
  512. as a Git submodule, which greatly simplified upgrading Jim-Tcl
  513. to benefit from new features and bugfixes in Jim-Tcl.
  514. @item @b{Need a crash course in Tcl?}
  515. @*@xref{Tcl Crash Course}.
  516. @end itemize
  517. @node Running
  518. @chapter Running
  519. @cindex command line options
  520. @cindex logfile
  521. @cindex directory search
  522. Properly installing OpenOCD sets up your operating system to grant it access
  523. to the debug adapters. On Linux, this usually involves installing a file
  524. in @file{/etc/udev/rules.d,} so OpenOCD has permissions. An example rules file
  525. that works for many common adapters is shipped with OpenOCD in the
  526. @file{contrib} directory. MS-Windows needs
  527. complex and confusing driver configuration for every peripheral. Such issues
  528. are unique to each operating system, and are not detailed in this User's Guide.
  529. Then later you will invoke the OpenOCD server, with various options to
  530. tell it how each debug session should work.
  531. The @option{--help} option shows:
  532. @verbatim
  533. bash$ openocd --help
  534. --help | -h display this help
  535. --version | -v display OpenOCD version
  536. --file | -f use configuration file <name>
  537. --search | -s dir to search for config files and scripts
  538. --debug | -d set debug level to 3
  539. | -d<n> set debug level to <level>
  540. --log_output | -l redirect log output to file <name>
  541. --command | -c run <command>
  542. @end verbatim
  543. If you don't give any @option{-f} or @option{-c} options,
  544. OpenOCD tries to read the configuration file @file{openocd.cfg}.
  545. To specify one or more different
  546. configuration files, use @option{-f} options. For example:
  547. @example
  548. openocd -f config1.cfg -f config2.cfg -f config3.cfg
  549. @end example
  550. Configuration files and scripts are searched for in
  551. @enumerate
  552. @item the current directory,
  553. @item any search dir specified on the command line using the @option{-s} option,
  554. @item any search dir specified using the @command{add_script_search_dir} command,
  555. @item a directory in the @env{OPENOCD_SCRIPTS} environment variable (if set),
  556. @item @file{%APPDATA%/OpenOCD} (only on Windows),
  557. @item @file{$HOME/Library/Preferences/org.openocd} (only on Darwin),
  558. @item @file{$XDG_CONFIG_HOME/openocd} (@env{$XDG_CONFIG_HOME} defaults to @file{$HOME/.config}),
  559. @item @file{$HOME/.openocd},
  560. @item the site wide script library @file{$pkgdatadir/site} and
  561. @item the OpenOCD-supplied script library @file{$pkgdatadir/scripts}.
  562. @end enumerate
  563. The first found file with a matching file name will be used.
  564. @quotation Note
  565. Don't try to use configuration script names or paths which
  566. include the "#" character. That character begins Tcl comments.
  567. @end quotation
  568. @section Simple setup, no customization
  569. In the best case, you can use two scripts from one of the script
  570. libraries, hook up your JTAG adapter, and start the server ... and
  571. your JTAG setup will just work "out of the box". Always try to
  572. start by reusing those scripts, but assume you'll need more
  573. customization even if this works. @xref{OpenOCD Project Setup}.
  574. If you find a script for your JTAG adapter, and for your board or
  575. target, you may be able to hook up your JTAG adapter then start
  576. the server with some variation of one of the following:
  577. @example
  578. openocd -f interface/ADAPTER.cfg -f board/MYBOARD.cfg
  579. openocd -f interface/ftdi/ADAPTER.cfg -f board/MYBOARD.cfg
  580. @end example
  581. You might also need to configure which reset signals are present,
  582. using @option{-c 'reset_config trst_and_srst'} or something similar.
  583. If all goes well you'll see output something like
  584. @example
  585. Open On-Chip Debugger 0.4.0 (2010-01-14-15:06)
  586. For bug reports, read
  588. Info : JTAG tap: lm3s.cpu tap/device found: 0x3ba00477
  589. (mfg: 0x23b, part: 0xba00, ver: 0x3)
  590. @end example
  591. Seeing that "tap/device found" message, and no warnings, means
  592. the JTAG communication is working. That's a key milestone, but
  593. you'll probably need more project-specific setup.
  594. @section What OpenOCD does as it starts
  595. OpenOCD starts by processing the configuration commands provided
  596. on the command line or, if there were no @option{-c command} or
  597. @option{-f file.cfg} options given, in @file{openocd.cfg}.
  598. @xref{configurationstage,,Configuration Stage}.
  599. At the end of the configuration stage it verifies the JTAG scan
  600. chain defined using those commands; your configuration should
  601. ensure that this always succeeds.
  602. Normally, OpenOCD then starts running as a server.
  603. Alternatively, commands may be used to terminate the configuration
  604. stage early, perform work (such as updating some flash memory),
  605. and then shut down without acting as a server.
  606. Once OpenOCD starts running as a server, it waits for connections from
  607. clients (Telnet, GDB, RPC) and processes the commands issued through
  608. those channels.
  609. If you are having problems, you can enable internal debug messages via
  610. the @option{-d} option.
  611. Also it is possible to interleave Jim-Tcl commands w/config scripts using the
  612. @option{-c} command line switch.
  613. To enable debug output (when reporting problems or working on OpenOCD
  614. itself), use the @option{-d} command line switch. This sets the
  615. @option{debug_level} to "3", outputting the most information,
  616. including debug messages. The default setting is "2", outputting only
  617. informational messages, warnings and errors. You can also change this
  618. setting from within a telnet or gdb session using @command{debug_level<n>}
  619. (@pxref{debuglevel,,debug_level}).
  620. You can redirect all output from the server to a file using the
  621. @option{-l <logfile>} switch.
  622. Note! OpenOCD will launch the GDB & telnet server even if it can not
  623. establish a connection with the target. In general, it is possible for
  624. the JTAG controller to be unresponsive until the target is set up
  625. correctly via e.g. GDB monitor commands in a GDB init script.
  626. @node OpenOCD Project Setup
  627. @chapter OpenOCD Project Setup
  628. To use OpenOCD with your development projects, you need to do more than
  629. just connect the JTAG adapter hardware (dongle) to your development board
  630. and start the OpenOCD server.
  631. You also need to configure your OpenOCD server so that it knows
  632. about your adapter and board, and helps your work.
  633. You may also want to connect OpenOCD to GDB, possibly
  634. using Eclipse or some other GUI.
  635. @section Hooking up the JTAG Adapter
  636. Today's most common case is a dongle with a JTAG cable on one side
  637. (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
  638. and a USB cable on the other.
  639. Instead of USB, some dongles use Ethernet;
  640. older ones may use a PC parallel port, or even a serial port.
  641. @enumerate
  642. @item @emph{Start with power to your target board turned off},
  643. and nothing connected to your JTAG adapter.
  644. If you're particularly paranoid, unplug power to the board.
  645. It's important to have the ground signal properly set up,
  646. unless you are using a JTAG adapter which provides
  647. galvanic isolation between the target board and the
  648. debugging host.
  649. @item @emph{Be sure it's the right kind of JTAG connector.}
  650. If your dongle has a 20-pin ARM connector, you need some kind
  651. of adapter (or octopus, see below) to hook it up to
  652. boards using 14-pin or 10-pin connectors ... or to 20-pin
  653. connectors which don't use ARM's pinout.
  654. In the same vein, make sure the voltage levels are compatible.
  655. Not all JTAG adapters have the level shifters needed to work
  656. with 1.2 Volt boards.
  657. @item @emph{Be certain the cable is properly oriented} or you might
  658. damage your board. In most cases there are only two possible
  659. ways to connect the cable.
  660. Connect the JTAG cable from your adapter to the board.
  661. Be sure it's firmly connected.
  662. In the best case, the connector is keyed to physically
  663. prevent you from inserting it wrong.
  664. This is most often done using a slot on the board's male connector
  665. housing, which must match a key on the JTAG cable's female connector.
  666. If there's no housing, then you must look carefully and
  667. make sure pin 1 on the cable hooks up to pin 1 on the board.
  668. Ribbon cables are frequently all grey except for a wire on one
  669. edge, which is red. The red wire is pin 1.
  670. Sometimes dongles provide cables where one end is an ``octopus'' of
  671. color coded single-wire connectors, instead of a connector block.
  672. These are great when converting from one JTAG pinout to another,
  673. but are tedious to set up.
  674. Use these with connector pinout diagrams to help you match up the
  675. adapter signals to the right board pins.
  676. @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
  677. A USB, parallel, or serial port connector will go to the host which
  678. you are using to run OpenOCD.
  679. For Ethernet, consult the documentation and your network administrator.
  680. For USB-based JTAG adapters you have an easy sanity check at this point:
  681. does the host operating system see the JTAG adapter? If you're running
  682. Linux, try the @command{lsusb} command. If that host is an
  683. MS-Windows host, you'll need to install a driver before OpenOCD works.
  684. @item @emph{Connect the adapter's power supply, if needed.}
  685. This step is primarily for non-USB adapters,
  686. but sometimes USB adapters need extra power.
  687. @item @emph{Power up the target board.}
  688. Unless you just let the magic smoke escape,
  689. you're now ready to set up the OpenOCD server
  690. so you can use JTAG to work with that board.
  691. @end enumerate
  692. Talk with the OpenOCD server using
  693. telnet (@code{telnet localhost 4444} on many systems) or GDB.
  694. @xref{GDB and OpenOCD}.
  695. @section Project Directory
  696. There are many ways you can configure OpenOCD and start it up.
  697. A simple way to organize them all involves keeping a
  698. single directory for your work with a given board.
  699. When you start OpenOCD from that directory,
  700. it searches there first for configuration files, scripts,
  701. files accessed through semihosting,
  702. and for code you upload to the target board.
  703. It is also the natural place to write files,
  704. such as log files and data you download from the board.
  705. @section Configuration Basics
  706. There are two basic ways of configuring OpenOCD, and
  707. a variety of ways you can mix them.
  708. Think of the difference as just being how you start the server:
  709. @itemize
  710. @item Many @option{-f file} or @option{-c command} options on the command line
  711. @item No options, but a @dfn{user config file}
  712. in the current directory named @file{openocd.cfg}
  713. @end itemize
  714. Here is an example @file{openocd.cfg} file for a setup
  715. using a Signalyzer FT2232-based JTAG adapter to talk to
  716. a board with an Atmel AT91SAM7X256 microcontroller:
  717. @example
  718. source [find interface/ftdi/signalyzer.cfg]
  719. # GDB can also flash my flash!
  720. gdb_memory_map enable
  721. gdb_flash_program enable
  722. source [find target/sam7x256.cfg]
  723. @end example
  724. Here is the command line equivalent of that configuration:
  725. @example
  726. openocd -f interface/ftdi/signalyzer.cfg \
  727. -c "gdb_memory_map enable" \
  728. -c "gdb_flash_program enable" \
  729. -f target/sam7x256.cfg
  730. @end example
  731. You could wrap such long command lines in shell scripts,
  732. each supporting a different development task.
  733. One might re-flash the board with a specific firmware version.
  734. Another might set up a particular debugging or run-time environment.
  735. @quotation Important
  736. At this writing (October 2009) the command line method has
  737. problems with how it treats variables.
  738. For example, after @option{-c "set VAR value"}, or doing the
  739. same in a script, the variable @var{VAR} will have no value
  740. that can be tested in a later script.
  741. @end quotation
  742. Here we will focus on the simpler solution: one user config
  743. file, including basic configuration plus any TCL procedures
  744. to simplify your work.
  745. @section User Config Files
  746. @cindex config file, user
  747. @cindex user config file
  748. @cindex config file, overview
  749. A user configuration file ties together all the parts of a project
  750. in one place.
  751. One of the following will match your situation best:
  752. @itemize
  753. @item Ideally almost everything comes from configuration files
  754. provided by someone else.
  755. For example, OpenOCD distributes a @file{scripts} directory
  756. (probably in @file{/usr/share/openocd/scripts} on Linux).
  757. Board and tool vendors can provide these too, as can individual
  758. user sites; the @option{-s} command line option lets you say
  759. where to find these files. (@xref{Running}.)
  760. The AT91SAM7X256 example above works this way.
  761. Three main types of non-user configuration file each have their
  762. own subdirectory in the @file{scripts} directory:
  763. @enumerate
  764. @item @b{interface} -- one for each different debug adapter;
  765. @item @b{board} -- one for each different board
  766. @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
  767. @end enumerate
  768. Best case: include just two files, and they handle everything else.
  769. The first is an interface config file.
  770. The second is board-specific, and it sets up the JTAG TAPs and
  771. their GDB targets (by deferring to some @file{target.cfg} file),
  772. declares all flash memory, and leaves you nothing to do except
  773. meet your deadline:
  774. @example
  775. source [find interface/olimex-jtag-tiny.cfg]
  776. source [find board/csb337.cfg]
  777. @end example
  778. Boards with a single microcontroller often won't need more
  779. than the target config file, as in the AT91SAM7X256 example.
  780. That's because there is no external memory (flash, DDR RAM), and
  781. the board differences are encapsulated by application code.
  782. @item Maybe you don't know yet what your board looks like to JTAG.
  783. Once you know the @file{interface.cfg} file to use, you may
  784. need help from OpenOCD to discover what's on the board.
  785. Once you find the JTAG TAPs, you can just search for appropriate
  786. target and board
  787. configuration files ... or write your own, from the bottom up.
  788. @xref{autoprobing,,Autoprobing}.
  789. @item You can often reuse some standard config files but
  790. need to write a few new ones, probably a @file{board.cfg} file.
  791. You will be using commands described later in this User's Guide,
  792. and working with the guidelines in the next chapter.
  793. For example, there may be configuration files for your JTAG adapter
  794. and target chip, but you need a new board-specific config file
  795. giving access to your particular flash chips.
  796. Or you might need to write another target chip configuration file
  797. for a new chip built around the Cortex-M3 core.
  798. @quotation Note
  799. When you write new configuration files, please submit
  800. them for inclusion in the next OpenOCD release.
  801. For example, a @file{board/newboard.cfg} file will help the
  802. next users of that board, and a @file{target/newcpu.cfg}
  803. will help support users of any board using that chip.
  804. @end quotation
  805. @item
  806. You may need to write some C code.
  807. It may be as simple as supporting a new FT2232 or parport
  808. based adapter; a bit more involved, like a NAND or NOR flash
  809. controller driver; or a big piece of work like supporting
  810. a new chip architecture.
  811. @end itemize
  812. Reuse the existing config files when you can.
  813. Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
  814. You may find a board configuration that's a good example to follow.
  815. When you write config files, separate the reusable parts
  816. (things every user of that interface, chip, or board needs)
  817. from ones specific to your environment and debugging approach.
  818. @itemize
  819. @item
  820. For example, a @code{gdb-attach} event handler that invokes
  821. the @command{reset init} command will interfere with debugging
  822. early boot code, which performs some of the same actions
  823. that the @code{reset-init} event handler does.
  824. @item
  825. Likewise, the @command{arm9 vector_catch} command (or
  826. @cindex vector_catch
  827. its siblings @command{xscale vector_catch}
  828. and @command{cortex_m vector_catch}) can be a time-saver
  829. during some debug sessions, but don't make everyone use that either.
  830. Keep those kinds of debugging aids in your user config file,
  831. along with messaging and tracing setup.
  832. (@xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.)
  833. @item
  834. You might need to override some defaults.
  835. For example, you might need to move, shrink, or back up the target's
  836. work area if your application needs much SRAM.
  837. @item
  838. TCP/IP port configuration is another example of something which
  839. is environment-specific, and should only appear in
  840. a user config file. @xref{tcpipports,,TCP/IP Ports}.
  841. @end itemize
  842. @section Project-Specific Utilities
  843. A few project-specific utility
  844. routines may well speed up your work.
  845. Write them, and keep them in your project's user config file.
  846. For example, if you are making a boot loader work on a
  847. board, it's nice to be able to debug the ``after it's
  848. loaded to RAM'' parts separately from the finicky early
  849. code which sets up the DDR RAM controller and clocks.
  850. A script like this one, or a more GDB-aware sibling,
  851. may help:
  852. @example
  853. proc ramboot @{ @} @{
  854. # Reset, running the target's "reset-init" scripts
  855. # to initialize clocks and the DDR RAM controller.
  856. # Leave the CPU halted.
  857. reset init
  858. # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
  859. load_image u-boot.bin 0x20000000
  860. # Start running.
  861. resume 0x20000000
  862. @}
  863. @end example
  864. Then once that code is working you will need to make it
  865. boot from NOR flash; a different utility would help.
  866. Alternatively, some developers write to flash using GDB.
  867. (You might use a similar script if you're working with a flash
  868. based microcontroller application instead of a boot loader.)
  869. @example
  870. proc newboot @{ @} @{
  871. # Reset, leaving the CPU halted. The "reset-init" event
  872. # proc gives faster access to the CPU and to NOR flash;
  873. # "reset halt" would be slower.
  874. reset init
  875. # Write standard version of U-Boot into the first two
  876. # sectors of NOR flash ... the standard version should
  877. # do the same lowlevel init as "reset-init".
  878. flash protect 0 0 1 off
  879. flash erase_sector 0 0 1
  880. flash write_bank 0 u-boot.bin 0x0
  881. flash protect 0 0 1 on
  882. # Reboot from scratch using that new boot loader.
  883. reset run
  884. @}
  885. @end example
  886. You may need more complicated utility procedures when booting
  887. from NAND.
  888. That often involves an extra bootloader stage,
  889. running from on-chip SRAM to perform DDR RAM setup so it can load
  890. the main bootloader code (which won't fit into that SRAM).
  891. Other helper scripts might be used to write production system images,
  892. involving considerably more than just a three stage bootloader.
  893. @section Target Software Changes
  894. Sometimes you may want to make some small changes to the software
  895. you're developing, to help make JTAG debugging work better.
  896. For example, in C or assembly language code you might
  897. use @code{#ifdef JTAG_DEBUG} (or its converse) around code
  898. handling issues like:
  899. @itemize @bullet
  900. @item @b{Watchdog Timers}...
  901. Watchdog timers are typically used to automatically reset systems if
  902. some application task doesn't periodically reset the timer. (The
  903. assumption is that the system has locked up if the task can't run.)
  904. When a JTAG debugger halts the system, that task won't be able to run
  905. and reset the timer ... potentially causing resets in the middle of
  906. your debug sessions.
  907. It's rarely a good idea to disable such watchdogs, since their usage
  908. needs to be debugged just like all other parts of your firmware.
  909. That might however be your only option.
  910. Look instead for chip-specific ways to stop the watchdog from counting
  911. while the system is in a debug halt state. It may be simplest to set
  912. that non-counting mode in your debugger startup scripts. You may however
  913. need a different approach when, for example, a motor could be physically
  914. damaged by firmware remaining inactive in a debug halt state. That might
  915. involve a type of firmware mode where that "non-counting" mode is disabled
  916. at the beginning then re-enabled at the end; a watchdog reset might fire
  917. and complicate the debug session, but hardware (or people) would be
  918. protected.@footnote{Note that many systems support a "monitor mode" debug
  919. that is a somewhat cleaner way to address such issues. You can think of
  920. it as only halting part of the system, maybe just one task,
  921. instead of the whole thing.
  922. At this writing, January 2010, OpenOCD based debugging does not support
  923. monitor mode debug, only "halt mode" debug.}
  924. @item @b{ARM Semihosting}...
  925. @cindex ARM semihosting
  926. When linked with a special runtime library provided with many
  927. toolchains@footnote{See chapter 8 "Semihosting" in
  928. @uref{,
  929. ARM DUI 0203I}, the "RealView Compilation Tools Developer Guide".
  930. The CodeSourcery EABI toolchain also includes a semihosting library.},
  931. your target code can use I/O facilities on the debug host. That library
  932. provides a small set of system calls which are handled by OpenOCD.
  933. It can let the debugger provide your system console and a file system,
  934. helping with early debugging or providing a more capable environment
  935. for sometimes-complex tasks like installing system firmware onto
  936. NAND or SPI flash.
  937. @item @b{ARM Wait-For-Interrupt}...
  938. Many ARM chips synchronize the JTAG clock using the core clock.
  939. Low power states which stop that core clock thus prevent JTAG access.
  940. Idle loops in tasking environments often enter those low power states
  941. via the @code{WFI} instruction (or its coprocessor equivalent, before ARMv7).
  942. You may want to @emph{disable that instruction} in source code,
  943. or otherwise prevent using that state,
  944. to ensure you can get JTAG access at any time.@footnote{As a more
  945. polite alternative, some processors have special debug-oriented
  946. registers which can be used to change various features including
  947. how the low power states are clocked while debugging.
  948. The STM32 DBGMCU_CR register is an example; at the cost of extra
  949. power consumption, JTAG can be used during low power states.}
  950. For example, the OpenOCD @command{halt} command may not
  951. work for an idle processor otherwise.
  952. @item @b{Delay after reset}...
  953. Not all chips have good support for debugger access
  954. right after reset; many LPC2xxx chips have issues here.
  955. Similarly, applications that reconfigure pins used for
  956. JTAG access as they start will also block debugger access.
  957. To work with boards like this, @emph{enable a short delay loop}
  958. the first thing after reset, before "real" startup activities.
  959. For example, one second's delay is usually more than enough
  960. time for a JTAG debugger to attach, so that
  961. early code execution can be debugged
  962. or firmware can be replaced.
  963. @item @b{Debug Communications Channel (DCC)}...
  964. Some processors include mechanisms to send messages over JTAG.
  965. Many ARM cores support these, as do some cores from other vendors.
  966. (OpenOCD may be able to use this DCC internally, speeding up some
  967. operations like writing to memory.)
  968. Your application may want to deliver various debugging messages
  969. over JTAG, by @emph{linking with a small library of code}
  970. provided with OpenOCD and using the utilities there to send
  971. various kinds of message.
  972. @xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.
  973. @end itemize
  974. @section Target Hardware Setup
  975. Chip vendors often provide software development boards which
  976. are highly configurable, so that they can support all options
  977. that product boards may require. @emph{Make sure that any
  978. jumpers or switches match the system configuration you are
  979. working with.}
  980. Common issues include:
  981. @itemize @bullet
  982. @item @b{JTAG setup} ...
  983. Boards may support more than one JTAG configuration.
  984. Examples include jumpers controlling pullups versus pulldowns
  985. on the nTRST and/or nSRST signals, and choice of connectors
  986. (e.g. which of two headers on the base board,
  987. or one from a daughtercard).
  988. For some Texas Instruments boards, you may need to jumper the
  989. EMU0 and EMU1 signals (which OpenOCD won't currently control).
  990. @item @b{Boot Modes} ...
  991. Complex chips often support multiple boot modes, controlled
  992. by external jumpers. Make sure this is set up correctly.
  993. For example many i.MX boards from NXP need to be jumpered
  994. to "ATX mode" to start booting using the on-chip ROM, when
  995. using second stage bootloader code stored in a NAND flash chip.
  996. Such explicit configuration is common, and not limited to
  997. booting from NAND. You might also need to set jumpers to
  998. start booting using code loaded from an MMC/SD card; external
  999. SPI flash; Ethernet, UART, or USB links; NOR flash; OneNAND
  1000. flash; some external host; or various other sources.
  1001. @item @b{Memory Addressing} ...
  1002. Boards which support multiple boot modes may also have jumpers
  1003. to configure memory addressing. One board, for example, jumpers
  1004. external chipselect 0 (used for booting) to address either
  1005. a large SRAM (which must be pre-loaded via JTAG), NOR flash,
  1006. or NAND flash. When it's jumpered to address NAND flash, that
  1007. board must also be told to start booting from on-chip ROM.
  1008. Your @file{board.cfg} file may also need to be told this jumper
  1009. configuration, so that it can know whether to declare NOR flash
  1010. using @command{flash bank} or instead declare NAND flash with
  1011. @command{nand device}; and likewise which probe to perform in
  1012. its @code{reset-init} handler.
  1013. A closely related issue is bus width. Jumpers might need to
  1014. distinguish between 8 bit or 16 bit bus access for the flash
  1015. used to start booting.
  1016. @item @b{Peripheral Access} ...
  1017. Development boards generally provide access to every peripheral
  1018. on the chip, sometimes in multiple modes (such as by providing
  1019. multiple audio codec chips).
  1020. This interacts with software
  1021. configuration of pin multiplexing, where for example a
  1022. given pin may be routed either to the MMC/SD controller
  1023. or the GPIO controller. It also often interacts with
  1024. configuration jumpers. One jumper may be used to route
  1025. signals to an MMC/SD card slot or an expansion bus (which
  1026. might in turn affect booting); others might control which
  1027. audio or video codecs are used.
  1028. @end itemize
  1029. Plus you should of course have @code{reset-init} event handlers
  1030. which set up the hardware to match that jumper configuration.
  1031. That includes in particular any oscillator or PLL used to clock
  1032. the CPU, and any memory controllers needed to access external
  1033. memory and peripherals. Without such handlers, you won't be
  1034. able to access those resources without working target firmware
  1035. which can do that setup ... this can be awkward when you're
  1036. trying to debug that target firmware. Even if there's a ROM
  1037. bootloader which handles a few issues, it rarely provides full
  1038. access to all board-specific capabilities.
  1039. @node Config File Guidelines
  1040. @chapter Config File Guidelines
  1041. This chapter is aimed at any user who needs to write a config file,
  1042. including developers and integrators of OpenOCD and any user who
  1043. needs to get a new board working smoothly.
  1044. It provides guidelines for creating those files.
  1045. You should find the following directories under
  1046. @t{$(INSTALLDIR)/scripts}, with config files maintained upstream. Use
  1047. them as-is where you can; or as models for new files.
  1048. @itemize @bullet
  1049. @item @file{interface} ...
  1050. These are for debug adapters. Files that specify configuration to use
  1051. specific JTAG, SWD and other adapters go here.
  1052. @item @file{board} ...
  1053. Think Circuit Board, PWA, PCB, they go by many names. Board files
  1054. contain initialization items that are specific to a board.
  1055. They reuse target configuration files, since the same
  1056. microprocessor chips are used on many boards,
  1057. but support for external parts varies widely. For
  1058. example, the SDRAM initialization sequence for the board, or the type
  1059. of external flash and what address it uses. Any initialization
  1060. sequence to enable that external flash or SDRAM should be found in the
  1061. board file. Boards may also contain multiple targets: two CPUs; or
  1062. a CPU and an FPGA.
  1063. @item @file{target} ...
  1064. Think chip. The ``target'' directory represents the JTAG TAPs
  1065. on a chip
  1066. which OpenOCD should control, not a board. Two common types of targets
  1067. are ARM chips and FPGA or CPLD chips.
  1068. When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
  1069. the target config file defines all of them.
  1070. @item @emph{more} ... browse for other library files which may be useful.
  1071. For example, there are various generic and CPU-specific utilities.
  1072. @end itemize
  1073. The @file{openocd.cfg} user config
  1074. file may override features in any of the above files by
  1075. setting variables before sourcing the target file, or by adding
  1076. commands specific to their situation.
  1077. @section Interface Config Files
  1078. The user config file
  1079. should be able to source one of these files with a command like this:
  1080. @example
  1081. source [find interface/FOOBAR.cfg]
  1082. @end example
  1083. A preconfigured interface file should exist for every debug adapter
  1084. in use today with OpenOCD.
  1085. That said, perhaps some of these config files
  1086. have only been used by the developer who created it.
  1087. A separate chapter gives information about how to set these up.
  1088. @xref{Debug Adapter Configuration}.
  1089. Read the OpenOCD source code (and Developer's Guide)
  1090. if you have a new kind of hardware interface
  1091. and need to provide a driver for it.
  1092. @section Board Config Files
  1093. @cindex config file, board
  1094. @cindex board config file
  1095. The user config file
  1096. should be able to source one of these files with a command like this:
  1097. @example
  1098. source [find board/FOOBAR.cfg]
  1099. @end example
  1100. The point of a board config file is to package everything
  1101. about a given board that user config files need to know.
  1102. In summary the board files should contain (if present)
  1103. @enumerate
  1104. @item One or more @command{source [find target/...cfg]} statements
  1105. @item NOR flash configuration (@pxref{norconfiguration,,NOR Configuration})
  1106. @item NAND flash configuration (@pxref{nandconfiguration,,NAND Configuration})
  1107. @item Target @code{reset} handlers for SDRAM and I/O configuration
  1108. @item JTAG adapter reset configuration (@pxref{Reset Configuration})
  1109. @item All things that are not ``inside a chip''
  1110. @end enumerate
  1111. Generic things inside target chips belong in target config files,
  1112. not board config files. So for example a @code{reset-init} event
  1113. handler should know board-specific oscillator and PLL parameters,
  1114. which it passes to target-specific utility code.
  1115. The most complex task of a board config file is creating such a
  1116. @code{reset-init} event handler.
  1117. Define those handlers last, after you verify the rest of the board
  1118. configuration works.
  1119. @subsection Communication Between Config files
  1120. In addition to target-specific utility code, another way that
  1121. board and target config files communicate is by following a
  1122. convention on how to use certain variables.
  1123. The full Tcl/Tk language supports ``namespaces'', but Jim-Tcl does not.
  1124. Thus the rule we follow in OpenOCD is this: Variables that begin with
  1125. a leading underscore are temporary in nature, and can be modified and
  1126. used at will within a target configuration file.
  1127. Complex board config files can do the things like this,
  1128. for a board with three chips:
  1129. @example
  1130. # Chip #1: PXA270 for network side, big endian
  1131. set CHIPNAME network
  1132. set ENDIAN big
  1133. source [find target/pxa270.cfg]
  1134. # on return: _TARGETNAME = network.cpu
  1135. # other commands can refer to the "network.cpu" target.
  1136. $_TARGETNAME configure .... events for this CPU..
  1137. # Chip #2: PXA270 for video side, little endian
  1138. set CHIPNAME video
  1139. set ENDIAN little
  1140. source [find target/pxa270.cfg]
  1141. # on return: _TARGETNAME = video.cpu
  1142. # other commands can refer to the "video.cpu" target.
  1143. $_TARGETNAME configure .... events for this CPU..
  1144. # Chip #3: Xilinx FPGA for glue logic
  1145. set CHIPNAME xilinx
  1146. unset ENDIAN
  1147. source [find target/spartan3.cfg]
  1148. @end example
  1149. That example is oversimplified because it doesn't show any flash memory,
  1150. or the @code{reset-init} event handlers to initialize external DRAM
  1151. or (assuming it needs it) load a configuration into the FPGA.
  1152. Such features are usually needed for low-level work with many boards,
  1153. where ``low level'' implies that the board initialization software may
  1154. not be working. (That's a common reason to need JTAG tools. Another
  1155. is to enable working with microcontroller-based systems, which often
  1156. have no debugging support except a JTAG connector.)
  1157. Target config files may also export utility functions to board and user
  1158. config files. Such functions should use name prefixes, to help avoid
  1159. naming collisions.
  1160. Board files could also accept input variables from user config files.
  1161. For example, there might be a @code{J4_JUMPER} setting used to identify
  1162. what kind of flash memory a development board is using, or how to set
  1163. up other clocks and peripherals.
  1164. @subsection Variable Naming Convention
  1165. @cindex variable names
  1166. Most boards have only one instance of a chip.
  1167. However, it should be easy to create a board with more than
  1168. one such chip (as shown above).
  1169. Accordingly, we encourage these conventions for naming
  1170. variables associated with different @file{target.cfg} files,
  1171. to promote consistency and
  1172. so that board files can override target defaults.
  1173. Inputs to target config files include:
  1174. @itemize @bullet
  1175. @item @code{CHIPNAME} ...
  1176. This gives a name to the overall chip, and is used as part of
  1177. tap identifier dotted names.
  1178. While the default is normally provided by the chip manufacturer,
  1179. board files may need to distinguish between instances of a chip.
  1180. @item @code{ENDIAN} ...
  1181. By default @option{little} - although chips may hard-wire @option{big}.
  1182. Chips that can't change endianness don't need to use this variable.
  1183. @item @code{CPUTAPID} ...
  1184. When OpenOCD examines the JTAG chain, it can be told verify the
  1185. chips against the JTAG IDCODE register.
  1186. The target file will hold one or more defaults, but sometimes the
  1187. chip in a board will use a different ID (perhaps a newer revision).
  1188. @end itemize
  1189. Outputs from target config files include:
  1190. @itemize @bullet
  1191. @item @code{_TARGETNAME} ...
  1192. By convention, this variable is created by the target configuration
  1193. script. The board configuration file may make use of this variable to
  1194. configure things like a ``reset init'' script, or other things
  1195. specific to that board and that target.
  1196. If the chip has 2 targets, the names are @code{_TARGETNAME0},
  1197. @code{_TARGETNAME1}, ... etc.
  1198. @end itemize
  1199. @subsection The reset-init Event Handler
  1200. @cindex event, reset-init
  1201. @cindex reset-init handler
  1202. Board config files run in the OpenOCD configuration stage;
  1203. they can't use TAPs or targets, since they haven't been
  1204. fully set up yet.
  1205. This means you can't write memory or access chip registers;
  1206. you can't even verify that a flash chip is present.
  1207. That's done later in event handlers, of which the target @code{reset-init}
  1208. handler is one of the most important.
  1209. Except on microcontrollers, the basic job of @code{reset-init} event
  1210. handlers is setting up flash and DRAM, as normally handled by boot loaders.
  1211. Microcontrollers rarely use boot loaders; they run right out of their
  1212. on-chip flash and SRAM memory. But they may want to use one of these
  1213. handlers too, if just for developer convenience.
  1214. @quotation Note
  1215. Because this is so very board-specific, and chip-specific, no examples
  1216. are included here.
  1217. Instead, look at the board config files distributed with OpenOCD.
  1218. If you have a boot loader, its source code will help; so will
  1219. configuration files for other JTAG tools
  1220. (@pxref{translatingconfigurationfiles,,Translating Configuration Files}).
  1221. @end quotation
  1222. Some of this code could probably be shared between different boards.
  1223. For example, setting up a DRAM controller often doesn't differ by
  1224. much except the bus width (16 bits or 32?) and memory timings, so a
  1225. reusable TCL procedure loaded by the @file{target.cfg} file might take
  1226. those as parameters.
  1227. Similarly with oscillator, PLL, and clock setup;
  1228. and disabling the watchdog.
  1229. Structure the code cleanly, and provide comments to help
  1230. the next developer doing such work.
  1231. (@emph{You might be that next person} trying to reuse init code!)
  1232. The last thing normally done in a @code{reset-init} handler is probing
  1233. whatever flash memory was configured. For most chips that needs to be
  1234. done while the associated target is halted, either because JTAG memory
  1235. access uses the CPU or to prevent conflicting CPU access.
  1236. @subsection JTAG Clock Rate
  1237. Before your @code{reset-init} handler has set up
  1238. the PLLs and clocking, you may need to run with
  1239. a low JTAG clock rate.
  1240. @xref{jtagspeed,,JTAG Speed}.
  1241. Then you'd increase that rate after your handler has
  1242. made it possible to use the faster JTAG clock.
  1243. When the initial low speed is board-specific, for example
  1244. because it depends on a board-specific oscillator speed, then
  1245. you should probably set it up in the board config file;
  1246. if it's target-specific, it belongs in the target config file.
  1247. For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
  1248. @uref{} gives details.}
  1249. is one sixth of the CPU clock; or one eighth for ARM11 cores.
  1250. Consult chip documentation to determine the peak JTAG clock rate,
  1251. which might be less than that.
  1252. @quotation Warning
  1253. On most ARMs, JTAG clock detection is coupled to the core clock, so
  1254. software using a @option{wait for interrupt} operation blocks JTAG access.
  1255. Adaptive clocking provides a partial workaround, but a more complete
  1256. solution just avoids using that instruction with JTAG debuggers.
  1257. @end quotation
  1258. If both the chip and the board support adaptive clocking,
  1259. use the @command{jtag_rclk}
  1260. command, in case your board is used with JTAG adapter which
  1261. also supports it. Otherwise use @command{adapter speed}.
  1262. Set the slow rate at the beginning of the reset sequence,
  1263. and the faster rate as soon as the clocks are at full speed.
  1264. @anchor{theinitboardprocedure}
  1265. @subsection The init_board procedure
  1266. @cindex init_board procedure
  1267. The concept of @code{init_board} procedure is very similar to @code{init_targets}
  1268. (@xref{theinittargetsprocedure,,The init_targets procedure}.) - it's a replacement of ``linear''
  1269. configuration scripts. This procedure is meant to be executed when OpenOCD enters run stage
  1270. (@xref{enteringtherunstage,,Entering the Run Stage},) after @code{init_targets}. The idea to have
  1271. separate @code{init_targets} and @code{init_board} procedures is to allow the first one to configure
  1272. everything target specific (internal flash, internal RAM, etc.) and the second one to configure
  1273. everything board specific (reset signals, chip frequency, reset-init event handler, external memory, etc.).
  1274. Additionally ``linear'' board config file will most likely fail when target config file uses
  1275. @code{init_targets} scheme (``linear'' script is executed before @code{init} and @code{init_targets} - after),
  1276. so separating these two configuration stages is very convenient, as the easiest way to overcome this
  1277. problem is to convert board config file to use @code{init_board} procedure. Board config scripts don't
  1278. need to override @code{init_targets} defined in target config files when they only need to add some specifics.
  1279. Just as @code{init_targets}, the @code{init_board} procedure can be overridden by ``next level'' script (which sources
  1280. the original), allowing greater code reuse.
  1281. @example
  1282. ### board_file.cfg ###
  1283. # source target file that does most of the config in init_targets
  1284. source [find target/target.cfg]
  1285. proc enable_fast_clock @{@} @{
  1286. # enables fast on-board clock source
  1287. # configures the chip to use it
  1288. @}
  1289. # initialize only board specifics - reset, clock, adapter frequency
  1290. proc init_board @{@} @{
  1291. reset_config trst_and_srst trst_pulls_srst
  1292. $_TARGETNAME configure -event reset-start @{
  1293. adapter speed 100
  1294. @}
  1295. $_TARGETNAME configure -event reset-init @{
  1296. enable_fast_clock
  1297. adapter speed 10000
  1298. @}
  1299. @}
  1300. @end example
  1301. @section Target Config Files
  1302. @cindex config file, target
  1303. @cindex target config file
  1304. Board config files communicate with target config files using
  1305. naming conventions as described above, and may source one or
  1306. more target config files like this:
  1307. @example
  1308. source [find target/FOOBAR.cfg]
  1309. @end example
  1310. The point of a target config file is to package everything
  1311. about a given chip that board config files need to know.
  1312. In summary the target files should contain
  1313. @enumerate
  1314. @item Set defaults
  1315. @item Add TAPs to the scan chain
  1316. @item Add CPU targets (includes GDB support)
  1317. @item CPU/Chip/CPU-Core specific features
  1318. @item On-Chip flash
  1319. @end enumerate
  1320. As a rule of thumb, a target file sets up only one chip.
  1321. For a microcontroller, that will often include a single TAP,
  1322. which is a CPU needing a GDB target, and its on-chip flash.
  1323. More complex chips may include multiple TAPs, and the target
  1324. config file may need to define them all before OpenOCD
  1325. can talk to the chip.
  1326. For example, some phone chips have JTAG scan chains that include
  1327. an ARM core for operating system use, a DSP,
  1328. another ARM core embedded in an image processing engine,
  1329. and other processing engines.
  1330. @subsection Default Value Boiler Plate Code
  1331. All target configuration files should start with code like this,
  1332. letting board config files express environment-specific
  1333. differences in how things should be set up.
  1334. @example
  1335. # Boards may override chip names, perhaps based on role,
  1336. # but the default should match what the vendor uses
  1337. if @{ [info exists CHIPNAME] @} @{
  1339. @} else @{
  1340. set _CHIPNAME sam7x256
  1341. @}
  1342. # ONLY use ENDIAN with targets that can change it.
  1343. if @{ [info exists ENDIAN] @} @{
  1344. set _ENDIAN $ENDIAN
  1345. @} else @{
  1346. set _ENDIAN little
  1347. @}
  1348. # TAP identifiers may change as chips mature, for example with
  1349. # new revision fields (the "3" here). Pick a good default; you
  1350. # can pass several such identifiers to the "jtag newtap" command.
  1351. if @{ [info exists CPUTAPID ] @} @{
  1353. @} else @{
  1354. set _CPUTAPID 0x3f0f0f0f
  1355. @}
  1356. @end example
  1357. @c but 0x3f0f0f0f is for an str73x part ...
  1358. @emph{Remember:} Board config files may include multiple target
  1359. config files, or the same target file multiple times
  1360. (changing at least @code{CHIPNAME}).
  1361. Likewise, the target configuration file should define
  1362. @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
  1363. use it later on when defining debug targets:
  1364. @example
  1365. set _TARGETNAME $_CHIPNAME.cpu
  1366. target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
  1367. @end example
  1368. @subsection Adding TAPs to the Scan Chain
  1369. After the ``defaults'' are set up,
  1370. add the TAPs on each chip to the JTAG scan chain.
  1371. @xref{TAP Declaration}, and the naming convention
  1372. for taps.
  1373. In the simplest case the chip has only one TAP,
  1374. probably for a CPU or FPGA.
  1375. The config file for the Atmel AT91SAM7X256
  1376. looks (in part) like this:
  1377. @example
  1378. jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
  1379. @end example
  1380. A board with two such at91sam7 chips would be able
  1381. to source such a config file twice, with different
  1382. values for @code{CHIPNAME}, so
  1383. it adds a different TAP each time.
  1384. If there are nonzero @option{-expected-id} values,
  1385. OpenOCD attempts to verify the actual tap id against those values.
  1386. It will issue error messages if there is mismatch, which
  1387. can help to pinpoint problems in OpenOCD configurations.
  1388. @example
  1389. JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
  1390. (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
  1391. ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
  1392. ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
  1393. ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
  1394. @end example
  1395. There are more complex examples too, with chips that have
  1396. multiple TAPs. Ones worth looking at include:
  1397. @itemize
  1398. @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
  1399. plus a JRC to enable them
  1400. @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
  1401. @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
  1402. is not currently used)
  1403. @end itemize
  1404. @subsection Add CPU targets
  1405. After adding a TAP for a CPU, you should set it up so that
  1406. GDB and other commands can use it.
  1407. @xref{CPU Configuration}.
  1408. For the at91sam7 example above, the command can look like this;
  1409. note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
  1410. to little endian, and this chip doesn't support changing that.
  1411. @example
  1412. set _TARGETNAME $_CHIPNAME.cpu
  1413. target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
  1414. @end example
  1415. Work areas are small RAM areas associated with CPU targets.
  1416. They are used by OpenOCD to speed up downloads,
  1417. and to download small snippets of code to program flash chips.
  1418. If the chip includes a form of ``on-chip-ram'' - and many do - define
  1419. a work area if you can.
  1420. Again using the at91sam7 as an example, this can look like:
  1421. @example
  1422. $_TARGETNAME configure -work-area-phys 0x00200000 \
  1423. -work-area-size 0x4000 -work-area-backup 0
  1424. @end example
  1425. @anchor{definecputargetsworkinginsmp}
  1426. @subsection Define CPU targets working in SMP
  1427. @cindex SMP
  1428. After setting targets, you can define a list of targets working in SMP.
  1429. @example
  1430. set _TARGETNAME_1 $_CHIPNAME.cpu1
  1431. set _TARGETNAME_2 $_CHIPNAME.cpu2
  1432. target create $_TARGETNAME_1 cortex_a -chain-position $_CHIPNAME.dap \
  1433. -coreid 0 -dbgbase $_DAP_DBG1
  1434. target create $_TARGETNAME_2 cortex_a -chain-position $_CHIPNAME.dap \
  1435. -coreid 1 -dbgbase $_DAP_DBG2
  1436. #define 2 targets working in smp.
  1437. target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1
  1438. @end example
  1439. In the above example on cortex_a, 2 cpus are working in SMP.
  1440. In SMP only one GDB instance is created and :
  1441. @itemize @bullet
  1442. @item a set of hardware breakpoint sets the same breakpoint on all targets in the list.
  1443. @item halt command triggers the halt of all targets in the list.
  1444. @item resume command triggers the write context and the restart of all targets in the list.
  1445. @item following a breakpoint: the target stopped by the breakpoint is displayed to the GDB session.
  1446. @item dedicated GDB serial protocol packets are implemented for switching/retrieving the target
  1447. displayed by the GDB session @pxref{usingopenocdsmpwithgdb,,Using OpenOCD SMP with GDB}.
  1448. @end itemize
  1449. The SMP behaviour can be disabled/enabled dynamically. On cortex_a following
  1450. command have been implemented.
  1451. @itemize @bullet
  1452. @item cortex_a smp on : enable SMP mode, behaviour is as described above.
  1453. @item cortex_a smp off : disable SMP mode, the current target is the one
  1454. displayed in the GDB session, only this target is now controlled by GDB
  1455. session. This behaviour is useful during system boot up.
  1456. @item cortex_a smp : display current SMP mode.
  1457. @item cortex_a smp_gdb : display/fix the core id displayed in GDB session see
  1458. following example.
  1459. @end itemize
  1460. @example
  1461. >cortex_a smp_gdb
  1462. gdb coreid 0 -> -1
  1463. #0 : coreid 0 is displayed to GDB ,
  1464. #-> -1 : next resume triggers a real resume
  1465. > cortex_a smp_gdb 1
  1466. gdb coreid 0 -> 1
  1467. #0 :coreid 0 is displayed to GDB ,
  1468. #->1 : next resume displays coreid 1 to GDB
  1469. > resume
  1470. > cortex_a smp_gdb
  1471. gdb coreid 1 -> 1
  1472. #1 :coreid 1 is displayed to GDB ,
  1473. #->1 : next resume displays coreid 1 to GDB
  1474. > cortex_a smp_gdb -1
  1475. gdb coreid 1 -> -1
  1476. #1 :coreid 1 is displayed to GDB,
  1477. #->-1 : next resume triggers a real resume
  1478. @end example
  1479. @subsection Chip Reset Setup
  1480. As a rule, you should put the @command{reset_config} command
  1481. into the board file. Most things you think you know about a
  1482. chip can be tweaked by the board.
  1483. Some chips have specific ways the TRST and SRST signals are
  1484. managed. In the unusual case that these are @emph{chip specific}
  1485. and can never be changed by board wiring, they could go here.
  1486. For example, some chips can't support JTAG debugging without
  1487. both signals.
  1488. Provide a @code{reset-assert} event handler if you can.
  1489. Such a handler uses JTAG operations to reset the target,
  1490. letting this target config be used in systems which don't
  1491. provide the optional SRST signal, or on systems where you
  1492. don't want to reset all targets at once.
  1493. Such a handler might write to chip registers to force a reset,
  1494. use a JRC to do that (preferable -- the target may be wedged!),
  1495. or force a watchdog timer to trigger.
  1496. (For Cortex-M targets, this is not necessary. The target
  1497. driver knows how to use trigger an NVIC reset when SRST is
  1498. not available.)
  1499. Some chips need special attention during reset handling if
  1500. they're going to be used with JTAG.
  1501. An example might be needing to send some commands right
  1502. after the target's TAP has been reset, providing a
  1503. @code{reset-deassert-post} event handler that writes a chip
  1504. register to report that JTAG debugging is being done.
  1505. Another would be reconfiguring the watchdog so that it stops
  1506. counting while the core is halted in the debugger.
  1507. JTAG clocking constraints often change during reset, and in
  1508. some cases target config files (rather than board config files)
  1509. are the right places to handle some of those issues.
  1510. For example, immediately after reset most chips run using a
  1511. slower clock than they will use later.
  1512. That means that after reset (and potentially, as OpenOCD
  1513. first starts up) they must use a slower JTAG clock rate
  1514. than they will use later.
  1515. @xref{jtagspeed,,JTAG Speed}.
  1516. @quotation Important
  1517. When you are debugging code that runs right after chip
  1518. reset, getting these issues right is critical.
  1519. In particular, if you see intermittent failures when
  1520. OpenOCD verifies the scan chain after reset,
  1521. look at how you are setting up JTAG clocking.
  1522. @end quotation
  1523. @anchor{theinittargetsprocedure}
  1524. @subsection The init_targets procedure
  1525. @cindex init_targets procedure
  1526. Target config files can either be ``linear'' (script executed line-by-line when parsed in
  1527. configuration stage, @xref{configurationstage,,Configuration Stage},) or they can contain a special
  1528. procedure called @code{init_targets}, which will be executed when entering run stage
  1529. (after parsing all config files or after @code{init} command, @xref{enteringtherunstage,,Entering the Run Stage}.)
  1530. Such procedure can be overridden by ``next level'' script (which sources the original).
  1531. This concept facilitates code reuse when basic target config files provide generic configuration
  1532. procedures and @code{init_targets} procedure, which can then be sourced and enhanced or changed in
  1533. a ``more specific'' target config file. This is not possible with ``linear'' config scripts,
  1534. because sourcing them executes every initialization commands they provide.
  1535. @example
  1536. ### generic_file.cfg ###
  1537. proc setup_my_chip @{chip_name flash_size ram_size@} @{
  1538. # basic initialization procedure ...
  1539. @}
  1540. proc init_targets @{@} @{
  1541. # initializes generic chip with 4kB of flash and 1kB of RAM
  1542. setup_my_chip MY_GENERIC_CHIP 4096 1024
  1543. @}
  1544. ### specific_file.cfg ###
  1545. source [find target/generic_file.cfg]
  1546. proc init_targets @{@} @{
  1547. # initializes specific chip with 128kB of flash and 64kB of RAM
  1548. setup_my_chip MY_CHIP_WITH_128K_FLASH_64KB_RAM 131072 65536
  1549. @}
  1550. @end example
  1551. The easiest way to convert ``linear'' config files to @code{init_targets} version is to
  1552. enclose every line of ``code'' (i.e. not @code{source} commands, procedures, etc.) in this procedure.
  1553. For an example of this scheme see LPC2000 target config files.
  1554. The @code{init_boards} procedure is a similar concept concerning board config files
  1555. (@xref{theinitboardprocedure,,The init_board procedure}.)
  1556. @anchor{theinittargeteventsprocedure}
  1557. @subsection The init_target_events procedure
  1558. @cindex init_target_events procedure
  1559. A special procedure called @code{init_target_events} is run just after
  1560. @code{init_targets} (@xref{theinittargetsprocedure,,The init_targets
  1561. procedure}.) and before @code{init_board}
  1562. (@xref{theinitboardprocedure,,The init_board procedure}.) It is used
  1563. to set up default target events for the targets that do not have those
  1564. events already assigned.
  1565. @subsection ARM Core Specific Hacks
  1566. If the chip has a DCC, enable it. If the chip is an ARM9 with some
  1567. special high speed download features - enable it.
  1568. If present, the MMU, the MPU and the CACHE should be disabled.
  1569. Some ARM cores are equipped with trace support, which permits
  1570. examination of the instruction and data bus activity. Trace
  1571. activity is controlled through an ``Embedded Trace Module'' (ETM)
  1572. on one of the core's scan chains. The ETM emits voluminous data
  1573. through a ``trace port''. (@xref{armhardwaretracing,,ARM Hardware Tracing}.)
  1574. If you are using an external trace port,
  1575. configure it in your board config file.
  1576. If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
  1577. configure it in your target config file.
  1578. @example
  1579. etm config $_TARGETNAME 16 normal full etb
  1580. etb config $_TARGETNAME $_CHIPNAME.etb
  1581. @end example
  1582. @subsection Internal Flash Configuration
  1583. This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
  1584. @b{Never ever} in the ``target configuration file'' define any type of
  1585. flash that is external to the chip. (For example a BOOT flash on
  1586. Chip Select 0.) Such flash information goes in a board file - not
  1587. the TARGET (chip) file.
  1588. Examples:
  1589. @itemize @bullet
  1590. @item at91sam7x256 - has 256K flash YES enable it.
  1591. @item str912 - has flash internal YES enable it.
  1592. @item imx27 - uses boot flash on CS0 - it goes in the board file.
  1593. @item pxa270 - again - CS0 flash - it goes in the board file.
  1594. @end itemize
  1595. @anchor{translatingconfigurationfiles}
  1596. @section Translating Configuration Files
  1597. @cindex translation
  1598. If you have a configuration file for another hardware debugger
  1599. or toolset (Abatron, BDI2000, BDI3000, CCS,
  1600. Lauterbach, SEGGER, Macraigor, etc.), translating
  1601. it into OpenOCD syntax is often quite straightforward. The most tricky
  1602. part of creating a configuration script is oftentimes the reset init
  1603. sequence where e.g. PLLs, DRAM and the like is set up.
  1604. One trick that you can use when translating is to write small
  1605. Tcl procedures to translate the syntax into OpenOCD syntax. This
  1606. can avoid manual translation errors and make it easier to
  1607. convert other scripts later on.
  1608. Example of transforming quirky arguments to a simple search and
  1609. replace job:
  1610. @example
  1611. # Lauterbach syntax(?)
  1612. #
  1613. # Data.Set c15:0x042f %long 0x40000015
  1614. #
  1615. # OpenOCD syntax when using procedure below.
  1616. #
  1617. # setc15 0x01 0x00050078
  1618. proc setc15 @{regs value@} @{
  1619. global TARGETNAME
  1620. echo [format "set p15 0x%04x, 0x%08x" $regs $value]
  1621. arm mcr 15 [expr ($regs>>12)&0x7] \
  1622. [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] \
  1623. [expr ($regs>>8)&0x7] $value
  1624. @}
  1625. @end example
  1626. @node Server Configuration
  1627. @chapter Server Configuration
  1628. @cindex initialization
  1629. The commands here are commonly found in the openocd.cfg file and are
  1630. used to specify what TCP/IP ports are used, and how GDB should be
  1631. supported.
  1632. @anchor{configurationstage}
  1633. @section Configuration Stage
  1634. @cindex configuration stage
  1635. @cindex config command
  1636. When the OpenOCD server process starts up, it enters a
  1637. @emph{configuration stage} which is the only time that
  1638. certain commands, @emph{configuration commands}, may be issued.
  1639. Normally, configuration commands are only available
  1640. inside startup scripts.
  1641. In this manual, the definition of a configuration command is
  1642. presented as a @emph{Config Command}, not as a @emph{Command}
  1643. which may be issued interactively.
  1644. The runtime @command{help} command also highlights configuration
  1645. commands, and those which may be issued at any time.
  1646. Those configuration commands include declaration of TAPs,
  1647. flash banks,
  1648. the interface used for JTAG communication,
  1649. and other basic setup.
  1650. The server must leave the configuration stage before it
  1651. may access or activate TAPs.
  1652. After it leaves this stage, configuration commands may no
  1653. longer be issued.
  1654. @anchor{enteringtherunstage}
  1655. @section Entering the Run Stage
  1656. The first thing OpenOCD does after leaving the configuration
  1657. stage is to verify that it can talk to the scan chain
  1658. (list of TAPs) which has been configured.
  1659. It will warn if it doesn't find TAPs it expects to find,
  1660. or finds TAPs that aren't supposed to be there.
  1661. You should see no errors at this point.
  1662. If you see errors, resolve them by correcting the
  1663. commands you used to configure the server.
  1664. Common errors include using an initial JTAG speed that's too
  1665. fast, and not providing the right IDCODE values for the TAPs
  1666. on the scan chain.
  1667. Once OpenOCD has entered the run stage, a number of commands
  1668. become available.
  1669. A number of these relate to the debug targets you may have declared.
  1670. For example, the @command{mww} command will not be available until
  1671. a target has been successfully instantiated.
  1672. If you want to use those commands, you may need to force
  1673. entry to the run stage.
  1674. @deffn {Config Command} {init}
  1675. This command terminates the configuration stage and
  1676. enters the run stage. This helps when you need to have
  1677. the startup scripts manage tasks such as resetting the target,
  1678. programming flash, etc. To reset the CPU upon startup, add "init" and
  1679. "reset" at the end of the config script or at the end of the OpenOCD
  1680. command line using the @option{-c} command line switch.
  1681. If this command does not appear in any startup/configuration file
  1682. OpenOCD executes the command for you after processing all
  1683. configuration files and/or command line options.
  1684. @b{NOTE:} This command normally occurs at or near the end of your
  1685. openocd.cfg file to force OpenOCD to ``initialize'' and make the
  1686. targets ready. For example: If your openocd.cfg file needs to
  1687. read/write memory on your target, @command{init} must occur before
  1688. the memory read/write commands. This includes @command{nand probe}.
  1689. @end deffn
  1690. @deffn {Overridable Procedure} {jtag_init}
  1691. This is invoked at server startup to verify that it can talk
  1692. to the scan chain (list of TAPs) which has been configured.
  1693. The default implementation first tries @command{jtag arp_init},
  1694. which uses only a lightweight JTAG reset before examining the
  1695. scan chain.
  1696. If that fails, it tries again, using a harder reset
  1697. from the overridable procedure @command{init_reset}.
  1698. Implementations must have verified the JTAG scan chain before
  1699. they return.
  1700. This is done by calling @command{jtag arp_init}
  1701. (or @command{jtag arp_init-reset}).
  1702. @end deffn
  1703. @anchor{tcpipports}
  1704. @section TCP/IP Ports
  1705. @cindex TCP port
  1706. @cindex server
  1707. @cindex port
  1708. @cindex security
  1709. The OpenOCD server accepts remote commands in several syntaxes.
  1710. Each syntax uses a different TCP/IP port, which you may specify
  1711. only during configuration (before those ports are opened).
  1712. For reasons including security, you may wish to prevent remote
  1713. access using one or more of these ports.
  1714. In such cases, just specify the relevant port number as "disabled".
  1715. If you disable all access through TCP/IP, you will need to
  1716. use the command line @option{-pipe} option.
  1717. @anchor{gdb_port}
  1718. @deffn {Config Command} {gdb_port} [number]
  1719. @cindex GDB server
  1720. Normally gdb listens to a TCP/IP port, but GDB can also
  1721. communicate via pipes(stdin/out or named pipes). The name
  1722. "gdb_port" stuck because it covers probably more than 90% of
  1723. the normal use cases.
  1724. No arguments reports GDB port. "pipe" means listen to stdin
  1725. output to stdout, an integer is base port number, "disabled"
  1726. disables the gdb server.
  1727. When using "pipe", also use log_output to redirect the log
  1728. output to a file so as not to flood the stdin/out pipes.
  1729. Any other string is interpreted as named pipe to listen to.
  1730. Output pipe is the same name as input pipe, but with 'o' appended,
  1731. e.g. /var/gdb, /var/gdbo.
  1732. The GDB port for the first target will be the base port, the
  1733. second target will listen on gdb_port + 1, and so on.
  1734. When not specified during the configuration stage,
  1735. the port @var{number} defaults to 3333.
  1736. When @var{number} is not a numeric value, incrementing it to compute
  1737. the next port number does not work. In this case, specify the proper
  1738. @var{number} for each target by using the option @code{-gdb-port} of the
  1739. commands @command{target create} or @command{$target_name configure}.
  1740. @xref{gdbportoverride,,option -gdb-port}.
  1741. Note: when using "gdb_port pipe", increasing the default remote timeout in
  1742. gdb (with 'set remotetimeout') is recommended. An insufficient timeout may
  1743. cause initialization to fail with "Unknown remote qXfer reply: OK".
  1744. @end deffn
  1745. @deffn {Config Command} {tcl_port} [number]
  1746. Specify or query the port used for a simplified RPC
  1747. connection that can be used by clients to issue TCL commands and get the
  1748. output from the Tcl engine.
  1749. Intended as a machine interface.
  1750. When not specified during the configuration stage,
  1751. the port @var{number} defaults to 6666.
  1752. When specified as "disabled", this service is not activated.
  1753. @end deffn
  1754. @deffn {Config Command} {telnet_port} [number]
  1755. Specify or query the
  1756. port on which to listen for incoming telnet connections.
  1757. This port is intended for interaction with one human through TCL commands.
  1758. When not specified during the configuration stage,
  1759. the port @var{number} defaults to 4444.
  1760. When specified as "disabled", this service is not activated.
  1761. @end deffn
  1762. @anchor{gdbconfiguration}
  1763. @section GDB Configuration
  1764. @cindex GDB
  1765. @cindex GDB configuration
  1766. You can reconfigure some GDB behaviors if needed.
  1767. The ones listed here are static and global.
  1768. @xref{targetconfiguration,,Target Configuration}, about configuring individual targets.
  1769. @xref{targetevents,,Target Events}, about configuring target-specific event handling.
  1770. @anchor{gdbbreakpointoverride}
  1771. @deffn {Command} {gdb_breakpoint_override} [@option{hard}|@option{soft}|@option{disable}]
  1772. Force breakpoint type for gdb @command{break} commands.
  1773. This option supports GDB GUIs which don't
  1774. distinguish hard versus soft breakpoints, if the default OpenOCD and
  1775. GDB behaviour is not sufficient. GDB normally uses hardware
  1776. breakpoints if the memory map has been set up for flash regions.
  1777. @end deffn
  1778. @anchor{gdbflashprogram}
  1779. @deffn {Config Command} {gdb_flash_program} (@option{enable}|@option{disable})
  1780. Set to @option{enable} to cause OpenOCD to program the flash memory when a
  1781. vFlash packet is received.
  1782. The default behaviour is @option{enable}.
  1783. @end deffn
  1784. @deffn {Config Command} {gdb_memory_map} (@option{enable}|@option{disable})
  1785. Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
  1786. requested. GDB will then know when to set hardware breakpoints, and program flash
  1787. using the GDB load command. @command{gdb_flash_program enable} must also be enabled
  1788. for flash programming to work.
  1789. Default behaviour is @option{enable}.
  1790. @xref{gdbflashprogram,,gdb_flash_program}.
  1791. @end deffn
  1792. @deffn {Config Command} {gdb_report_data_abort} (@option{enable}|@option{disable})
  1793. Specifies whether data aborts cause an error to be reported
  1794. by GDB memory read packets.
  1795. The default behaviour is @option{disable};
  1796. use @option{enable} see these errors reported.
  1797. @end deffn
  1798. @deffn {Config Command} {gdb_report_register_access_error} (@option{enable}|@option{disable})
  1799. Specifies whether register accesses requested by GDB register read/write
  1800. packets report errors or not.
  1801. The default behaviour is @option{disable};
  1802. use @option{enable} see these errors reported.
  1803. @end deffn
  1804. @deffn {Config Command} {gdb_target_description} (@option{enable}|@option{disable})
  1805. Set to @option{enable} to cause OpenOCD to send the target descriptions to gdb via qXfer:features:read packet.
  1806. The default behaviour is @option{enable}.
  1807. @end deffn
  1808. @deffn {Command} {gdb_save_tdesc}
  1809. Saves the target description file to the local file system.
  1810. The file name is @i{target_name}.xml.
  1811. @end deffn
  1812. @anchor{eventpolling}
  1813. @section Event Polling
  1814. Hardware debuggers are parts of asynchronous systems,
  1815. where significant events can happen at any time.
  1816. The OpenOCD server needs to detect some of these events,
  1817. so it can report them to through TCL command line
  1818. or to GDB.
  1819. Examples of such events include:
  1820. @itemize
  1821. @item One of the targets can stop running ... maybe it triggers
  1822. a code breakpoint or data watchpoint, or halts itself.
  1823. @item Messages may be sent over ``debug message'' channels ... many
  1824. targets support such messages sent over JTAG,
  1825. for receipt by the person debugging or tools.
  1826. @item Loss of power ... some adapters can detect these events.
  1827. @item Resets not issued through JTAG ... such reset sources
  1828. can include button presses or other system hardware, sometimes
  1829. including the target itself (perhaps through a watchdog).
  1830. @item Debug instrumentation sometimes supports event triggering
  1831. such as ``trace buffer full'' (so it can quickly be emptied)
  1832. or other signals (to correlate with code behavior).
  1833. @end itemize
  1834. None of those events are signaled through standard JTAG signals.
  1835. However, most conventions for JTAG connectors include voltage
  1836. level and system reset (SRST) signal detection.
  1837. Some connectors also include instrumentation signals, which
  1838. can imply events when those signals are inputs.
  1839. In general, OpenOCD needs to periodically check for those events,
  1840. either by looking at the status of signals on the JTAG connector
  1841. or by sending synchronous ``tell me your status'' JTAG requests
  1842. to the various active targets.
  1843. There is a command to manage and monitor that polling,
  1844. which is normally done in the background.
  1845. @deffn {Command} {poll} [@option{on}|@option{off}]
  1846. Poll the current target for its current state.
  1847. (Also, @pxref{targetcurstate,,target curstate}.)
  1848. If that target is in debug mode, architecture
  1849. specific information about the current state is printed.
  1850. An optional parameter
  1851. allows background polling to be enabled and disabled.
  1852. You could use this from the TCL command shell, or
  1853. from GDB using @command{monitor poll} command.
  1854. Leave background polling enabled while you're using GDB.
  1855. @example
  1856. > poll
  1857. background polling: on
  1858. target state: halted
  1859. target halted in ARM state due to debug-request, \
  1860. current mode: Supervisor
  1861. cpsr: 0x800000d3 pc: 0x11081bfc
  1862. MMU: disabled, D-Cache: disabled, I-Cache: enabled
  1863. >
  1864. @end example
  1865. @end deffn
  1866. @node Debug Adapter Configuration
  1867. @chapter Debug Adapter Configuration
  1868. @cindex config file, interface
  1869. @cindex interface config file
  1870. Correctly installing OpenOCD includes making your operating system give
  1871. OpenOCD access to debug adapters. Once that has been done, Tcl commands
  1872. are used to select which one is used, and to configure how it is used.
  1873. @quotation Note
  1874. Because OpenOCD started out with a focus purely on JTAG, you may find
  1875. places where it wrongly presumes JTAG is the only transport protocol
  1876. in use. Be aware that recent versions of OpenOCD are removing that
  1877. limitation. JTAG remains more functional than most other transports.
  1878. Other transports do not support boundary scan operations, or may be
  1879. specific to a given chip vendor. Some might be usable only for
  1880. programming flash memory, instead of also for debugging.
  1881. @end quotation
  1882. Debug Adapters/Interfaces/Dongles are normally configured
  1883. through commands in an interface configuration
  1884. file which is sourced by your @file{openocd.cfg} file, or
  1885. through a command line @option{-f interface/....cfg} option.
  1886. @example
  1887. source [find interface/olimex-jtag-tiny.cfg]
  1888. @end example
  1889. These commands tell
  1890. OpenOCD what type of JTAG adapter you have, and how to talk to it.
  1891. A few cases are so simple that you only need to say what driver to use:
  1892. @example
  1893. # jlink interface
  1894. adapter driver jlink
  1895. @end example
  1896. Most adapters need a bit more configuration than that.
  1897. @section Adapter Configuration
  1898. The @command{adapter driver} command tells OpenOCD what type of debug adapter you are
  1899. using. Depending on the type of adapter, you may need to use one or
  1900. more additional commands to further identify or configure the adapter.
  1901. @deffn {Config Command} {adapter driver} name
  1902. Use the adapter driver @var{name} to connect to the
  1903. target.
  1904. @end deffn
  1905. @deffn {Command} {adapter list}
  1906. List the debug adapter drivers that have been built into
  1907. the running copy of OpenOCD.
  1908. @end deffn
  1909. @deffn {Config Command} {adapter transports} transport_name+
  1910. Specifies the transports supported by this debug adapter.
  1911. The adapter driver builds-in similar knowledge; use this only
  1912. when external configuration (such as jumpering) changes what
  1913. the hardware can support.
  1914. @end deffn
  1915. @deffn {Command} {adapter name}
  1916. Returns the name of the debug adapter driver being used.
  1917. @end deffn
  1918. @anchor{adapter_usb_location}
  1919. @deffn {Config Command} {adapter usb location} [<bus>-<port>[.<port>]...]
  1920. Displays or specifies the physical USB port of the adapter to use. The path
  1921. roots at @var{bus} and walks down the physical ports, with each
  1922. @var{port} option specifying a deeper level in the bus topology, the last
  1923. @var{port} denoting where the target adapter is actually plugged.
  1924. The USB bus topology can be queried with the command @emph{lsusb -t} or @emph{dmesg}.
  1925. This command is only available if your libusb1 is at least version 1.0.16.
  1926. @end deffn
  1927. @section Interface Drivers
  1928. Each of the interface drivers listed here must be explicitly
  1929. enabled when OpenOCD is configured, in order to be made
  1930. available at run time.
  1931. @deffn {Interface Driver} {amt_jtagaccel}
  1932. Amontec Chameleon in its JTAG Accelerator configuration,
  1933. connected to a PC's EPP mode parallel port.
  1934. This defines some driver-specific commands:
  1935. @deffn {Config Command} {parport port} number
  1936. Specifies either the address of the I/O port (default: 0x378 for LPT1) or
  1937. the number of the @file{/dev/parport} device.
  1938. @end deffn
  1939. @deffn {Config Command} {rtck} [@option{enable}|@option{disable}]
  1940. Displays status of RTCK option.
  1941. Optionally sets that option first.
  1942. @end deffn
  1943. @end deffn
  1944. @deffn {Interface Driver} {arm-jtag-ew}
  1945. Olimex ARM-JTAG-EW USB adapter
  1946. This has one driver-specific command:
  1947. @deffn {Command} {armjtagew_info}
  1948. Logs some status
  1949. @end deffn
  1950. @end deffn
  1951. @deffn {Interface Driver} {at91rm9200}
  1952. Supports bitbanged JTAG from the local system,
  1953. presuming that system is an Atmel AT91rm9200
  1954. and a specific set of GPIOs is used.
  1955. @c command: at91rm9200_device NAME
  1956. @c chooses among list of bit configs ... only one option
  1957. @end deffn
  1958. @deffn {Interface Driver} {cmsis-dap}
  1959. ARM CMSIS-DAP compliant based adapter v1 (USB HID based)
  1960. or v2 (USB bulk).
  1961. @deffn {Config Command} {cmsis_dap_vid_pid} [vid pid]+
  1962. The vendor ID and product ID of the CMSIS-DAP device. If not specified
  1963. the driver will attempt to auto detect the CMSIS-DAP device.
  1964. Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
  1965. @example
  1966. cmsis_dap_vid_pid 0xc251 0xf001 0x0d28 0x0204
  1967. @end example
  1968. @end deffn
  1969. @deffn {Config Command} {cmsis_dap_serial} [serial]
  1970. Specifies the @var{serial} of the CMSIS-DAP device to use.
  1971. If not specified, serial numbers are not considered.
  1972. @end deffn
  1973. @deffn {Config Command} {cmsis_dap_backend} [@option{auto}|@option{usb_bulk}|@option{hid}]
  1974. Specifies how to communicate with the adapter:
  1975. @itemize @minus
  1976. @item @option{hid} Use HID generic reports - CMSIS-DAP v1
  1977. @item @option{usb_bulk} Use USB bulk - CMSIS-DAP v2
  1978. @item @option{auto} First try USB bulk CMSIS-DAP v2, if not found try HID CMSIS-DAP v1.
  1979. This is the default if @command{cmsis_dap_backend} is not specified.
  1980. @end itemize
  1981. @end deffn
  1982. @deffn {Config Command} {cmsis_dap_usb interface} [number]
  1983. Specifies the @var{number} of the USB interface to use in v2 mode (USB bulk).
  1984. In most cases need not to be specified and interfaces are searched by
  1985. interface string or for user class interface.
  1986. @end deffn
  1987. @deffn {Command} {cmsis-dap info}
  1988. Display various device information, like hardware version, firmware version, current bus status.
  1989. @end deffn
  1990. @end deffn
  1991. @deffn {Interface Driver} {dummy}
  1992. A dummy software-only driver for debugging.
  1993. @end deffn
  1994. @deffn {Interface Driver} {ep93xx}
  1995. Cirrus Logic EP93xx based single-board computer bit-banging (in development)
  1996. @end deffn
  1997. @deffn {Interface Driver} {ftdi}
  1998. This driver is for adapters using the MPSSE (Multi-Protocol Synchronous Serial
  1999. Engine) mode built into many FTDI chips, such as the FT2232, FT4232 and FT232H.
  2000. The driver is using libusb-1.0 in asynchronous mode to talk to the FTDI device,
  2001. bypassing intermediate libraries like libftdi or D2XX.
  2002. Support for new FTDI based adapters can be added completely through
  2003. configuration files, without the need to patch and rebuild OpenOCD.
  2004. The driver uses a signal abstraction to enable Tcl configuration files to
  2005. define outputs for one or several FTDI GPIO. These outputs can then be
  2006. controlled using the @command{ftdi set_signal} command. Special signal names
  2007. are reserved for nTRST, nSRST and LED (for blink) so that they, if defined,
  2008. will be used for their customary purpose. Inputs can be read using the
  2009. @command{ftdi get_signal} command.
  2010. To support SWD, a signal named SWD_EN must be defined. It is set to 1 when the
  2011. SWD protocol is selected. When set, the adapter should route the SWDIO pin to
  2012. the data input. An SWDIO_OE signal, if defined, will be set to 1 or 0 as
  2013. required by the protocol, to tell the adapter to drive the data output onto
  2014. the SWDIO pin or keep the SWDIO pin Hi-Z, respectively.
  2015. Depending on the type of buffer attached to the FTDI GPIO, the outputs have to
  2016. be controlled differently. In order to support tristateable signals such as
  2017. nSRST, both a data GPIO and an output-enable GPIO can be specified for each
  2018. signal. The following output buffer configurations are supported:
  2019. @itemize @minus
  2020. @item Push-pull with one FTDI output as (non-)inverted data line
  2021. @item Open drain with one FTDI output as (non-)inverted output-enable
  2022. @item Tristate with one FTDI output as (non-)inverted data line and another
  2023. FTDI output as (non-)inverted output-enable
  2024. @item Unbuffered, using the FTDI GPIO as a tristate output directly by
  2025. switching data and direction as necessary
  2026. @end itemize
  2027. These interfaces have several commands, used to configure the driver
  2028. before initializing the JTAG scan chain:
  2029. @deffn {Config Command} {ftdi vid_pid} [vid pid]+
  2030. The vendor ID and product ID of the adapter. Up to eight
  2031. [@var{vid}, @var{pid}] pairs may be given, e.g.
  2032. @example
  2033. ftdi vid_pid 0x0403 0xcff8 0x15ba 0x0003
  2034. @end example
  2035. @end deffn
  2036. @deffn {Config Command} {ftdi device_desc} description
  2037. Provides the USB device description (the @emph{iProduct string})
  2038. of the adapter. If not specified, the device description is ignored
  2039. during device selection.
  2040. @end deffn
  2041. @deffn {Config Command} {ftdi serial} serial-number
  2042. Specifies the @var{serial-number} of the adapter to use,
  2043. in case the vendor provides unique IDs and more than one adapter
  2044. is connected to the host.
  2045. If not specified, serial numbers are not considered.
  2046. (Note that USB serial numbers can be arbitrary Unicode strings,
  2047. and are not restricted to containing only decimal digits.)
  2048. @end deffn
  2049. @deffn {Config Command} {ftdi channel} channel
  2050. Selects the channel of the FTDI device to use for MPSSE operations. Most
  2051. adapters use the default, channel 0, but there are exceptions.
  2052. @end deffn
  2053. @deffn {Config Command} {ftdi layout_init} data direction
  2054. Specifies the initial values of the FTDI GPIO data and direction registers.
  2055. Each value is a 16-bit number corresponding to the concatenation of the high
  2056. and low FTDI GPIO registers. The values should be selected based on the
  2057. schematics of the adapter, such that all signals are set to safe levels with
  2058. minimal impact on the target system. Avoid floating inputs, conflicting outputs
  2059. and initially asserted reset signals.
  2060. @end deffn
  2061. @deffn {Command} {ftdi layout_signal} name [@option{-data}|@option{-ndata} data_mask] [@option{-input}|@option{-ninput} input_mask] [@option{-oe}|@option{-noe} oe_mask] [@option{-alias}|@option{-nalias} name]
  2062. Creates a signal with the specified @var{name}, controlled by one or more FTDI
  2063. GPIO pins via a range of possible buffer connections. The masks are FTDI GPIO
  2064. register bitmasks to tell the driver the connection and type of the output
  2065. buffer driving the respective signal. @var{data_mask} is the bitmask for the
  2066. pin(s) connected to the data input of the output buffer. @option{-ndata} is
  2067. used with inverting data inputs and @option{-data} with non-inverting inputs.
  2068. The @option{-oe} (or @option{-noe}) option tells where the output-enable (or
  2069. not-output-enable) input to the output buffer is connected. The options
  2070. @option{-input} and @option{-ninput} specify the bitmask for pins to be read
  2071. with the method @command{ftdi get_signal}.
  2072. Both @var{data_mask} and @var{oe_mask} need not be specified. For example, a
  2073. simple open-collector transistor driver would be specified with @option{-oe}
  2074. only. In that case the signal can only be set to drive low or to Hi-Z and the
  2075. driver will complain if the signal is set to drive high. Which means that if
  2076. it's a reset signal, @command{reset_config} must be specified as
  2077. @option{srst_open_drain}, not @option{srst_push_pull}.
  2078. A special case is provided when @option{-data} and @option{-oe} is set to the
  2079. same bitmask. Then the FTDI pin is considered being connected straight to the
  2080. target without any buffer. The FTDI pin is then switched between output and
  2081. input as necessary to provide the full set of low, high and Hi-Z
  2082. characteristics. In all other cases, the pins specified in a signal definition
  2083. are always driven by the FTDI.
  2084. If @option{-alias} or @option{-nalias} is used, the signal is created
  2085. identical (or with data inverted) to an already specified signal
  2086. @var{name}.
  2087. @end deffn
  2088. @deffn {Command} {ftdi set_signal} name @option{0}|@option{1}|@option{z}
  2089. Set a previously defined signal to the specified level.
  2090. @itemize @minus
  2091. @item @option{0}, drive low
  2092. @item @option{1}, drive high
  2093. @item @option{z}, set to high-impedance
  2094. @end itemize
  2095. @end deffn
  2096. @deffn {Command} {ftdi get_signal} name
  2097. Get the value of a previously defined signal.
  2098. @end deffn
  2099. @deffn {Command} {ftdi tdo_sample_edge} @option{rising}|@option{falling}
  2100. Configure TCK edge at which the adapter samples the value of the TDO signal
  2101. Due to signal propagation delays, sampling TDO on rising TCK can become quite
  2102. peculiar at high JTAG clock speeds. However, FTDI chips offer a possibility to sample
  2103. TDO on falling edge of TCK. With some board/adapter configurations, this may increase
  2104. stability at higher JTAG clocks.
  2105. @itemize @minus
  2106. @item @option{rising}, sample TDO on rising edge of TCK - this is the default
  2107. @item @option{falling}, sample TDO on falling edge of TCK
  2108. @end itemize
  2109. @end deffn
  2110. For example adapter definitions, see the configuration files shipped in the
  2111. @file{interface/ftdi} directory.
  2112. @end deffn
  2113. @deffn {Interface Driver} {ft232r}
  2114. This driver is implementing synchronous bitbang mode of an FTDI FT232R,
  2115. FT230X, FT231X and similar USB UART bridge ICs by reusing RS232 signals as GPIO.
  2116. It currently doesn't support using CBUS pins as GPIO.
  2117. List of connections (default physical pin numbers for FT232R in 28-pin SSOP package):
  2118. @itemize @minus
  2119. @item RXD(5) - TDI
  2120. @item TXD(1) - TCK
  2121. @item RTS(3) - TDO
  2122. @item CTS(11) - TMS
  2123. @item DTR(2) - TRST
  2124. @item DCD(10) - SRST
  2125. @end itemize
  2126. User can change default pinout by supplying configuration
  2127. commands with GPIO numbers or RS232 signal names.
  2128. GPIO numbers correspond to bit numbers in FTDI GPIO register.
  2129. They differ from physical pin numbers.
  2130. For details see actual FTDI chip datasheets.
  2131. Every JTAG line must be configured to unique GPIO number
  2132. different than any other JTAG line, even those lines
  2133. that are sometimes not used like TRST or SRST.
  2134. FT232R
  2135. @itemize @minus
  2136. @item bit 7 - RI
  2137. @item bit 6 - DCD
  2138. @item bit 5 - DSR
  2139. @item bit 4 - DTR
  2140. @item bit 3 - CTS
  2141. @item bit 2 - RTS
  2142. @item bit 1 - RXD
  2143. @item bit 0 - TXD
  2144. @end itemize
  2145. These interfaces have several commands, used to configure the driver
  2146. before initializing the JTAG scan chain:
  2147. @deffn {Config Command} {ft232r_vid_pid} @var{vid} @var{pid}
  2148. The vendor ID and product ID of the adapter. If not specified, default
  2149. 0x0403:0x6001 is used.
  2150. @end deffn
  2151. @deffn {Config Command} {ft232r_serial_desc} @var{serial}
  2152. Specifies the @var{serial} of the adapter to use, in case the
  2153. vendor provides unique IDs and more than one adapter is connected to
  2154. the host. If not specified, serial numbers are not considered.
  2155. @end deffn
  2156. @deffn {Config Command} {ft232r_jtag_nums} @var{tck} @var{tms} @var{tdi} @var{tdo}
  2157. Set four JTAG GPIO numbers at once.
  2158. If not specified, default 0 3 1 2 or TXD CTS RXD RTS is used.
  2159. @end deffn
  2160. @deffn {Config Command} {ft232r_tck_num} @var{tck}
  2161. Set TCK GPIO number. If not specified, default 0 or TXD is used.
  2162. @end deffn
  2163. @deffn {Config Command} {ft232r_tms_num} @var{tms}
  2164. Set TMS GPIO number. If not specified, default 3 or CTS is used.
  2165. @end deffn
  2166. @deffn {Config Command} {ft232r_tdi_num} @var{tdi}
  2167. Set TDI GPIO number. If not specified, default 1 or RXD is used.
  2168. @end deffn
  2169. @deffn {Config Command} {ft232r_tdo_num} @var{tdo}
  2170. Set TDO GPIO number. If not specified, default 2 or RTS is used.
  2171. @end deffn
  2172. @deffn {Config Command} {ft232r_trst_num} @var{trst}
  2173. Set TRST GPIO number. If not specified, default 4 or DTR is used.
  2174. @end deffn
  2175. @deffn {Config Command} {ft232r_srst_num} @var{srst}
  2176. Set SRST GPIO number. If not specified, default 6 or DCD is used.
  2177. @end deffn
  2178. @deffn {Config Command} {ft232r_restore_serial} @var{word}
  2179. Restore serial port after JTAG. This USB bitmode control word
  2180. (16-bit) will be sent before quit. Lower byte should
  2181. set GPIO direction register to a "sane" state:
  2182. 0x15 for TXD RTS DTR as outputs (1), others as inputs (0). Higher
  2183. byte is usually 0 to disable bitbang mode.
  2184. When kernel driver reattaches, serial port should continue to work.
  2185. Value 0xFFFF disables sending control word and serial port,
  2186. then kernel driver will not reattach.
  2187. If not specified, default 0xFFFF is used.
  2188. @end deffn
  2189. @end deffn
  2190. @deffn {Interface Driver} {remote_bitbang}
  2191. Drive JTAG from a remote process. This sets up a UNIX or TCP socket connection
  2192. with a remote process and sends ASCII encoded bitbang requests to that process
  2193. instead of directly driving JTAG.
  2194. The remote_bitbang driver is useful for debugging software running on
  2195. processors which are being simulated.
  2196. @deffn {Config Command} {remote_bitbang port} number
  2197. Specifies the TCP port of the remote process to connect to or 0 to use UNIX
  2198. sockets instead of TCP.
  2199. @end deffn
  2200. @deffn {Config Command} {remote_bitbang host} hostname
  2201. Specifies the hostname of the remote process to connect to using TCP, or the
  2202. name of the UNIX socket to use if remote_bitbang port is 0.
  2203. @end deffn
  2204. For example, to connect remotely via TCP to the host foobar you might have
  2205. something like:
  2206. @example
  2207. adapter driver remote_bitbang
  2208. remote_bitbang port 3335
  2209. remote_bitbang host foobar
  2210. @end example
  2211. To connect to another process running locally via UNIX sockets with socket
  2212. named mysocket:
  2213. @example
  2214. adapter driver remote_bitbang
  2215. remote_bitbang port 0
  2216. remote_bitbang host mysocket
  2217. @end example
  2218. @end deffn
  2219. @deffn {Interface Driver} {usb_blaster}
  2220. USB JTAG/USB-Blaster compatibles over one of the userspace libraries
  2221. for FTDI chips. These interfaces have several commands, used to
  2222. configure the driver before initializing the JTAG scan chain:
  2223. @deffn {Config Command} {usb_blaster_device_desc} description
  2224. Provides the USB device description (the @emph{iProduct string})
  2225. of the FTDI FT245 device. If not
  2226. specified, the FTDI default value is used. This setting is only valid
  2227. if compiled with FTD2XX support.
  2228. @end deffn
  2229. @deffn {Config Command} {usb_blaster_vid_pid} vid pid
  2230. The vendor ID and product ID of the FTDI FT245 device. If not specified,
  2231. default values are used.
  2232. Currently, only one @var{vid}, @var{pid} pair may be given, e.g. for
  2233. Altera USB-Blaster (default):
  2234. @example
  2235. usb_blaster_vid_pid 0x09FB 0x6001
  2236. @end example
  2237. The following VID/PID is for Kolja Waschk's USB JTAG:
  2238. @example
  2239. usb_blaster_vid_pid 0x16C0 0x06AD
  2240. @end example
  2241. @end deffn
  2242. @deffn {Command} {usb_blaster_pin} (@option{pin6}|@option{pin8}) (@option{0}|@option{1}|@option{s}|@option{t})
  2243. Sets the state or function of the unused GPIO pins on USB-Blasters
  2244. (pins 6 and 8 on the female JTAG header). These pins can be used as
  2245. SRST and/or TRST provided the appropriate connections are made on the
  2246. target board.
  2247. For example, to use pin 6 as SRST:
  2248. @example
  2249. usb_blaster_pin pin6 s
  2250. reset_config srst_only
  2251. @end example
  2252. @end deffn
  2253. @deffn {Config Command} {usb_blaster_lowlevel_driver} (@option{ftdi}|@option{ublast2})
  2254. Chooses the low level access method for the adapter. If not specified,
  2255. @option{ftdi} is selected unless it wasn't enabled during the
  2256. configure stage. USB-Blaster II needs @option{ublast2}.
  2257. @end deffn
  2258. @deffn {Config Command} {usb_blaster_firmware} @var{path}
  2259. This command specifies @var{path} to access USB-Blaster II firmware
  2260. image. To be used with USB-Blaster II only.
  2261. @end deffn
  2262. @end deffn
  2263. @deffn {Interface Driver} {gw16012}
  2264. Gateworks GW16012 JTAG programmer.
  2265. This has one driver-specific command:
  2266. @deffn {Config Command} {parport port} [port_number]
  2267. Display either the address of the I/O port
  2268. (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
  2269. If a parameter is provided, first switch to use that port.
  2270. This is a write-once setting.
  2271. @end deffn
  2272. @end deffn
  2273. @deffn {Interface Driver} {jlink}
  2274. SEGGER J-Link family of USB adapters. It currently supports JTAG and SWD
  2275. transports.
  2276. @quotation Compatibility Note
  2277. SEGGER released many firmware versions for the many hardware versions they
  2278. produced. OpenOCD was extensively tested and intended to run on all of them,
  2279. but some combinations were reported as incompatible. As a general
  2280. recommendation, it is advisable to use the latest firmware version
  2281. available for each hardware version. However the current V8 is a moving
  2282. target, and SEGGER firmware versions released after the OpenOCD was
  2283. released may not be compatible. In such cases it is recommended to
  2284. revert to the last known functional version. For 0.5.0, this is from
  2285. "Feb 8 2012 14:30:39", packed with 4.42c. For 0.6.0, the last known
  2286. version is from "May 3 2012 18:36:22", packed with 4.46f.
  2287. @end quotation
  2288. @deffn {Command} {jlink hwstatus}
  2289. Display various hardware related information, for example target voltage and pin
  2290. states.
  2291. @end deffn
  2292. @deffn {Command} {jlink freemem}
  2293. Display free device internal memory.
  2294. @end deffn
  2295. @deffn {Command} {jlink jtag} [@option{2}|@option{3}]
  2296. Set the JTAG command version to be used. Without argument, show the actual JTAG
  2297. command version.
  2298. @end deffn
  2299. @deffn {Command} {jlink config}
  2300. Display the device configuration.
  2301. @end deffn
  2302. @deffn {Command} {jlink config targetpower} [@option{on}|@option{off}]
  2303. Set the target power state on JTAG-pin 19. Without argument, show the target
  2304. power state.
  2305. @end deffn
  2306. @deffn {Command} {jlink config mac} [@option{ff:ff:ff:ff:ff:ff}]
  2307. Set the MAC address of the device. Without argument, show the MAC address.
  2308. @end deffn
  2309. @deffn {Command} {jlink config ip} [@option{A.B.C.D}(@option{/E}|@option{F.G.H.I})]
  2310. Set the IP configuration of the device, where A.B.C.D is the IP address, E the
  2311. bit of the subnet mask and F.G.H.I the subnet mask. Without arguments, show the
  2312. IP configuration.
  2313. @end deffn
  2314. @deffn {Command} {jlink config usb} [@option{0} to @option{3}]
  2315. Set the USB address of the device. This will also change the USB Product ID
  2316. (PID) of the device. Without argument, show the USB address.
  2317. @end deffn
  2318. @deffn {Command} {jlink config reset}
  2319. Reset the current configuration.
  2320. @end deffn
  2321. @deffn {Command} {jlink config write}
  2322. Write the current configuration to the internal persistent storage.
  2323. @end deffn
  2324. @deffn {Command} {jlink emucom write <channel> <data>}
  2325. Write data to an EMUCOM channel. The data needs to be encoded as hexadecimal
  2326. pairs.
  2327. The following example shows how to write the three bytes 0xaa, 0x0b and 0x23 to
  2328. the EMUCOM channel 0x10:
  2329. @example
  2330. > jlink emucom write 0x10 aa0b23
  2331. @end example
  2332. @end deffn
  2333. @deffn {Command} {jlink emucom read <channel> <length>}
  2334. Read data from an EMUCOM channel. The read data is encoded as hexadecimal
  2335. pairs.
  2336. The following example shows how to read 4 bytes from the EMUCOM channel 0x0:
  2337. @example
  2338. > jlink emucom read 0x0 4
  2339. 77a90000
  2340. @end example
  2341. @end deffn
  2342. @deffn {Config Command} {jlink usb} <@option{0} to @option{3}>
  2343. Set the USB address of the interface, in case more than one adapter is connected
  2344. to the host. If not specified, USB addresses are not considered. Device
  2345. selection via USB address is not always unambiguous. It is recommended to use
  2346. the serial number instead, if possible.
  2347. As a configuration command, it can be used only before 'init'.
  2348. @end deffn
  2349. @deffn {Config Command} {jlink serial} <serial number>
  2350. Set the serial number of the interface, in case more than one adapter is
  2351. connected to the host. If not specified, serial numbers are not considered.
  2352. As a configuration command, it can be used only before 'init'.
  2353. @end deffn
  2354. @end deffn
  2355. @deffn {Interface Driver} {kitprog}
  2356. This driver is for Cypress Semiconductor's KitProg adapters. The KitProg is an
  2357. SWD-only adapter that is designed to be used with Cypress's PSoC and PRoC device
  2358. families, but it is possible to use it with some other devices. If you are using
  2359. this adapter with a PSoC or a PRoC, you may need to add
  2360. @command{kitprog_init_acquire_psoc} or @command{kitprog acquire_psoc} to your
  2361. configuration script.
  2362. Note that this driver is for the proprietary KitProg protocol, not the CMSIS-DAP
  2363. mode introduced in firmware 2.14. If the KitProg is in CMSIS-DAP mode, it cannot
  2364. be used with this driver, and must either be used with the cmsis-dap driver or
  2365. switched back to KitProg mode. See the Cypress KitProg User Guide for
  2366. instructions on how to switch KitProg modes.
  2367. Known limitations:
  2368. @itemize @bullet
  2369. @item The frequency of SWCLK cannot be configured, and varies between 1.6 MHz
  2370. and 2.7 MHz.
  2371. @item For firmware versions below 2.14, "JTAG to SWD" sequences are replaced by
  2372. "SWD line reset" in the driver. This is for two reasons. First, the KitProg does
  2373. not support sending arbitrary SWD sequences, and only firmware 2.14 and later
  2374. implement both "JTAG to SWD" and "SWD line reset" in firmware. Earlier firmware
  2375. versions only implement "SWD line reset". Second, due to a firmware quirk, an
  2376. SWD sequence must be sent after every target reset in order to re-establish
  2377. communications with the target.
  2378. @item Due in part to the limitation above, KitProg devices with firmware below
  2379. version 2.14 will need to use @command{kitprog_init_acquire_psoc} in order to
  2380. communicate with PSoC 5LP devices. This is because, assuming debug is not
  2381. disabled on the PSoC, the PSoC 5LP needs its JTAG interface switched to SWD
  2382. mode before communication can begin, but prior to firmware 2.14, "JTAG to SWD"
  2383. could only be sent with an acquisition sequence.
  2384. @end itemize
  2385. @deffn {Config Command} {kitprog_init_acquire_psoc}
  2386. Indicate that a PSoC acquisition sequence needs to be run during adapter init.
  2387. Please be aware that the acquisition sequence hard-resets the target.
  2388. @end deffn
  2389. @deffn {Config Command} {kitprog_serial} serial
  2390. Select a KitProg device by its @var{serial}. If left unspecified, the first
  2391. device detected by OpenOCD will be used.
  2392. @end deffn
  2393. @deffn {Command} {kitprog acquire_psoc}
  2394. Run a PSoC acquisition sequence immediately. Typically, this should not be used
  2395. outside of the target-specific configuration scripts since it hard-resets the
  2396. target as a side-effect.
  2397. This is necessary for "reset halt" on some PSoC 4 series devices.
  2398. @end deffn
  2399. @deffn {Command} {kitprog info}
  2400. Display various adapter information, such as the hardware version, firmware
  2401. version, and target voltage.
  2402. @end deffn
  2403. @end deffn
  2404. @deffn {Interface Driver} {parport}
  2405. Supports PC parallel port bit-banging cables:
  2406. Wigglers, PLD download cable, and more.
  2407. These interfaces have several commands, used to configure the driver
  2408. before initializing the JTAG scan chain:
  2409. @deffn {Config Command} {parport cable} name
  2410. Set the layout of the parallel port cable used to connect to the target.
  2411. This is a write-once setting.
  2412. Currently valid cable @var{name} values include:
  2413. @itemize @minus
  2414. @item @b{altium} Altium Universal JTAG cable.
  2415. @item @b{arm-jtag} Same as original wiggler except SRST and
  2416. TRST connections reversed and TRST is also inverted.
  2417. @item @b{chameleon} The Amontec Chameleon's CPLD when operated
  2418. in configuration mode. This is only used to
  2419. program the Chameleon itself, not a connected target.
  2420. @item @b{dlc5} The Xilinx Parallel cable III.
  2421. @item @b{flashlink} The ST Parallel cable.
  2422. @item @b{lattice} Lattice ispDOWNLOAD Cable
  2423. @item @b{old_amt_wiggler} The Wiggler configuration that comes with
  2424. some versions of
  2425. Amontec's Chameleon Programmer. The new version available from
  2426. the website uses the original Wiggler layout ('@var{wiggler}')
  2427. @item @b{triton} The parallel port adapter found on the
  2428. ``Karo Triton 1 Development Board''.
  2429. This is also the layout used by the HollyGates design
  2430. (see @uref{}).
  2431. @item @b{wiggler} The original Wiggler layout, also supported by
  2432. several clones, such as the Olimex ARM-JTAG
  2433. @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
  2434. @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
  2435. @end itemize
  2436. @end deffn
  2437. @deffn {Config Command} {parport port} [port_number]
  2438. Display either the address of the I/O port
  2439. (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
  2440. If a parameter is provided, first switch to use that port.
  2441. This is a write-once setting.
  2442. When using PPDEV to access the parallel port, use the number of the parallel port:
  2443. @option{parport port 0} (the default). If @option{parport port 0x378} is specified
  2444. you may encounter a problem.
  2445. @end deffn
  2446. @deffn {Config Command} {parport toggling_time} [nanoseconds]
  2447. Displays how many nanoseconds the hardware needs to toggle TCK;
  2448. the parport driver uses this value to obey the
  2449. @command{adapter speed} configuration.
  2450. When the optional @var{nanoseconds} parameter is given,
  2451. that setting is changed before displaying the current value.
  2452. The default setting should work reasonably well on commodity PC hardware.
  2453. However, you may want to calibrate for your specific hardware.
  2454. @quotation Tip
  2455. To measure the toggling time with a logic analyzer or a digital storage
  2456. oscilloscope, follow the procedure below:
  2457. @example
  2458. > parport toggling_time 1000
  2459. > adapter speed 500
  2460. @end example
  2461. This sets the maximum JTAG clock speed of the hardware, but
  2462. the actual speed probably deviates from the requested 500 kHz.
  2463. Now, measure the time between the two closest spaced TCK transitions.
  2464. You can use @command{runtest 1000} or something similar to generate a
  2465. large set of samples.
  2466. Update the setting to match your measurement:
  2467. @example
  2468. > parport toggling_time <measured nanoseconds>
  2469. @end example
  2470. Now the clock speed will be a better match for @command{adapter speed}
  2471. command given in OpenOCD scripts and event handlers.
  2472. You can do something similar with many digital multimeters, but note
  2473. that you'll probably need to run the clock continuously for several
  2474. seconds before it decides what clock rate to show. Adjust the
  2475. toggling time up or down until the measured clock rate is a good
  2476. match with the rate you specified in the @command{adapter speed} command;
  2477. be conservative.
  2478. @end quotation
  2479. @end deffn
  2480. @deffn {Config Command} {parport write_on_exit} (@option{on}|@option{off})
  2481. This will configure the parallel driver to write a known
  2482. cable-specific value to the parallel interface on exiting OpenOCD.
  2483. @end deffn
  2484. For example, the interface configuration file for a
  2485. classic ``Wiggler'' cable on LPT2 might look something like this:
  2486. @example
  2487. adapter driver parport
  2488. parport port 0x278
  2489. parport cable wiggler
  2490. @end example
  2491. @end deffn
  2492. @deffn {Interface Driver} {presto}
  2493. ASIX PRESTO USB JTAG programmer.
  2494. @deffn {Config Command} {presto serial} serial_string
  2495. Configures the USB serial number of the Presto device to use.
  2496. @end deffn
  2497. @end deffn
  2498. @deffn {Interface Driver} {rlink}
  2499. Raisonance RLink USB adapter
  2500. @end deffn
  2501. @deffn {Interface Driver} {usbprog}
  2502. usbprog is a freely programmable USB adapter.
  2503. @end deffn
  2504. @deffn {Interface Driver} {vsllink}
  2505. vsllink is part of Versaloon which is a versatile USB programmer.
  2506. @quotation Note
  2507. This defines quite a few driver-specific commands,
  2508. which are not currently documented here.
  2509. @end quotation
  2510. @end deffn
  2511. @anchor{hla_interface}
  2512. @deffn {Interface Driver} {hla}
  2513. This is a driver that supports multiple High Level Adapters.
  2514. This type of adapter does not expose some of the lower level api's
  2515. that OpenOCD would normally use to access the target.
  2516. Currently supported adapters include the STMicroelectronics ST-LINK, TI ICDI
  2517. and Nuvoton Nu-Link.
  2518. ST-LINK firmware version >= V2.J21.S4 recommended due to issues with earlier
  2519. versions of firmware where serial number is reset after first use. Suggest
  2520. using ST firmware update utility to upgrade ST-LINK firmware even if current
  2521. version reported is V2.J21.S4.
  2522. @deffn {Config Command} {hla_device_desc} description
  2523. Currently Not Supported.
  2524. @end deffn
  2525. @deffn {Config Command} {hla_serial} serial
  2526. Specifies the serial number of the adapter.
  2527. @end deffn
  2528. @deffn {Config Command} {hla_layout} (@option{stlink}|@option{icdi}|@option{nulink})
  2529. Specifies the adapter layout to use.
  2530. @end deffn
  2531. @deffn {Config Command} {hla_vid_pid} [vid pid]+
  2532. Pairs of vendor IDs and product IDs of the device.
  2533. @end deffn
  2534. @deffn {Config Command} {hla_stlink_backend} (usb | tcp [port])
  2535. @emph{ST-Link only:} Choose between 'exclusive' USB communication (the default backend) or
  2536. 'shared' mode using ST-Link TCP server (the default port is 7184).
  2537. @emph{Note:} ST-Link TCP server is a binary application provided by ST
  2538. available from @url{,
  2539. ST-LINK server software module}.
  2540. @end deffn
  2541. @deffn {Command} {hla_command} command
  2542. Execute a custom adapter-specific command. The @var{command} string is
  2543. passed as is to the underlying adapter layout handler.
  2544. @end deffn
  2545. @end deffn
  2546. @anchor{st_link_dap_interface}
  2547. @deffn {Interface Driver} {st-link}
  2548. This is a driver that supports STMicroelectronics adapters ST-LINK/V2
  2549. (from firmware V2J24) and STLINK-V3, thanks to a new API that provides
  2550. directly access the arm ADIv5 DAP.
  2551. The new API provide access to multiple AP on the same DAP, but the
  2552. maximum number of the AP port is limited by the specific firmware version
  2553. (e.g. firmware V2J29 has 3 as maximum AP number, while V2J32 has 8).
  2554. An error is returned for any AP number above the maximum allowed value.
  2555. @emph{Note:} Either these same adapters and their older versions are
  2556. also supported by @ref{hla_interface, the hla interface driver}.
  2557. @deffn {Config Command} {st-link backend} (usb | tcp [port])
  2558. Choose between 'exclusive' USB communication (the default backend) or
  2559. 'shared' mode using ST-Link TCP server (the default port is 7184).
  2560. @emph{Note:} ST-Link TCP server is a binary application provided by ST
  2561. available from @url{,
  2562. ST-LINK server software module}.
  2563. @emph{Note:} ST-Link TCP server does not support the SWIM transport.
  2564. @end deffn
  2565. @deffn {Config Command} {st-link serial} serial
  2566. Specifies the serial number of the adapter.
  2567. @end deffn
  2568. @deffn {Config Command} {st-link vid_pid} [vid pid]+
  2569. Pairs of vendor IDs and product IDs of the device.
  2570. @end deffn
  2571. @end deffn
  2572. @deffn {Interface Driver} {opendous}
  2573. opendous-jtag is a freely programmable USB adapter.
  2574. @end deffn
  2575. @deffn {Interface Driver} {ulink}
  2576. This is the Keil ULINK v1 JTAG debugger.
  2577. @end deffn
  2578. @deffn {Interface Driver} {xds110}
  2579. The XDS110 is included as the embedded debug probe on many Texas Instruments
  2580. LaunchPad evaluation boards. The XDS110 is also available as a stand-alone USB
  2581. debug probe with the added capability to supply power to the target board. The
  2582. following commands are supported by the XDS110 driver:
  2583. @deffn {Config Command} {xds110 serial} serial_string
  2584. Specifies the serial number of which XDS110 probe to use. Otherwise, the first
  2585. XDS110 found will be used.
  2586. @end deffn
  2587. @deffn {Config Command} {xds110 supply} voltage_in_millivolts
  2588. Available only on the XDS110 stand-alone probe. Sets the voltage level of the
  2589. XDS110 power supply. A value of 0 leaves the supply off. Otherwise, the supply
  2590. can be set to any value in the range 1800 to 3600 millivolts.
  2591. @end deffn
  2592. @deffn {Command} {xds110 info}
  2593. Displays information about the connected XDS110 debug probe (e.g. firmware
  2594. version).
  2595. @end deffn
  2596. @end deffn
  2597. @deffn {Interface Driver} {xlnx_pcie_xvc}
  2598. This driver supports the Xilinx Virtual Cable (XVC) over PCI Express.
  2599. It is commonly found in Xilinx based PCI Express designs. It allows debugging
  2600. fabric based JTAG/SWD devices such as Cortex-M1/M3 microcontrollers. Access to this is
  2601. exposed via extended capability registers in the PCI Express configuration space.
  2602. For more information see Xilinx PG245 (Section on From_PCIE_to_JTAG mode).
  2603. @deffn {Config Command} {xlnx_pcie_xvc config} device
  2604. Specifies the PCI Express device via parameter @var{device} to use.
  2605. The correct value for @var{device} can be obtained by looking at the output
  2606. of lscpi -D (first column) for the corresponding device.
  2607. The string will be of the format "DDDD:BB:SS.F" such as "0000:65:00.1".
  2608. @end deffn
  2609. @end deffn
  2610. @deffn {Interface Driver} {bcm2835gpio}
  2611. This SoC is present in Raspberry Pi which is a cheap single-board computer
  2612. exposing some GPIOs on its expansion header.
  2613. The driver accesses memory-mapped GPIO peripheral registers directly
  2614. for maximum performance, but the only possible race condition is for
  2615. the pins' modes/muxing (which is highly unlikely), so it should be
  2616. able to coexist nicely with both sysfs bitbanging and various
  2617. peripherals' kernel drivers. The driver restores the previous
  2618. configuration on exit.
  2619. See @file{interface/raspberrypi-native.cfg} for a sample config and
  2620. pinout.
  2621. @deffn {Config Command} {bcm2835gpio jtag_nums} @var{tck} @var{tms} @var{tdi} @var{tdo}
  2622. Set JTAG transport GPIO numbers for TCK, TMS, TDI, and TDO (in that order).
  2623. Must be specified to enable JTAG transport. These pins can also be specified
  2624. individually.
  2625. @end deffn
  2626. @deffn {Config Command} {bcm2835gpio tck_num} @var{tck}
  2627. Set TCK GPIO number. Must be specified to enable JTAG transport. Can also be
  2628. specified using the configuration command @command{bcm2835gpio jtag_nums}.
  2629. @end deffn
  2630. @deffn {Config Command} {bcm2835gpio tms_num} @var{tms}
  2631. Set TMS GPIO number. Must be specified to enable JTAG transport. Can also be
  2632. specified using the configuration command @command{bcm2835gpio jtag_nums}.
  2633. @end deffn
  2634. @deffn {Config Command} {bcm2835gpio tdo_num} @var{tdo}
  2635. Set TDO GPIO number. Must be specified to enable JTAG transport. Can also be
  2636. specified using the configuration command @command{bcm2835gpio jtag_nums}.
  2637. @end deffn
  2638. @deffn {Config Command} {bcm2835gpio tdi_num} @var{tdi}
  2639. Set TDI GPIO number. Must be specified to enable JTAG transport. Can also be
  2640. specified using the configuration command @command{bcm2835gpio jtag_nums}.
  2641. @end deffn
  2642. @deffn {Config Command} {bcm2835gpio swd_nums} @var{swclk} @var{swdio}
  2643. Set SWD transport GPIO numbers for SWCLK and SWDIO (in that order). Must be
  2644. specified to enable SWD transport. These pins can also be specified individually.
  2645. @end deffn
  2646. @deffn {Config Command} {bcm2835gpio swclk_num} @var{swclk}
  2647. Set SWCLK GPIO number. Must be specified to enable SWD transport. Can also be
  2648. specified using the configuration command @command{bcm2835gpio swd_nums}.
  2649. @end deffn
  2650. @deffn {Config Command} {bcm2835gpio swdio_num} @var{swdio}
  2651. Set SWDIO GPIO number. Must be specified to enable SWD transport. Can also be
  2652. specified using the configuration command @command{bcm2835gpio swd_nums}.
  2653. @end deffn
  2654. @deffn {Config Command} {bcm2835gpio swdio_dir_num} @var{swdio} @var{dir}
  2655. Set SWDIO direction control pin GPIO number. If specified, this pin can be used
  2656. to control the direction of an external buffer on the SWDIO pin (set=output
  2657. mode, clear=input mode). If not specified, this feature is disabled.
  2658. @end deffn
  2659. @deffn {Config Command} {bcm2835gpio srst_num} @var{srst}
  2660. Set SRST GPIO number. Must be specified to enable SRST.
  2661. @end deffn
  2662. @deffn {Config Command} {bcm2835gpio trst_num} @var{trst}
  2663. Set TRST GPIO number. Must be specified to enable TRST.
  2664. @end deffn
  2665. @deffn {Config Command} {bcm2835gpio speed_coeffs} @var{speed_coeff} @var{speed_offset}
  2666. Set SPEED_COEFF and SPEED_OFFSET for delay calculations. If unspecified,
  2667. speed_coeff defaults to 113714, and speed_offset defaults to 28.
  2668. @end deffn
  2669. @deffn {Config Command} {bcm2835gpio peripheral_base} @var{base}
  2670. Set the peripheral base register address to access GPIOs. For the RPi1, use
  2671. 0x20000000. For RPi2 and RPi3, use 0x3F000000. For RPi4, use 0xFE000000. A full
  2672. list can be found in the
  2673. @uref{, official guide}.
  2674. @end deffn
  2675. @end deffn
  2676. @deffn {Interface Driver} {imx_gpio}
  2677. i.MX SoC is present in many community boards. Wandboard is an example
  2678. of the one which is most popular.
  2679. This driver is mostly the same as bcm2835gpio.
  2680. See @file{interface/imx-native.cfg} for a sample config and
  2681. pinout.
  2682. @end deffn
  2683. @deffn {Interface Driver} {linuxgpiod}
  2684. Linux provides userspace access to GPIO through libgpiod since Linux kernel version v4.6.
  2685. The driver emulates either JTAG and SWD transport through bitbanging.
  2686. See @file{interface/dln-2-gpiod.cfg} for a sample config.
  2687. @end deffn
  2688. @deffn {Interface Driver} {sysfsgpio}
  2689. Linux legacy userspace access to GPIO through sysfs is deprecated from Linux kernel version v5.3.
  2690. Prefer using @b{linuxgpiod}, instead.
  2691. See @file{interface/sysfsgpio-raspberrypi.cfg} for a sample config.
  2692. @end deffn
  2693. @deffn {Interface Driver} {openjtag}
  2694. OpenJTAG compatible USB adapter.
  2695. This defines some driver-specific commands:
  2696. @deffn {Config Command} {openjtag variant} variant
  2697. Specifies the variant of the OpenJTAG adapter (see @uref{}).
  2698. Currently valid @var{variant} values include:
  2699. @itemize @minus
  2700. @item @b{standard} Standard variant (default).
  2701. @item @b{cy7c65215} Cypress CY7C65215 Dual Channel USB-Serial Bridge Controller
  2702. (see @uref{}).
  2703. @end itemize
  2704. @end deffn
  2705. @deffn {Config Command} {openjtag device_desc} string
  2706. The USB device description string of the adapter.
  2707. This value is only used with the standard variant.
  2708. @end deffn
  2709. @end deffn
  2710. @deffn {Interface Driver} {jtag_dpi}
  2711. SystemVerilog Direct Programming Interface (DPI) compatible driver for
  2712. JTAG devices in emulation. The driver acts as a client for the SystemVerilog
  2713. DPI server interface.
  2714. @deffn {Config Command} {jtag_dpi set_port} port
  2715. Specifies the TCP/IP port number of the SystemVerilog DPI server interface.
  2716. @end deffn
  2717. @deffn {Config Command} {jtag_dpi set_address} address
  2718. Specifies the TCP/IP address of the SystemVerilog DPI server interface.
  2719. @end deffn
  2720. @end deffn
  2721. @deffn {Interface Driver} {buspirate}
  2722. This driver is for the Bus Pirate (see @url{}) and compatible devices.
  2723. It uses a simple data protocol over a serial port connection.
  2724. Most hardware development boards have a UART, a real serial port, or a virtual USB serial device, so this driver
  2725. allows you to start building your own JTAG adapter without the complexity of a custom USB connection.
  2726. @deffn {Config Command} {buspirate port} serial_port
  2727. Specify the serial port's filename. For example:
  2728. @example
  2729. buspirate port /dev/ttyUSB0
  2730. @end example
  2731. @end deffn
  2732. @deffn {Config Command} {buspirate speed} (normal|fast)
  2733. Set the communication speed to 115k (normal) or 1M (fast). For example:
  2734. @example
  2735. buspirate mode normal
  2736. @end example
  2737. @end deffn
  2738. @deffn {Config Command} {buspirate mode} (normal|open-drain)
  2739. Set the Bus Pirate output mode.
  2740. @itemize @minus
  2741. @item In normal mode (push/pull), do not enable the pull-ups, and do not connect I/O header pin VPU to JTAG VREF.
  2742. @item In open drain mode, you will then need to enable the pull-ups.
  2743. @end itemize
  2744. For example:
  2745. @example
  2746. buspirate mode normal
  2747. @end example
  2748. @end deffn
  2749. @deffn {Config Command} {buspirate pullup} (0|1)
  2750. Whether to connect (1) or not (0) the I/O header pin VPU (JTAG VREF)
  2751. to the pull-up/pull-down resistors on MOSI (JTAG TDI), CLK (JTAG TCK), MISO (JTAG TDO) and CS (JTAG TMS).
  2752. For example:
  2753. @example
  2754. buspirate pullup 0
  2755. @end example
  2756. @end deffn
  2757. @deffn {Config Command} {buspirate vreg} (0|1)
  2758. Whether to enable (1) or disable (0) the built-in voltage regulator,
  2759. which can be used to supply power to a test circuit through
  2760. I/O header pins +3V3 and +5V. For example:
  2761. @example
  2762. buspirate vreg 0
  2763. @end example
  2764. @end deffn
  2765. @deffn {Command} {buspirate led} (0|1)
  2766. Turns the Bus Pirate's LED on (1) or off (0). For example:
  2767. @end deffn
  2768. @example
  2769. buspirate led 1
  2770. @end example
  2771. @end deffn
  2772. @section Transport Configuration
  2773. @cindex Transport
  2774. As noted earlier, depending on the version of OpenOCD you use,
  2775. and the debug adapter you are using,
  2776. several transports may be available to
  2777. communicate with debug targets (or perhaps to program flash memory).
  2778. @deffn {Command} {transport list}
  2779. displays the names of the transports supported by this
  2780. version of OpenOCD.
  2781. @end deffn
  2782. @deffn {Command} {transport select} @option{transport_name}
  2783. Select which of the supported transports to use in this OpenOCD session.
  2784. When invoked with @option{transport_name}, attempts to select the named
  2785. transport. The transport must be supported by the debug adapter
  2786. hardware and by the version of OpenOCD you are using (including the
  2787. adapter's driver).
  2788. If no transport has been selected and no @option{transport_name} is
  2789. provided, @command{transport select} auto-selects the first transport
  2790. supported by the debug adapter.
  2791. @command{transport select} always returns the name of the session's selected
  2792. transport, if any.
  2793. @end deffn
  2794. @subsection JTAG Transport
  2795. @cindex JTAG
  2796. JTAG is the original transport supported by OpenOCD, and most
  2797. of the OpenOCD commands support it.
  2798. JTAG transports expose a chain of one or more Test Access Points (TAPs),
  2799. each of which must be explicitly declared.
  2800. JTAG supports both debugging and boundary scan testing.
  2801. Flash programming support is built on top of debug support.
  2802. JTAG transport is selected with the command @command{transport select
  2803. jtag}. Unless your adapter uses either @ref{hla_interface,the hla interface
  2804. driver} (in which case the command is @command{transport select hla_jtag})
  2805. or @ref{st_link_dap_interface,the st-link interface driver} (in which case
  2806. the command is @command{transport select dapdirect_jtag}).
  2807. @subsection SWD Transport
  2808. @cindex SWD
  2809. @cindex Serial Wire Debug
  2810. SWD (Serial Wire Debug) is an ARM-specific transport which exposes one
  2811. Debug Access Point (DAP, which must be explicitly declared.
  2812. (SWD uses fewer signal wires than JTAG.)
  2813. SWD is debug-oriented, and does not support boundary scan testing.
  2814. Flash programming support is built on top of debug support.
  2815. (Some processors support both JTAG and SWD.)
  2816. SWD transport is selected with the command @command{transport select
  2817. swd}. Unless your adapter uses either @ref{hla_interface,the hla interface
  2818. driver} (in which case the command is @command{transport select hla_swd})
  2819. or @ref{st_link_dap_interface,the st-link interface driver} (in which case
  2820. the command is @command{transport select dapdirect_swd}).
  2821. @deffn {Config Command} {swd newdap} ...
  2822. Declares a single DAP which uses SWD transport.
  2823. Parameters are currently the same as "jtag newtap" but this is
  2824. expected to change.
  2825. @end deffn
  2826. @deffn {Command} {swd wcr trn prescale}
  2827. Updates TRN (turnaround delay) and prescaling.fields of the
  2828. Wire Control Register (WCR).
  2829. No parameters: displays current settings.
  2830. @end deffn
  2831. @subsection SPI Transport
  2832. @cindex SPI
  2833. @cindex Serial Peripheral Interface
  2834. The Serial Peripheral Interface (SPI) is a general purpose transport
  2835. which uses four wire signaling. Some processors use it as part of a
  2836. solution for flash programming.
  2837. @anchor{swimtransport}
  2838. @subsection SWIM Transport
  2839. @cindex SWIM
  2840. @cindex Single Wire Interface Module
  2841. The Single Wire Interface Module (SWIM) is a low-pin-count debug protocol used
  2842. by the STMicroelectronics MCU family STM8 and documented in the
  2843. @uref{, User Manual UM470}.
  2844. SWIM does not support boundary scan testing nor multiple cores.
  2845. The SWIM transport is selected with the command @command{transport select swim}.
  2846. The concept of TAPs does not fit in the protocol since SWIM does not implement
  2847. a scan chain. Nevertheless, the current SW model of OpenOCD requires defining a
  2848. virtual SWIM TAP through the command @command{swim newtap basename tap_type}.
  2849. The TAP definition must precede the target definition command
  2850. @command{target create target_name stm8 -chain-position basename.tap_type}.
  2851. @anchor{jtagspeed}
  2852. @section JTAG Speed
  2853. JTAG clock setup is part of system setup.
  2854. It @emph{does not belong with interface setup} since any interface
  2855. only knows a few of the constraints for the JTAG clock speed.
  2856. Sometimes the JTAG speed is
  2857. changed during the target initialization process: (1) slow at
  2858. reset, (2) program the CPU clocks, (3) run fast.
  2859. Both the "slow" and "fast" clock rates are functions of the
  2860. oscillators used, the chip, the board design, and sometimes
  2861. power management software that may be active.
  2862. The speed used during reset, and the scan chain verification which
  2863. follows reset, can be adjusted using a @code{reset-start}
  2864. target event handler.
  2865. It can then be reconfigured to a faster speed by a
  2866. @code{reset-init} target event handler after it reprograms those
  2867. CPU clocks, or manually (if something else, such as a boot loader,
  2868. sets up those clocks).
  2869. @xref{targetevents,,Target Events}.
  2870. When the initial low JTAG speed is a chip characteristic, perhaps
  2871. because of a required oscillator speed, provide such a handler
  2872. in the target config file.
  2873. When that speed is a function of a board-specific characteristic
  2874. such as which speed oscillator is used, it belongs in the board
  2875. config file instead.
  2876. In both cases it's safest to also set the initial JTAG clock rate
  2877. to that same slow speed, so that OpenOCD never starts up using a
  2878. clock speed that's faster than the scan chain can support.
  2879. @example
  2880. jtag_rclk 3000
  2881. $_TARGET.cpu configure -event reset-start @{ jtag_rclk 3000 @}
  2882. @end example
  2883. If your system supports adaptive clocking (RTCK), configuring
  2884. JTAG to use that is probably the most robust approach.
  2885. However, it introduces delays to synchronize clocks; so it
  2886. may not be the fastest solution.
  2887. @b{NOTE:} Script writers should consider using @command{jtag_rclk}
  2888. instead of @command{adapter speed}, but only for (ARM) cores and boards
  2889. which support adaptive clocking.
  2890. @deffn {Command} {adapter speed} max_speed_kHz
  2891. A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
  2892. JTAG interfaces usually support a limited number of
  2893. speeds. The speed actually used won't be faster
  2894. than the speed specified.
  2895. Chip data sheets generally include a top JTAG clock rate.
  2896. The actual rate is often a function of a CPU core clock,
  2897. and is normally less than that peak rate.
  2898. For example, most ARM cores accept at most one sixth of the CPU clock.
  2899. Speed 0 (khz) selects RTCK method.
  2900. @xref{faqrtck,,FAQ RTCK}.
  2901. If your system uses RTCK, you won't need to change the
  2902. JTAG clocking after setup.
  2903. Not all interfaces, boards, or targets support ``rtck''.
  2904. If the interface device can not
  2905. support it, an error is returned when you try to use RTCK.
  2906. @end deffn
  2907. @defun jtag_rclk fallback_speed_kHz
  2908. @cindex adaptive clocking
  2909. @cindex RTCK
  2910. This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
  2911. If that fails (maybe the interface, board, or target doesn't
  2912. support it), falls back to the specified frequency.
  2913. @example
  2914. # Fall back to 3mhz if RTCK is not supported
  2915. jtag_rclk 3000
  2916. @end example
  2917. @end defun
  2918. @node Reset Configuration
  2919. @chapter Reset Configuration
  2920. @cindex Reset Configuration
  2921. Every system configuration may require a different reset
  2922. configuration. This can also be quite confusing.
  2923. Resets also interact with @var{reset-init} event handlers,
  2924. which do things like setting up clocks and DRAM, and
  2925. JTAG clock rates. (@xref{jtagspeed,,JTAG Speed}.)
  2926. They can also interact with JTAG routers.
  2927. Please see the various board files for examples.
  2928. @quotation Note
  2929. To maintainers and integrators:
  2930. Reset configuration touches several things at once.
  2931. Normally the board configuration file
  2932. should define it and assume that the JTAG adapter supports
  2933. everything that's wired up to the board's JTAG connector.
  2934. However, the target configuration file could also make note
  2935. of something the silicon vendor has done inside the chip,
  2936. which will be true for most (or all) boards using that chip.
  2937. And when the JTAG adapter doesn't support everything, the
  2938. user configuration file will need to override parts of
  2939. the reset configuration provided by other files.
  2940. @end quotation
  2941. @section Types of Reset
  2942. There are many kinds of reset possible through JTAG, but
  2943. they may not all work with a given board and adapter.
  2944. That's part of why reset configuration can be error prone.
  2945. @itemize @bullet
  2946. @item
  2947. @emph{System Reset} ... the @emph{SRST} hardware signal
  2948. resets all chips connected to the JTAG adapter, such as processors,
  2949. power management chips, and I/O controllers. Normally resets triggered
  2950. with this signal behave exactly like pressing a RESET button.
  2951. @item
  2952. @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
  2953. just the TAP controllers connected to the JTAG adapter.
  2954. Such resets should not be visible to the rest of the system; resetting a
  2955. device's TAP controller just puts that controller into a known state.
  2956. @item
  2957. @emph{Emulation Reset} ... many devices can be reset through JTAG
  2958. commands. These resets are often distinguishable from system
  2959. resets, either explicitly (a "reset reason" register says so)
  2960. or implicitly (not all parts of the chip get reset).
  2961. @item
  2962. @emph{Other Resets} ... system-on-chip devices often support
  2963. several other types of reset.
  2964. You may need to arrange that a watchdog timer stops
  2965. while debugging, preventing a watchdog reset.
  2966. There may be individual module resets.
  2967. @end itemize
  2968. In the best case, OpenOCD can hold SRST, then reset
  2969. the TAPs via TRST and send commands through JTAG to halt the
  2970. CPU at the reset vector before the 1st instruction is executed.
  2971. Then when it finally releases the SRST signal, the system is
  2972. halted under debugger control before any code has executed.
  2973. This is the behavior required to support the @command{reset halt}
  2974. and @command{reset init} commands; after @command{reset init} a
  2975. board-specific script might do things like setting up DRAM.
  2976. (@xref{resetcommand,,Reset Command}.)
  2977. @anchor{srstandtrstissues}
  2978. @section SRST and TRST Issues
  2979. Because SRST and TRST are hardware signals, they can have a
  2980. variety of system-specific constraints. Some of the most
  2981. common issues are:
  2982. @itemize @bullet
  2983. @item @emph{Signal not available} ... Some boards don't wire
  2984. SRST or TRST to the JTAG connector. Some JTAG adapters don't
  2985. support such signals even if they are wired up.
  2986. Use the @command{reset_config} @var{signals} options to say
  2987. when either of those signals is not connected.
  2988. When SRST is not available, your code might not be able to rely
  2989. on controllers having been fully reset during code startup.
  2990. Missing TRST is not a problem, since JTAG-level resets can
  2991. be triggered using with TMS signaling.
  2992. @item @emph{Signals shorted} ... Sometimes a chip, board, or
  2993. adapter will connect SRST to TRST, instead of keeping them separate.
  2994. Use the @command{reset_config} @var{combination} options to say
  2995. when those signals aren't properly independent.
  2996. @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
  2997. delay circuit, reset supervisor, or on-chip features can extend
  2998. the effect of a JTAG adapter's reset for some time after the adapter
  2999. stops issuing the reset. For example, there may be chip or board
  3000. requirements that all reset pulses last for at least a
  3001. certain amount of time; and reset buttons commonly have
  3002. hardware debouncing.
  3003. Use the @command{adapter srst delay} and @command{jtag_ntrst_delay}
  3004. commands to say when extra delays are needed.
  3005. @item @emph{Drive type} ... Reset lines often have a pullup
  3006. resistor, letting the JTAG interface treat them as open-drain
  3007. signals. But that's not a requirement, so the adapter may need
  3008. to use push/pull output drivers.
  3009. Also, with weak pullups it may be advisable to drive
  3010. signals to both levels (push/pull) to minimize rise times.
  3011. Use the @command{reset_config} @var{trst_type} and
  3012. @var{srst_type} parameters to say how to drive reset signals.
  3013. @item @emph{Special initialization} ... Targets sometimes need
  3014. special JTAG initialization sequences to handle chip-specific
  3015. issues (not limited to errata).
  3016. For example, certain JTAG commands might need to be issued while
  3017. the system as a whole is in a reset state (SRST active)
  3018. but the JTAG scan chain is usable (TRST inactive).
  3019. Many systems treat combined assertion of SRST and TRST as a
  3020. trigger for a harder reset than SRST alone.
  3021. Such custom reset handling is discussed later in this chapter.
  3022. @end itemize
  3023. There can also be other issues.
  3024. Some devices don't fully conform to the JTAG specifications.
  3025. Trivial system-specific differences are common, such as
  3026. SRST and TRST using slightly different names.
  3027. There are also vendors who distribute key JTAG documentation for
  3028. their chips only to developers who have signed a Non-Disclosure
  3029. Agreement (NDA).
  3030. Sometimes there are chip-specific extensions like a requirement to use
  3031. the normally-optional TRST signal (precluding use of JTAG adapters which
  3032. don't pass TRST through), or needing extra steps to complete a TAP reset.
  3033. In short, SRST and especially TRST handling may be very finicky,
  3034. needing to cope with both architecture and board specific constraints.
  3035. @section Commands for Handling Resets
  3036. @deffn {Command} {adapter srst pulse_width} milliseconds
  3037. Minimum amount of time (in milliseconds) OpenOCD should wait
  3038. after asserting nSRST (active-low system reset) before
  3039. allowing it to be deasserted.
  3040. @end deffn
  3041. @deffn {Command} {adapter srst delay} milliseconds
  3042. How long (in milliseconds) OpenOCD should wait after deasserting
  3043. nSRST (active-low system reset) before starting new JTAG operations.
  3044. When a board has a reset button connected to SRST line it will
  3045. probably have hardware debouncing, implying you should use this.
  3046. @end deffn
  3047. @deffn {Command} {jtag_ntrst_assert_width} milliseconds
  3048. Minimum amount of time (in milliseconds) OpenOCD should wait
  3049. after asserting nTRST (active-low JTAG TAP reset) before
  3050. allowing it to be deasserted.
  3051. @end deffn
  3052. @deffn {Command} {jtag_ntrst_delay} milliseconds
  3053. How long (in milliseconds) OpenOCD should wait after deasserting
  3054. nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
  3055. @end deffn
  3056. @anchor{reset_config}
  3057. @deffn {Command} {reset_config} mode_flag ...
  3058. This command displays or modifies the reset configuration
  3059. of your combination of JTAG board and target in target
  3060. configuration scripts.
  3061. Information earlier in this section describes the kind of problems
  3062. the command is intended to address (@pxref{srstandtrstissues,,SRST and TRST Issues}).
  3063. As a rule this command belongs only in board config files,
  3064. describing issues like @emph{board doesn't connect TRST};
  3065. or in user config files, addressing limitations derived
  3066. from a particular combination of interface and board.
  3067. (An unlikely example would be using a TRST-only adapter
  3068. with a board that only wires up SRST.)
  3069. The @var{mode_flag} options can be specified in any order, but only one
  3070. of each type -- @var{signals}, @var{combination}, @var{gates},
  3071. @var{trst_type}, @var{srst_type} and @var{connect_type}
  3072. -- may be specified at a time.
  3073. If you don't provide a new value for a given type, its previous
  3074. value (perhaps the default) is unchanged.
  3075. For example, this means that you don't need to say anything at all about
  3076. TRST just to declare that if the JTAG adapter should want to drive SRST,
  3077. it must explicitly be driven high (@option{srst_push_pull}).
  3078. @itemize
  3079. @item
  3080. @var{signals} can specify which of the reset signals are connected.
  3081. For example, If the JTAG interface provides SRST, but the board doesn't
  3082. connect that signal properly, then OpenOCD can't use it.
  3083. Possible values are @option{none} (the default), @option{trst_only},
  3084. @option{srst_only} and @option{trst_and_srst}.
  3085. @quotation Tip
  3086. If your board provides SRST and/or TRST through the JTAG connector,
  3087. you must declare that so those signals can be used.
  3088. @end quotation
  3089. @item
  3090. The @var{combination} is an optional value specifying broken reset
  3091. signal implementations.
  3092. The default behaviour if no option given is @option{separate},
  3093. indicating everything behaves normally.
  3094. @option{srst_pulls_trst} states that the
  3095. test logic is reset together with the reset of the system (e.g. NXP
  3096. LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
  3097. the system is reset together with the test logic (only hypothetical, I
  3098. haven't seen hardware with such a bug, and can be worked around).
  3099. @option{combined} implies both @option{srst_pulls_trst} and
  3100. @option{trst_pulls_srst}.
  3101. @item
  3102. The @var{gates} tokens control flags that describe some cases where
  3103. JTAG may be unavailable during reset.
  3104. @option{srst_gates_jtag} (default)
  3105. indicates that asserting SRST gates the
  3106. JTAG clock. This means that no communication can happen on JTAG
  3107. while SRST is asserted.
  3108. Its converse is @option{srst_nogate}, indicating that JTAG commands
  3109. can safely be issued while SRST is active.
  3110. @item
  3111. The @var{connect_type} tokens control flags that describe some cases where
  3112. SRST is asserted while connecting to the target. @option{srst_nogate}
  3113. is required to use this option.
  3114. @option{connect_deassert_srst} (default)
  3115. indicates that SRST will not be asserted while connecting to the target.
  3116. Its converse is @option{connect_assert_srst}, indicating that SRST will
  3117. be asserted before any target connection.
  3118. Only some targets support this feature, STM32 and STR9 are examples.
  3119. This feature is useful if you are unable to connect to your target due
  3120. to incorrect options byte config or illegal program execution.
  3121. @end itemize
  3122. The optional @var{trst_type} and @var{srst_type} parameters allow the
  3123. driver mode of each reset line to be specified. These values only affect
  3124. JTAG interfaces with support for different driver modes, like the Amontec
  3125. JTAGkey and JTAG Accelerator. Also, they are necessarily ignored if the
  3126. relevant signal (TRST or SRST) is not connected.
  3127. @itemize
  3128. @item
  3129. Possible @var{trst_type} driver modes for the test reset signal (TRST)
  3130. are the default @option{trst_push_pull}, and @option{trst_open_drain}.
  3131. Most boards connect this signal to a pulldown, so the JTAG TAPs
  3132. never leave reset unless they are hooked up to a JTAG adapter.
  3133. @item
  3134. Possible @var{srst_type} driver modes for the system reset signal (SRST)
  3135. are the default @option{srst_open_drain}, and @option{srst_push_pull}.
  3136. Most boards connect this signal to a pullup, and allow the
  3137. signal to be pulled low by various events including system
  3138. power-up and pressing a reset button.
  3139. @end itemize
  3140. @end deffn
  3141. @section Custom Reset Handling
  3142. @cindex events
  3143. OpenOCD has several ways to help support the various reset
  3144. mechanisms provided by chip and board vendors.
  3145. The commands shown in the previous section give standard parameters.
  3146. There are also @emph{event handlers} associated with TAPs or Targets.
  3147. Those handlers are Tcl procedures you can provide, which are invoked
  3148. at particular points in the reset sequence.
  3149. @emph{When SRST is not an option} you must set
  3150. up a @code{reset-assert} event handler for your target.
  3151. For example, some JTAG adapters don't include the SRST signal;
  3152. and some boards have multiple targets, and you won't always
  3153. want to reset everything at once.
  3154. After configuring those mechanisms, you might still
  3155. find your board doesn't start up or reset correctly.
  3156. For example, maybe it needs a slightly different sequence
  3157. of SRST and/or TRST manipulations, because of quirks that
  3158. the @command{reset_config} mechanism doesn't address;
  3159. or asserting both might trigger a stronger reset, which
  3160. needs special attention.
  3161. Experiment with lower level operations, such as
  3162. @command{adapter assert}, @command{adapter deassert}
  3163. and the @command{jtag arp_*} operations shown here,
  3164. to find a sequence of operations that works.
  3165. @xref{JTAG Commands}.
  3166. When you find a working sequence, it can be used to override
  3167. @command{jtag_init}, which fires during OpenOCD startup
  3168. (@pxref{configurationstage,,Configuration Stage});
  3169. or @command{init_reset}, which fires during reset processing.
  3170. You might also want to provide some project-specific reset
  3171. schemes. For example, on a multi-target board the standard
  3172. @command{reset} command would reset all targets, but you
  3173. may need the ability to reset only one target at time and
  3174. thus want to avoid using the board-wide SRST signal.
  3175. @deffn {Overridable Procedure} {init_reset} mode
  3176. This is invoked near the beginning of the @command{reset} command,
  3177. usually to provide as much of a cold (power-up) reset as practical.
  3178. By default it is also invoked from @command{jtag_init} if
  3179. the scan chain does not respond to pure JTAG operations.
  3180. The @var{mode} parameter is the parameter given to the
  3181. low level reset command (@option{halt},
  3182. @option{init}, or @option{run}), @option{setup},
  3183. or potentially some other value.
  3184. The default implementation just invokes @command{jtag arp_init-reset}.
  3185. Replacements will normally build on low level JTAG
  3186. operations such as @command{adapter assert} and @command{adapter deassert}.
  3187. Operations here must not address individual TAPs
  3188. (or their associated targets)
  3189. until the JTAG scan chain has first been verified to work.
  3190. Implementations must have verified the JTAG scan chain before
  3191. they return.
  3192. This is done by calling @command{jtag arp_init}
  3193. (or @command{jtag arp_init-reset}).
  3194. @end deffn
  3195. @deffn {Command} {jtag arp_init}
  3196. This validates the scan chain using just the four
  3197. standard JTAG signals (TMS, TCK, TDI, TDO).
  3198. It starts by issuing a JTAG-only reset.
  3199. Then it performs checks to verify that the scan chain configuration
  3200. matches the TAPs it can observe.
  3201. Those checks include checking IDCODE values for each active TAP,
  3202. and verifying the length of their instruction registers using
  3203. TAP @code{-ircapture} and @code{-irmask} values.
  3204. If these tests all pass, TAP @code{setup} events are
  3205. issued to all TAPs with handlers for that event.
  3206. @end deffn
  3207. @deffn {Command} {jtag arp_init-reset}
  3208. This uses TRST and SRST to try resetting
  3209. everything on the JTAG scan chain
  3210. (and anything else connected to SRST).
  3211. It then invokes the logic of @command{jtag arp_init}.
  3212. @end deffn
  3213. @node TAP Declaration
  3214. @chapter TAP Declaration
  3215. @cindex TAP declaration
  3216. @cindex TAP configuration
  3217. @emph{Test Access Ports} (TAPs) are the core of JTAG.
  3218. TAPs serve many roles, including:
  3219. @itemize @bullet
  3220. @item @b{Debug Target} A CPU TAP can be used as a GDB debug target.
  3221. @item @b{Flash Programming} Some chips program the flash directly via JTAG.
  3222. Others do it indirectly, making a CPU do it.
  3223. @item @b{Program Download} Using the same CPU support GDB uses,
  3224. you can initialize a DRAM controller, download code to DRAM, and then
  3225. start running that code.
  3226. @item @b{Boundary Scan} Most chips support boundary scan, which
  3227. helps test for board assembly problems like solder bridges
  3228. and missing connections.
  3229. @end itemize
  3230. OpenOCD must know about the active TAPs on your board(s).
  3231. Setting up the TAPs is the core task of your configuration files.
  3232. Once those TAPs are set up, you can pass their names to code
  3233. which sets up CPUs and exports them as GDB targets,
  3234. probes flash memory, performs low-level JTAG operations, and more.
  3235. @section Scan Chains
  3236. @cindex scan chain
  3237. TAPs are part of a hardware @dfn{scan chain},
  3238. which is a daisy chain of TAPs.
  3239. They also need to be added to
  3240. OpenOCD's software mirror of that hardware list,
  3241. giving each member a name and associating other data with it.
  3242. Simple scan chains, with a single TAP, are common in
  3243. systems with a single microcontroller or microprocessor.
  3244. More complex chips may have several TAPs internally.
  3245. Very complex scan chains might have a dozen or more TAPs:
  3246. several in one chip, more in the next, and connecting
  3247. to other boards with their own chips and TAPs.
  3248. You can display the list with the @command{scan_chain} command.
  3249. (Don't confuse this with the list displayed by the @command{targets}
  3250. command, presented in the next chapter.
  3251. That only displays TAPs for CPUs which are configured as
  3252. debugging targets.)
  3253. Here's what the scan chain might look like for a chip more than one TAP:
  3254. @verbatim
  3255. TapName Enabled IdCode Expected IrLen IrCap IrMask
  3256. -- ------------------ ------- ---------- ---------- ----- ----- ------
  3257. 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0x01 0x03
  3258. 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x01 0x0f
  3259. 2 omap5912.unknown Y 0x00000000 0x00000000 8 0x01 0x03
  3260. @end verbatim
  3261. OpenOCD can detect some of that information, but not all
  3262. of it. @xref{autoprobing,,Autoprobing}.
  3263. Unfortunately, those TAPs can't always be autoconfigured,
  3264. because not all devices provide good support for that.
  3265. JTAG doesn't require supporting IDCODE instructions, and
  3266. chips with JTAG routers may not link TAPs into the chain
  3267. until they are told to do so.
  3268. The configuration mechanism currently supported by OpenOCD
  3269. requires explicit configuration of all TAP devices using
  3270. @command{jtag newtap} commands, as detailed later in this chapter.
  3271. A command like this would declare one tap and name it @code{chip1.cpu}:
  3272. @example
  3273. jtag newtap chip1 cpu -irlen 4 -expected-id 0x3ba00477
  3274. @end example
  3275. Each target configuration file lists the TAPs provided
  3276. by a given chip.
  3277. Board configuration files combine all the targets on a board,
  3278. and so forth.
  3279. Note that @emph{the order in which TAPs are declared is very important.}
  3280. That declaration order must match the order in the JTAG scan chain,
  3281. both inside a single chip and between them.
  3282. @xref{faqtaporder,,FAQ TAP Order}.
  3283. For example, the STMicroelectronics STR912 chip has
  3284. three separate TAPs@footnote{See the ST
  3285. document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
  3286. 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
  3287. @url{}}.
  3288. To configure those taps, @file{target/str912.cfg}
  3289. includes commands something like this:
  3290. @example
  3291. jtag newtap str912 flash ... params ...
  3292. jtag newtap str912 cpu ... params ...
  3293. jtag newtap str912 bs ... params ...
  3294. @end example
  3295. Actual config files typically use a variable such as @code{$_CHIPNAME}
  3296. instead of literals like @option{str912}, to support more than one chip
  3297. of each type. @xref{Config File Guidelines}.
  3298. @deffn {Command} {jtag names}
  3299. Returns the names of all current TAPs in the scan chain.
  3300. Use @command{jtag cget} or @command{jtag tapisenabled}
  3301. to examine attributes and state of each TAP.
  3302. @example
  3303. foreach t [jtag names] @{
  3304. puts [format "TAP: %s\n" $t]
  3305. @}
  3306. @end example
  3307. @end deffn
  3308. @deffn {Command} {scan_chain}
  3309. Displays the TAPs in the scan chain configuration,
  3310. and their status.
  3311. The set of TAPs listed by this command is fixed by
  3312. exiting the OpenOCD configuration stage,
  3313. but systems with a JTAG router can
  3314. enable or disable TAPs dynamically.
  3315. @end deffn
  3316. @c FIXME! "jtag cget" should be able to return all TAP
  3317. @c attributes, like "$target_name cget" does for targets.
  3318. @c Probably want "jtag eventlist", and a "tap-reset" event
  3319. @c (on entry to RESET state).
  3320. @section TAP Names
  3321. @cindex dotted name
  3322. When TAP objects are declared with @command{jtag newtap},
  3323. a @dfn{} is created for the TAP, combining the
  3324. name of a module (usually a chip) and a label for the TAP.
  3325. For example: @code{xilinx.tap}, @code{str912.flash},
  3326. @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
  3327. Many other commands use that to manipulate or
  3328. refer to the TAP. For example, CPU configuration uses the
  3329. name, as does declaration of NAND or NOR flash banks.
  3330. The components of a dotted name should follow ``C'' symbol
  3331. name rules: start with an alphabetic character, then numbers
  3332. and underscores are OK; while others (including dots!) are not.
  3333. @section TAP Declaration Commands
  3334. @deffn {Config Command} {jtag newtap} chipname tapname configparams...
  3335. Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
  3336. and configured according to the various @var{configparams}.
  3337. The @var{chipname} is a symbolic name for the chip.
  3338. Conventionally target config files use @code{$_CHIPNAME},
  3339. defaulting to the model name given by the chip vendor but
  3340. overridable.
  3341. @cindex TAP naming convention
  3342. The @var{tapname} reflects the role of that TAP,
  3343. and should follow this convention:
  3344. @itemize @bullet
  3345. @item @code{bs} -- For boundary scan if this is a separate TAP;
  3346. @item @code{cpu} -- The main CPU of the chip, alternatively
  3347. @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
  3348. @code{arm1} and @code{arm2} on chips with two ARMs, and so forth;
  3349. @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
  3350. @item @code{flash} -- If the chip has a flash TAP, like the str912;
  3351. @item @code{jrc} -- For JTAG route controller (example: the ICEPick modules
  3352. on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
  3353. @item @code{tap} -- Should be used only for FPGA- or CPLD-like devices
  3354. with a single TAP;
  3355. @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
  3356. @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
  3357. For example, the Freescale i.MX31 has a SDMA (Smart DMA) with
  3358. a JTAG TAP; that TAP should be named @code{sdma}.
  3359. @end itemize
  3360. Every TAP requires at least the following @var{configparams}:
  3361. @itemize @bullet
  3362. @item @code{-irlen} @var{NUMBER}
  3363. @*The length in bits of the
  3364. instruction register, such as 4 or 5 bits.
  3365. @end itemize
  3366. A TAP may also provide optional @var{configparams}:
  3367. @itemize @bullet
  3368. @item @code{-disable} (or @code{-enable})
  3369. @*Use the @code{-disable} parameter to flag a TAP which is not
  3370. linked into the scan chain after a reset using either TRST
  3371. or the JTAG state machine's @sc{reset} state.
  3372. You may use @code{-enable} to highlight the default state
  3373. (the TAP is linked in).
  3374. @xref{enablinganddisablingtaps,,Enabling and Disabling TAPs}.
  3375. @item @code{-expected-id} @var{NUMBER}
  3376. @*A non-zero @var{number} represents a 32-bit IDCODE
  3377. which you expect to find when the scan chain is examined.
  3378. These codes are not required by all JTAG devices.
  3379. @emph{Repeat the option} as many times as required if more than one
  3380. ID code could appear (for example, multiple versions).
  3381. Specify @var{number} as zero to suppress warnings about IDCODE
  3382. values that were found but not included in the list.
  3383. Provide this value if at all possible, since it lets OpenOCD
  3384. tell when the scan chain it sees isn't right. These values
  3385. are provided in vendors' chip documentation, usually a technical
  3386. reference manual. Sometimes you may need to probe the JTAG
  3387. hardware to find these values.
  3388. @xref{autoprobing,,Autoprobing}.
  3389. @item @code{-ignore-version}
  3390. @*Specify this to ignore the JTAG version field in the @code{-expected-id}
  3391. option. When vendors put out multiple versions of a chip, or use the same
  3392. JTAG-level ID for several largely-compatible chips, it may be more practical
  3393. to ignore the version field than to update config files to handle all of
  3394. the various chip IDs. The version field is defined as bit 28-31 of the IDCODE.
  3395. @item @code{-ircapture} @var{NUMBER}
  3396. @*The bit pattern loaded by the TAP into the JTAG shift register
  3397. on entry to the @sc{ircapture} state, such as 0x01.
  3398. JTAG requires the two LSBs of this value to be 01.
  3399. By default, @code{-ircapture} and @code{-irmask} are set
  3400. up to verify that two-bit value. You may provide
  3401. additional bits if you know them, or indicate that
  3402. a TAP doesn't conform to the JTAG specification.
  3403. @item @code{-irmask} @var{NUMBER}
  3404. @*A mask used with @code{-ircapture}
  3405. to verify that instruction scans work correctly.
  3406. Such scans are not used by OpenOCD except to verify that
  3407. there seems to be no problems with JTAG scan chain operations.
  3408. @item @code{-ignore-syspwrupack}
  3409. @*Specify this to ignore the CSYSPWRUPACK bit in the ARM DAP DP CTRL/STAT
  3410. register during initial examination and when checking the sticky error bit.
  3411. This bit is normally checked after setting the CSYSPWRUPREQ bit, but some
  3412. devices do not set the ack bit until sometime later.
  3413. @end itemize
  3414. @end deffn
  3415. @section Other TAP commands
  3416. @deffn {Command} {jtag cget} @option{-idcode}
  3417. Get the value of the IDCODE found in hardware.
  3418. @end deffn
  3419. @deffn {Command} {jtag cget} @option{-event} event_name
  3420. @deffnx {Command} {jtag configure} @option{-event} event_name handler
  3421. At this writing this TAP attribute
  3422. mechanism is limited and used mostly for event handling.
  3423. (It is not a direct analogue of the @code{cget}/@code{configure}
  3424. mechanism for debugger targets.)
  3425. See the next section for information about the available events.
  3426. The @code{configure} subcommand assigns an event handler,
  3427. a TCL string which is evaluated when the event is triggered.
  3428. The @code{cget} subcommand returns that handler.
  3429. @end deffn
  3430. @section TAP Events
  3431. @cindex events
  3432. @cindex TAP events
  3433. OpenOCD includes two event mechanisms.
  3434. The one presented here applies to all JTAG TAPs.
  3435. The other applies to debugger targets,
  3436. which are associated with certain TAPs.
  3437. The TAP events currently defined are:
  3438. @itemize @bullet
  3439. @item @b{post-reset}
  3440. @* The TAP has just completed a JTAG reset.
  3441. The tap may still be in the JTAG @sc{reset} state.
  3442. Handlers for these events might perform initialization sequences
  3443. such as issuing TCK cycles, TMS sequences to ensure
  3444. exit from the ARM SWD mode, and more.
  3445. Because the scan chain has not yet been verified, handlers for these events
  3446. @emph{should not issue commands which scan the JTAG IR or DR registers}
  3447. of any particular target.
  3448. @b{NOTE:} As this is written (September 2009), nothing prevents such access.
  3449. @item @b{setup}
  3450. @* The scan chain has been reset and verified.
  3451. This handler may enable TAPs as needed.
  3452. @item @b{tap-disable}
  3453. @* The TAP needs to be disabled. This handler should
  3454. implement @command{jtag tapdisable}
  3455. by issuing the relevant JTAG commands.
  3456. @item @b{tap-enable}
  3457. @* The TAP needs to be enabled. This handler should
  3458. implement @command{jtag tapenable}
  3459. by issuing the relevant JTAG commands.
  3460. @end itemize
  3461. If you need some action after each JTAG reset which isn't actually
  3462. specific to any TAP (since you can't yet trust the scan chain's
  3463. contents to be accurate), you might:
  3464. @example
  3465. jtag configure CHIP.jrc -event post-reset @{
  3466. echo "JTAG Reset done"
  3467. ... non-scan jtag operations to be done after reset
  3468. @}
  3469. @end example
  3470. @anchor{enablinganddisablingtaps}
  3471. @section Enabling and Disabling TAPs
  3472. @cindex JTAG Route Controller
  3473. @cindex jrc
  3474. In some systems, a @dfn{JTAG Route Controller} (JRC)
  3475. is used to enable and/or disable specific JTAG TAPs.
  3476. Many ARM-based chips from Texas Instruments include
  3477. an ``ICEPick'' module, which is a JRC.
  3478. Such chips include DaVinci and OMAP3 processors.
  3479. A given TAP may not be visible until the JRC has been
  3480. told to link it into the scan chain; and if the JRC
  3481. has been told to unlink that TAP, it will no longer
  3482. be visible.
  3483. Such routers address problems that JTAG ``bypass mode''
  3484. ignores, such as:
  3485. @itemize
  3486. @item The scan chain can only go as fast as its slowest TAP.
  3487. @item Having many TAPs slows instruction scans, since all
  3488. TAPs receive new instructions.
  3489. @item TAPs in the scan chain must be powered up, which wastes
  3490. power and prevents debugging some power management mechanisms.
  3491. @end itemize
  3492. The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
  3493. as implied by the existence of JTAG routers.
  3494. However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
  3495. does include a kind of JTAG router functionality.
  3496. @c (a) currently the event handlers don't seem to be able to
  3497. @c fail in a way that could lead to no-change-of-state.
  3498. In OpenOCD, tap enabling/disabling is invoked by the Tcl commands
  3499. shown below, and is implemented using TAP event handlers.
  3500. So for example, when defining a TAP for a CPU connected to
  3501. a JTAG router, your @file{target.cfg} file
  3502. should define TAP event handlers using
  3503. code that looks something like this:
  3504. @example
  3505. jtag configure CHIP.cpu -event tap-enable @{
  3506. ... jtag operations using CHIP.jrc
  3507. @}
  3508. jtag configure CHIP.cpu -event tap-disable @{
  3509. ... jtag operations using CHIP.jrc
  3510. @}
  3511. @end example
  3512. Then you might want that CPU's TAP enabled almost all the time:
  3513. @example
  3514. jtag configure $CHIP.jrc -event setup "jtag tapenable $CHIP.cpu"
  3515. @end example
  3516. Note how that particular setup event handler declaration
  3517. uses quotes to evaluate @code{$CHIP} when the event is configured.
  3518. Using brackets @{ @} would cause it to be evaluated later,
  3519. at runtime, when it might have a different value.
  3520. @deffn {Command} {jtag tapdisable}
  3521. If necessary, disables the tap
  3522. by sending it a @option{tap-disable} event.
  3523. Returns the string "1" if the tap
  3524. specified by @var{} is enabled,
  3525. and "0" if it is disabled.
  3526. @end deffn
  3527. @deffn {Command} {jtag tapenable}
  3528. If necessary, enables the tap
  3529. by sending it a @option{tap-enable} event.
  3530. Returns the string "1" if the tap
  3531. specified by @var{} is enabled,
  3532. and "0" if it is disabled.
  3533. @end deffn
  3534. @deffn {Command} {jtag tapisenabled}
  3535. Returns the string "1" if the tap
  3536. specified by @var{} is enabled,
  3537. and "0" if it is disabled.
  3538. @quotation Note
  3539. Humans will find the @command{scan_chain} command more helpful
  3540. for querying the state of the JTAG taps.
  3541. @end quotation
  3542. @end deffn
  3543. @anchor{autoprobing}
  3544. @section Autoprobing
  3545. @cindex autoprobe
  3546. @cindex JTAG autoprobe
  3547. TAP configuration is the first thing that needs to be done
  3548. after interface and reset configuration. Sometimes it's
  3549. hard finding out what TAPs exist, or how they are identified.
  3550. Vendor documentation is not always easy to find and use.
  3551. To help you get past such problems, OpenOCD has a limited
  3552. @emph{autoprobing} ability to look at the scan chain, doing
  3553. a @dfn{blind interrogation} and then reporting the TAPs it finds.
  3554. To use this mechanism, start the OpenOCD server with only data
  3555. that configures your JTAG interface, and arranges to come up
  3556. with a slow clock (many devices don't support fast JTAG clocks
  3557. right when they come out of reset).
  3558. For example, your @file{openocd.cfg} file might have:
  3559. @example
  3560. source [find interface/olimex-arm-usb-tiny-h.cfg]
  3561. reset_config trst_and_srst
  3562. jtag_rclk 8
  3563. @end example
  3564. When you start the server without any TAPs configured, it will
  3565. attempt to autoconfigure the TAPs. There are two parts to this:
  3566. @enumerate
  3567. @item @emph{TAP discovery} ...
  3568. After a JTAG reset (sometimes a system reset may be needed too),
  3569. each TAP's data registers will hold the contents of either the
  3570. IDCODE or BYPASS register.
  3571. If JTAG communication is working, OpenOCD will see each TAP,
  3572. and report what @option{-expected-id} to use with it.
  3573. @item @emph{IR Length discovery} ...
  3574. Unfortunately JTAG does not provide a reliable way to find out
  3575. the value of the @option{-irlen} parameter to use with a TAP
  3576. that is discovered.
  3577. If OpenOCD can discover the length of a TAP's instruction
  3578. register, it will report it.
  3579. Otherwise you may need to consult vendor documentation, such
  3580. as chip data sheets or BSDL files.
  3581. @end enumerate
  3582. In many cases your board will have a simple scan chain with just
  3583. a single device. Here's what OpenOCD reported with one board
  3584. that's a bit more complex:
  3585. @example
  3586. clock speed 8 kHz
  3587. There are no enabled taps. AUTO PROBING MIGHT NOT WORK!!
  3588. AUTO auto0.tap - use "jtag newtap auto0 tap -expected-id 0x2b900f0f ..."
  3589. AUTO auto1.tap - use "jtag newtap auto1 tap -expected-id 0x07926001 ..."
  3590. AUTO auto2.tap - use "jtag newtap auto2 tap -expected-id 0x0b73b02f ..."
  3591. AUTO auto0.tap - use "... -irlen 4"
  3592. AUTO auto1.tap - use "... -irlen 4"
  3593. AUTO auto2.tap - use "... -irlen 6"
  3594. no gdb ports allocated as no target has been specified
  3595. @end example
  3596. Given that information, you should be able to either find some existing
  3597. config files to use, or create your own. If you create your own, you
  3598. would configure from the bottom up: first a @file{target.cfg} file
  3599. with these TAPs, any targets associated with them, and any on-chip
  3600. resources; then a @file{board.cfg} with off-chip resources, clocking,
  3601. and so forth.
  3602. @anchor{dapdeclaration}
  3603. @section DAP declaration (ARMv6-M, ARMv7 and ARMv8 targets)
  3604. @cindex DAP declaration
  3605. Since OpenOCD version 0.11.0, the Debug Access Port (DAP) is
  3606. no longer implicitly created together with the target. It must be
  3607. explicitly declared using the @command{dap create} command. For all ARMv6-M, ARMv7
  3608. and ARMv8 targets, the option "@option{-dap} @var{dap_name}" has to be used
  3609. instead of "@option{-chain-position} @var{}" when the target is created.
  3610. The @command{dap} command group supports the following sub-commands:
  3611. @deffn {Command} {dap create} dap_name @option{-chain-position} configparams...
  3612. Declare a DAP instance named @var{dap_name} linked to the JTAG tap
  3613. @var{}. This also creates a new command (@command{dap_name})
  3614. which is used for various purposes including additional configuration.
  3615. There can only be one DAP for each JTAG tap in the system.
  3616. A DAP may also provide optional @var{configparams}:
  3617. @itemize @bullet
  3618. @item @code{-ignore-syspwrupack}
  3619. @*Specify this to ignore the CSYSPWRUPACK bit in the ARM DAP DP CTRL/STAT
  3620. register during initial examination and when checking the sticky error bit.
  3621. This bit is normally checked after setting the CSYSPWRUPREQ bit, but some
  3622. devices do not set the ack bit until sometime later.
  3623. @end itemize
  3624. @end deffn
  3625. @deffn {Command} {dap names}
  3626. This command returns a list of all registered DAP objects. It it useful mainly
  3627. for TCL scripting.
  3628. @end deffn
  3629. @deffn {Command} {dap info} [num]
  3630. Displays the ROM table for MEM-AP @var{num},
  3631. defaulting to the currently selected AP of the currently selected target.
  3632. @end deffn
  3633. @deffn {Command} {dap init}
  3634. Initialize all registered DAPs. This command is used internally
  3635. during initialization. It can be issued at any time after the
  3636. initialization, too.
  3637. @end deffn
  3638. The following commands exist as subcommands of DAP instances:
  3639. @deffn {Command} {$dap_name info} [num]
  3640. Displays the ROM table for MEM-AP @var{num},
  3641. defaulting to the currently selected AP.
  3642. @end deffn
  3643. @deffn {Command} {$dap_name apid} [num]
  3644. Displays ID register from AP @var{num}, defaulting to the currently selected AP.
  3645. @end deffn
  3646. @anchor{DAP subcommand apreg}
  3647. @deffn {Command} {$dap_name apreg} ap_num reg [value]
  3648. Displays content of a register @var{reg} from AP @var{ap_num}
  3649. or set a new value @var{value}.
  3650. @var{reg} is byte address of a word register, 0, 4, 8 ... 0xfc.
  3651. @end deffn
  3652. @deffn {Command} {$dap_name apsel} [num]
  3653. Select AP @var{num}, defaulting to 0.
  3654. @end deffn
  3655. @deffn {Command} {$dap_name dpreg} reg [value]
  3656. Displays the content of DP register at address @var{reg}, or set it to a new
  3657. value @var{value}.
  3658. In case of SWD, @var{reg} is a value in packed format
  3659. @math{dpbanksel << 4 | addr} and assumes values 0, 4, 8 ... 0xfc.
  3660. In case of JTAG it only assumes values 0, 4, 8 and 0xc.
  3661. @emph{Note:} Consider using @command{poll off} to avoid any disturbing
  3662. background activity by OpenOCD while you are operating at such low-level.
  3663. @end deffn
  3664. @deffn {Command} {$dap_name baseaddr} [num]
  3665. Displays debug base address from MEM-AP @var{num},
  3666. defaulting to the currently selected AP.
  3667. @end deffn
  3668. @deffn {Command} {$dap_name memaccess} [value]
  3669. Displays the number of extra tck cycles in the JTAG idle to use for MEM-AP
  3670. memory bus access [0-255], giving additional time to respond to reads.
  3671. If @var{value} is defined, first assigns that.
  3672. @end deffn
  3673. @deffn {Command} {$dap_name apcsw} [value [mask]]
  3674. Displays or changes CSW bit pattern for MEM-AP transfers.
  3675. At the begin of each memory access the CSW pattern is extended (bitwise or-ed)
  3676. by @dfn{Size} and @dfn{AddrInc} bit-fields according to transfer requirements
  3677. and the result is written to the real CSW register. All bits except dynamically
  3678. updated fields @dfn{Size} and @dfn{AddrInc} can be changed by changing
  3679. the CSW pattern. Refer to ARM ADI v5 manual chapter 7.6.4 and appendix A
  3680. for details.
  3681. Use @var{value} only syntax if you want to set the new CSW pattern as a whole.
  3682. The example sets HPROT1 bit (required by Cortex-M) and clears the rest of
  3683. the pattern:
  3684. @example
  3685. kx.dap apcsw 0x2000000
  3686. @end example
  3687. If @var{mask} is also used, the CSW pattern is changed only on bit positions
  3688. where the mask bit is 1. The following example sets HPROT3 (cacheable)
  3689. and leaves the rest of the pattern intact. It configures memory access through
  3690. DCache on Cortex-M7.
  3691. @example
  3692. set CSW_HPROT3_CACHEABLE [expr 1 << 27]
  3694. @end example
  3695. Another example clears SPROT bit and leaves the rest of pattern intact:
  3696. @example
  3697. set CSW_SPROT [expr 1 << 30]
  3698. samv.dap apcsw 0 $CSW_SPROT
  3699. @end example
  3700. @emph{Note:} If you want to check the real value of CSW, not CSW pattern, use
  3701. @code{xxx.dap apreg 0}. @xref{DAP subcommand apreg,,}.
  3702. @emph{Warning:} Some of the CSW bits are vital for working memory transfer.
  3703. If you set a wrong CSW pattern and MEM-AP stopped working, use the following
  3704. example with a proper dap name:
  3705. @example
  3706. xxx.dap apcsw default
  3707. @end example
  3708. @end deffn
  3709. @deffn {Config Command} {$dap_name ti_be_32_quirks} [@option{enable}]
  3710. Set/get quirks mode for TI TMS450/TMS570 processors
  3711. Disabled by default
  3712. @end deffn
  3713. @node CPU Configuration
  3714. @chapter CPU Configuration
  3715. @cindex GDB target
  3716. This chapter discusses how to set up GDB debug targets for CPUs.
  3717. You can also access these targets without GDB
  3718. (@pxref{Architecture and Core Commands},
  3719. and @ref{targetstatehandling,,Target State handling}) and
  3720. through various kinds of NAND and NOR flash commands.
  3721. If you have multiple CPUs you can have multiple such targets.
  3722. We'll start by looking at how to examine the targets you have,
  3723. then look at how to add one more target and how to configure it.
  3724. @section Target List
  3725. @cindex target, current
  3726. @cindex target, list
  3727. All targets that have been set up are part of a list,
  3728. where each member has a name.
  3729. That name should normally be the same as the TAP name.
  3730. You can display the list with the @command{targets}
  3731. (plural!) command.
  3732. This display often has only one CPU; here's what it might
  3733. look like with more than one:
  3734. @verbatim
  3735. TargetName Type Endian TapName State
  3736. -- ------------------ ---------- ------ ------------------ ------------
  3737. 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
  3738. 1 MyTarget cortex_m little tap-disabled
  3739. @end verbatim
  3740. One member of that list is the @dfn{current target}, which
  3741. is implicitly referenced by many commands.
  3742. It's the one marked with a @code{*} near the target name.
  3743. In particular, memory addresses often refer to the address
  3744. space seen by that current target.
  3745. Commands like @command{mdw} (memory display words)
  3746. and @command{flash erase_address} (erase NOR flash blocks)
  3747. are examples; and there are many more.
  3748. Several commands let you examine the list of targets:
  3749. @deffn {Command} {target current}
  3750. Returns the name of the current target.
  3751. @end deffn
  3752. @deffn {Command} {target names}
  3753. Lists the names of all current targets in the list.
  3754. @example
  3755. foreach t [target names] @{
  3756. puts [format "Target: %s\n" $t]
  3757. @}
  3758. @end example
  3759. @end deffn
  3760. @c yep, "target list" would have been better.
  3761. @c plus maybe "target setdefault".
  3762. @deffn {Command} {targets} [name]
  3763. @emph{Note: the name of this command is plural. Other target
  3764. command names are singular.}
  3765. With no parameter, this command displays a table of all known
  3766. targets in a user friendly form.
  3767. With a parameter, this command sets the current target to
  3768. the given target with the given @var{name}; this is
  3769. only relevant on boards which have more than one target.
  3770. @end deffn
  3771. @section Target CPU Types
  3772. @cindex target type
  3773. @cindex CPU type
  3774. Each target has a @dfn{CPU type}, as shown in the output of
  3775. the @command{targets} command. You need to specify that type
  3776. when calling @command{target create}.
  3777. The CPU type indicates more than just the instruction set.
  3778. It also indicates how that instruction set is implemented,
  3779. what kind of debug support it integrates,
  3780. whether it has an MMU (and if so, what kind),
  3781. what core-specific commands may be available
  3782. (@pxref{Architecture and Core Commands}),
  3783. and more.
  3784. It's easy to see what target types are supported,
  3785. since there's a command to list them.
  3786. @anchor{targettypes}
  3787. @deffn {Command} {target types}
  3788. Lists all supported target types.
  3789. At this writing, the supported CPU types are:
  3790. @itemize @bullet
  3791. @item @code{aarch64} -- this is an ARMv8-A core with an MMU.
  3792. @item @code{arm11} -- this is a generation of ARMv6 cores.
  3793. @item @code{arm720t} -- this is an ARMv4 core with an MMU.
  3794. @item @code{arm7tdmi} -- this is an ARMv4 core.
  3795. @item @code{arm920t} -- this is an ARMv4 core with an MMU.
  3796. @item @code{arm926ejs} -- this is an ARMv5 core with an MMU.
  3797. @item @code{arm946e} -- this is an ARMv5 core with an MMU.
  3798. @item @code{arm966e} -- this is an ARMv5 core.
  3799. @item @code{arm9tdmi} -- this is an ARMv4 core.
  3800. @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
  3801. (Support for this is preliminary and incomplete.)
  3802. @item @code{avr32_ap7k} -- this an AVR32 core.
  3803. @item @code{cortex_a} -- this is an ARMv7-A core with an MMU.
  3804. @item @code{cortex_m} -- this is an ARMv7-M core, supporting only the
  3805. compact Thumb2 instruction set. Supports also ARMv6-M and ARMv8-M cores
  3806. @item @code{cortex_r4} -- this is an ARMv7-R core.
  3807. @item @code{dragonite} -- resembles arm966e.
  3808. @item @code{dsp563xx} -- implements Freescale's 24-bit DSP.
  3809. (Support for this is still incomplete.)
  3810. @item @code{dsp5680xx} -- implements Freescale's 5680x DSP.
  3811. @item @code{esirisc} -- this is an EnSilica eSi-RISC core.
  3812. The current implementation supports eSi-32xx cores.
  3813. @item @code{fa526} -- resembles arm920 (w/o Thumb).
  3814. @item @code{feroceon} -- resembles arm926.
  3815. @item @code{hla_target} -- a Cortex-M alternative to work with HL adapters like ST-Link.
  3816. @item @code{ls1_sap} -- this is the SAP on NXP LS102x CPUs,
  3817. allowing access to physical memory addresses independently of CPU cores.
  3818. @item @code{mem_ap} -- this is an ARM debug infrastructure Access Port without
  3819. a CPU, through which bus read and write cycles can be generated; it may be
  3820. useful for working with non-CPU hardware behind an AP or during development of
  3821. support for new CPUs.
  3822. It's possible to connect a GDB client to this target (the GDB port has to be
  3823. specified, @xref{gdbportoverride,,option -gdb-port}.), and a fake ARM core will
  3824. be emulated to comply to GDB remote protocol.
  3825. @item @code{mips_m4k} -- a MIPS core.
  3826. @item @code{mips_mips64} -- a MIPS64 core.
  3827. @item @code{nds32_v2} -- this is an Andes NDS32 v2 core.
  3828. @item @code{nds32_v3} -- this is an Andes NDS32 v3 core.
  3829. @item @code{nds32_v3m} -- this is an Andes NDS32 v3m core.
  3830. @item @code{or1k} -- this is an OpenRISC 1000 core.
  3831. The current implementation supports three JTAG TAP cores:
  3832. @itemize @minus
  3833. @item @code{OpenCores TAP} (See: @url{{}jtag})
  3834. @item @code{Altera Virtual JTAG TAP} (See: @url{})
  3835. @item @code{Xilinx BSCAN_* virtual JTAG interface} (See: @url{})
  3836. @end itemize
  3837. And two debug interfaces cores:
  3838. @itemize @minus
  3839. @item @code{Advanced debug interface}
  3840. @*(See: @url{{}adv_debug_sys})
  3841. @item @code{SoC Debug Interface}
  3842. @*(See: @url{{}dbg_interface})
  3843. @end itemize
  3844. @item @code{quark_d20xx} -- an Intel Quark D20xx core.
  3845. @item @code{quark_x10xx} -- an Intel Quark X10xx core.
  3846. @item @code{riscv} -- a RISC-V core.
  3847. @item @code{stm8} -- implements an STM8 core.
  3848. @item @code{testee} -- a dummy target for cases without a real CPU, e.g. CPLD.
  3849. @item @code{xscale} -- this is actually an architecture,
  3850. not a CPU type. It is based on the ARMv5 architecture.
  3851. @end itemize
  3852. @end deffn
  3853. To avoid being confused by the variety of ARM based cores, remember
  3854. this key point: @emph{ARM is a technology licencing company}.
  3855. (See: @url{}.)
  3856. The CPU name used by OpenOCD will reflect the CPU design that was
  3857. licensed, not a vendor brand which incorporates that design.
  3858. Name prefixes like arm7, arm9, arm11, and cortex
  3859. reflect design generations;
  3860. while names like ARMv4, ARMv5, ARMv6, ARMv7 and ARMv8
  3861. reflect an architecture version implemented by a CPU design.
  3862. @anchor{targetconfiguration}
  3863. @section Target Configuration
  3864. Before creating a ``target'', you must have added its TAP to the scan chain.
  3865. When you've added that TAP, you will have a @code{}
  3866. which is used to set up the CPU support.
  3867. The chip-specific configuration file will normally configure its CPU(s)
  3868. right after it adds all of the chip's TAPs to the scan chain.
  3869. Although you can set up a target in one step, it's often clearer if you
  3870. use shorter commands and do it in two steps: create it, then configure
  3871. optional parts.
  3872. All operations on the target after it's created will use a new
  3873. command, created as part of target creation.
  3874. The two main things to configure after target creation are
  3875. a work area, which usually has target-specific defaults even
  3876. if the board setup code overrides them later;
  3877. and event handlers (@pxref{targetevents,,Target Events}), which tend
  3878. to be much more board-specific.
  3879. The key steps you use might look something like this
  3880. @example
  3881. dap create mychip.dap -chain-position mychip.cpu
  3882. target create MyTarget cortex_m -dap mychip.dap
  3883. MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
  3884. MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
  3885. MyTarget configure -event reset-init @{ myboard_reinit @}
  3886. @end example
  3887. You should specify a working area if you can; typically it uses some
  3888. on-chip SRAM.
  3889. Such a working area can speed up many things, including bulk
  3890. writes to target memory;
  3891. flash operations like checking to see if memory needs to be erased;
  3892. GDB memory checksumming;
  3893. and more.
  3894. @quotation Warning
  3895. On more complex chips, the work area can become
  3896. inaccessible when application code
  3897. (such as an operating system)
  3898. enables or disables the MMU.
  3899. For example, the particular MMU context used to access the virtual
  3900. address will probably matter ... and that context might not have
  3901. easy access to other addresses needed.
  3902. At this writing, OpenOCD doesn't have much MMU intelligence.
  3903. @end quotation
  3904. It's often very useful to define a @code{reset-init} event handler.
  3905. For systems that are normally used with a boot loader,
  3906. common tasks include updating clocks and initializing memory
  3907. controllers.
  3908. That may be needed to let you write the boot loader into flash,
  3909. in order to ``de-brick'' your board; or to load programs into
  3910. external DDR memory without having run the boot loader.
  3911. @deffn {Config Command} {target create} target_name type configparams...
  3912. This command creates a GDB debug target that refers to a specific JTAG tap.
  3913. It enters that target into a list, and creates a new
  3914. command (@command{@var{target_name}}) which is used for various
  3915. purposes including additional configuration.
  3916. @itemize @bullet
  3917. @item @var{target_name} ... is the name of the debug target.
  3918. By convention this should be the same as the @emph{}
  3919. of the TAP associated with this target, which must be specified here
  3920. using the @code{-chain-position @var{}} configparam.
  3921. This name is also used to create the target object command,
  3922. referred to here as @command{$target_name},
  3923. and in other places the target needs to be identified.
  3924. @item @var{type} ... specifies the target type. @xref{targettypes,,target types}.
  3925. @item @var{configparams} ... all parameters accepted by
  3926. @command{$target_name configure} are permitted.
  3927. If the target is big-endian, set it here with @code{-endian big}.
  3928. You @emph{must} set the @code{-chain-position @var{}} or
  3929. @code{-dap @var{dap_name}} here.
  3930. @end itemize
  3931. @end deffn
  3932. @deffn {Command} {$target_name configure} configparams...
  3933. The options accepted by this command may also be
  3934. specified as parameters to @command{target create}.
  3935. Their values can later be queried one at a time by
  3936. using the @command{$target_name cget} command.
  3937. @emph{Warning:} changing some of these after setup is dangerous.
  3938. For example, moving a target from one TAP to another;
  3939. and changing its endianness.
  3940. @itemize @bullet
  3941. @item @code{-chain-position} @var{} -- names the TAP
  3942. used to access this target.
  3943. @item @code{-dap} @var{dap_name} -- names the DAP used to access
  3944. this target. @xref{dapdeclaration,,DAP declaration}, on how to
  3945. create and manage DAP instances.
  3946. @item @code{-endian} (@option{big}|@option{little}) -- specifies
  3947. whether the CPU uses big or little endian conventions
  3948. @item @code{-event} @var{event_name} @var{event_body} --
  3949. @xref{targetevents,,Target Events}.
  3950. Note that this updates a list of named event handlers.
  3951. Calling this twice with two different event names assigns
  3952. two different handlers, but calling it twice with the
  3953. same event name assigns only one handler.
  3954. Current target is temporarily overridden to the event issuing target
  3955. before handler code starts and switched back after handler is done.
  3956. @item @code{-work-area-backup} (@option{0}|@option{1}) -- says
  3957. whether the work area gets backed up; by default,
  3958. @emph{it is not backed up.}
  3959. When possible, use a working_area that doesn't need to be backed up,
  3960. since performing a backup slows down operations.
  3961. For example, the beginning of an SRAM block is likely to
  3962. be used by most build systems, but the end is often unused.
  3963. @item @code{-work-area-size} @var{size} -- specify work are size,
  3964. in bytes. The same size applies regardless of whether its physical
  3965. or virtual address is being used.
  3966. @item @code{-work-area-phys} @var{address} -- set the work area
  3967. base @var{address} to be used when no MMU is active.
  3968. @item @code{-work-area-virt} @var{address} -- set the work area
  3969. base @var{address} to be used when an MMU is active.
  3970. @emph{Do not specify a value for this except on targets with an MMU.}
  3971. The value should normally correspond to a static mapping for the
  3972. @code{-work-area-phys} address, set up by the current operating system.
  3973. @anchor{rtostype}
  3974. @item @code{-rtos} @var{rtos_type} -- enable rtos support for target,
  3975. @var{rtos_type} can be one of @option{auto}, @option{eCos},
  3976. @option{ThreadX}, @option{FreeRTOS}, @option{linux}, @option{ChibiOS},
  3977. @option{embKernel}, @option{mqx}, @option{uCOS-III}, @option{nuttx},
  3978. @option{RIOT}, @option{Zephyr}
  3979. @xref{gdbrtossupport,,RTOS Support}.
  3980. @item @code{-defer-examine} -- skip target examination at initial JTAG chain
  3981. scan and after a reset. A manual call to arp_examine is required to
  3982. access the target for debugging.
  3983. @item @code{-ap-num} @var{ap_number} -- set DAP access port for target,
  3984. @var{ap_number} is the numeric index of the DAP AP the target is connected to.
  3985. Use this option with systems where multiple, independent cores are connected
  3986. to separate access ports of the same DAP.
  3987. @item @code{-cti} @var{cti_name} -- set Cross-Trigger Interface (CTI) connected
  3988. to the target. Currently, only the @code{aarch64} target makes use of this option,
  3989. where it is a mandatory configuration for the target run control.
  3990. @xref{armcrosstrigger,,ARM Cross-Trigger Interface},
  3991. for instruction on how to declare and control a CTI instance.
  3992. @anchor{gdbportoverride}
  3993. @item @code{-gdb-port} @var{number} -- see command @command{gdb_port} for the
  3994. possible values of the parameter @var{number}, which are not only numeric values.
  3995. Use this option to override, for this target only, the global parameter set with
  3996. command @command{gdb_port}.
  3997. @xref{gdb_port,,command gdb_port}.
  3998. @item @code{-gdb-max-connections} @var{number} -- EXPERIMENTAL: set the maximum
  3999. number of GDB connections that are allowed for the target. Default is 1.
  4000. A negative value for @var{number} means unlimited connections.
  4001. See @xref{gdbmeminspect,,Using GDB as a non-intrusive memory inspector}.
  4002. @end itemize
  4003. @end deffn
  4004. @section Other $target_name Commands
  4005. @cindex object command
  4006. The Tcl/Tk language has the concept of object commands,
  4007. and OpenOCD adopts that same model for targets.
  4008. A good Tk example is a on screen button.
  4009. Once a button is created a button
  4010. has a name (a path in Tk terms) and that name is useable as a first
  4011. class command. For example in Tk, one can create a button and later
  4012. configure it like this:
  4013. @example
  4014. # Create
  4015. button .foobar -background red -command @{ foo @}
  4016. # Modify
  4017. .foobar configure -foreground blue
  4018. # Query
  4019. set x [.foobar cget -background]
  4020. # Report
  4021. puts [format "The button is %s" $x]
  4022. @end example
  4023. In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
  4024. button, and its object commands are invoked the same way.
  4025. @example
  4026. str912.cpu mww 0x1234 0x42
  4027. omap3530.cpu mww 0x5555 123
  4028. @end example
  4029. The commands supported by OpenOCD target objects are:
  4030. @deffn {Command} {$target_name arp_examine} @option{allow-defer}
  4031. @deffnx {Command} {$target_name arp_halt}
  4032. @deffnx {Command} {$target_name arp_poll}
  4033. @deffnx {Command} {$target_name arp_reset}
  4034. @deffnx {Command} {$target_name arp_waitstate}
  4035. Internal OpenOCD scripts (most notably @file{startup.tcl})
  4036. use these to deal with specific reset cases.
  4037. They are not otherwise documented here.
  4038. @end deffn
  4039. @deffn {Command} {$target_name array2mem} arrayname width address count
  4040. @deffnx {Command} {$target_name mem2array} arrayname width address count
  4041. These provide an efficient script-oriented interface to memory.
  4042. The @code{array2mem} primitive writes bytes, halfwords, words
  4043. or double-words; while @code{mem2array} reads them.
  4044. In both cases, the TCL side uses an array, and
  4045. the target side uses raw memory.
  4046. The efficiency comes from enabling the use of
  4047. bulk JTAG data transfer operations.
  4048. The script orientation comes from working with data
  4049. values that are packaged for use by TCL scripts;
  4050. @command{mdw} type primitives only print data they retrieve,
  4051. and neither store nor return those values.
  4052. @itemize
  4053. @item @var{arrayname} ... is the name of an array variable
  4054. @item @var{width} ... is 8/16/32/64 - indicating the memory access size
  4055. @item @var{address} ... is the target memory address
  4056. @item @var{count} ... is the number of elements to process
  4057. @end itemize
  4058. @end deffn
  4059. @deffn {Command} {$target_name cget} queryparm
  4060. Each configuration parameter accepted by
  4061. @command{$target_name configure}
  4062. can be individually queried, to return its current value.
  4063. The @var{queryparm} is a parameter name
  4064. accepted by that command, such as @code{-work-area-phys}.
  4065. There are a few special cases:
  4066. @itemize @bullet
  4067. @item @code{-event} @var{event_name} -- returns the handler for the
  4068. event named @var{event_name}.
  4069. This is a special case because setting a handler requires
  4070. two parameters.
  4071. @item @code{-type} -- returns the target type.
  4072. This is a special case because this is set using
  4073. @command{target create} and can't be changed
  4074. using @command{$target_name configure}.
  4075. @end itemize
  4076. For example, if you wanted to summarize information about
  4077. all the targets you might use something like this:
  4078. @example
  4079. foreach name [target names] @{
  4080. set y [$name cget -endian]
  4081. set z [$name cget -type]
  4082. puts [format "Chip %d is %s, Endian: %s, type: %s" \
  4083. $x $name $y $z]
  4084. @}
  4085. @end example
  4086. @end deffn
  4087. @anchor{targetcurstate}
  4088. @deffn {Command} {$target_name curstate}
  4089. Displays the current target state:
  4090. @code{debug-running},
  4091. @code{halted},
  4092. @code{reset},
  4093. @code{running}, or @code{unknown}.
  4094. (Also, @pxref{eventpolling,,Event Polling}.)
  4095. @end deffn
  4096. @deffn {Command} {$target_name eventlist}
  4097. Displays a table listing all event handlers
  4098. currently associated with this target.
  4099. @xref{targetevents,,Target Events}.
  4100. @end deffn
  4101. @deffn {Command} {$target_name invoke-event} event_name
  4102. Invokes the handler for the event named @var{event_name}.
  4103. (This is primarily intended for use by OpenOCD framework
  4104. code, for example by the reset code in @file{startup.tcl}.)
  4105. @end deffn
  4106. @deffn {Command} {$target_name mdd} [phys] addr [count]
  4107. @deffnx {Command} {$target_name mdw} [phys] addr [count]
  4108. @deffnx {Command} {$target_name mdh} [phys] addr [count]
  4109. @deffnx {Command} {$target_name mdb} [phys] addr [count]
  4110. Display contents of address @var{addr}, as
  4111. 64-bit doublewords (@command{mdd}),
  4112. 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
  4113. or 8-bit bytes (@command{mdb}).
  4114. When the current target has an MMU which is present and active,
  4115. @var{addr} is interpreted as a virtual address.
  4116. Otherwise, or if the optional @var{phys} flag is specified,
  4117. @var{addr} is interpreted as a physical address.
  4118. If @var{count} is specified, displays that many units.
  4119. (If you want to manipulate the data instead of displaying it,
  4120. see the @code{mem2array} primitives.)
  4121. @end deffn
  4122. @deffn {Command} {$target_name mwd} [phys] addr doubleword [count]
  4123. @deffnx {Command} {$target_name mww} [phys] addr word [count]
  4124. @deffnx {Command} {$target_name mwh} [phys] addr halfword [count]
  4125. @deffnx {Command} {$target_name mwb} [phys] addr byte [count]
  4126. Writes the specified @var{doubleword} (64 bits), @var{word} (32 bits),
  4127. @var{halfword} (16 bits), or @var{byte} (8-bit) value,
  4128. at the specified address @var{addr}.
  4129. When the current target has an MMU which is present and active,
  4130. @var{addr} is interpreted as a virtual address.
  4131. Otherwise, or if the optional @var{phys} flag is specified,
  4132. @var{addr} is interpreted as a physical address.
  4133. If @var{count} is specified, fills that many units of consecutive address.
  4134. @end deffn
  4135. @anchor{targetevents}
  4136. @section Target Events
  4137. @cindex target events
  4138. @cindex events
  4139. At various times, certain things can happen, or you want them to happen.
  4140. For example:
  4141. @itemize @bullet
  4142. @item What should happen when GDB connects? Should your target reset?
  4143. @item When GDB tries to flash the target, do you need to enable the flash via a special command?
  4144. @item Is using SRST appropriate (and possible) on your system?
  4145. Or instead of that, do you need to issue JTAG commands to trigger reset?
  4146. SRST usually resets everything on the scan chain, which can be inappropriate.
  4147. @item During reset, do you need to write to certain memory locations
  4148. to set up system clocks or
  4149. to reconfigure the SDRAM?
  4150. How about configuring the watchdog timer, or other peripherals,
  4151. to stop running while you hold the core stopped for debugging?
  4152. @end itemize
  4153. All of the above items can be addressed by target event handlers.
  4154. These are set up by @command{$target_name configure -event} or
  4155. @command{target create ... -event}.
  4156. The programmer's model matches the @code{-command} option used in Tcl/Tk
  4157. buttons and events. The two examples below act the same, but one creates
  4158. and invokes a small procedure while the other inlines it.
  4159. @example
  4160. proc my_init_proc @{ @} @{
  4161. echo "Disabling watchdog..."
  4162. mww 0xfffffd44 0x00008000
  4163. @}
  4164. mychip.cpu configure -event reset-init my_init_proc
  4165. mychip.cpu configure -event reset-init @{
  4166. echo "Disabling watchdog..."
  4167. mww 0xfffffd44 0x00008000
  4168. @}
  4169. @end example
  4170. The following target events are defined:
  4171. @itemize @bullet
  4172. @item @b{debug-halted}
  4173. @* The target has halted for debug reasons (i.e.: breakpoint)
  4174. @item @b{debug-resumed}
  4175. @* The target has resumed (i.e.: GDB said run)
  4176. @item @b{early-halted}
  4177. @* Occurs early in the halt process
  4178. @item @b{examine-start}
  4179. @* Before target examine is called.
  4180. @item @b{examine-end}
  4181. @* After target examine is called with no errors.
  4182. @item @b{examine-fail}
  4183. @* After target examine fails.
  4184. @item @b{gdb-attach}
  4185. @* When GDB connects. Issued before any GDB communication with the target
  4186. starts. GDB expects the target is halted during attachment.
  4187. @xref{gdbmeminspect,,GDB as a non-intrusive memory inspector}, how to
  4188. connect GDB to running target.
  4189. The event can be also used to set up the target so it is possible to probe flash.
  4190. Probing flash is necessary during GDB connect if you want to use
  4191. @pxref{programmingusinggdb,,programming using GDB}.
  4192. Another use of the flash memory map is for GDB to automatically choose
  4193. hardware or software breakpoints depending on whether the breakpoint
  4194. is in RAM or read only memory.
  4195. Default is @code{halt}
  4196. @item @b{gdb-detach}
  4197. @* When GDB disconnects
  4198. @item @b{gdb-end}
  4199. @* When the target has halted and GDB is not doing anything (see early halt)
  4200. @item @b{gdb-flash-erase-start}
  4201. @* Before the GDB flash process tries to erase the flash (default is
  4202. @code{reset init})
  4203. @item @b{gdb-flash-erase-end}
  4204. @* After the GDB flash process has finished erasing the flash
  4205. @item @b{gdb-flash-write-start}
  4206. @* Before GDB writes to the flash
  4207. @item @b{gdb-flash-write-end}
  4208. @* After GDB writes to the flash (default is @code{reset halt})
  4209. @item @b{gdb-start}
  4210. @* Before the target steps, GDB is trying to start/resume the target
  4211. @item @b{halted}
  4212. @* The target has halted
  4213. @item @b{reset-assert-pre}
  4214. @* Issued as part of @command{reset} processing
  4215. after @command{reset-start} was triggered
  4216. but before either SRST alone is asserted on the scan chain,
  4217. or @code{reset-assert} is triggered.
  4218. @item @b{reset-assert}
  4219. @* Issued as part of @command{reset} processing
  4220. after @command{reset-assert-pre} was triggered.
  4221. When such a handler is present, cores which support this event will use
  4222. it instead of asserting SRST.
  4223. This support is essential for debugging with JTAG interfaces which
  4224. don't include an SRST line (JTAG doesn't require SRST), and for
  4225. selective reset on scan chains that have multiple targets.
  4226. @item @b{reset-assert-post}
  4227. @* Issued as part of @command{reset} processing
  4228. after @code{reset-assert} has been triggered.
  4229. or the target asserted SRST on the entire scan chain.
  4230. @item @b{reset-deassert-pre}
  4231. @* Issued as part of @command{reset} processing
  4232. after @code{reset-assert-post} has been triggered.
  4233. @item @b{reset-deassert-post}
  4234. @* Issued as part of @command{reset} processing
  4235. after @code{reset-deassert-pre} has been triggered
  4236. and (if the target is using it) after SRST has been
  4237. released on the scan chain.
  4238. @item @b{reset-end}
  4239. @* Issued as the final step in @command{reset} processing.
  4240. @item @b{reset-init}
  4241. @* Used by @b{reset init} command for board-specific initialization.
  4242. This event fires after @emph{reset-deassert-post}.
  4243. This is where you would configure PLLs and clocking, set up DRAM so
  4244. you can download programs that don't fit in on-chip SRAM, set up pin
  4245. multiplexing, and so on.
  4246. (You may be able to switch to a fast JTAG clock rate here, after
  4247. the target clocks are fully set up.)
  4248. @item @b{reset-start}
  4249. @* Issued as the first step in @command{reset} processing
  4250. before @command{reset-assert-pre} is called.
  4251. This is the most robust place to use @command{jtag_rclk}
  4252. or @command{adapter speed} to switch to a low JTAG clock rate,
  4253. when reset disables PLLs needed to use a fast clock.
  4254. @item @b{resume-start}
  4255. @* Before any target is resumed
  4256. @item @b{resume-end}
  4257. @* After all targets have resumed
  4258. @item @b{resumed}
  4259. @* Target has resumed
  4260. @item @b{step-start}
  4261. @* Before a target is single-stepped
  4262. @item @b{step-end}
  4263. @* After single-step has completed
  4264. @item @b{trace-config}
  4265. @* After target hardware trace configuration was changed
  4266. @end itemize
  4267. @quotation Note
  4268. OpenOCD events are not supposed to be preempt by another event, but this
  4269. is not enforced in current code. Only the target event @b{resumed} is
  4270. executed with polling disabled; this avoids polling to trigger the event
  4271. @b{halted}, reversing the logical order of execution of their handlers.
  4272. Future versions of OpenOCD will prevent the event preemption and will
  4273. disable the schedule of polling during the event execution. Do not rely
  4274. on polling in any event handler; this means, don't expect the status of
  4275. a core to change during the execution of the handler. The event handler
  4276. will have to enable polling or use @command{$target_name arp_poll} to
  4277. check if the core has changed status.
  4278. @end quotation
  4279. @node Flash Commands
  4280. @chapter Flash Commands
  4281. OpenOCD has different commands for NOR and NAND flash;
  4282. the ``flash'' command works with NOR flash, while
  4283. the ``nand'' command works with NAND flash.
  4284. This partially reflects different hardware technologies:
  4285. NOR flash usually supports direct CPU instruction and data bus access,
  4286. while data from a NAND flash must be copied to memory before it can be
  4287. used. (SPI flash must also be copied to memory before use.)
  4288. However, the documentation also uses ``flash'' as a generic term;
  4289. for example, ``Put flash configuration in board-specific files''.
  4290. Flash Steps:
  4291. @enumerate
  4292. @item Configure via the command @command{flash bank}
  4293. @* Do this in a board-specific configuration file,
  4294. passing parameters as needed by the driver.
  4295. @item Operate on the flash via @command{flash subcommand}
  4296. @* Often commands to manipulate the flash are typed by a human, or run
  4297. via a script in some automated way. Common tasks include writing a
  4298. boot loader, operating system, or other data.
  4299. @item GDB Flashing
  4300. @* Flashing via GDB requires the flash be configured via ``flash
  4301. bank'', and the GDB flash features be enabled.
  4302. @xref{gdbconfiguration,,GDB Configuration}.
  4303. @end enumerate
  4304. Many CPUs have the ability to ``boot'' from the first flash bank.
  4305. This means that misprogramming that bank can ``brick'' a system,
  4306. so that it can't boot.
  4307. JTAG tools, like OpenOCD, are often then used to ``de-brick'' the
  4308. board by (re)installing working boot firmware.
  4309. @anchor{norconfiguration}
  4310. @section Flash Configuration Commands
  4311. @cindex flash configuration
  4312. @deffn {Config Command} {flash bank} name driver base size chip_width bus_width target [driver_options]
  4313. Configures a flash bank which provides persistent storage
  4314. for addresses from @math{base} to @math{base + size - 1}.
  4315. These banks will often be visible to GDB through the target's memory map.
  4316. In some cases, configuring a flash bank will activate extra commands;
  4317. see the driver-specific documentation.
  4318. @itemize @bullet
  4319. @item @var{name} ... may be used to reference the flash bank
  4320. in other flash commands. A number is also available.
  4321. @item @var{driver} ... identifies the controller driver
  4322. associated with the flash bank being declared.
  4323. This is usually @code{cfi} for external flash, or else
  4324. the name of a microcontroller with embedded flash memory.
  4325. @xref{flashdriverlist,,Flash Driver List}.
  4326. @item @var{base} ... Base address of the flash chip.
  4327. @item @var{size} ... Size of the chip, in bytes.
  4328. For some drivers, this value is detected from the hardware.
  4329. @item @var{chip_width} ... Width of the flash chip, in bytes;
  4330. ignored for most microcontroller drivers.
  4331. @item @var{bus_width} ... Width of the data bus used to access the
  4332. chip, in bytes; ignored for most microcontroller drivers.
  4333. @item @var{target} ... Names the target used to issue
  4334. commands to the flash controller.
  4335. @comment Actually, it's currently a controller-specific parameter...
  4336. @item @var{driver_options} ... drivers may support, or require,
  4337. additional parameters. See the driver-specific documentation
  4338. for more information.
  4339. @end itemize
  4340. @quotation Note
  4341. This command is not available after OpenOCD initialization has completed.
  4342. Use it in board specific configuration files, not interactively.
  4343. @end quotation
  4344. @end deffn
  4345. @comment less confusing would be: "flash list" (like "nand list")
  4346. @deffn {Command} {flash banks}
  4347. Prints a one-line summary of each device that was
  4348. declared using @command{flash bank}, numbered from zero.
  4349. Note that this is the @emph{plural} form;
  4350. the @emph{singular} form is a very different command.
  4351. @end deffn
  4352. @deffn {Command} {flash list}
  4353. Retrieves a list of associative arrays for each device that was
  4354. declared using @command{flash bank}, numbered from zero.
  4355. This returned list can be manipulated easily from within scripts.
  4356. @end deffn
  4357. @deffn {Command} {flash probe} num
  4358. Identify the flash, or validate the parameters of the configured flash. Operation
  4359. depends on the flash type.
  4360. The @var{num} parameter is a value shown by @command{flash banks}.
  4361. Most flash commands will implicitly @emph{autoprobe} the bank;
  4362. flash drivers can distinguish between probing and autoprobing,
  4363. but most don't bother.
  4364. @end deffn
  4365. @section Preparing a Target before Flash Programming
  4366. The target device should be in well defined state before the flash programming
  4367. begins.
  4368. @emph{Always issue} @command{reset init} before @ref{flashprogrammingcommands,,Flash Programming Commands}.
  4369. Do not issue another @command{reset} or @command{reset halt} or @command{resume}
  4370. until the programming session is finished.
  4371. If you use @ref{programmingusinggdb,,Programming using GDB},
  4372. the target is prepared automatically in the event gdb-flash-erase-start
  4373. The jimtcl script @command{program} calls @command{reset init} explicitly.
  4374. @section Erasing, Reading, Writing to Flash
  4375. @cindex flash erasing
  4376. @cindex flash reading
  4377. @cindex flash writing
  4378. @cindex flash programming
  4379. @anchor{flashprogrammingcommands}
  4380. One feature distinguishing NOR flash from NAND or serial flash technologies
  4381. is that for read access, it acts exactly like any other addressable memory.
  4382. This means you can use normal memory read commands like @command{mdw} or
  4383. @command{dump_image} with it, with no special @command{flash} subcommands.
  4384. @xref{memoryaccess,,Memory access}, and @ref{imageaccess,,Image access}.
  4385. Write access works differently. Flash memory normally needs to be erased
  4386. before it's written. Erasing a sector turns all of its bits to ones, and
  4387. writing can turn ones into zeroes. This is why there are special commands
  4388. for interactive erasing and writing, and why GDB needs to know which parts
  4389. of the address space hold NOR flash memory.
  4390. @quotation Note
  4391. Most of these erase and write commands leverage the fact that NOR flash
  4392. chips consume target address space. They implicitly refer to the current
  4393. JTAG target, and map from an address in that target's address space
  4394. back to a flash bank.
  4395. @comment In May 2009, those mappings may fail if any bank associated
  4396. @comment with that target doesn't successfully autoprobe ... bug worth fixing?
  4397. A few commands use abstract addressing based on bank and sector numbers,
  4398. and don't depend on searching the current target and its address space.
  4399. Avoid confusing the two command models.
  4400. @end quotation
  4401. Some flash chips implement software protection against accidental writes,
  4402. since such buggy writes could in some cases ``brick'' a system.
  4403. For such systems, erasing and writing may require sector protection to be
  4404. disabled first.
  4405. Examples include CFI flash such as ``Intel Advanced Bootblock flash'',
  4406. and AT91SAM7 on-chip flash.
  4407. @xref{flashprotect,,flash protect}.
  4408. @deffn {Command} {flash erase_sector} num first last
  4409. Erase sectors in bank @var{num}, starting at sector @var{first}
  4410. up to and including @var{last}.
  4411. Sector numbering starts at 0.
  4412. Providing a @var{last} sector of @option{last}
  4413. specifies "to the end of the flash bank".
  4414. The @var{num} parameter is a value shown by @command{flash banks}.
  4415. @end deffn
  4416. @deffn {Command} {flash erase_address} [@option{pad}] [@option{unlock}] address length
  4417. Erase sectors starting at @var{address} for @var{length} bytes.
  4418. Unless @option{pad} is specified, @math{address} must begin a
  4419. flash sector, and @math{address + length - 1} must end a sector.
  4420. Specifying @option{pad} erases extra data at the beginning and/or
  4421. end of the specified region, as needed to erase only full sectors.
  4422. The flash bank to use is inferred from the @var{address}, and
  4423. the specified length must stay within that bank.
  4424. As a special case, when @var{length} is zero and @var{address} is
  4425. the start of the bank, the whole flash is erased.
  4426. If @option{unlock} is specified, then the flash is unprotected
  4427. before erase starts.
  4428. @end deffn
  4429. @deffn {Command} {flash filld} address double-word length
  4430. @deffnx {Command} {flash fillw} address word length
  4431. @deffnx {Command} {flash fillh} address halfword length
  4432. @deffnx {Command} {flash fillb} address byte length
  4433. Fills flash memory with the specified @var{double-word} (64 bits), @var{word} (32 bits),
  4434. @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
  4435. starting at @var{address} and continuing
  4436. for @var{length} units (word/halfword/byte).
  4437. No erasure is done before writing; when needed, that must be done
  4438. before issuing this command.
  4439. Writes are done in blocks of up to 1024 bytes, and each write is
  4440. verified by reading back the data and comparing it to what was written.
  4441. The flash bank to use is inferred from the @var{address} of
  4442. each block, and the specified length must stay within that bank.
  4443. @end deffn
  4444. @comment no current checks for errors if fill blocks touch multiple banks!
  4445. @deffn {Command} {flash mdw} addr [count]
  4446. @deffnx {Command} {flash mdh} addr [count]
  4447. @deffnx {Command} {flash mdb} addr [count]
  4448. Display contents of address @var{addr}, as
  4449. 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
  4450. or 8-bit bytes (@command{mdb}).
  4451. If @var{count} is specified, displays that many units.
  4452. Reads from flash using the flash driver, therefore it enables reading
  4453. from a bank not mapped in target address space.
  4454. The flash bank to use is inferred from the @var{address} of
  4455. each block, and the specified length must stay within that bank.
  4456. @end deffn
  4457. @deffn {Command} {flash write_bank} num filename [offset]
  4458. Write the binary @file{filename} to flash bank @var{num},
  4459. starting at @var{offset} bytes from the beginning of the bank. If @var{offset}
  4460. is omitted, start at the beginning of the flash bank.
  4461. The @var{num} parameter is a value shown by @command{flash banks}.
  4462. @end deffn
  4463. @deffn {Command} {flash read_bank} num filename [offset [length]]
  4464. Read @var{length} bytes from the flash bank @var{num} starting at @var{offset}
  4465. and write the contents to the binary @file{filename}. If @var{offset} is
  4466. omitted, start at the beginning of the flash bank. If @var{length} is omitted,
  4467. read the remaining bytes from the flash bank.
  4468. The @var{num} parameter is a value shown by @command{flash banks}.
  4469. @end deffn
  4470. @deffn {Command} {flash verify_bank} num filename [offset]
  4471. Compare the contents of the binary file @var{filename} with the contents of the
  4472. flash bank @var{num} starting at @var{offset}. If @var{offset} is omitted,
  4473. start at the beginning of the flash bank. Fail if the contents do not match.
  4474. The @var{num} parameter is a value shown by @command{flash banks}.
  4475. @end deffn
  4476. @deffn {Command} {flash write_image} [erase] [unlock] filename [offset] [type]
  4477. Write the image @file{filename} to the current target's flash bank(s).
  4478. Only loadable sections from the image are written.
  4479. A relocation @var{offset} may be specified, in which case it is added
  4480. to the base address for each section in the image.
  4481. The file [@var{type}] can be specified
  4482. explicitly as @option{bin} (binary), @option{ihex} (Intel hex),
  4483. @option{elf} (ELF file), @option{s19} (Motorola s19).
  4484. @option{mem}, or @option{builder}.
  4485. The relevant flash sectors will be erased prior to programming
  4486. if the @option{erase} parameter is given. If @option{unlock} is
  4487. provided, then the flash banks are unlocked before erase and
  4488. program. The flash bank to use is inferred from the address of
  4489. each image section.
  4490. @quotation Warning
  4491. Be careful using the @option{erase} flag when the flash is holding
  4492. data you want to preserve.
  4493. Portions of the flash outside those described in the image's
  4494. sections might be erased with no notice.
  4495. @itemize
  4496. @item
  4497. When a section of the image being written does not fill out all the
  4498. sectors it uses, the unwritten parts of those sectors are necessarily
  4499. also erased, because sectors can't be partially erased.
  4500. @item
  4501. Data stored in sector "holes" between image sections are also affected.
  4502. For example, "@command{flash write_image erase ...}" of an image with
  4503. one byte at the beginning of a flash bank and one byte at the end
  4504. erases the entire bank -- not just the two sectors being written.
  4505. @end itemize
  4506. Also, when flash protection is important, you must re-apply it after
  4507. it has been removed by the @option{unlock} flag.
  4508. @end quotation
  4509. @end deffn
  4510. @deffn {Command} {flash verify_image} filename [offset] [type]
  4511. Verify the image @file{filename} to the current target's flash bank(s).
  4512. Parameters follow the description of 'flash write_image'.
  4513. In contrast to the 'verify_image' command, for banks with specific
  4514. verify method, that one is used instead of the usual target's read
  4515. memory methods. This is necessary for flash banks not readable by
  4516. ordinary memory reads.
  4517. This command gives only an overall good/bad result for each bank, not
  4518. addresses of individual failed bytes as it's intended only as quick
  4519. check for successful programming.
  4520. @end deffn
  4521. @section Other Flash commands
  4522. @cindex flash protection
  4523. @deffn {Command} {flash erase_check} num
  4524. Check erase state of sectors in flash bank @var{num},
  4525. and display that status.
  4526. The @var{num} parameter is a value shown by @command{flash banks}.
  4527. @end deffn
  4528. @deffn {Command} {flash info} num [sectors]
  4529. Print info about flash bank @var{num}, a list of protection blocks
  4530. and their status. Use @option{sectors} to show a list of sectors instead.
  4531. The @var{num} parameter is a value shown by @command{flash banks}.
  4532. This command will first query the hardware, it does not print cached
  4533. and possibly stale information.
  4534. @end deffn
  4535. @anchor{flashprotect}
  4536. @deffn {Command} {flash protect} num first last (@option{on}|@option{off})
  4537. Enable (@option{on}) or disable (@option{off}) protection of flash blocks
  4538. in flash bank @var{num}, starting at protection block @var{first}
  4539. and continuing up to and including @var{last}.
  4540. Providing a @var{last} block of @option{last}
  4541. specifies "to the end of the flash bank".
  4542. The @var{num} parameter is a value shown by @command{flash banks}.
  4543. The protection block is usually identical to a flash sector.
  4544. Some devices may utilize a protection block distinct from flash sector.
  4545. See @command{flash info} for a list of protection blocks.
  4546. @end deffn
  4547. @deffn {Command} {flash padded_value} num value
  4548. Sets the default value used for padding any image sections, This should
  4549. normally match the flash bank erased value. If not specified by this
  4550. command or the flash driver then it defaults to 0xff.
  4551. @end deffn
  4552. @anchor{program}
  4553. @deffn {Command} {program} filename [preverify] [verify] [reset] [exit] [offset]
  4554. This is a helper script that simplifies using OpenOCD as a standalone
  4555. programmer. The only required parameter is @option{filename}, the others are optional.
  4556. @xref{Flash Programming}.
  4557. @end deffn
  4558. @anchor{flashdriverlist}
  4559. @section Flash Driver List
  4560. As noted above, the @command{flash bank} command requires a driver name,
  4561. and allows driver-specific options and behaviors.
  4562. Some drivers also activate driver-specific commands.
  4563. @deffn {Flash Driver} {virtual}
  4564. This is a special driver that maps a previously defined bank to another
  4565. address. All bank settings will be copied from the master physical bank.
  4566. The @var{virtual} driver defines one mandatory parameters,
  4567. @itemize
  4568. @item @var{master_bank} The bank that this virtual address refers to.
  4569. @end itemize
  4570. So in the following example addresses 0xbfc00000 and 0x9fc00000 refer to
  4571. the flash bank defined at address 0x1fc00000. Any command executed on
  4572. the virtual banks is actually performed on the physical banks.
  4573. @example
  4574. flash bank $_FLASHNAME pic32mx 0x1fc00000 0 0 0 $_TARGETNAME
  4575. flash bank vbank0 virtual 0xbfc00000 0 0 0 \
  4577. flash bank vbank1 virtual 0x9fc00000 0 0 0 \
  4579. @end example
  4580. @end deffn
  4581. @subsection External Flash
  4582. @deffn {Flash Driver} {cfi}
  4583. @cindex Common Flash Interface
  4584. @cindex CFI
  4585. The ``Common Flash Interface'' (CFI) is the main standard for
  4586. external NOR flash chips, each of which connects to a
  4587. specific external chip select on the CPU.
  4588. Frequently the first such chip is used to boot the system.
  4589. Your board's @code{reset-init} handler might need to
  4590. configure additional chip selects using other commands (like: @command{mww} to
  4591. configure a bus and its timings), or
  4592. perhaps configure a GPIO pin that controls the ``write protect'' pin
  4593. on the flash chip.
  4594. The CFI driver can use a target-specific working area to significantly
  4595. speed up operation.
  4596. The CFI driver can accept the following optional parameters, in any order:
  4597. @itemize
  4598. @item @var{jedec_probe} ... is used to detect certain non-CFI flash ROMs,
  4599. like AM29LV010 and similar types.
  4600. @item @var{x16_as_x8} ... when a 16-bit flash is hooked up to an 8-bit bus.
  4601. @item @var{bus_swap} ... when data bytes in a 16-bit flash needs to be swapped.
  4602. @item @var{data_swap} ... when data bytes in a 16-bit flash needs to be
  4603. swapped when writing data values (i.e. not CFI commands).
  4604. @end itemize
  4605. To configure two adjacent banks of 16 MBytes each, both sixteen bits (two bytes)
  4606. wide on a sixteen bit bus:
  4607. @example
  4608. flash bank $_FLASHNAME cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
  4609. flash bank $_FLASHNAME cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
  4610. @end example
  4611. To configure one bank of 32 MBytes
  4612. built from two sixteen bit (two byte) wide parts wired in parallel
  4613. to create a thirty-two bit (four byte) bus with doubled throughput:
  4614. @example
  4615. flash bank $_FLASHNAME cfi 0x00000000 0x02000000 2 4 $_TARGETNAME
  4616. @end example
  4617. @c "cfi part_id" disabled
  4618. @end deffn
  4619. @deffn {Flash Driver} {jtagspi}
  4620. @cindex Generic JTAG2SPI driver
  4621. @cindex SPI
  4622. @cindex jtagspi
  4623. @cindex bscan_spi
  4624. Several FPGAs and CPLDs can retrieve their configuration (bitstream) from a
  4625. SPI flash connected to them. To access this flash from the host, the device
  4626. is first programmed with a special proxy bitstream that
  4627. exposes the SPI flash on the device's JTAG interface. The flash can then be
  4628. accessed through JTAG.
  4629. Since signaling between JTAG and SPI is compatible, all that is required for
  4630. a proxy bitstream is to connect TDI-MOSI, TDO-MISO, TCK-CLK and activate
  4631. the flash chip select when the JTAG state machine is in SHIFT-DR. Such
  4632. a bitstream for several Xilinx FPGAs can be found in
  4633. @file{contrib/loaders/flash/fpga/}. It requires
  4634. @uref{, migen} and a Xilinx toolchain to build.
  4635. This flash bank driver requires a target on a JTAG tap and will access that
  4636. tap directly. Since no support from the target is needed, the target can be a
  4637. "testee" dummy. Since the target does not expose the flash memory
  4638. mapping, target commands that would otherwise be expected to access the flash
  4639. will not work. These include all @command{*_image} and
  4640. @command{$target_name m*} commands as well as @command{program}. Equivalent
  4641. functionality is available through the @command{flash write_bank},
  4642. @command{flash read_bank}, and @command{flash verify_bank} commands.
  4643. @itemize
  4644. @item @var{ir} ... is loaded into the JTAG IR to map the flash as the JTAG DR.
  4645. For the bitstreams generated from @file{} this is the
  4646. @var{USER1} instruction.
  4647. @end itemize
  4648. @example
  4649. target create $_TARGETNAME testee -chain-position $_CHIPNAME.fpga
  4650. set _XILINX_USER1 0x02
  4651. flash bank $_FLASHNAME spi 0x0 0 0 0 \
  4653. @end example
  4654. @end deffn
  4655. @deffn {Flash Driver} {xcf}
  4656. @cindex Xilinx Platform flash driver
  4657. @cindex xcf
  4658. Xilinx FPGAs can be configured from specialized flash ICs named Platform Flash.
  4659. It is (almost) regular NOR flash with erase sectors, program pages, etc. The
  4660. only difference is special registers controlling its FPGA specific behavior.
  4661. They must be properly configured for successful FPGA loading using
  4662. additional @var{xcf} driver command:
  4663. @deffn {Command} {xcf ccb} <bank_id>
  4664. command accepts additional parameters:
  4665. @itemize
  4666. @item @var{external|internal} ... selects clock source.
  4667. @item @var{serial|parallel} ... selects serial or parallel data bus mode.
  4668. @item @var{slave|master} ... selects slave of master mode for flash device.
  4669. @item @var{40|20} ... selects clock frequency in MHz for internal clock
  4670. in master mode.
  4671. @end itemize
  4672. @example
  4673. xcf ccb 0 external parallel slave 40
  4674. @end example
  4675. All of them must be specified even if clock frequency is pointless
  4676. in slave mode. If only bank id specified than command prints current
  4677. CCB register value. Note: there is no need to write this register
  4678. every time you erase/program data sectors because it stores in
  4679. dedicated sector.
  4680. @end deffn
  4681. @deffn {Command} {xcf configure} <bank_id>
  4682. Initiates FPGA loading procedure. Useful if your board has no "configure"
  4683. button.
  4684. @example
  4685. xcf configure 0
  4686. @end example
  4687. @end deffn
  4688. Additional driver notes:
  4689. @itemize
  4690. @item Only single revision supported.
  4691. @item Driver automatically detects need of bit reverse, but
  4692. only "bin" (raw binary, do not confuse it with "bit") and "mcs"
  4693. (Intel hex) file types supported.
  4694. @item For additional info check xapp972.pdf and ug380.pdf.
  4695. @end itemize
  4696. @end deffn
  4697. @deffn {Flash Driver} {lpcspifi}
  4698. @cindex NXP SPI Flash Interface
  4699. @cindex SPIFI
  4700. @cindex lpcspifi
  4701. NXP's LPC43xx and LPC18xx families include a proprietary SPI
  4702. Flash Interface (SPIFI) peripheral that can drive and provide
  4703. memory mapped access to external SPI flash devices.
  4704. The lpcspifi driver initializes this interface and provides
  4705. program and erase functionality for these serial flash devices.
  4706. Use of this driver @b{requires} a working area of at least 1kB
  4707. to be configured on the target device; more than this will
  4708. significantly reduce flash programming times.
  4709. The setup command only requires the @var{base} parameter. All
  4710. other parameters are ignored, and the flash size and layout
  4711. are configured by the driver.
  4712. @example
  4713. flash bank $_FLASHNAME lpcspifi 0x14000000 0 0 0 $_TARGETNAME
  4714. @end example
  4715. @end deffn
  4716. @deffn {Flash Driver} {stmsmi}
  4717. @cindex STMicroelectronics Serial Memory Interface
  4718. @cindex SMI
  4719. @cindex stmsmi
  4720. Some devices from STMicroelectronics (e.g. STR75x MCU family,
  4721. SPEAr MPU family) include a proprietary
  4722. ``Serial Memory Interface'' (SMI) controller able to drive external
  4723. SPI flash devices.
  4724. Depending on specific device and board configuration, up to 4 external
  4725. flash devices can be connected.
  4726. SMI makes the flash content directly accessible in the CPU address
  4727. space; each external device is mapped in a memory bank.
  4728. CPU can directly read data, execute code and boot from SMI banks.
  4729. Normal OpenOCD commands like @command{mdw} can be used to display
  4730. the flash content.
  4731. The setup command only requires the @var{base} parameter in order
  4732. to identify the memory bank.
  4733. All other parameters are ignored. Additional information, like
  4734. flash size, are detected automatically.
  4735. @example
  4736. flash bank $_FLASHNAME stmsmi 0xf8000000 0 0 0 $_TARGETNAME
  4737. @end example
  4738. @end deffn
  4739. @deffn {Flash Driver} {stmqspi}
  4740. @cindex STMicroelectronics QuadSPI/OctoSPI Interface
  4741. @cindex QuadSPI
  4742. @cindex OctoSPI
  4743. @cindex stmqspi
  4744. Some devices from STMicroelectronics include a proprietary ``QuadSPI Interface''
  4745. (e.g. STM32F4, STM32F7, STM32L4) or ``OctoSPI Interface'' (e.g. STM32L4+)
  4746. controller able to drive one or even two (dual mode) external SPI flash devices.
  4747. The OctoSPI is a superset of QuadSPI, its presence is detected automatically.
  4748. Currently only the regular command mode is supported, whereas the HyperFlash
  4749. mode is not.
  4750. QuadSPI/OctoSPI makes the flash contents directly accessible in the CPU address
  4751. space; in case of dual mode both devices must be of the same type and are
  4752. mapped in the same memory bank (even and odd addresses interleaved).
  4753. CPU can directly read data, execute code (but not boot) from QuadSPI bank.
  4754. The 'flash bank' command only requires the @var{base} parameter and the extra
  4755. parameter @var{io_base} in order to identify the memory bank. Both are fixed
  4756. by hardware, see datasheet or RM. All other parameters are ignored.
  4757. The controller must be initialized after each reset and properly configured
  4758. for memory-mapped read operation for the particular flash chip(s), for the full
  4759. list of available register settings cf. the controller's RM. This setup is quite
  4760. board specific (that's why booting from this memory is not possible). The
  4761. flash driver infers all parameters from current controller register values when
  4762. 'flash probe @var{bank_id}' is executed.
  4763. Normal OpenOCD commands like @command{mdw} can be used to display the flash content,
  4764. but only after proper controller initialization as described above. However,
  4765. due to a silicon bug in some devices, attempting to access the very last word
  4766. should be avoided.
  4767. It is possible to use two (even different) flash chips alternatingly, if individual
  4768. bank chip selects are available. For some package variants, this is not the case
  4769. due to limited pin count. To switch from one to another, adjust FSEL bit accordingly
  4770. and re-issue 'flash probe bank_id'. Note that the bank base address will @emph{not}
  4771. change, so the address spaces of both devices will overlap. In dual flash mode
  4772. both chips must be identical regarding size and most other properties.
  4773. Block or sector protection internal to the flash chip is not handled by this
  4774. driver at all, but can be dealt with manually by the 'cmd' command, see below.
  4775. The sector protection via 'flash protect' command etc. is completely internal to
  4776. openocd, intended only to prevent accidental erase or overwrite and it does not
  4777. persist across openocd invocations.
  4778. OpenOCD contains a hardcoded list of flash devices with their properties,
  4779. these are auto-detected. If a device is not included in this list, SFDP discovery
  4780. is attempted. If this fails or gives inappropriate results, manual setting is
  4781. required (see 'set' command).
  4782. @example
  4783. flash bank $_FLASHNAME stmqspi 0x90000000 0 0 0 \
  4784. $_TARGETNAME 0xA0001000
  4785. flash bank $_FLASHNAME stmqspi 0x70000000 0 0 0 \
  4786. $_TARGETNAME 0xA0001400
  4787. @end example
  4788. There are three specific commands
  4789. @deffn {Command} {stmqspi mass_erase} bank_id
  4790. Clears sector protections and performs a mass erase. Works only if there is no
  4791. chip specific write protection engaged.
  4792. @end deffn
  4793. @deffn {Command} {stmqspi set} bank_id name total_size page_size read_cmd fread_cmd pprg_cmd mass_erase_cmd sector_size sector_erase_cmd
  4794. Set flash parameters: @var{name} human readable string, @var{total_size} size
  4795. in bytes, @var{page_size} is write page size. @var{read_cmd}, @var{fread_cmd} and @var{pprg_cmd}
  4796. are commands for reading and page programming. @var{fread_cmd} is used in DPI and QPI modes,
  4797. @var{read_cmd} in normal SPI (single line) mode. @var{mass_erase_cmd}, @var{sector_size}
  4798. and @var{sector_erase_cmd} are optional.
  4799. This command is required if chip id is not hardcoded yet and e.g. for EEPROMs or FRAMs
  4800. which don't support an id command.
  4801. In dual mode parameters of both chips are set identically. The parameters refer to
  4802. a single chip, so the whole bank gets twice the specified capacity etc.
  4803. @end deffn
  4804. @deffn {Command} {stmqspi cmd} bank_id resp_num cmd_byte ...
  4805. If @var{resp_num} is zero, sends command @var{cmd_byte} and following data
  4806. bytes. In dual mode command byte is sent to @emph{both} chips but data bytes are
  4807. sent @emph{alternatingly} to chip 1 and 2, first to flash 1, second to flash 2, etc.,
  4808. i.e. the total number of bytes (including cmd_byte) must be odd.
  4809. If @var{resp_num} is not zero, cmd and at most four following data bytes are
  4810. sent, in dual mode @emph{simultaneously} to both chips. Then @var{resp_num} bytes
  4811. are read interleaved from both chips starting with chip 1. In this case
  4812. @var{resp_num} must be even.
  4813. Note the hardware dictated subtle difference of those two cases in dual-flash mode.
  4814. To check basic communication settings, issue
  4815. @example
  4816. stmqspi cmd bank_id 0 0x04; stmqspi cmd bank_id 1 0x05
  4817. stmqspi cmd bank_id 0 0x06; stmqspi cmd bank_id 1 0x05
  4818. @end example
  4819. for single flash mode or
  4820. @example
  4821. stmqspi cmd bank_id 0 0x04; stmqspi cmd bank_id 2 0x05
  4822. stmqspi cmd bank_id 0 0x06; stmqspi cmd bank_id 2 0x05
  4823. @end example
  4824. for dual flash mode. This should return the status register contents.
  4825. In 8-line mode, @var{cmd_byte} is sent twice - first time as given, second time
  4826. complemented. Additionally, in 8-line mode only, some commands (e.g. Read Status)
  4827. need a dummy address, e.g.
  4828. @example
  4829. stmqspi cmd bank_id 1 0x05 0x00 0x00 0x00 0x00
  4830. @end example
  4831. should return the status register contents.
  4832. @end deffn
  4833. @end deffn
  4834. @deffn {Flash Driver} {mrvlqspi}
  4835. This driver supports QSPI flash controller of Marvell's Wireless
  4836. Microcontroller platform.
  4837. The flash size is autodetected based on the table of known JEDEC IDs
  4838. hardcoded in the OpenOCD sources.
  4839. @example
  4840. flash bank $_FLASHNAME mrvlqspi 0x0 0 0 0 $_TARGETNAME 0x46010000
  4841. @end example
  4842. @end deffn
  4843. @deffn {Flash Driver} {ath79}
  4844. @cindex Atheros ath79 SPI driver
  4845. @cindex ath79
  4846. Members of ATH79 SoC family from Atheros include a SPI interface with 3
  4847. chip selects.
  4848. On reset a SPI flash connected to the first chip select (CS0) is made
  4849. directly read-accessible in the CPU address space (up to 16MBytes)
  4850. and is usually used to store the bootloader and operating system.
  4851. Normal OpenOCD commands like @command{mdw} can be used to display
  4852. the flash content while it is in memory-mapped mode (only the first
  4853. 4MBytes are accessible without additional configuration on reset).
  4854. The setup command only requires the @var{base} parameter in order
  4855. to identify the memory bank. The actual value for the base address
  4856. is not otherwise used by the driver. However the mapping is passed
  4857. to gdb. Thus for the memory mapped flash (chipselect CS0) the base
  4858. address should be the actual memory mapped base address. For unmapped
  4859. chipselects (CS1 and CS2) care should be taken to use a base address
  4860. that does not overlap with real memory regions.
  4861. Additional information, like flash size, are detected automatically.
  4862. An optional additional parameter sets the chipselect for the bank,
  4863. with the default CS0.
  4864. CS1 and CS2 require additional GPIO setup before they can be used
  4865. since the alternate function must be enabled on the GPIO pin
  4866. CS1/CS2 is routed to on the given SoC.
  4867. @example
  4868. flash bank $_FLASHNAME ath79 0xbf000000 0 0 0 $_TARGETNAME
  4869. # When using multiple chipselects the base should be different
  4870. # for each, otherwise the write_image command is not able to
  4871. # distinguish the banks.
  4872. flash bank flash0 ath79 0xbf000000 0 0 0 $_TARGETNAME cs0
  4873. flash bank flash1 ath79 0x10000000 0 0 0 $_TARGETNAME cs1
  4874. flash bank flash2 ath79 0x20000000 0 0 0 $_TARGETNAME cs2
  4875. @end example
  4876. @end deffn
  4877. @deffn {Flash Driver} {fespi}
  4878. @cindex Freedom E SPI
  4879. @cindex fespi
  4880. SiFive's Freedom E SPI controller, used in HiFive and other boards.
  4881. @example
  4882. flash bank $_FLASHNAME fespi 0x20000000 0 0 0 $_TARGETNAME
  4883. @end example
  4884. @end deffn
  4885. @subsection Internal Flash (Microcontrollers)
  4886. @deffn {Flash Driver} {aduc702x}
  4887. The ADUC702x analog microcontrollers from Analog Devices
  4888. include internal flash and use ARM7TDMI cores.
  4889. The aduc702x flash driver works with models ADUC7019 through ADUC7028.
  4890. The setup command only requires the @var{target} argument
  4891. since all devices in this family have the same memory layout.
  4892. @example
  4893. flash bank $_FLASHNAME aduc702x 0 0 0 0 $_TARGETNAME
  4894. @end example
  4895. @end deffn
  4896. @deffn {Flash Driver} {ambiqmicro}
  4897. @cindex ambiqmicro
  4898. @cindex apollo
  4899. All members of the Apollo microcontroller family from
  4900. Ambiq Micro include internal flash and use ARM's Cortex-M4 core.
  4901. The host connects over USB to an FTDI interface that communicates
  4902. with the target using SWD.
  4903. The @var{ambiqmicro} driver reads the Chip Information Register detect
  4904. the device class of the MCU.
  4905. The Flash and SRAM sizes directly follow device class, and are used
  4906. to set up the flash banks.
  4907. If this fails, the driver will use default values set to the minimum
  4908. sizes of an Apollo chip.
  4909. All Apollo chips have two flash banks of the same size.
  4910. In all cases the first flash bank starts at location 0,
  4911. and the second bank starts after the first.
  4912. @example
  4913. # Flash bank 0
  4914. flash bank $_FLASHNAME ambiqmicro 0 0x00040000 0 0 $_TARGETNAME
  4915. # Flash bank 1 - same size as bank0, starts after bank 0.
  4916. flash bank $_FLASHNAME ambiqmicro 0x00040000 0x00040000 0 0 \
  4917. $_TARGETNAME
  4918. @end example
  4919. Flash is programmed using custom entry points into the bootloader.
  4920. This is the only way to program the flash as no flash control registers
  4921. are available to the user.
  4922. The @var{ambiqmicro} driver adds some additional commands:
  4923. @deffn {Command} {ambiqmicro mass_erase} <bank>
  4924. Erase entire bank.
  4925. @end deffn
  4926. @deffn {Command} {ambiqmicro page_erase} <bank> <first> <last>
  4927. Erase device pages.
  4928. @end deffn
  4929. @deffn {Command} {ambiqmicro program_otp} <bank> <offset> <count>
  4930. Program OTP is a one time operation to create write protected flash.
  4931. The user writes sectors to SRAM starting at 0x10000010.
  4932. Program OTP will write these sectors from SRAM to flash, and write protect
  4933. the flash.
  4934. @end deffn
  4935. @end deffn
  4936. @anchor{at91samd}
  4937. @deffn {Flash Driver} {at91samd}
  4938. @cindex at91samd
  4939. All members of the ATSAM D2x, D1x, D0x, ATSAMR, ATSAML and ATSAMC microcontroller
  4940. families from Atmel include internal flash and use ARM's Cortex-M0+ core.
  4941. Do not use for ATSAM D51 and E5x: use @xref{atsame5}.
  4942. The devices have one flash bank:
  4943. @example
  4944. flash bank $_FLASHNAME at91samd 0x00000000 0 1 1 $_TARGETNAME
  4945. @end example
  4946. @deffn {Command} {at91samd chip-erase}
  4947. Issues a complete Flash erase via the Device Service Unit (DSU). This can be
  4948. used to erase a chip back to its factory state and does not require the
  4949. processor to be halted.
  4950. @end deffn
  4951. @deffn {Command} {at91samd set-security}
  4952. Secures the Flash via the Set Security Bit (SSB) command. This prevents access
  4953. to the Flash and can only be undone by using the chip-erase command which
  4954. erases the Flash contents and turns off the security bit. Warning: at this
  4955. time, openocd will not be able to communicate with a secured chip and it is
  4956. therefore not possible to chip-erase it without using another tool.
  4957. @example
  4958. at91samd set-security enable
  4959. @end example
  4960. @end deffn
  4961. @deffn {Command} {at91samd eeprom}
  4962. Shows or sets the EEPROM emulation size configuration, stored in the User Row
  4963. of the Flash. When setting, the EEPROM size must be specified in bytes and it
  4964. must be one of the permitted sizes according to the datasheet. Settings are
  4965. written immediately but only take effect on MCU reset. EEPROM emulation
  4966. requires additional firmware support and the minimum EEPROM size may not be
  4967. the same as the minimum that the hardware supports. Set the EEPROM size to 0
  4968. in order to disable this feature.
  4969. @example
  4970. at91samd eeprom
  4971. at91samd eeprom 1024
  4972. @end example
  4973. @end deffn
  4974. @deffn {Command} {at91samd bootloader}
  4975. Shows or sets the bootloader size configuration, stored in the User Row of the
  4976. Flash. This is called the BOOTPROT region. When setting, the bootloader size
  4977. must be specified in bytes and it must be one of the permitted sizes according
  4978. to the datasheet. Settings are written immediately but only take effect on
  4979. MCU reset. Setting the bootloader size to 0 disables bootloader protection.
  4980. @example
  4981. at91samd bootloader
  4982. at91samd bootloader 16384
  4983. @end example
  4984. @end deffn
  4985. @deffn {Command} {at91samd dsu_reset_deassert}
  4986. This command releases internal reset held by DSU
  4987. and prepares reset vector catch in case of reset halt.
  4988. Command is used internally in event reset-deassert-post.
  4989. @end deffn
  4990. @deffn {Command} {at91samd nvmuserrow}
  4991. Writes or reads the entire 64 bit wide NVM user row register which is located at
  4992. 0x804000. This register includes various fuses lock-bits and factory calibration
  4993. data. Reading the register is done by invoking this command without any
  4994. arguments. Writing is possible by giving 1 or 2 hex values. The first argument
  4995. is the register value to be written and the second one is an optional changemask.
  4996. Every bit which value in changemask is 0 will stay unchanged. The lock- and
  4997. reserved-bits are masked out and cannot be changed.
  4998. @example
  4999. # Read user row
  5000. >at91samd nvmuserrow
  5002. # Write 0xFFFFFC5DD8E0C788 to user row
  5003. >at91samd nvmuserrow 0xFFFFFC5DD8E0C788
  5004. # Write 0x12300 to user row but leave other bits and low
  5005. # byte unchanged
  5006. >at91samd nvmuserrow 0x12345 0xFFF00
  5007. @end example
  5008. @end deffn
  5009. @end deffn
  5010. @anchor{at91sam3}
  5011. @deffn {Flash Driver} {at91sam3}
  5012. @cindex at91sam3
  5013. All members of the AT91SAM3 microcontroller family from
  5014. Atmel include internal flash and use ARM's Cortex-M3 core. The driver
  5015. currently (6/22/09) recognizes the AT91SAM3U[1/2/4][C/E] chips. Note
  5016. that the driver was orginaly developed and tested using the
  5017. AT91SAM3U4E, using a SAM3U-EK eval board. Support for other chips in
  5018. the family was cribbed from the data sheet. @emph{Note to future
  5019. readers/updaters: Please remove this worrisome comment after other
  5020. chips are confirmed.}
  5021. The AT91SAM3U4[E/C] (256K) chips have two flash banks; most other chips
  5022. have one flash bank. In all cases the flash banks are at
  5023. the following fixed locations:
  5024. @example
  5025. # Flash bank 0 - all chips
  5026. flash bank $_FLASHNAME at91sam3 0x00080000 0 1 1 $_TARGETNAME