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63 lines
1.7 KiB

  1. # imx31 config
  2. #
  3. reset_config trst_and_srst
  4. if { [info exists CHIPNAME] } {
  5. set _CHIPNAME $CHIPNAME
  6. } else {
  7. set _CHIPNAME imx31
  8. }
  9. if { [info exists ENDIAN] } {
  10. set _ENDIAN $ENDIAN
  11. } else {
  12. set _ENDIAN little
  13. }
  14. if { [info exists CPUTAPID ] } {
  15. set _CPUTAPID $CPUTAPID
  16. } else {
  17. set _CPUTAPID 0x07b3601d
  18. }
  19. if { [info exists SDMATAPID ] } {
  20. set _SDMATAPID $SDMATAPID
  21. } else {
  22. set _SDMATAPID 0x2190101d
  23. }
  24. #========================================
  25. # The "system jtag controller"
  26. # IMX31 reference manual, page 6-28 - figure 6-14
  27. if { [info exists SJCTAPID ] } {
  28. set _SJCTAPID $SJCTAPID
  29. } else {
  30. set _SJCTAPID 0x2b900f0f
  31. }
  32. jtag newtap $_CHIPNAME sjc -irlen 4 -ircapture 0x0 -irmask 0x0 -expected-id $_SJCTAPID
  33. # The "SDMA" - <S>mart <DMA> controller debug tap
  34. # Based on some IO pins - this can be disabled & removed
  35. # See diagram: 6-14
  36. # SIGNAL NAME:
  37. # SJC_MOD - controls multiplexer - disables ARM1136
  38. # SDMA_BYPASS - disables SDMA -
  39. #
  40. # Per ARM: DDI0211J_arm1136_r1p5_trm.pdf - the ARM 1136 as a 5 bit IR register
  41. jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
  42. # No IDCODE for this TAP
  43. jtag newtap $_CHIPNAME whatchacallit -irlen 4 -ircapture 0 -irmask 0xf -expected-id 0x0
  44. # Per section 40.17.1, table 40-85 the IR register is 4 bits
  45. # But this conflicts with Diagram 6-13, "3bits ir and drs"
  46. jtag newtap $_CHIPNAME smda -irlen 5 -ircapture 0x1 -irmask 0xf -expected-id $_SDMATAPID
  47. set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
  48. target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME
  49. proc power_restore {} { puts "Sensed power restore. No action." }
  50. proc srst_deasserted {} { puts "Sensed nSRST deasserted. No action." }