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  1. \input texinfo @c -*-texinfo-*-
  2. @c %**start of header
  3. @setfilename
  4. @settitle Open On-Chip Debugger (openocd)
  5. @c %**end of header
  6. @titlepage
  7. @title Open On-Chip Debugger (openocd)
  8. @page
  9. @vskip 0pt plus 1filll
  10. @end titlepage
  11. @contents
  12. @node Top, About, , (dir)
  13. @top OpenOCD
  14. The Manual always document the latest version of OpenOCD available from SVN.
  15. @menu
  16. * About:: About Openocd.
  17. * Developers::
  18. * Building:: Building Openocd
  19. * Running:: Running Openocd
  20. * Configuration:: Openocd Configuration.
  21. * Commands:: Openocd Commands
  22. * Sample Scripts:: Sample Target Scripts
  23. * FAQ:: Frequently Asked Questions
  24. * License:: GNU Free Documentation License
  25. * Index:: Main index.
  26. @end menu
  27. @node About
  28. @unnumbered About
  29. @cindex about
  30. The Open On-Chip Debugger (openocd) aims to provide debugging, in-system programming
  31. and boundary-scan testing for embedded target devices. The targets are interfaced
  32. using JTAG (IEEE 1149.1) compliant hardware, but this may be extended to other
  33. connection types in the future.
  34. Openocd currently supports Wiggler (clones), FTDI FT2232 based JTAG interfaces, the
  35. Amontec JTAG Accelerator, and the Gateworks GW1602. It allows ARM7 (ARM7TDMI and ARM720t),
  36. ARM9 (ARM920t, ARM922t, ARM926ej--s, ARM966e--s), XScale (PXA25x, IXP42x) and
  37. Cortex-M3 (Luminary Stellaris LM3 and ST STM32) based cores to be debugged.
  38. Flash writing is supported for external CFI compatible flashes (Intel and AMD/Spansion
  39. command set) and several internal flashes (LPC2000, AT91SAM7, STR7x, STR9x, LM3
  40. and STM32x). Preliminary support for using the LPC3180's NAND flash controller is included.
  41. @node Developers
  42. @chapter Developers
  43. @cindex developers
  44. Openocd has been created by Dominic Rath as part of a diploma thesis written at the
  45. University of Applied Sciences Augsburg (@uref{}).
  46. Others interested in improving the state of free and open debug and testing technology
  47. are welcome to participate.
  48. Other developers have contributed support for additional targets and flashes as well
  49. as numerous bugfixes and enhancements. See the AUTHORS file for regular contributors.
  50. @node Building
  51. @chapter Building
  52. @cindex building openocd
  53. You can download the current SVN version with SVN client of your choice from the
  54. following repositories:
  55. (@uref{svn://}
  56. or
  57. (@uref{}
  58. Using the SVN command line client, you could use the following command to fetch the
  59. latest version (make sure there is no (non-svn) directory called "openocd" in the
  60. current directory):
  61. @smallexample
  62. svn checkout svn://
  63. @end smallexample
  64. Building the OpenOCD requires a recent version of the GNU autotools.
  65. On my build system, I'm using autoconf 2.13 and automake 1.9. For building on Windows,
  66. you have to use Cygwin. Make sure that your @env{PATH} environment variable contains no
  67. other locations with Unix utils (like UnxUtils) - these can't handle the Cygwin
  68. paths, resulting in obscure dependency errors (This is an observation I've gathered
  69. from the logs of one user - correct me if I'm wrong).
  70. You further need the appropriate driver files, if you want to build support for
  71. a FTDI FT2232 based interface:
  72. @itemize @bullet
  73. @item @b{ftdi2232} libftdi ((@uref{})
  74. @item @b{ftd2xx} libftd2xx ((@uref{})
  75. @item When using the Amontec JTAGkey, you have to get the drivers from the Amontec
  76. homepage (@uref{}), as the JTAGkey uses a non-standard VID/PID.
  77. @end itemize
  78. Please note that the ftdi2232 variant (using libftdi) isn't supported under Cygwin.
  79. You have to use the ftd2xx variant (using FTDI's D2XX) on Cygwin.
  80. In general, the D2XX driver provides superior performance (several times as fast),
  81. but has the draw-back of being binary-only - though that isn't as worse, as it isn't
  82. a kernel module, only a user space library.
  83. To build OpenOCD (on both Linux and Cygwin), use the following commands:
  84. @smallexample
  85. ./bootstrap
  86. @end smallexample
  87. Bootstrap generates the configure script, and prepares building on your system.
  88. @smallexample
  89. ./configure
  90. @end smallexample
  91. Configure generates the Makefiles used to build OpenOCD
  92. @smallexample
  93. make
  94. @end smallexample
  95. Make builds the OpenOCD, and places the final executable in ./src/
  96. The configure script takes several options, specifying which JTAG interfaces
  97. should be included:
  98. @itemize @bullet
  99. @item
  100. --enable-parport
  101. @item
  102. --enable-parport_ppdev
  103. @item
  104. --enable-amtjtagaccel
  105. @item
  106. --enable-ft2232_ftd2xx
  107. @footnote{Using the latest D2XX drivers from FTDI and following their installation
  108. instructions, I had to use @option{--enable-ft2232_libftd2xx} for the OpenOCD to
  109. build properly}
  110. @item
  111. --enable-ft2232_libftdi
  112. @item
  113. --with-ftd2xx=/path/to/d2xx/
  114. @end itemize
  115. If you want to access the parallel port using the PPDEV interface you have to specify
  116. both the @option{--enable-parport} AND the @option{--enable-parport_ppdev} option since
  117. the @option{--enable-parport_ppdev} option actually is an option to the parport driver
  118. (see (@uref{} for more info).
  119. Cygwin users have to specify the location of the FTDI D2XX package. This should be an
  120. absolute path containing no spaces.
  121. Linux users should copy the various parts of the D2XX package to the appropriate
  122. locations, i.e. /usr/include, /usr/lib.
  123. @node Running
  124. @chapter Running
  125. @cindex running openocd
  126. The OpenOCD runs as a daemon, waiting for connections from clients (Telnet or GDB).
  127. Run with @option{--help} or @option{-h} to view the available command line arguments.
  128. It reads its configuration by default from the file openocd.cfg located in the current
  129. working directory. This may be overwritten with the @option{-f <configfile>} command line
  130. switch.
  131. To enable debug output (when reporting problems or working on OpenOCD itself), use
  132. the @option{-d} command line switch. This sets the debug_level to "3", outputting
  133. the most information, including debug messages. The default setting is "2", outputting
  134. only informational messages, warnings and errors. You can also change this setting
  135. from within a telnet or gdb session (@option{debug_level <n>}).
  136. You can redirect all output from the daemon to a file using the @option{-l <logfile>} switch.
  137. @node Configuration
  138. @chapter Configuration
  139. @cindex configuration
  140. The Open On-Chip Debugger (OpenOCD) runs as a daemon, and reads it current configuration
  141. by default from the file openocd.cfg in the current directory. A different configuration
  142. file can be specified with the @option{-f <conf.file>} given at the openocd command line.
  143. The configuration file is used to specify on which ports the daemon listens for new
  144. connections, the JTAG interface used to connect to the target, the layout of the JTAG
  145. chain, the targets that should be debugged, and connected flashes.
  146. @section Daemon configuration
  147. @itemize @bullet
  148. @item @b{telnet_port} <@var{number}>
  149. @cindex telnet_port
  150. Port on which to listen for incoming telnet connections
  151. @item @b{gdb_port} <@var{number}>
  152. @cindex gdb_port
  153. First port on which to listen for incoming GDB connections. The GDB port for the
  154. first target will be gdb_port, the second target will listen on gdb_port + 1, and so on.
  155. @item @b{daemon_startup} <@var{mode}> either @samp{attach} or @samp{reset}
  156. @cindex daemon_startup
  157. Tells the OpenOCD whether it should reset the target when the daemon is launched, or
  158. if it should just attach to the target.
  159. @end itemize
  160. @section JTAG interface configuration
  161. @itemize @bullet
  162. @item @b{interface} <@var{name}>
  163. @cindex interface
  164. Use the interface driver <@var{name}> to connect to the target. Currently supported
  165. interfaces are
  166. @itemize @minus
  167. @item parport
  168. PC parallel port bit-banging (Wigglers, PLD download cable, ...)
  169. @end itemize
  170. @itemize @minus
  171. @item amt_jtagaccel
  172. Amontec Chameleon in its JTAG Accelerator configuration connected to a PC's EPP
  173. mode parallel port
  174. @end itemize
  175. @itemize @minus
  176. @item ft2232
  177. FTDI FT2232 based devices using either the open-source libftdi or the binary only
  178. FTD2XX driver. The FTD2XX is superior in performance, but not available on every
  179. platform. The libftdi uses libusb, and should be portable to all systems that provide
  180. libusb.
  181. @end itemize
  182. @itemize @minus
  183. @item ep93xx
  184. Cirrus Logic EP93xx based single-board computer bit-banging (in development)
  185. @end itemize
  186. @end itemize
  187. @itemize @bullet
  188. @item @b{jtag_speed} <@var{number}>
  189. @cindex jtag_speed
  190. Limit the maximum speed of the JTAG interface. Usually, a value of zero means maximum
  191. speed. The actual effect of this option depends on the JTAG interface used.
  192. @item @b{reset_config} <@var{signals}> [@var{combination}] [@var{trst_type}] [@var{srst_type}]
  193. @cindex reset_config
  194. The configuration of the reset signals available on the JTAG interface AND the target.
  195. If the JTAG interface provides SRST, but the target doesn't connect that signal properly,
  196. then OpenOCD can't use it. <@var{signals}> can be @samp{none}, @samp{trst_only},
  197. @samp{srst_only} or @samp{trst_and_srst}.
  198. [@var{combination}] is an optional value specifying broken reset signal implementations.
  199. @samp{srst_pulls_trst} states that the testlogic is reset together with the reset of
  200. the system (e.g. Philips LPC2000, "broken" board layout), @samp{trst_pulls_srst} says
  201. that the system is reset together with the test logic (only hypothetical, I haven't
  202. seen hardware with such a bug, and can be worked around).
  203. The [@var{trst_type}] and [@var{srst_type}] parameters allow the driver type of the
  204. reset lines to be specified. Possible values are @samp{trst_push_pull} (default)
  205. and @samp{trst_open_drain} for the test reset signal, and @samp{srst_open_drain}
  206. (default) and @samp{srst_push_pull} for the system reset. These values only affect
  207. JTAG interfaces with support for different drivers, like the Amontec JTAGkey and JTAGAccelerator.
  208. @item @b{jtag_device} <@var{IR length}> <@var{IR capture}> <@var{IR mask}> <@var{IDCODE instruction}>
  209. @cindex jtag_device
  210. Describes the devices that form the JTAG daisy chain, with the first device being
  211. the one closest to TDO. The parameters are the length of the instruction register
  212. (4 for all ARM7/9s), the value captured during Capture-IR (0x1 for ARM7/9), and a mask
  213. of bits that should be validated when doing IR scans (all four bits (0xf) for ARM7/9).
  214. The IDCODE instruction will in future be used to query devices for their JTAG
  215. identification code. This line is the same for all ARM7 and ARM9 devices.
  216. Other devices, like CPLDs, require different parameters. An example configuration
  217. line for a Xilinx XC9500 CPLD would look like this:
  218. @smallexample
  219. jtag_device 8 0x01 0x0e3 0xfe
  220. @end smallexample
  221. The instruction register (IR) is 8 bits long, during Capture-IR 0x01 is loaded into
  222. the IR, but only bits 0-1 and 5-7 should be checked, the others (2-4) might vary.
  223. The IDCODE instruction is 0xfe.
  224. @item @b{jtag_nsrst_delay} <@var{ms}>
  225. @cindex jtag_nsrst_delay
  226. How long (in miliseconds) the OpenOCD should wait after deasserting nSRST before
  227. starting new JTAG operations.
  228. @item @b{jtag_ntrst_delay} <@var{ms}>
  229. @cindex jtag_ntrst_delay
  230. How long (in miliseconds) the OpenOCD should wait after deasserting nTRST before
  231. starting new JTAG operations.
  232. The jtag_n[st]rst_delay options are useful if reset circuitry (like a reset supervisor,
  233. or on-chip features) keep a reset line asserted for some time after the external reset
  234. got deasserted.
  235. @end itemize
  236. @section parport options
  237. @itemize @bullet
  238. @item @b{parport_port} <@var{number}>
  239. @cindex parport_port
  240. Either the address of the I/O port (default: 0x378 for LPT1) or the number of
  241. the @file{/dev/parport} device
  242. When using PPDEV to access the parallel port, use the number of the parallel port:
  243. @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
  244. you may encounter a problem.
  245. @item @b{parport_cable} <@var{name}>
  246. @cindex parport_cable
  247. The layout of the parallel port cable used to connect to the target.
  248. Currently supported cables are
  249. @itemize @minus
  250. @item wiggler
  251. @cindex wiggler
  252. Original Wiggler layout, also supported by several clones, such
  253. as the Olimex ARM-JTAG
  254. @item old_amt_wiggler
  255. @cindex old_amt_wiggler
  256. The Wiggler configuration that comes with Amontec's Chameleon Programmer. The new
  257. version available from the website uses the original Wiggler layout ('@var{wiggler}')
  258. @item chameleon
  259. @cindex chameleon
  260. Describes the connection of the Amontec Chameleon's CPLD when operated in
  261. configuration mode. This is only used to program the Chameleon itself, not
  262. a connected target.
  263. @item dlc5
  264. @cindex dlc5
  265. Xilinx Parallel cable III.
  266. @item triton
  267. @cindex triton
  268. The parallel port adapter found on the 'Karo Triton 1 Development Board'.
  269. This is also the layout used by the HollyGates design
  270. (see @uref{}).
  271. @item flashlink
  272. @cindex flashlink
  273. ST Parallel cable.
  274. @end itemize
  275. @end itemize
  276. @section amt_jtagaccel options
  277. @itemize @bullet
  278. @item @b{parport_port} <@var{number}>
  279. @cindex parport_port
  280. Either the address of the I/O port (default: 0x378 for LPT1) or the number of the
  281. @file{/dev/parport} device
  282. @end itemize
  283. @section ft2232 options
  284. @itemize @bullet
  285. @item @b{ft2232_device_desc} <@var{description}>
  286. @cindex ft2232_device_desc
  287. The USB device description of the FTDI FT2232 device. If not specified, the FTDI
  288. default value is used. This setting is only valid if compiled with FTD2XX support.
  289. @item @b{ft2232_layout} <@var{name}>
  290. @cindex ft2232_layout
  291. The layout of the FT2232 GPIO signals used to control output-enables and reset
  292. signals. Valid layouts are
  293. @itemize @minus
  294. @item usbjtag
  295. The "USBJTAG-1" layout described in the original OpenOCD diploma thesis
  296. @item jtagkey
  297. Amontec JTAGkey and JTAGkey-tiny
  298. @item signalyzer
  299. Signalyzer
  300. @item olimex-jtag
  301. Olimex ARM-USB-OCD
  302. @item m5960
  303. American Microsystems M5960
  304. @item evb_lm3s811
  305. Luminary Micro EVB_LM3S811 as a JTAG interface (not onboard processor), no TRST or
  306. SRST signals on external connector
  307. @item comstick
  308. Hitex STR9 comstick
  309. @end itemize
  310. @item @b{ft2232_vid_pid} <@var{vid}> <@var{pid}>
  311. The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
  312. default values are used. This command is not available on Windows.
  313. @item @b{ft2232_latency} <@var{ms}>
  314. On some systems using ft2232 based JTAG interfaces the FT_Read function call in
  315. ft2232_read() fails to return the expected number of bytes. This can be caused by
  316. USB communication delays and has proved hard to reproduce and debug. Setting the
  317. FT2232 latency timer to a larger value increases delays for short USB packages but it
  318. also reduces the risk of timeouts before receiving the expected number of bytes.
  319. The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
  320. @end itemize
  321. @section ep93xx options
  322. @cindex ep93xx options
  323. Currently, there are no options available for the ep93xx interface.
  324. @page
  325. @section Target configuration
  326. @itemize @bullet
  327. @item @b{target} <@var{type}> <@var{endianess}> <@var{reset_mode}> <@var{JTAG pos}>
  328. <@var{variant}>
  329. @cindex target
  330. Defines a target that should be debugged. Currently supported types are:
  331. @itemize @minus
  332. @item arm7tdmi
  333. @item arm720t
  334. @item arm9tdmi
  335. @item arm920t
  336. @item arm922t
  337. @item arm926ejs
  338. @item arm966e
  339. @item cortex_m3
  340. @item xscale
  341. @end itemize
  342. If you want to use a target board that is not on this list, see Adding a new
  343. target board
  344. Endianess may be @option{little} or @option{big}.
  345. The reset_mode specifies what should happen to the target when a reset occurs:
  346. @itemize @minus
  347. @item reset_halt
  348. @cindex reset_halt
  349. Immediately request a target halt after reset. This allows targets to be debugged
  350. from the very first instruction. This is only possible with targets and JTAG
  351. interfaces that correctly implement the reset signals.
  352. @item reset_init
  353. @cindex reset_init
  354. Similar to @option{reset_halt}, but executes the script file defined to handle the
  355. 'reset' event for the target. Like @option{reset_halt} this only works with
  356. correct reset implementations.
  357. @item reset_run
  358. @cindex reset_run
  359. Simply let the target run after a reset.
  360. @item run_and_halt
  361. @cindex run_and_halt
  362. Let the target run for some time (default: 1s), and then request halt.
  363. @item run_and_init
  364. @cindex run_and_init
  365. A combination of @option{reset_init} and @option{run_and_halt}. The target is allowed
  366. to run for some time, then halted, and the @option{reset} event script is executed.
  367. @end itemize
  368. On JTAG interfaces / targets where system reset and test-logic reset can't be driven
  369. completely independent (like the LPC2000 series), or where the JTAG interface is
  370. unavailable for some time during startup (like the STR7 series), you can't use
  371. @option{reset_halt} or @option{reset_init}.
  372. @item @b{target_script} <@var{target#}> <@var{event}> <@var{script_file}>
  373. @cindex target_script
  374. Event is either @var{reset} or @var{post_halt} or @var{pre_resume}.
  375. TODO: describe exact semantic of events
  376. @item @b{run_and_halt_time} <@var{target#}> <@var{time_in_ms}>
  377. @cindex run_and_halt_time
  378. The amount of time the debugger should wait after releasing reset before it asserts
  379. a debug request. This is used by the @option{run_and_halt} and @option{run_and_init}
  380. reset modes.
  381. @item @b{working_area} <@var{target#}> <@var{address}> <@var{size}>
  382. <@var{backup}|@var{nobackup}>
  383. @cindex working_area
  384. Specifies a working area for the debugger to use. This may be used to speed-up
  385. downloads to target memory and flash operations, or to perform otherwise unavailable
  386. operations (some coprocessor operations on ARM7/9 systems, for example). The last
  387. parameter decides whether the memory should be preserved <@var{backup}>. If possible, use
  388. a working_area that doesn't need to be backed up, as that slows down operation.
  389. @end itemize
  390. @subsection arm7tdmi options
  391. @cindex arm7tdmi options
  392. target arm7tdmi <@var{endianess}> <@var{reset_mode}> <@var{jtag#}>
  393. The arm7tdmi target definition requires at least one additional argument, specifying
  394. the position of the target in the JTAG daisy-chain. The first JTAG device is number 0.
  395. The optional [@var{variant}] parameter has been removed in recent versions.
  396. The correct feature set is determined at runtime.
  397. @subsection arm720t options
  398. @cindex arm720t options
  399. ARM720t options are similar to ARM7TDMI options.
  400. @subsection arm9tdmi options
  401. @cindex arm9tdmi options
  402. ARM9TDMI options are similar to ARM7TDMI options. Supported variants are
  403. @option{arm920t}, @option{arm922t} and @option{arm940t}.
  404. This enables the hardware single-stepping support found on these cores.
  405. @subsection arm920t options
  406. @cindex arm920t options
  407. ARM920t options are similar to ARM9TDMI options.
  408. @subsection arm966e options
  409. @cindex arm966e options
  410. ARM966e options are similar to ARM9TDMI options.
  411. @subsection xscale options
  412. @cindex xscale options
  413. Supported variants are @option{ixp42x}, @option{ixp45x}, @option{ixp46x},
  414. @option{pxa250}, @option{pxa255}, @option{pxa26x}.
  415. @section Flash configuration
  416. @cindex Flash configuration
  417. @itemize @bullet
  418. @item @b{flash bank} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}>
  419. <@var{bus_width}> <@var{target#}> [@var{driver_options ...}]
  420. @cindex flash bank
  421. Configures a flash bank at <@var{base}> of <@var{size}> bytes and <@var{chip_width}>
  422. and <@var{bus_width}> bytes using the selected flash <driver>.
  423. @item @b{flash autoerase} <@option{on}|@option{off}>
  424. @cindex flash autoerase
  425. auto erase flash banks prior to writing. Currently only works when using
  426. @option{flash write_image} command. Default is @option{off}.
  427. @end itemize
  428. @subsection lpc2000 options
  429. @cindex lpc2000 options
  430. @b{flash bank lpc2000} <@var{base}> <@var{size}> 0 0 <@var{target#}> <@var{variant}>
  431. <@var{clock}> [@var{calc_checksum}]
  432. LPC flashes don't require the chip and bus width to be specified. Additional
  433. parameters are the <@var{variant}>, which may be @var{lpc2000_v1} (older LPC21xx and LPC22xx)
  434. or @var{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx), the number
  435. of the target this flash belongs to (first is 0), the frequency at which the core
  436. is currently running (in kHz - must be an integral number), and the optional keyword
  437. @var{calc_checksum}, telling the driver to calculate a valid checksum for the exception
  438. vector table.
  439. @subsection cfi options
  440. @cindex cfi options
  441. @b{flash bank cfi} <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}>
  442. <@var{target#}>
  443. CFI flashes require the number of the target they're connected to as an additional
  444. argument. The CFI driver makes use of a working area (specified for the target)
  445. to significantly speed up operation.
  446. @subsection at91sam7 options
  447. @cindex at91sam7 options
  448. @b{flash bank at91sam7} 0 0 0 0 <@var{target#>}>
  449. AT91SAM7 flashes only require the target#, all other values are looked up after
  450. reading the chip-id and type.
  451. @subsection str7 options
  452. @cindex str7 options
  453. @b{flash bank str7x} <@var{base}> <@var{size}> 0 0 <@var{target#}> <@var{variant}>
  454. variant can be either STR71x, STR73x or STR75x.
  455. @subsection str9 options
  456. @cindex str9 options
  457. @b{flash bank str9x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
  458. The str9 needs the flash controller to be configured prior to Flash programming, eg.
  459. @smallexample
  460. str9x flash_config 0 4 2 0 0x80000
  461. @end smallexample
  462. This will setup the BBSR, NBBSR, BBADR and NBBADR registers respectively.
  463. @subsection str9 options (str9xpec driver)
  464. @b{flash bank str9xpec} <@var{base}> <@var{size}> 0 0 <@var{target#}>
  465. Before using the flash commands the turbo mode will need enabling using str9xpec
  466. @option{enable_turbo} <@var{num>.}
  467. Only use this driver for locking/unlocking the device or configuring the option bytes.
  468. Use the standard str9 driver for programming.
  469. @subsection stellaris (LM3Sxxx) options
  470. @cindex stellaris (LM3Sxxx) options
  471. @b{flash bank stellaris} <@var{base}> <@var{size}> 0 0 <@var{target#}>
  472. stellaris flash plugin only require the target#.
  473. @subsection stm32x options
  474. @cindex stm32x options
  475. @b{flash bank stm32x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
  476. stm32x flash plugin only require the target#.
  477. @node Commands
  478. @chapter Commands
  479. @cindex commands
  480. The Open On-Chip Debugger (OpenOCD) allows user interaction through a telnet interface
  481. (default: port 4444) and a GDB server (default: port 3333). The command line interpreter
  482. is available from both the telnet interface and a GDB session. To issue commands to the
  483. interpreter from within a GDB session, use the @option{monitor} command, e.g. use
  484. @option{monitor poll} to issue the @option{poll} command. All output is relayed through the
  485. GDB session.
  486. @section Daemon
  487. @itemize @bullet
  488. @item @b{sleep} <@var{msec}>
  489. @cindex sleep
  490. Wait for n milliseconds before resuming. Useful in connection with script files
  491. (@var{script} command and @var{target_script} configuration).
  492. @item @b{shutdown}
  493. @cindex shutdown
  494. Close the OpenOCD daemon, disconnecting all clients (GDB, Telnet).
  495. @item @b{debug_level} [@var{n}]
  496. @cindex debug_level
  497. Display or adjust debug level to n<0-3>
  498. @item @b{log_output} <@var{file}>
  499. @cindex log_output
  500. Redirect logging to <file> (default: stderr)
  501. @item @b{script} <@var{file}>
  502. @cindex script
  503. Execute commands from <file>
  504. @end itemize
  505. @subsection Target state handling
  506. @itemize @bullet
  507. @item @b{poll} [@option{on}|@option{off}]
  508. @cindex poll
  509. Poll the target for its current state. If the target is in debug mode, architecture
  510. specific information about the current state are printed. An optional parameter
  511. allows continuous polling to be enabled and disabled.
  512. @item @b{halt}
  513. @cindex halt
  514. Send a halt request to the target. The debugger signals the debug request,
  515. and waits for the target to enter debug mode.
  516. @item @b{resume} [@var{address}]
  517. @cindex resume
  518. Resume the target at its current code position, or at an optional address.
  519. @item @b{step} [@var{address}]
  520. @cindex step
  521. Single-step the target at its current code position, or at an optional address.
  522. @item @b{reset} [@option{run}|@option{halt}|@option{init}|@option{run_and_halt}
  523. |@option{run_and_init}]
  524. @cindex reset
  525. Do a hard-reset. The optional parameter specifies what should happen after the reset.
  526. This optional parameter overwrites the setting specified in the configuration file,
  527. making the new behaviour the default for the @option{reset} command.
  528. @itemize @minus
  529. @item run
  530. @cindex reset run
  531. Let the target run.
  532. @item halt
  533. @cindex reset halt
  534. Immediately halt the target (works only with certain configurations).
  535. @item init
  536. @cindex reset init
  537. Immediately halt the target, and execute the reset script (works only with certain
  538. configurations)
  539. @item run_and_halt
  540. @cindex reset run_and_halt
  541. Let the target run for a certain amount of time, then request a halt.
  542. @item run_and_init
  543. @cindex reset run_and_init
  544. Let the target run for a certain amount of time, then request a halt. Execute the
  545. reset script once the target entered debug mode.
  546. @end itemize
  547. @end itemize
  548. @subsection Memory access commands
  549. These commands allow accesses of a specific size to the memory system:
  550. @itemize @bullet
  551. @item @b{mdw} <@var{addr}> [@var{count}]
  552. @cindex mdw
  553. display memory words
  554. @item @b{mdh} <@var{addr}> [@var{count}]
  555. @cindex mdh
  556. display memory half-words
  557. @item @b{mdb} <@var{addr}> [@var{count}]
  558. @cindex mdb
  559. display memory bytes
  560. @item @b{mww} <@var{addr}> <@var{value}>
  561. @cindex mww
  562. write memory word
  563. @item @b{mwh} <@var{addr}> <@var{value}>
  564. @cindex mwh
  565. write memory half-word
  566. @item @b{mwb} <@var{addr}> <@var{value}>
  567. @cindex mwb
  568. write memory byte
  569. @item @b{load_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
  570. @cindex load_image
  571. Load image <@var{file}> to target memory at <@var{address}>
  572. @item @b{dump_image} <@var{file}> <@var{address}> <@var{size}>
  573. @cindex dump_image
  574. Dump <@var{size}> bytes of target memory starting at <@var{address}> to a
  575. (binary) <@var{file}>.
  576. @item @b{verify_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
  577. @cindex verify_image
  578. Verify <@var{file}> to target memory starting at <@var{address}>.
  579. @item @b{load_binary} <@var{file}> <@var{address}> [DEPRECATED]
  580. @cindex load_binary
  581. Load binary <@var{file}> to target memory at <@var{address}>
  582. @item @b{dump_binary} <@var{file}> <@var{address}> <@var{size}> [DEPRECATED]
  583. @cindex dump_binary
  584. Dump <@var{size}> bytes of target memory starting at <@var{address}> to a
  585. (binary) <@var{file}>.
  586. @end itemize
  587. @subsection Flash commands
  588. @cindex Flash commands
  589. @itemize @bullet
  590. @item @b{flash banks}
  591. @cindex flash banks
  592. List configured flash banks
  593. @item @b{flash info} <@var{num}>
  594. @cindex flash info
  595. Print info about flash bank <@option{num}>
  596. @item @b{flash probe} <@var{num}>
  597. @cindex flash probe
  598. Identify the flash, or validate the parameters of the configured flash. Operation
  599. depends on the flash type.
  600. @item @b{flash erase_check} <@var{num}>
  601. @cindex flash erase_check
  602. Check erase state of sectors in flash bank <@var{num}>. This is the only operation that
  603. updates the erase state information displayed by @option{flash info}. That means you have
  604. to issue an @option{erase_check} command after erasing or programming the device to get
  605. updated information.
  606. @item @b{flash protect_check} <@var{num}>
  607. @cindex flash protect_check
  608. Check protection state of sectors in flash bank <num>.
  609. @item @b{flash erase} <@var{num}> <@var{first}> <@var{last}>
  610. @cindex flash erase
  611. Erase sectors at bank <@var{num}>, starting at sector <@var{first}> up to and including
  612. <@var{last}>. Sector numbering starts at 0. Depending on the flash type, erasing might
  613. require the protection to be disabled first (e.g. Intel Advanced Bootblock flash using
  614. the CFI driver).
  615. @item @b{flash write} <@var{num}> <@var{file}> <@var{offset}> [DEPRECATED]
  616. @cindex flash write
  617. Write the binary <@var{file}> to flash bank <@var{num}>, starting at <@var{offset}>
  618. bytes from the beginning of the bank. This command was replaced by the new command
  619. @option{flash write_binary} using the same syntax.
  620. @item @b{flash write_binary} <@var{num}> <@var{file}> <@var{offset}>
  621. @cindex flash write_binary
  622. Write the binary <@var{file}> to flash bank <@var{num}>, starting at
  623. <@option{offset}> bytes from the beginning of the bank.
  624. @item @b{flash write_image} <@var{file}> [@var{offset}] [@var{type}]
  625. @cindex flash write_image
  626. Write the image <@var{file}> to the current target's flash bank(s). A relocation
  627. [@var{offset}] can be specified and the file [@var{type}] can be specified
  628. explicitly as @option{bin} (binary), @option{ihex} (Intel hex), @option{elf}
  629. (ELF file) or @option{s19} (Motorola s19).
  630. @item @b{flash protect} <@var{num}> <@var{first}> <@var{last}> <@option{on}|@option{off}>
  631. @cindex flash protect
  632. Enable (@var{on}) or disable (@var{off}) protection of flash sectors <@var{first}> to
  633. <@var{last}> of @option{flash bank} <@var{num}>.
  634. @item @b{flash auto_erase} <@var{on}|@var{off}>
  635. @cindex flash auto_erase
  636. Enable (@option{on}) to erase flash banks prior to writing using the flash @option{write_image} command
  637. only. Default is (@option{off}), flash banks have to be erased using @option{flash erase} command.
  638. @end itemize
  639. @page
  640. @section Target Specific Commands
  641. @cindex Target Specific Commands
  642. @subsection AT91SAM7 specific commands
  643. @cindex AT91SAM7 specific commands
  644. The flash configuration is deduced from the chip identification register. The flash
  645. controller handles erases automatically on a page (128/265 byte) basis so erase is
  646. not necessary for flash programming. AT91SAM7 processors with less than 512K flash
  647. only have a single flash bank embedded on chip. AT91SAM7xx512 have two flash planes
  648. that can be erased separatly.Only an EraseAll command is supported by the controller
  649. for each flash plane and this is called with
  650. @itemize @bullet
  651. @item @b{flash erase} <@var{num}> @var{first_plane} @var{last_plane}
  652. bulk erase flash planes first_plane to last_plane.
  653. @item @b{at91sam7 gpnvm} <@var{num}> <@var{bit}> <@option{set}|@option{clear}>
  654. @cindex at91sam7 gpnvm
  655. set or clear a gpnvm bit for the processor
  656. @end itemize
  657. @subsection STR9 specific commands
  658. @cindex STR9 specific commands
  659. These are flash specific commands when using the str9xpec driver.
  660. @itemize @bullet
  661. @item @b{str9xpec enable_turbo} <@var{num}>
  662. @cindex str9xpec enable_turbo
  663. enable turbo mode, simply this will remove the str9 from the chain and talk
  664. directly to the embedded flash controller.
  665. @item @b{str9xpec disable_turbo} <@var{num}>
  666. @cindex str9xpec disable_turbo
  667. restore the str9 into jtag chain.
  668. @item @b{str9xpec lock} <@var{num}>
  669. @cindex str9xpec lock
  670. lock str9 device. The str9 will only respond to an unlock command that will
  671. erase the device.
  672. @item @b{str9xpec unlock} <@var{num}>
  673. @cindex str9xpec unlock
  674. unlock str9 device.
  675. @item @b{str9xpec options_read} <@var{num}>
  676. @cindex str9xpec options_read
  677. read str9 option bytes.
  678. @item @b{str9xpec options_write} <@var{num}>
  679. @cindex str9xpec options_write
  680. write str9 option bytes.
  681. @end itemize
  682. @subsection STR9 configuration
  683. @cindex STR9 configuration
  684. @itemize @bullet
  685. @item @b{str9x flash_config} <@var{bank}> <@var{BBSR}> <@var{NBBSR}>
  686. <@var{BBADR}> <@var{NBBADR}>
  687. @cindex str9x flash_config
  688. Configure str9 flash controller.
  689. @smallexample
  690. eg. str9x flash_config 0 4 2 0 0x80000
  691. This will setup
  692. BBSR - Boot Bank Size register
  693. NBBSR - Non Boot Bank Size register
  694. BBADR - Boot Bank Start Address register
  695. NBBADR - Boot Bank Start Address register
  696. @end smallexample
  697. @end itemize
  698. @subsection STR9 option byte configuration
  699. @cindex STR9 option byte configuration
  700. @itemize @bullet
  701. @item @b{str9xpec options_cmap} <@var{num}> <@option{bank0}|@option{bank1}>
  702. @cindex str9xpec options_cmap
  703. configure str9 boot bank.
  704. @item @b{str9xpec options_lvdthd} <@var{num}> <@option{2.4v}|@option{2.7v}>
  705. @cindex str9xpec options_lvdthd
  706. configure str9 lvd threshold.
  707. @item @b{str9xpec options_lvdsel} <@var{num}> <@option{vdd}|@option{vdd_vddq}>
  708. @cindex str9xpec options_lvdsel
  709. configure str9 lvd source.
  710. @item @b{str9xpec options_lvdwarn} <@var{bank}> <@option{vdd}|@option{vdd_vddq}>
  711. @cindex str9xpec options_lvdwarn
  712. configure str9 lvd reset warning source.
  713. @end itemize
  714. @subsection STM32x specific commands
  715. @cindex STM32x specific commands
  716. These are flash specific commands when using the stm32x driver.
  717. @itemize @bullet
  718. @item @b{stm32x lock} <@var{num}>
  719. @cindex stm32x lock
  720. lock stm32 device.
  721. @item @b{stm32x unlock} <@var{num}>
  722. @cindex stm32x unlock
  723. unlock stm32 device.
  724. @item @b{stm32x options_read} <@var{num}>
  725. @cindex stm32x options_read
  726. read stm32 option bytes.
  727. @item @b{stm32x options_write} <@var{num}> <@option{SWWDG}|@option{HWWDG}>
  728. <@option{RSTSTNDBY}|@option{NORSTSTNDBY}> <@option{RSTSTOP}|@option{NORSTSTOP}>
  729. @cindex stm32x options_write
  730. write stm32 option bytes.
  731. @item @b{stm32x mass_erase} <@var{num}>
  732. @cindex stm32x mass_erase
  733. mass erase flash memory.
  734. @end itemize
  735. @page
  736. @section Arcitecture Specific Commands
  737. @cindex Arcitecture Specific Commands
  738. @subsection ARMV4/5 specific commands
  739. @cindex ARMV4/5 specific commands
  740. These commands are specific to ARM architecture v4 and v5, like all ARM7/9 systems
  741. or Intel XScale (XScale isn't supported yet).
  742. @itemize @bullet
  743. @item @b{armv4_5 reg}
  744. @cindex armv4_5 reg
  745. Display a list of all banked core registers, fetching the current value from every
  746. core mode if necessary. OpenOCD versions before rev. 60 didn't fetch the current
  747. register value.
  748. @item @b{armv4_5 core_mode} [@option{arm}|@option{thumb}]
  749. @cindex armv4_5 core_mode
  750. Displays the core_mode, optionally changing it to either ARM or Thumb mode.
  751. The target is resumed in the currently set @option{core_mode}.
  752. @end itemize
  753. @subsection ARM7/9 specific commands
  754. @cindex ARM7/9 specific commands
  755. These commands are specific to ARM7 and ARM9 targets, like ARM7TDMI, ARM720t,
  756. ARM920t or ARM926EJ-S.
  757. @itemize @bullet
  758. @item @b{arm7_9 sw_bkpts} <@option{enable}|@option{disable}>
  759. @cindex arm7_9 sw_bkpts
  760. Enable/disable use of software breakpoints. On ARMv4 systems, this reserves
  761. one of the watchpoint registers to implement software breakpoints. Disabling
  762. SW Bkpts frees that register again.
  763. @item @b{arm7_9 force_hw_bkpts} <@option{enable}|@option{disable}>
  764. @cindex arm7_9 force_hw_bkpts
  765. When @option{force_hw_bkpts} is enabled, the @option{sw_bkpts} support is disabled, and all
  766. breakpoints are turned into hardware breakpoints.
  767. @item @b{arm7_9 dbgrq} <@option{enable}|@option{disable}>
  768. @cindex arm7_9 dbgrq
  769. Enable use of the DBGRQ bit to force entry into debug mode. This should be
  770. safe for all but ARM7TDMI--S cores (like Philips LPC).
  771. @item @b{arm7_9 fast_writes} <@option{enable}|@option{disable}>
  772. @cindex arm7_9 fast_writes [DEPRECATED]
  773. See @option{arm7_9 fast_memory_access} instead.
  774. @item @b{arm7_9 fast_memory_access} <@option{enable}|@option{disable}>
  775. @cindex arm7_9 fast_memory_access
  776. Allow the OpenOCD to read and write memory without checking completion of
  777. the operation. This provides a huge speed increase, especially with USB JTAG
  778. cables (FT2232), but might be unsafe if used with targets running at a very low
  779. speed, like the 32kHz startup clock of an AT91RM9200.
  780. @item @b{arm7_9 dcc_downloads} <@option{enable}|@option{disable}>
  781. @cindex arm7_9 dcc_downloads
  782. Enable the use of the debug communications channel (DCC) to write larger (>128 byte)
  783. amounts of memory. DCC downloads offer a huge speed increase, but might be potentially
  784. unsafe, especially with targets running at a very low speed. This command was introduced
  785. with OpenOCD rev. 60.
  786. @end itemize
  787. @subsection ARM920T specific commands
  788. @cindex ARM920T specific commands
  789. @itemize @bullet
  790. @item @b{arm920t cache_info}
  791. @cindex arm920t cache_info
  792. Print information about the caches found. This allows you to see if your target
  793. is a ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
  794. @item @b{arm920t md<bhw>_phys} <@var{addr}> [@var{count}]
  795. @cindex arm920t md<bhw>_phys
  796. Display memory at physical address addr.
  797. @item @b{arm920t mw<bhw>_phys} <@var{addr}> <@var{value}>
  798. @cindex arm920t mw<bhw>_phys
  799. Write memory at physical address addr.
  800. @item @b{arm920t read_cache} <@var{filename}>
  801. @cindex arm920t read_cache
  802. Dump the content of ICache and DCache to a file.
  803. @item @b{arm920t read_mmu} <@var{filename}>
  804. @cindex arm920t read_mmu
  805. Dump the content of the ITLB and DTLB to a file.
  806. @item @b{arm920t virt2phys} <@var{VA}>
  807. @cindex arm920t virt2phys
  808. Translate a virtual address to a physical address.
  809. @end itemize
  810. @page
  811. @section Debug commands
  812. @cindex Debug commands
  813. The following commands give direct access to the core, and are most likely
  814. only useful while debugging the OpenOCD.
  815. @itemize @bullet
  816. @item @b{arm7_9 write_xpsr} <@var{32-bit value}> <@option{0=cpsr}, @option{1=spsr}>
  817. @cindex arm7_9 write_xpsr
  818. Immediately write either the current program status register (CPSR) or the saved
  819. program status register (SPSR), without changing the register cache (as displayed
  820. by the @option{reg} and @option{armv4_5 reg} commands).
  821. @item @b{arm7_9 write_xpsr_im8} <@var{8-bit value}> <@var{rotate 4-bit}>
  822. <@var{0=cpsr},@var{1=spsr}>
  823. @cindex arm7_9 write_xpsr_im8
  824. Write the 8-bit value rotated right by 2*rotate bits, using an immediate write
  825. operation (similar to @option{write_xpsr}).
  826. @item @b{arm7_9 write_core_reg} <@var{num}> <@var{mode}> <@var{value}>
  827. @cindex arm7_9 write_core_reg
  828. Write a core register, without changing the register cache (as displayed by the
  829. @option{reg} and @option{armv4_5 reg} commands). The <@var{mode}> argument takes the
  830. encoding of the [M4:M0] bits of the PSR.
  831. @end itemize
  832. @page
  833. @section JTAG commands
  834. @cindex JTAG commands
  835. @itemize @bullet
  836. @item @b{scan_chain}
  837. @cindex scan_chain
  838. Print current scan chain configuration.
  839. @item @b{jtag_reset}
  840. @cindex jtag_reset
  841. Toggle reset lines <@var{trst}> <@var{srst}>.
  842. @item @b{endstate} <@var{tap_state}>
  843. @cindex endstate
  844. Finish JTAG operations in <@var{tap_state}>.
  845. @item @b{runtest} <@var{num_cycles}>
  846. @cindex runtest
  847. Move to Run-Test/Idle, and execute <@var{num_cycles}>
  848. @item @b{statemove} [@var{tap_state}]
  849. @cindex statemove
  850. Move to current endstate or [@var{tap_state}]
  851. @item @b{irscan}
  852. @cindex irscan
  853. Execute IR scan <@var{device}> <@var{instr}> [@var{dev2}] [@var{instr2}] ...
  854. @item @b{drscan}
  855. @cindex drscan
  856. Execute DR scan <@var{device}> [@var{dev2}] [@var{var2}] ...
  857. @item @b{verify_ircapture}
  858. @cindex verify_ircapture
  859. Verify value captured during Capture-IR <@option{enable}|@option{disable}>
  860. @item @b{var}
  861. @cindex var
  862. Allocate, display or delete variable <@var{name}> [@var{num_fields}|@var{del}] [@var{size1}] ...
  863. @item @b{field}
  864. @cindex field
  865. Display/modify variable field <@var{var}> <@var{field}> [@var{value}|@var{flip}]
  866. @end itemize
  867. @node Sample Scripts
  868. @chapter Sample Scripts
  869. @cindex scripts
  870. This page will collect some script examples for different CPUs.
  871. The configuration script can be divided in the following section:
  872. @itemize @bullet
  873. @item deamon configuration
  874. @item interface
  875. @item jtag scan chain
  876. @item target configuration
  877. @item flash configuration
  878. @end itemize
  879. Detailed information about each section can be found at OpenOCD configuration
  880. @section OMAP5912 Flash Debug
  881. @cindex OMAP5912 Flash Debug
  882. The following two scripts was used with an wiggler PP and and a TI OMAP5912
  883. dual core processor (@uref{}) on a OMAP5912 OSK board
  884. @uref{(}).
  885. @subsection Openocd config
  886. @smallexample
  887. #daemon configuration
  888. telnet_port 4444
  889. gdb_port 3333
  890. #interface
  891. interface parport
  892. parport_port 0x378
  893. parport_cable wiggler
  894. jtag_speed 0
  895. #use combined on interfaces or targets that can't set TRST/SRST separately
  896. reset_config trst_and_srst
  897. #jtag scan chain
  898. #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
  899. jtag_device 38 0x0 0x0 0x0
  900. jtag_device 4 0x1 0x0 0xe
  901. jtag_device 8 0x0 0x0 0x0
  902. #target configuration
  903. daemon_startup reset
  904. #target <type> <endianness> <reset mode> <chainpos> <variant>
  905. target arm926ejs little run_and_init 1 arm926ejs
  906. target_script 0 reset omap5912_osk.init
  907. run_and_halt_time 0 30
  908. # omap5912 lcd frame buffer as working area
  909. working_area 0 0x20000000 0x3e800 nobackup
  910. #flash bank <driver> <base> <size> <chip_width> <bus_width>
  911. flash bank cfi 0x00000000 0x1000000 2 2 0
  912. @end smallexample
  913. @subsection Openocd init
  914. @smallexample
  915. #
  916. # halt target
  917. #
  918. poll
  919. sleep 1
  920. halt
  921. wait_halt
  922. #
  923. # disable wdt
  924. #
  925. mww 0xfffec808 0x000000f5
  926. mww 0xfffec808 0x000000a0
  927. mww 0xfffeb048 0x0000aaaa
  928. sleep 500
  929. mww 0xfffeb048 0x00005555
  930. sleep 500
  931. #
  932. # detect flash
  933. #
  934. flash probe 0
  935. @end smallexample
  936. @section STR71x Script
  937. @cindex STR71x Script
  938. The following script was used with an Amontec JTAGkey and a STR710 / STR711 cpu:
  939. @smallexample
  940. #daemon configuration
  941. telnet_port 4444
  942. gdb_port 3333
  943. #interface
  944. interface ft2232
  945. ft2232_device_desc "Amontec JTAGkey A"
  946. ft2232_layout jtagkey
  947. ft2232_vid_pid 0x0403 0xcff8
  948. jtag_speed 0
  949. #use combined on interfaces or targets that can't set TRST/SRST separately
  950. reset_config trst_and_srst srst_pulls_trst
  951. #jtag scan chain
  952. #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
  953. jtag_device 4 0x1 0xf 0xe
  954. #target configuration
  955. daemon_startup reset
  956. #target <type> <startup mode>
  957. #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
  958. target arm7tdmi little run_and_halt 0 arm7tdmi
  959. run_and_halt_time 0 30
  960. working_area 0 0x2000C000 0x4000 nobackup
  961. #flash bank <driver> <base> <size> <chip_width> <bus_width>
  962. flash bank str7x 0x40000000 0x00040000 0 0 0 STR71x
  963. @end smallexample
  964. @section STR750 Script
  965. @cindex STR750 Script
  966. The following script was used with an Amontec JTAGkey and a STR750 cpu:
  967. @smallexample
  968. #daemon configuration
  969. telnet_port 4444
  970. gdb_port 3333
  971. #interface
  972. interface ft2232
  973. ft2232_device_desc "Amontec JTAGkey A"
  974. ft2232_layout jtagkey
  975. ft2232_vid_pid 0x0403 0xcff8
  976. jtag_speed 19
  977. #use combined on interfaces or targets that can't set TRST/SRST separately
  978. #reset_config trst_and_srst srst_pulls_trst
  979. reset_config trst_and_srst srst_pulls_trst
  980. #jtag scan chain
  981. #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
  982. jtag_device 4 0x1 0xf 0xe
  983. #jtag nTRST and nSRST delay
  984. jtag_nsrst_delay 500
  985. jtag_ntrst_delay 500
  986. #target configuration
  987. daemon_startup reset
  988. #target <type> <startup mode>
  989. #target arm7tdmi <reset mode> <chainpos> <endianness> <variant>
  990. target arm7tdmi little run_and_halt 0 arm7tdmi
  991. run_and_halt_time 0 30
  992. working_area 0 0x40000000 0x4000 nobackup
  993. #flash bank <driver> <base> <size> <chip_width> <bus_width>
  994. flash bank str7x 0x20000000 0x000040000 0 0 0 STR75x
  995. @end smallexample
  996. @section STR912 Script
  997. @cindex STR912 Script
  998. The following script was used with an Amontec JTAGkey and a STR912 cpu:
  999. @smallexample
  1000. #daemon configuration
  1001. telnet_port 4444
  1002. gdb_port 3333
  1003. #interface
  1004. interface ft2232
  1005. ft2232_device_desc "Amontec JTAGkey A"
  1006. ft2232_layout jtagkey
  1007. jtag_speed 1
  1008. #use combined on interfaces or targets that can't set TRST/SRST separately
  1009. reset_config trst_and_srst
  1010. #jtag scan chain
  1011. #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
  1012. jtag_device 8 0x1 0x1 0xfe
  1013. jtag_device 4 0x1 0xf 0xe
  1014. jtag_device 5 0x1 0x1 0x1e
  1015. #target configuration
  1016. daemon_startup reset
  1017. #target <type> <startup mode>
  1018. #target arm966e <endianness> <reset mode> <chainpos> <variant>
  1019. target arm966e little reset_halt 1 arm966e
  1020. run_and_halt_time 0 30
  1021. working_area 0 0x50000000 16384 nobackup
  1022. #flash bank <driver> <base> <size> <chip_width> <bus_width>
  1023. flash bank str9x 0x00000000 0x00080000 0 0 0
  1024. @end smallexample
  1025. @section STM32x Script
  1026. @cindex STM32x Script
  1027. The following script was used with an Amontec JTAGkey and a STM32x cpu:
  1028. @smallexample
  1029. #daemon configuration
  1030. telnet_port 4444
  1031. gdb_port 3333
  1032. #interface
  1033. interface ft2232
  1034. ft2232_device_desc "Amontec JTAGkey A"
  1035. ft2232_layout jtagkey
  1036. jtag_speed 10
  1037. #use combined on interfaces or targets that can't set TRST/SRST separately
  1038. reset_config trst_and_srst
  1039. #jtag scan chain
  1040. #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
  1041. jtag_device 4 0x1 0xf 0xe
  1042. jtag_device 5 0x1 0x1 0x1e
  1043. #target configuration
  1044. daemon_startup reset
  1045. #target <type> <startup mode>
  1046. #target cortex_m3 <endianness> <reset mode> <chainpos> <variant>
  1047. target cortex_m3 little run_and_halt 0
  1048. run_and_halt_time 0 30
  1049. working_area 0 0x20000000 16384 nobackup
  1050. #flash bank <driver> <base> <size> <chip_width> <bus_width>
  1051. flash bank stm32x 0x08000000 0x00010000 0 0 0
  1052. @end smallexample
  1053. @section LPC2294 Script
  1054. @cindex LPC2294 Script
  1055. The following script was used with an Amontec JTAGkey and a LPC2294 cpu:
  1056. @smallexample
  1057. #daemon configuration
  1058. telnet_port 4444
  1059. gdb_port 3333
  1060. #interface
  1061. interface ft2232
  1062. ft2232_device_desc "Amontec JTAGkey A"
  1063. ft2232_layout jtagkey
  1064. ft2232_vid_pid 0x0403 0xcff8
  1065. jtag_speed 2
  1066. #use combined on interfaces or targets that can't set TRST/SRST separately
  1067. reset_config trst_and_srst srst_pulls_trst
  1068. #jtag scan chain
  1069. #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
  1070. jtag_device 4 0x1 0xf 0xe
  1071. #target configuration
  1072. daemon_startup reset
  1073. #target <type> <startup mode>
  1074. #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
  1075. target arm7tdmi little run_and_halt 0 arm7tdmi-s_r4
  1076. run_and_halt_time 0 30
  1077. working_area 0 0x40000000 0x40000 nobackup
  1078. #flash configuration
  1079. flash bank lpc2000 0x0 0x40000 0 0 0 lpc2000_v1 14765 calc_checksum
  1080. @end smallexample
  1081. @section AT91R40008 Script
  1082. @cindex AT91R40008 Script
  1083. The following script was used with an Amontec JTAGkey and a AT91R40008 cpu:
  1084. @smallexample
  1085. #daemon configuration
  1086. telnet_port 4444
  1087. gdb_port 3333
  1088. #interface
  1089. interface ft2232
  1090. ft2232_device_desc "Amontec JTAGkey A"
  1091. ft2232_layout jtagkey
  1092. ft2232_vid_pid 0x0403 0xcff8
  1093. jtag_speed 0
  1094. jtag_nsrst_delay 200
  1095. jtag_ntrst_delay 200
  1096. #use combined on interfaces or targets that can't set TRST/SRST separately
  1097. reset_config srst_only srst_pulls_trst
  1098. #jtag scan chain
  1099. #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
  1100. jtag_device 4 0x1 0xf 0xe
  1101. #target configuration
  1102. daemon_startup reset
  1103. #target <type> <startup mode>
  1104. #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
  1105. target arm7tdmi little run_and_halt 0 arm7tdmi
  1106. run_and_halt_time 0 30
  1107. @end smallexample
  1108. @section LPC2129 Script
  1109. @cindex LPC2129 Script
  1110. The following script was used with an wiggler PP and a LPC-2129 cpu:
  1111. @smallexample
  1112. #daemon configuration
  1113. telnet_port 4444
  1114. gdb_port 3333
  1115. #interface
  1116. interface parport
  1117. parport_port 0x378
  1118. parport_cable wiggler
  1119. jtag_speed 0
  1120. #use combined on interfaces or targets that can't set TRST/SRST separately
  1121. reset_config trst_and_srst srst_pulls_trst
  1122. #jtag scan chain
  1123. #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
  1124. jtag_device 4 0x1 0xf 0xe
  1125. #target configuration
  1126. daemon_startup reset
  1127. #target <type> <startup mode>
  1128. #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
  1129. target arm7tdmi little run_and_halt 0 arm7tdmi-s_r4
  1130. run_and_halt_time 0 30
  1131. working_area 0 0x00000000 0x400000 nobackup
  1132. #flash bank <driver> <base> <size> <chip_width> <bus_width>
  1133. flash bank lpc2000 0x0 0x40000 0 0 0 lpc2000_v1 14765 calc_checksum
  1134. @end smallexample
  1135. @section AT91SAM7s Script
  1136. @cindex AT91SAM7s Script
  1137. The following script was used with an Olimex ARM-JTAG-OCD and a AT91SAM7S64 cpu:
  1138. @smallexample
  1139. #daemon configuration
  1140. telnet_port 4444
  1141. gdb_port 3333
  1142. #interface
  1143. interface ft2232
  1144. ft2232_device_desc "Olimex OpenOCD JTAG A"
  1145. ft2232_layout olimex-jtag
  1146. ft2232_vid_pid 0x15BA 0x0003
  1147. jtag_speed 0
  1148. jtag_nsrst_delay 200
  1149. jtag_ntrst_delay 200
  1150. #use combined on interfaces or targets that can't set TRST/SRST separately
  1151. reset_config srst_only srst_pulls_trst
  1152. #jtag scan chain
  1153. #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
  1154. jtag_device 4 0x1 0xf 0xe
  1155. #target configuration
  1156. daemon_startup reset
  1157. #target <type> <startup mode>
  1158. #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
  1159. target arm7tdmi little run_and_halt 0 arm7tdmi
  1160. run_and_halt_time 0 30
  1161. # flash-options AT91
  1162. working_area 0 0x00200000 0x4000 nobackup
  1163. flash bank at91sam7 0 0 0 0 0
  1164. # Information:
  1165. # erase command (telnet-interface) for complete flash:
  1166. # flash erase <num> 0 numlockbits-1 (can be seen from output of flash info 0)
  1167. # SAM7S64 with 16 lockbits and bank 0: flash erase 0 0 15
  1168. # set/clear NVM-Bits:
  1169. # at91sam7 gpnvm <num> <bit> <set|clear>
  1170. # disable locking from SAM-BA:
  1171. # flash protect 0 0 1 off
  1172. @end smallexample
  1173. @section XSCALE IXP42x Script
  1174. @cindex XSCALE IXP42x Script
  1175. The following script was used with an Amontec JTAGkey-Tiny and a xscale ixp42x cpu:
  1176. @smallexample
  1177. #daemon configuration
  1178. telnet_port 4444
  1179. gdb_port 3333
  1180. #interface
  1181. interface ft2232
  1182. ft2232_device_desc "Amontec JTAGkey A"
  1183. ft2232_layout jtagkey
  1184. ft2232_vid_pid 0x0403 0xcff8
  1185. jtag_speed 0
  1186. jtag_nsrst_delay 200
  1187. jtag_ntrst_delay 200
  1188. #use combined on interfaces or targets that can't set TRST/SRST separately
  1189. reset_config srst_only srst_pulls_trst
  1190. #jtag scan chain
  1191. #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
  1192. jtag_device 7 0x1 0x7f 0x7e
  1193. #target configuration
  1194. daemon_startup reset
  1195. #target <type> <startup mode>
  1196. #target arm7tdmi <reset mode> <chainpos> <endianness> <variant>
  1197. target xscale big run_and_halt 0 IXP42x
  1198. run_and_halt_time 0 30
  1199. @end smallexample
  1200. @section Cirrus Logic EP9301 Script
  1201. @cindex Cirrus Logic EP9301 Script
  1202. The following script was used with FT2232 based JTAG interfaces and a
  1203. Cirrus Logic EP9301 processor on an Olimex CS-E9301 board.
  1204. @smallexample
  1205. #daemon configuration
  1206. telnet_port 4444
  1207. gdb_port 3333
  1208. #interface
  1209. interface ft2232
  1210. #Olimex ARM-USB-OCD
  1211. #ft2232_device_desc "Olimex OpenOCD JTAG"
  1212. #ft2232_layout olimex-jtag
  1213. #ft2232_vid_pid 0x15ba 0x0003
  1214. #Amontec JTAGkey (and JTAGkey-Tiny)
  1215. #Serial is only necessary if more than one JTAGkey is connected
  1216. ft2232_device_desc "Amontec JTAGkey A"
  1217. #ft2232_serial AMTJKV31
  1218. #ft2232_serial T1P3S2W8
  1219. ft2232_layout jtagkey
  1220. ft2232_vid_pid 0x0403 0xcff8
  1221. #wiggler/parallel port interface
  1222. #interface parport
  1223. #parport_port 0x378
  1224. #parport_cable wiggler
  1225. #jtag_speed 0
  1226. jtag_speed 1
  1227. reset_config trst_and_srst
  1228. #jtag scan chain
  1229. #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
  1230. jtag_device 4 0x1 0xf 0xe
  1231. jtag_nsrst_delay 100
  1232. jtag_ntrst_delay 100
  1233. #target configuration
  1234. daemon_startup attach
  1235. #target <type> <endianess> <reset mode>
  1236. target arm920t little reset_halt 0
  1237. working_area 0 0x80014000 0x1000 backup
  1238. #flash configuration
  1239. #flash bank <driver> <base> <size> <chip_width> <bus_width> [driver_options ...]
  1240. flash bank cfi 0x60000000 0x1000000 2 2 0
  1241. @end smallexample
  1242. @section Hilscher netX 100 / 500 Script
  1243. @cindex Hilscher netX 100 / 500 Script
  1244. The following script was used with an Amontec JTAGkey and a Hilscher
  1245. netX 500 cpu:
  1246. @smallexample
  1247. #daemon configuration
  1248. telnet_port 4444
  1249. gdb_port 3333
  1250. #interface
  1251. interface ft2232
  1252. ft2232_device_desc "Amontec JTAGkey A"
  1253. ft2232_layout jtagkey
  1254. ft2232_vid_pid 0x0403 0xcff8
  1255. jtag_speed 5
  1256. #use combined on interfaces or targets that can't set TRST/SRST separately
  1257. reset_config trst_and_srst
  1258. #jtag scan chain
  1259. #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
  1260. jtag_device 4 0x1 0xf 0xe
  1261. jtag_nsrst_delay 100
  1262. jtag_ntrst_delay 100
  1263. #target configuration
  1264. daemon_startup reset
  1265. #target <type> <endianness> <startup mode> <chainpos> <variant>
  1266. target arm926ejs little run_and_halt 0 arm926ejs
  1267. run_and_halt_time 0 500
  1268. @end smallexample
  1269. @section Marvell/Intel PXA270 Script
  1270. @cindex Marvell/Intel PXA270 Script
  1271. @smallexample
  1272. # config for Intel PXA270
  1273. # not, as of 2007-06-22, openocd only works with the
  1274. # libftd2xx library from ftdi. libftdi does not work.
  1275. telnet_port 3333
  1276. gdb_port 4444
  1277. interface ft2232
  1278. ft2232_layout olimex-jtag
  1279. ft2232_vid_pid 0x15BA 0x0003
  1280. ft2232_device_desc "Olimex OpenOCD JTAG"
  1281. jtag_speed 0
  1282. # set jtag_nsrst_delay to the delay introduced by your reset circuit
  1283. # the rest of the needed delays are built into the openocd program
  1284. jtag_nsrst_delay 260
  1285. # set the jtag_ntrst_delay to the delay introduced by a reset circuit
  1286. # the rest of the needed delays are built into the openocd program
  1287. jtag_ntrst_delay 0
  1288. #use combined on interfaces or targets that can't set TRST/SRST separately
  1289. reset_config trst_and_srst separate
  1290. #jtag scan chain
  1291. #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
  1292. jtag_device 7 0x1 0x7f 0x7e
  1293. #target configuration
  1294. daemon_startup reset
  1295. target xscale little reset_halt 0 pxa27x
  1296. # maps to PXA internal RAM. If you are using a PXA255
  1297. # you must initialize SDRAM or leave this option off
  1298. working_area 0 0x5c000000 0x10000 nobackup
  1299. run_and_halt_time 0 30
  1300. #flash bank <driver> <base> <size> <chip_width> <bus_width>
  1301. # works for P30 flash
  1302. flash bank cfi 0x00000000 0x1000000 2 4 0
  1303. @end smallexample
  1304. @node FAQ
  1305. @chapter FAQ
  1306. @cindex faq
  1307. @enumerate
  1308. @item OpenOCD complains about a missing cygwin1.dll
  1309. Make sure you have Cygwin installed, or at least a version of OpenOCD that
  1310. claims to come with all the necessary dlls. When using Cygwin, try launching
  1311. the OpenOCD from the Cygwin shell.
  1312. @item I'm trying to set a breakpoint using GDB (or a frontend like Insight or
  1313. Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213
  1314. arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".
  1315. GDB issues software breakpoints when a normal breakpoint is requested, or to implement
  1316. source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720t or ARM920t,
  1317. software breakpoints consume one of the two available hardware breakpoints,
  1318. and are therefor disabled by default. If your code is running from RAM, you
  1319. can enable software breakpoints with the @option{arm7_9 sw_bkpts enable} command. If
  1320. your code resides in Flash, you can't use software breakpoints, but you can force
  1321. OpenOCD to use hardware breakpoints instead: @option{arm7_9 force_hw_bkpts enable}.
  1322. @item When erasing or writing LPC2000 on-chip flash, the operation fails sometimes
  1323. and works sometimes fine.
  1324. Make sure the core frequency specified in the @option{flash lpc2000} line matches the
  1325. clock at the time you're programming the flash. If you've specified the crystal's
  1326. frequency, make sure the PLL is disabled, if you've specified the full core speed
  1327. (e.g. 60MHz), make sure the PLL is enabled.
  1328. @item When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
  1329. I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed
  1330. out while waiting for end of scan, rtck was disabled".
  1331. Make sure your PC's parallel port operates in EPP mode. You might have to try several
  1332. settings in your PC Bios (ECP, EPP, and different versions of those).
  1333. @item When debugging with the OpenOCD and GDB (plain GDB, Insight, or Eclipse),
  1334. I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():
  1335. memory read caused data abort".
  1336. The errors are non-fatal, and are the result of GDB trying to trace stack frames
  1337. beyond the last valid frame. It might be possible to prevent this by setting up
  1338. a proper "initial" stack frame, if you happen to know what exactly has to
  1339. be done, feel free to add this here.
  1340. @item I get the following message in the OpenOCD console (or log file):
  1341. "Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".
  1342. This warning doesn't indicate any serious problem, as long as you don't want to
  1343. debug your core right out of reset. Your .cfg file specified @option{jtag_reset
  1344. trst_and_srst srst_pulls_trst} to tell the OpenOCD that either your board,
  1345. your debugger or your target uC (e.g. LPC2000) can't assert the two reset signals
  1346. independently. With this setup, it's not possible to halt the core right out of
  1347. reset, everything else should work fine.
  1348. @item When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto
  1349. Toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be
  1350. unstable. When single-stepping over large blocks of code, GDB and OpenOCD
  1351. quit with an error message. Is there a stability issue with OpenOCD?
  1352. No, this is not a stability issue concering OpenOCD. Most users have solved
  1353. this issue by simply using a self-powered USB Hub, which they connect their
  1354. Amontec JTAGkey to. Apparently, some computers do not provide a USB power
  1355. supply stable enough for the Amontec JTAGkey to be operated.
  1356. @item When using the Amontec JTAGkey, sometimes OpenOCD crashes with the
  1357. following error messages: "Error: ft2232.c:201 ft2232_read(): FT_Read returned:
  1358. 4" and "Error: ft2232.c:365 ft2232_send_and_recv(): couldn't read from FT2232".
  1359. What does that mean and what might be the reason for this?
  1360. First of all, the reason might be the USB power supply. Try using a self-powered
  1361. hub instead of a direct connection to your computer. Secondly, the error code 4
  1362. corresponds to an FT_IO_ERROR, which means that the driver for the FTDI USB
  1363. Chip ran into some sort of error - this points us to a USB problem.
  1364. @item When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following
  1365. error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054".
  1366. What does that mean and what might be the reason for this?
  1367. Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB)
  1368. has closed the connection to OpenOCD. This might be a GDB issue.
  1369. @item In the configuration file in the section where flash device configurations
  1370. are described, there is a parameter for specifying the clock frequency for
  1371. LPC2000 internal flash devices (e.g.
  1372. @option{flash bank lpc2000 0x0 0x40000 0 0 lpc2000_v1 0 14746 calc_checksum}),
  1373. which must be sepcified in kilohertz. However, I do have a quartz crystal of a
  1374. frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz, i.e. 14,745.600 kHz).
  1375. Is it possible to specify real numbers for the clock frequency?
  1376. No. The clock frequency specified here must be given as an integral number.
  1377. However, this clock frequency is used by the In-Application-Programming (IAP)
  1378. routines of the LPC2000 family only, which seems to be very tolerant concerning
  1379. the given clock frequency, so a slight difference between the specified clock
  1380. frequency and the actual clock frequency will not cause any trouble.
  1381. @item Do I have to keep a specific order for the commands in the configuration file?
  1382. Well, yes and no. Commands can be given in arbitrary order, yet the devices
  1383. listed for the JTAG scan chain must be given in the right order (jtag_device),
  1384. with the device closest to the TDO-Pin being listed first. In general,
  1385. whenever objects of the same type exist which require an index number, then
  1386. these objects must be given in the right order (jtag_devices, targets and flash
  1387. banks - a target references a jtag_device and a flash bank references a target).
  1388. @item Sometimes my debugging session terminates with an error. When I look into the
  1389. log file, I can see these error messages: Error: arm7_9_common.c:561
  1390. arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP
  1391. @end enumerate
  1392. @include fdl.texi
  1393. @node Index
  1394. @unnumbered Index
  1395. @printindex cp
  1396. @bye