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  1. /***************************************************************************
  2. * Copyright (C) 2005 by Dominic Rath *
  3. * Dominic.Rath@gmx.de *
  4. * *
  5. * This program is free software; you can redistribute it and/or modify *
  6. * it under the terms of the GNU General Public License as published by *
  7. * the Free Software Foundation; either version 2 of the License, or *
  8. * (at your option) any later version. *
  9. * *
  10. * This program is distributed in the hope that it will be useful, *
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  13. * GNU General Public License for more details. *
  14. * *
  15. * You should have received a copy of the GNU General Public License *
  16. * along with this program; if not, write to the *
  17. * Free Software Foundation, Inc., *
  18. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
  19. ***************************************************************************/
  20. #ifdef HAVE_CONFIG_H
  21. #include "config.h"
  22. #endif
  23. #include "replacements.h"
  24. #include "stm32x.h"
  25. #include "flash.h"
  26. #include "target.h"
  27. #include "log.h"
  28. #include "armv7m.h"
  29. #include "algorithm.h"
  30. #include "binarybuffer.h"
  31. #include <stdlib.h>
  32. #include <string.h>
  33. int stm32x_register_commands(struct command_context_s *cmd_ctx);
  34. int stm32x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
  35. int stm32x_erase(struct flash_bank_s *bank, int first, int last);
  36. int stm32x_protect(struct flash_bank_s *bank, int set, int first, int last);
  37. int stm32x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
  38. int stm32x_probe(struct flash_bank_s *bank);
  39. int stm32x_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  40. int stm32x_protect_check(struct flash_bank_s *bank);
  41. int stm32x_erase_check(struct flash_bank_s *bank);
  42. int stm32x_info(struct flash_bank_s *bank, char *buf, int buf_size);
  43. int stm32x_handle_lock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  44. int stm32x_handle_unlock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  45. int stm32x_handle_options_read_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  46. int stm32x_handle_options_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  47. int stm32x_handle_mass_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  48. flash_driver_t stm32x_flash =
  49. {
  50. .name = "stm32x",
  51. .register_commands = stm32x_register_commands,
  52. .flash_bank_command = stm32x_flash_bank_command,
  53. .erase = stm32x_erase,
  54. .protect = stm32x_protect,
  55. .write = stm32x_write,
  56. .probe = stm32x_probe,
  57. .erase_check = stm32x_erase_check,
  58. .protect_check = stm32x_protect_check,
  59. .info = stm32x_info
  60. };
  61. int stm32x_register_commands(struct command_context_s *cmd_ctx)
  62. {
  63. command_t *stm32x_cmd = register_command(cmd_ctx, NULL, "stm32x", NULL, COMMAND_ANY, "stm32x flash specific commands");
  64. register_command(cmd_ctx, stm32x_cmd, "lock", stm32x_handle_lock_command, COMMAND_EXEC,
  65. "lock device");
  66. register_command(cmd_ctx, stm32x_cmd, "unlock", stm32x_handle_unlock_command, COMMAND_EXEC,
  67. "unlock protected device");
  68. register_command(cmd_ctx, stm32x_cmd, "mass_erase", stm32x_handle_mass_erase_command, COMMAND_EXEC,
  69. "mass erase device");
  70. register_command(cmd_ctx, stm32x_cmd, "options_read", stm32x_handle_options_read_command, COMMAND_EXEC,
  71. "read device option bytes");
  72. register_command(cmd_ctx, stm32x_cmd, "options_write", stm32x_handle_options_write_command, COMMAND_EXEC,
  73. "write device option bytes");
  74. return ERROR_OK;
  75. }
  76. int stm32x_build_block_list(struct flash_bank_s *bank)
  77. {
  78. int i;
  79. int num_sectors = 0;
  80. switch (bank->size)
  81. {
  82. case 32 * 1024:
  83. num_sectors = 32;
  84. break;
  85. case 64 * 1024:
  86. num_sectors = 64;
  87. break;
  88. case 128 * 1024:
  89. num_sectors = 128;
  90. break;
  91. default:
  92. ERROR("BUG: unknown bank->size encountered");
  93. exit(-1);
  94. }
  95. bank->num_sectors = num_sectors;
  96. bank->sectors = malloc(sizeof(flash_sector_t) * num_sectors);
  97. for (i = 0; i < num_sectors; i++)
  98. {
  99. bank->sectors[i].offset = i * 1024;
  100. bank->sectors[i].size = 1024;
  101. bank->sectors[i].is_erased = -1;
  102. bank->sectors[i].is_protected = 1;
  103. }
  104. return ERROR_OK;
  105. }
  106. /* flash bank stm32x <base> <size> 0 0 <target#>
  107. */
  108. int stm32x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
  109. {
  110. stm32x_flash_bank_t *stm32x_info;
  111. if (argc < 6)
  112. {
  113. WARNING("incomplete flash_bank stm32x configuration");
  114. return ERROR_FLASH_BANK_INVALID;
  115. }
  116. stm32x_info = malloc(sizeof(stm32x_flash_bank_t));
  117. bank->driver_priv = stm32x_info;
  118. if (bank->base != 0x08000000)
  119. {
  120. WARNING("overriding flash base address for STM32x device with 0x08000000");
  121. bank->base = 0x08000000;
  122. }
  123. stm32x_build_block_list(bank);
  124. stm32x_info->write_algorithm = NULL;
  125. return ERROR_OK;
  126. }
  127. u32 stm32x_get_flash_status(flash_bank_t *bank)
  128. {
  129. target_t *target = bank->target;
  130. u32 status;
  131. target_read_u32(target, STM32_FLASH_SR, &status);
  132. return status;
  133. }
  134. u32 stm32x_wait_status_busy(flash_bank_t *bank, int timeout)
  135. {
  136. u32 status;
  137. /* wait for busy to clear */
  138. while (((status = stm32x_get_flash_status(bank)) & FLASH_BSY) && (timeout-- > 0))
  139. {
  140. DEBUG("status: 0x%x", status);
  141. usleep(1000);
  142. }
  143. return status;
  144. }
  145. int stm32x_read_options(struct flash_bank_s *bank)
  146. {
  147. u32 optiondata;
  148. stm32x_flash_bank_t *stm32x_info = NULL;
  149. target_t *target = bank->target;
  150. stm32x_info = bank->driver_priv;
  151. /* read current option bytes */
  152. target_read_u32(target, STM32_FLASH_OBR, &optiondata);
  153. stm32x_info->option_bytes.user_options = (u16)0xFFF8|((optiondata >> 2) & 0x07);
  154. stm32x_info->option_bytes.RDP = (optiondata & (1 << OPT_READOUT)) ? 0xFFFF : 0x5AA5;
  155. if (optiondata & (1 << OPT_READOUT))
  156. INFO("Device Security Bit Set");
  157. /* each bit refers to a 4bank protection */
  158. target_read_u32(target, STM32_FLASH_WRPR, &optiondata);
  159. stm32x_info->option_bytes.protection[0] = (u16)optiondata;
  160. stm32x_info->option_bytes.protection[1] = (u16)(optiondata >> 8);
  161. stm32x_info->option_bytes.protection[2] = (u16)(optiondata >> 16);
  162. stm32x_info->option_bytes.protection[3] = (u16)(optiondata >> 24);
  163. return ERROR_OK;
  164. }
  165. int stm32x_erase_options(struct flash_bank_s *bank)
  166. {
  167. stm32x_flash_bank_t *stm32x_info = NULL;
  168. target_t *target = bank->target;
  169. u32 status;
  170. stm32x_info = bank->driver_priv;
  171. /* read current options */
  172. stm32x_read_options(bank);
  173. /* unlock flash registers */
  174. target_write_u32(target, STM32_FLASH_KEYR, KEY1);
  175. target_write_u32(target, STM32_FLASH_KEYR, KEY2);
  176. /* unlock option flash registers */
  177. target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
  178. target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
  179. /* erase option bytes */
  180. target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER|FLASH_OPTWRE);
  181. target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER|FLASH_STRT|FLASH_OPTWRE);
  182. status = stm32x_wait_status_busy(bank, 10);
  183. if( status & FLASH_WRPRTERR )
  184. return ERROR_FLASH_OPERATION_FAILED;
  185. if( status & FLASH_PGERR )
  186. return ERROR_FLASH_OPERATION_FAILED;
  187. /* clear readout protection and complementary option bytes
  188. * this will also force a device unlock if set */
  189. stm32x_info->option_bytes.RDP = 0x5AA5;
  190. return ERROR_OK;
  191. }
  192. int stm32x_write_options(struct flash_bank_s *bank)
  193. {
  194. stm32x_flash_bank_t *stm32x_info = NULL;
  195. target_t *target = bank->target;
  196. u32 status;
  197. stm32x_info = bank->driver_priv;
  198. /* unlock flash registers */
  199. target_write_u32(target, STM32_FLASH_KEYR, KEY1);
  200. target_write_u32(target, STM32_FLASH_KEYR, KEY2);
  201. /* unlock option flash registers */
  202. target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
  203. target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
  204. /* program option bytes */
  205. target_write_u32(target, STM32_FLASH_CR, FLASH_OPTPG|FLASH_OPTWRE);
  206. /* write user option byte */
  207. target_write_u16(target, STM32_OB_USER, stm32x_info->option_bytes.user_options);
  208. status = stm32x_wait_status_busy(bank, 10);
  209. if( status & FLASH_WRPRTERR )
  210. return ERROR_FLASH_OPERATION_FAILED;
  211. if( status & FLASH_PGERR )
  212. return ERROR_FLASH_OPERATION_FAILED;
  213. /* write protection byte 1 */
  214. target_write_u16(target, STM32_OB_WRP0, stm32x_info->option_bytes.protection[0]);
  215. status = stm32x_wait_status_busy(bank, 10);
  216. if( status & FLASH_WRPRTERR )
  217. return ERROR_FLASH_OPERATION_FAILED;
  218. if( status & FLASH_PGERR )
  219. return ERROR_FLASH_OPERATION_FAILED;
  220. /* write protection byte 2 */
  221. target_write_u16(target, STM32_OB_WRP1, stm32x_info->option_bytes.protection[1]);
  222. status = stm32x_wait_status_busy(bank, 10);
  223. if( status & FLASH_WRPRTERR )
  224. return ERROR_FLASH_OPERATION_FAILED;
  225. if( status & FLASH_PGERR )
  226. return ERROR_FLASH_OPERATION_FAILED;
  227. /* write protection byte 3 */
  228. target_write_u16(target, STM32_OB_WRP2, stm32x_info->option_bytes.protection[2]);
  229. status = stm32x_wait_status_busy(bank, 10);
  230. if( status & FLASH_WRPRTERR )
  231. return ERROR_FLASH_OPERATION_FAILED;
  232. if( status & FLASH_PGERR )
  233. return ERROR_FLASH_OPERATION_FAILED;
  234. /* write protection byte 4 */
  235. target_write_u16(target, STM32_OB_WRP3, stm32x_info->option_bytes.protection[3]);
  236. status = stm32x_wait_status_busy(bank, 10);
  237. if( status & FLASH_WRPRTERR )
  238. return ERROR_FLASH_OPERATION_FAILED;
  239. if( status & FLASH_PGERR )
  240. return ERROR_FLASH_OPERATION_FAILED;
  241. /* write readout protection bit */
  242. target_write_u16(target, STM32_OB_RDP, stm32x_info->option_bytes.RDP);
  243. status = stm32x_wait_status_busy(bank, 10);
  244. if( status & FLASH_WRPRTERR )
  245. return ERROR_FLASH_OPERATION_FAILED;
  246. if( status & FLASH_PGERR )
  247. return ERROR_FLASH_OPERATION_FAILED;
  248. target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
  249. return ERROR_OK;
  250. }
  251. int stm32x_blank_check(struct flash_bank_s *bank, int first, int last)
  252. {
  253. target_t *target = bank->target;
  254. u8 *buffer;
  255. int i;
  256. int nBytes;
  257. if ((first < 0) || (last > bank->num_sectors))
  258. return ERROR_FLASH_SECTOR_INVALID;
  259. if (target->state != TARGET_HALTED)
  260. {
  261. return ERROR_TARGET_NOT_HALTED;
  262. }
  263. buffer = malloc(256);
  264. for (i = first; i <= last; i++)
  265. {
  266. bank->sectors[i].is_erased = 1;
  267. target->type->read_memory(target, bank->base + bank->sectors[i].offset, 4, 256/4, buffer);
  268. for (nBytes = 0; nBytes < 256; nBytes++)
  269. {
  270. if (buffer[nBytes] != 0xFF)
  271. {
  272. bank->sectors[i].is_erased = 0;
  273. break;
  274. }
  275. }
  276. }
  277. free(buffer);
  278. return ERROR_OK;
  279. }
  280. int stm32x_protect_check(struct flash_bank_s *bank)
  281. {
  282. target_t *target = bank->target;
  283. u32 protection;
  284. int i, s;
  285. int num_bits;
  286. if (target->state != TARGET_HALTED)
  287. {
  288. return ERROR_TARGET_NOT_HALTED;
  289. }
  290. /* each bit refers to a 4bank protection */
  291. target_read_u32(target, STM32_FLASH_WRPR, &protection);
  292. /* each protection bit is for 4 1K pages */
  293. num_bits = (bank->num_sectors / 4);
  294. for (i = 0; i < num_bits; i++)
  295. {
  296. int set = 1;
  297. if( protection & (1 << i))
  298. set = 0;
  299. for (s = 0; s < 4; s++)
  300. bank->sectors[(i * 4) + s].is_protected = set;
  301. }
  302. return ERROR_OK;
  303. }
  304. int stm32x_erase(struct flash_bank_s *bank, int first, int last)
  305. {
  306. target_t *target = bank->target;
  307. int i;
  308. u32 status;
  309. if (target->state != TARGET_HALTED)
  310. {
  311. return ERROR_TARGET_NOT_HALTED;
  312. }
  313. /* unlock flash registers */
  314. target_write_u32(target, STM32_FLASH_KEYR, KEY1);
  315. target_write_u32(target, STM32_FLASH_KEYR, KEY2);
  316. for (i = first; i <= last; i++)
  317. {
  318. target_write_u32(target, STM32_FLASH_CR, FLASH_PER);
  319. target_write_u32(target, STM32_FLASH_AR, bank->base + bank->sectors[i].offset);
  320. target_write_u32(target, STM32_FLASH_CR, FLASH_PER|FLASH_STRT);
  321. status = stm32x_wait_status_busy(bank, 10);
  322. if( status & FLASH_WRPRTERR )
  323. return ERROR_FLASH_OPERATION_FAILED;
  324. if( status & FLASH_PGERR )
  325. return ERROR_FLASH_OPERATION_FAILED;
  326. bank->sectors[i].is_erased = 1;
  327. }
  328. target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
  329. return ERROR_OK;
  330. }
  331. int stm32x_protect(struct flash_bank_s *bank, int set, int first, int last)
  332. {
  333. stm32x_flash_bank_t *stm32x_info = NULL;
  334. target_t *target = bank->target;
  335. u16 prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
  336. int i, reg, bit;
  337. int status;
  338. u32 protection;
  339. stm32x_info = bank->driver_priv;
  340. if (target->state != TARGET_HALTED)
  341. {
  342. return ERROR_TARGET_NOT_HALTED;
  343. }
  344. if ((first && (first % 4)) || ((last + 1) && (last + 1) % 4))
  345. {
  346. WARNING("sector start/end incorrect - stm32 has 4K sector protection");
  347. return ERROR_FLASH_SECTOR_INVALID;
  348. }
  349. /* each bit refers to a 4bank protection */
  350. target_read_u32(target, STM32_FLASH_WRPR, &protection);
  351. prot_reg[0] = (u16)protection;
  352. prot_reg[1] = (u16)(protection >> 8);
  353. prot_reg[2] = (u16)(protection >> 16);
  354. prot_reg[3] = (u16)(protection >> 24);
  355. for (i = first; i <= last; i++)
  356. {
  357. reg = (i / 4) / 8;
  358. bit = (i / 4) - (reg * 8);
  359. if( set )
  360. prot_reg[reg] &= ~(1 << bit);
  361. else
  362. prot_reg[reg] |= (1 << bit);
  363. }
  364. if ((status = stm32x_erase_options(bank)) != ERROR_OK)
  365. return status;
  366. stm32x_info->option_bytes.protection[0] = prot_reg[0];
  367. stm32x_info->option_bytes.protection[1] = prot_reg[1];
  368. stm32x_info->option_bytes.protection[2] = prot_reg[2];
  369. stm32x_info->option_bytes.protection[3] = prot_reg[3];
  370. return stm32x_write_options(bank);
  371. }
  372. int stm32x_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
  373. {
  374. stm32x_flash_bank_t *stm32x_info = bank->driver_priv;
  375. target_t *target = bank->target;
  376. u32 buffer_size = 8192;
  377. working_area_t *source;
  378. u32 address = bank->base + offset;
  379. reg_param_t reg_params[4];
  380. armv7m_algorithm_t armv7m_info;
  381. int retval = ERROR_OK;
  382. u8 stm32x_flash_write_code[] = {
  383. /* write: */
  384. 0xDF, 0xF8, 0x24, 0x40, /* ldr r4, STM32_FLASH_CR */
  385. 0x09, 0x4D, /* ldr r5, STM32_FLASH_SR */
  386. 0x4F, 0xF0, 0x01, 0x03, /* mov r3, #1 */
  387. 0x23, 0x60, /* str r3, [r4, #0] */
  388. 0x30, 0xF8, 0x02, 0x3B, /* ldrh r3, [r0], #2 */
  389. 0x21, 0xF8, 0x02, 0x3B, /* strh r3, [r1], #2 */
  390. /* busy: */
  391. 0x2B, 0x68, /* ldr r3, [r5, #0] */
  392. 0x13, 0xF0, 0x01, 0x0F, /* tst r3, #0x01 */
  393. 0xFB, 0xD0, /* beq busy */
  394. 0x13, 0xF0, 0x14, 0x0F, /* tst r3, #0x14 */
  395. 0x01, 0xD1, /* bne exit */
  396. 0x01, 0x3A, /* subs r2, r2, #1 */
  397. 0xED, 0xD1, /* bne write */
  398. /* exit: */
  399. 0xFE, 0xE7, /* b exit */
  400. 0x10, 0x20, 0x02, 0x40, /* STM32_FLASH_CR: .word 0x40022010 */
  401. 0x0C, 0x20, 0x02, 0x40 /* STM32_FLASH_SR: .word 0x4002200C */
  402. };
  403. /* flash write code */
  404. if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code), &stm32x_info->write_algorithm) != ERROR_OK)
  405. {
  406. WARNING("no working area available, can't do block memory writes");
  407. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  408. };
  409. target_write_buffer(target, stm32x_info->write_algorithm->address, sizeof(stm32x_flash_write_code), stm32x_flash_write_code);
  410. /* memory buffer */
  411. while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
  412. {
  413. buffer_size /= 2;
  414. if (buffer_size <= 256)
  415. {
  416. /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
  417. if (stm32x_info->write_algorithm)
  418. target_free_working_area(target, stm32x_info->write_algorithm);
  419. WARNING("no large enough working area available, can't do block memory writes");
  420. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  421. }
  422. };
  423. armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
  424. armv7m_info.core_mode = ARMV7M_MODE_ANY;
  425. armv7m_info.core_state = ARMV7M_STATE_THUMB;
  426. init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
  427. init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
  428. init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
  429. init_reg_param(&reg_params[3], "r3", 32, PARAM_IN);
  430. while (count > 0)
  431. {
  432. u32 thisrun_count = (count > (buffer_size / 2)) ? (buffer_size / 2) : count;
  433. target_write_buffer(target, source->address, thisrun_count * 2, buffer);
  434. buf_set_u32(reg_params[0].value, 0, 32, source->address);
  435. buf_set_u32(reg_params[1].value, 0, 32, address);
  436. buf_set_u32(reg_params[2].value, 0, 32, thisrun_count);
  437. if ((retval = target->type->run_algorithm(target, 0, NULL, 4, reg_params, stm32x_info->write_algorithm->address, \
  438. stm32x_info->write_algorithm->address + (sizeof(stm32x_flash_write_code) - 10), 10000, &armv7m_info)) != ERROR_OK)
  439. {
  440. ERROR("error executing str7x flash write algorithm");
  441. break;
  442. }
  443. if (buf_get_u32(reg_params[3].value, 0, 32) & 0x14)
  444. {
  445. retval = ERROR_FLASH_OPERATION_FAILED;
  446. break;
  447. }
  448. buffer += thisrun_count * 2;
  449. address += thisrun_count * 2;
  450. count -= thisrun_count;
  451. }
  452. target_free_working_area(target, source);
  453. target_free_working_area(target, stm32x_info->write_algorithm);
  454. destroy_reg_param(&reg_params[0]);
  455. destroy_reg_param(&reg_params[1]);
  456. destroy_reg_param(&reg_params[2]);
  457. destroy_reg_param(&reg_params[3]);
  458. return retval;
  459. }
  460. int stm32x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
  461. {
  462. target_t *target = bank->target;
  463. u32 words_remaining = (count / 2);
  464. u32 bytes_remaining = (count & 0x00000001);
  465. u32 address = bank->base + offset;
  466. u32 bytes_written = 0;
  467. u8 status;
  468. u32 retval;
  469. if (target->state != TARGET_HALTED)
  470. {
  471. return ERROR_TARGET_NOT_HALTED;
  472. }
  473. if (offset & 0x1)
  474. {
  475. WARNING("offset 0x%x breaks required 2-byte alignment", offset);
  476. return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
  477. }
  478. /* unlock flash registers */
  479. target_write_u32(target, STM32_FLASH_KEYR, KEY1);
  480. target_write_u32(target, STM32_FLASH_KEYR, KEY2);
  481. /* multiple half words (2-byte) to be programmed? */
  482. if (words_remaining > 0)
  483. {
  484. /* try using a block write */
  485. if ((retval = stm32x_write_block(bank, buffer, offset, words_remaining)) != ERROR_OK)
  486. {
  487. if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
  488. {
  489. /* if block write failed (no sufficient working area),
  490. * we use normal (slow) single dword accesses */
  491. WARNING("couldn't use block writes, falling back to single memory accesses");
  492. }
  493. else if (retval == ERROR_FLASH_OPERATION_FAILED)
  494. {
  495. ERROR("flash writing failed with error code: 0x%x", retval);
  496. return ERROR_FLASH_OPERATION_FAILED;
  497. }
  498. }
  499. else
  500. {
  501. buffer += words_remaining * 2;
  502. address += words_remaining * 2;
  503. words_remaining = 0;
  504. }
  505. }
  506. while (words_remaining > 0)
  507. {
  508. target_write_u32(target, STM32_FLASH_CR, FLASH_PG);
  509. target_write_u16(target, address, *(u16*)(buffer + bytes_written));
  510. status = stm32x_wait_status_busy(bank, 5);
  511. if( status & FLASH_WRPRTERR )
  512. return ERROR_FLASH_OPERATION_FAILED;
  513. if( status & FLASH_PGERR )
  514. return ERROR_FLASH_OPERATION_FAILED;
  515. bytes_written += 2;
  516. words_remaining--;
  517. address += 2;
  518. }
  519. if (bytes_remaining)
  520. {
  521. u8 last_halfword[2] = {0xff, 0xff};
  522. int i = 0;
  523. while(bytes_remaining > 0)
  524. {
  525. last_halfword[i++] = *(buffer + bytes_written);
  526. bytes_remaining--;
  527. bytes_written++;
  528. }
  529. target_write_u32(target, STM32_FLASH_CR, FLASH_PG);
  530. target_write_u16(target, address, *(u16*)last_halfword);
  531. status = stm32x_wait_status_busy(bank, 5);
  532. if( status & FLASH_WRPRTERR )
  533. return ERROR_FLASH_OPERATION_FAILED;
  534. if( status & FLASH_PGERR )
  535. return ERROR_FLASH_OPERATION_FAILED;
  536. }
  537. target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
  538. return ERROR_OK;
  539. }
  540. int stm32x_probe(struct flash_bank_s *bank)
  541. {
  542. return ERROR_OK;
  543. }
  544. int stm32x_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
  545. {
  546. return ERROR_OK;
  547. }
  548. int stm32x_erase_check(struct flash_bank_s *bank)
  549. {
  550. return stm32x_blank_check(bank, 0, bank->num_sectors - 1);
  551. }
  552. int stm32x_info(struct flash_bank_s *bank, char *buf, int buf_size)
  553. {
  554. snprintf(buf, buf_size, "stm32x flash driver info" );
  555. return ERROR_OK;
  556. }
  557. int stm32x_handle_lock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
  558. {
  559. flash_bank_t *bank;
  560. target_t *target = NULL;
  561. stm32x_flash_bank_t *stm32x_info = NULL;
  562. if (argc < 1)
  563. {
  564. command_print(cmd_ctx, "stm32x lock <bank>");
  565. return ERROR_OK;
  566. }
  567. bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
  568. if (!bank)
  569. {
  570. command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
  571. return ERROR_OK;
  572. }
  573. stm32x_info = bank->driver_priv;
  574. target = bank->target;
  575. if (target->state != TARGET_HALTED)
  576. {
  577. return ERROR_TARGET_NOT_HALTED;
  578. }
  579. if (stm32x_erase_options(bank) != ERROR_OK)
  580. {
  581. command_print(cmd_ctx, "stm32x failed to erase options");
  582. return ERROR_OK;
  583. }
  584. /* set readout protection */
  585. stm32x_info->option_bytes.RDP = 0;
  586. if (stm32x_write_options(bank) != ERROR_OK)
  587. {
  588. command_print(cmd_ctx, "stm32x failed to lock device");
  589. return ERROR_OK;
  590. }
  591. command_print(cmd_ctx, "stm32x locked");
  592. return ERROR_OK;
  593. }
  594. int stm32x_handle_unlock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
  595. {
  596. flash_bank_t *bank;
  597. target_t *target = NULL;
  598. stm32x_flash_bank_t *stm32x_info = NULL;
  599. if (argc < 1)
  600. {
  601. command_print(cmd_ctx, "stm32x unlock <bank>");
  602. return ERROR_OK;
  603. }
  604. bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
  605. if (!bank)
  606. {
  607. command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
  608. return ERROR_OK;
  609. }
  610. stm32x_info = bank->driver_priv;
  611. target = bank->target;
  612. if (target->state != TARGET_HALTED)
  613. {
  614. return ERROR_TARGET_NOT_HALTED;
  615. }
  616. if (stm32x_erase_options(bank) != ERROR_OK)
  617. {
  618. command_print(cmd_ctx, "stm32x failed to unlock device");
  619. return ERROR_OK;
  620. }
  621. if (stm32x_write_options(bank) != ERROR_OK)
  622. {
  623. command_print(cmd_ctx, "stm32x failed to lock device");
  624. return ERROR_OK;
  625. }
  626. command_print(cmd_ctx, "stm32x unlocked");
  627. return ERROR_OK;
  628. }
  629. int stm32x_handle_options_read_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
  630. {
  631. flash_bank_t *bank;
  632. u32 optionbyte;
  633. target_t *target = NULL;
  634. stm32x_flash_bank_t *stm32x_info = NULL;
  635. if (argc < 1)
  636. {
  637. command_print(cmd_ctx, "stm32x options_read <bank>");
  638. return ERROR_OK;
  639. }
  640. bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
  641. if (!bank)
  642. {
  643. command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
  644. return ERROR_OK;
  645. }
  646. stm32x_info = bank->driver_priv;
  647. target = bank->target;
  648. if (target->state != TARGET_HALTED)
  649. {
  650. return ERROR_TARGET_NOT_HALTED;
  651. }
  652. target_read_u32(target, STM32_FLASH_OBR, &optionbyte);
  653. command_print(cmd_ctx, "Option Byte: 0x%x", optionbyte);
  654. if (buf_get_u32((u8*)&optionbyte, OPT_ERROR, 1))
  655. command_print(cmd_ctx, "Option Byte Complement Error");
  656. if (buf_get_u32((u8*)&optionbyte, OPT_READOUT, 1))
  657. command_print(cmd_ctx, "Readout Protection On");
  658. else
  659. command_print(cmd_ctx, "Readout Protection Off");
  660. if (buf_get_u32((u8*)&optionbyte, OPT_RDWDGSW, 1))
  661. command_print(cmd_ctx, "Software Watchdog");
  662. else
  663. command_print(cmd_ctx, "Hardware Watchdog");
  664. if (buf_get_u32((u8*)&optionbyte, OPT_RDRSTSTOP, 1))
  665. command_print(cmd_ctx, "Stop: No reset generated");
  666. else
  667. command_print(cmd_ctx, "Stop: Reset generated");
  668. if (buf_get_u32((u8*)&optionbyte, OPT_RDRSTSTDBY, 1))
  669. command_print(cmd_ctx, "Standby: No reset generated");
  670. else
  671. command_print(cmd_ctx, "Standby: Reset generated");
  672. return ERROR_OK;
  673. }
  674. int stm32x_handle_options_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
  675. {
  676. flash_bank_t *bank;
  677. target_t *target = NULL;
  678. stm32x_flash_bank_t *stm32x_info = NULL;
  679. u16 optionbyte = 0xF8;
  680. if (argc < 4)
  681. {
  682. command_print(cmd_ctx, "stm32x options_write <bank> <SWWDG|HWWDG> <RSTSTNDBY|NORSTSTNDBY> <RSTSTOP|NORSTSTOP>");
  683. return ERROR_OK;
  684. }
  685. bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
  686. if (!bank)
  687. {
  688. command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
  689. return ERROR_OK;
  690. }
  691. stm32x_info = bank->driver_priv;
  692. target = bank->target;
  693. if (target->state != TARGET_HALTED)
  694. {
  695. return ERROR_TARGET_NOT_HALTED;
  696. }
  697. if (strcmp(args[1], "SWWDG") == 0)
  698. {
  699. optionbyte |= (1<<0);
  700. }
  701. else
  702. {
  703. optionbyte &= ~(1<<0);
  704. }
  705. if (strcmp(args[2], "NORSTSTNDBY") == 0)
  706. {
  707. optionbyte |= (1<<1);
  708. }
  709. else
  710. {
  711. optionbyte &= ~(1<<1);
  712. }
  713. if (strcmp(args[3], "NORSTSTOP") == 0)
  714. {
  715. optionbyte |= (1<<2);
  716. }
  717. else
  718. {
  719. optionbyte &= ~(1<<2);
  720. }
  721. if (stm32x_erase_options(bank) != ERROR_OK)
  722. {
  723. command_print(cmd_ctx, "stm32x failed to erase options");
  724. return ERROR_OK;
  725. }
  726. stm32x_info->option_bytes.user_options = optionbyte;
  727. if (stm32x_write_options(bank) != ERROR_OK)
  728. {
  729. command_print(cmd_ctx, "stm32x failed to write options");
  730. return ERROR_OK;
  731. }
  732. command_print(cmd_ctx, "stm32x write options complete");
  733. return ERROR_OK;
  734. }
  735. int stm32x_handle_mass_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
  736. {
  737. target_t *target = NULL;
  738. stm32x_flash_bank_t *stm32x_info = NULL;
  739. flash_bank_t *bank;
  740. u32 status;
  741. if (argc < 1)
  742. {
  743. command_print(cmd_ctx, "stm32x mass_erase <bank>");
  744. return ERROR_OK;
  745. }
  746. bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
  747. if (!bank)
  748. {
  749. command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
  750. return ERROR_OK;
  751. }
  752. stm32x_info = bank->driver_priv;
  753. target = bank->target;
  754. if (target->state != TARGET_HALTED)
  755. {
  756. return ERROR_TARGET_NOT_HALTED;
  757. }
  758. /* unlock option flash registers */
  759. target_write_u32(target, STM32_FLASH_KEYR, KEY1);
  760. target_write_u32(target, STM32_FLASH_KEYR, KEY2);
  761. /* mass erase flash memory */
  762. target_write_u32(target, STM32_FLASH_CR, FLASH_MER);
  763. target_write_u32(target, STM32_FLASH_CR, FLASH_MER|FLASH_STRT);
  764. status = stm32x_wait_status_busy(bank, 10);
  765. target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
  766. if( status & FLASH_WRPRTERR )
  767. {
  768. command_print(cmd_ctx, "stm32x device protected");
  769. return ERROR_OK;
  770. }
  771. if( status & FLASH_PGERR )
  772. {
  773. command_print(cmd_ctx, "stm32x device programming failed");
  774. return ERROR_OK;
  775. }
  776. command_print(cmd_ctx, "stm32x mass erase complete");
  777. return ERROR_OK;
  778. }