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  1. /***************************************************************************
  2. * Copyright (C) 2008 by Spencer Oliver *
  3. * spen@spen-soft.co.uk *
  4. * *
  5. * Copyright (C) 2008 by David T.L. Wong *
  6. * *
  7. * Copyright (C) 2009 by David N. Claffey <dnclaffey@gmail.com> *
  8. * *
  9. * Copyright (C) 2011 by Drasko DRASKOVIC *
  10. * drasko.draskovic@gmail.com *
  11. * *
  12. * This program is free software; you can redistribute it and/or modify *
  13. * it under the terms of the GNU General Public License as published by *
  14. * the Free Software Foundation; either version 2 of the License, or *
  15. * (at your option) any later version. *
  16. * *
  17. * This program is distributed in the hope that it will be useful, *
  18. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  19. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  20. * GNU General Public License for more details. *
  21. * *
  22. * You should have received a copy of the GNU General Public License *
  23. * along with this program; if not, write to the *
  24. * Free Software Foundation, Inc., *
  25. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
  26. ***************************************************************************/
  27. /*
  28. * This version has optimized assembly routines for 32 bit operations:
  29. * - read word
  30. * - write word
  31. * - write array of words
  32. *
  33. * One thing to be aware of is that the MIPS32 cpu will execute the
  34. * instruction after a branch instruction (one delay slot).
  35. *
  36. * For example:
  37. * LW $2, ($5 +10)
  38. * B foo
  39. * LW $1, ($2 +100)
  40. *
  41. * The LW $1, ($2 +100) instruction is also executed. If this is
  42. * not wanted a NOP can be inserted:
  43. *
  44. * LW $2, ($5 +10)
  45. * B foo
  46. * NOP
  47. * LW $1, ($2 +100)
  48. *
  49. * or the code can be changed to:
  50. *
  51. * B foo
  52. * LW $2, ($5 +10)
  53. * LW $1, ($2 +100)
  54. *
  55. * The original code contained NOPs. I have removed these and moved
  56. * the branches.
  57. *
  58. * I also moved the PRACC_STACK to 0xFF204000. This allows
  59. * the use of 16 bits offsets to get pointers to the input
  60. * and output area relative to the stack. Note that the stack
  61. * isn't really a stack (the stack pointer is not 'moving')
  62. * but a FIFO simulated in software.
  63. *
  64. * These changes result in a 35% speed increase when programming an
  65. * external flash.
  66. *
  67. * More improvement could be gained if the registers do no need
  68. * to be preserved but in that case the routines should be aware
  69. * OpenOCD is used as a flash programmer or as a debug tool.
  70. *
  71. * Nico Coesel
  72. */
  73. #ifdef HAVE_CONFIG_H
  74. #include "config.h"
  75. #endif
  76. #include <helper/time_support.h>
  77. #include "mips32.h"
  78. #include "mips32_pracc.h"
  79. struct mips32_pracc_context {
  80. uint32_t *local_iparam;
  81. int num_iparam;
  82. uint32_t *local_oparam;
  83. int num_oparam;
  84. const uint32_t *code;
  85. int code_len;
  86. uint32_t stack[32];
  87. int stack_offset;
  88. struct mips_ejtag *ejtag_info;
  89. };
  90. static int mips32_pracc_sync_cache(struct mips_ejtag *ejtag_info,
  91. uint32_t start_addr, uint32_t end_addr);
  92. static int mips32_pracc_clean_invalidate_cache(struct mips_ejtag *ejtag_info,
  93. uint32_t start_addr, uint32_t end_addr);
  94. static int wait_for_pracc_rw(struct mips_ejtag *ejtag_info, uint32_t *ctrl)
  95. {
  96. uint32_t ejtag_ctrl;
  97. long long then = timeval_ms();
  98. int timeout;
  99. int retval;
  100. /* wait for the PrAcc to become "1" */
  101. mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
  102. while (1) {
  103. ejtag_ctrl = ejtag_info->ejtag_ctrl;
  104. retval = mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
  105. if (retval != ERROR_OK)
  106. return retval;
  107. if (ejtag_ctrl & EJTAG_CTRL_PRACC)
  108. break;
  109. timeout = timeval_ms() - then;
  110. if (timeout > 1000) {
  111. LOG_DEBUG("DEBUGMODULE: No memory access in progress!");
  112. return ERROR_JTAG_DEVICE_ERROR;
  113. }
  114. }
  115. *ctrl = ejtag_ctrl;
  116. return ERROR_OK;
  117. }
  118. static int mips32_pracc_exec_read(struct mips32_pracc_context *ctx, uint32_t address)
  119. {
  120. struct mips_ejtag *ejtag_info = ctx->ejtag_info;
  121. int offset;
  122. uint32_t ejtag_ctrl, data;
  123. if ((address >= MIPS32_PRACC_PARAM_IN)
  124. && (address < MIPS32_PRACC_PARAM_IN + ctx->num_iparam * 4)) {
  125. offset = (address - MIPS32_PRACC_PARAM_IN) / 4;
  126. data = ctx->local_iparam[offset];
  127. } else if ((address >= MIPS32_PRACC_PARAM_OUT)
  128. && (address < MIPS32_PRACC_PARAM_OUT + ctx->num_oparam * 4)) {
  129. offset = (address - MIPS32_PRACC_PARAM_OUT) / 4;
  130. data = ctx->local_oparam[offset];
  131. } else if ((address >= MIPS32_PRACC_TEXT)
  132. && (address < MIPS32_PRACC_TEXT + ctx->code_len * 4)) {
  133. offset = (address - MIPS32_PRACC_TEXT) / 4;
  134. data = ctx->code[offset];
  135. } else if (address == MIPS32_PRACC_STACK) {
  136. if (ctx->stack_offset <= 0) {
  137. LOG_ERROR("Error: Pracc stack out of bounds");
  138. return ERROR_JTAG_DEVICE_ERROR;
  139. }
  140. /* save to our debug stack */
  141. data = ctx->stack[--ctx->stack_offset];
  142. } else {
  143. /* TODO: send JMP 0xFF200000 instruction. Hopefully processor jump back
  144. * to start of debug vector */
  145. LOG_ERROR("Error reading unexpected address 0x%8.8" PRIx32 "", address);
  146. return ERROR_JTAG_DEVICE_ERROR;
  147. }
  148. /* Send the data out */
  149. mips_ejtag_set_instr(ctx->ejtag_info, EJTAG_INST_DATA);
  150. mips_ejtag_drscan_32_out(ctx->ejtag_info, data);
  151. /* Clear the access pending bit (let the processor eat!) */
  152. ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_PRACC;
  153. mips_ejtag_set_instr(ctx->ejtag_info, EJTAG_INST_CONTROL);
  154. mips_ejtag_drscan_32_out(ctx->ejtag_info, ejtag_ctrl);
  155. return jtag_execute_queue();
  156. }
  157. static int mips32_pracc_exec_write(struct mips32_pracc_context *ctx, uint32_t address)
  158. {
  159. uint32_t ejtag_ctrl, data;
  160. int offset;
  161. struct mips_ejtag *ejtag_info = ctx->ejtag_info;
  162. int retval;
  163. mips_ejtag_set_instr(ctx->ejtag_info, EJTAG_INST_DATA);
  164. retval = mips_ejtag_drscan_32(ctx->ejtag_info, &data);
  165. if (retval != ERROR_OK)
  166. return retval;
  167. /* Clear access pending bit */
  168. ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_PRACC;
  169. mips_ejtag_set_instr(ctx->ejtag_info, EJTAG_INST_CONTROL);
  170. mips_ejtag_drscan_32_out(ctx->ejtag_info, ejtag_ctrl);
  171. retval = jtag_execute_queue();
  172. if (retval != ERROR_OK)
  173. return retval;
  174. if ((address >= MIPS32_PRACC_PARAM_OUT)
  175. && (address < MIPS32_PRACC_PARAM_OUT + ctx->num_oparam * 4)) {
  176. offset = (address - MIPS32_PRACC_PARAM_OUT) / 4;
  177. ctx->local_oparam[offset] = data;
  178. } else if (address == MIPS32_PRACC_STACK) {
  179. if (ctx->stack_offset >= 32) {
  180. LOG_ERROR("Error: Pracc stack out of bounds");
  181. return ERROR_JTAG_DEVICE_ERROR;
  182. }
  183. /* save data onto our stack */
  184. ctx->stack[ctx->stack_offset++] = data;
  185. } else {
  186. LOG_ERROR("Error writing unexpected address 0x%8.8" PRIx32 "", address);
  187. return ERROR_JTAG_DEVICE_ERROR;
  188. }
  189. return ERROR_OK;
  190. }
  191. int mips32_pracc_exec(struct mips_ejtag *ejtag_info, int code_len, const uint32_t *code,
  192. int num_param_in, uint32_t *param_in, int num_param_out, uint32_t *param_out, int cycle)
  193. {
  194. uint32_t ejtag_ctrl;
  195. uint32_t address;
  196. struct mips32_pracc_context ctx;
  197. int retval;
  198. int pass = 0;
  199. ctx.local_iparam = param_in;
  200. ctx.local_oparam = param_out;
  201. ctx.num_iparam = num_param_in;
  202. ctx.num_oparam = num_param_out;
  203. ctx.code = code;
  204. ctx.code_len = code_len;
  205. ctx.ejtag_info = ejtag_info;
  206. ctx.stack_offset = 0;
  207. while (1) {
  208. retval = wait_for_pracc_rw(ejtag_info, &ejtag_ctrl);
  209. if (retval != ERROR_OK)
  210. return retval;
  211. address = 0;
  212. mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS);
  213. retval = mips_ejtag_drscan_32(ejtag_info, &address);
  214. if (retval != ERROR_OK)
  215. return retval;
  216. /* Check for read or write */
  217. if (ejtag_ctrl & EJTAG_CTRL_PRNW) {
  218. retval = mips32_pracc_exec_write(&ctx, address);
  219. if (retval != ERROR_OK)
  220. return retval;
  221. } else {
  222. /* Check to see if its reading at the debug vector. The first pass through
  223. * the module is always read at the vector, so the first one we allow. When
  224. * the second read from the vector occurs we are done and just exit. */
  225. if ((address == MIPS32_PRACC_TEXT) && (pass++))
  226. break;
  227. retval = mips32_pracc_exec_read(&ctx, address);
  228. if (retval != ERROR_OK)
  229. return retval;
  230. }
  231. if (cycle == 0)
  232. break;
  233. }
  234. /* stack sanity check */
  235. if (ctx.stack_offset != 0)
  236. LOG_DEBUG("Pracc Stack not zero");
  237. return ERROR_OK;
  238. }
  239. inline void pracc_queue_init(struct pracc_queue_info *ctx)
  240. {
  241. ctx->retval = ERROR_OK;
  242. ctx->code_count = 0;
  243. ctx->store_count = 0;
  244. ctx->pracc_list = malloc(2 * ctx->max_code * sizeof(uint32_t));
  245. if (ctx->pracc_list == NULL) {
  246. LOG_ERROR("Out of memory");
  247. ctx->retval = ERROR_FAIL;
  248. }
  249. }
  250. inline void pracc_add(struct pracc_queue_info *ctx, uint32_t addr, uint32_t instr)
  251. {
  252. ctx->pracc_list[ctx->max_code + ctx->code_count] = addr;
  253. ctx->pracc_list[ctx->code_count++] = instr;
  254. if (addr)
  255. ctx->store_count++;
  256. }
  257. inline void pracc_queue_free(struct pracc_queue_info *ctx)
  258. {
  259. if (ctx->code_count > ctx->max_code) /* Only for internal check, will be erased */
  260. LOG_ERROR("Internal error, code count: %d > max code: %d", ctx->code_count, ctx->max_code);
  261. if (ctx->pracc_list != NULL)
  262. free(ctx->pracc_list);
  263. }
  264. int mips32_pracc_queue_exec(struct mips_ejtag *ejtag_info, struct pracc_queue_info *ctx, uint32_t *buf)
  265. {
  266. if (ejtag_info->mode == 0)
  267. return mips32_pracc_exec(ejtag_info, ctx->code_count, ctx->pracc_list, 0, NULL,
  268. ctx->store_count, buf, ctx->code_count - 1);
  269. union scan_in {
  270. uint8_t scan_96[12];
  271. struct {
  272. uint8_t ctrl[4];
  273. uint8_t data[4];
  274. uint8_t addr[4];
  275. } scan_32;
  276. } *scan_in = malloc(sizeof(union scan_in) * (ctx->code_count + ctx->store_count));
  277. if (scan_in == NULL) {
  278. LOG_ERROR("Out of memory");
  279. return ERROR_FAIL;
  280. }
  281. unsigned num_clocks =
  282. ((uint64_t)(ejtag_info->scan_delay) * jtag_get_speed_khz() + 500000) / 1000000;
  283. uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_PRACC;
  284. mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ALL);
  285. int scan_count = 0;
  286. for (int i = 0; i != 2 * ctx->code_count; i++) {
  287. uint32_t data = 0;
  288. if (i & 1u) { /* Check store address from previous instruction, if not the first */
  289. if (i < 2 || 0 == ctx->pracc_list[ctx->max_code + (i / 2) - 1])
  290. continue;
  291. } else
  292. data = ctx->pracc_list[i / 2];
  293. jtag_add_clocks(num_clocks);
  294. mips_ejtag_add_scan_96(ejtag_info, ejtag_ctrl, data, scan_in[scan_count++].scan_96);
  295. }
  296. int retval = jtag_execute_queue(); /* execute queued scans */
  297. if (retval != ERROR_OK)
  298. goto exit;
  299. uint32_t fetch_addr = MIPS32_PRACC_TEXT; /* start address */
  300. scan_count = 0;
  301. for (int i = 0; i != 2 * ctx->code_count; i++) { /* verify every pracc access */
  302. uint32_t store_addr = 0;
  303. if (i & 1u) { /* Read store addres from previous instruction, if not the first */
  304. store_addr = ctx->pracc_list[ctx->max_code + (i / 2) - 1];
  305. if (i < 2 || 0 == store_addr)
  306. continue;
  307. }
  308. ejtag_ctrl = buf_get_u32(scan_in[scan_count].scan_32.ctrl, 0, 32);
  309. if (!(ejtag_ctrl & EJTAG_CTRL_PRACC)) {
  310. LOG_ERROR("Error: access not pending count: %d", scan_count);
  311. retval = ERROR_FAIL;
  312. goto exit;
  313. }
  314. uint32_t addr = buf_get_u32(scan_in[scan_count].scan_32.addr, 0, 32);
  315. if (store_addr != 0) {
  316. if (!(ejtag_ctrl & EJTAG_CTRL_PRNW)) {
  317. LOG_ERROR("Not a store/write access, count: %d", scan_count);
  318. retval = ERROR_FAIL;
  319. goto exit;
  320. }
  321. if (addr != store_addr) {
  322. LOG_ERROR("Store address mismatch, read: %x expected: %x count: %d",
  323. addr, store_addr, scan_count);
  324. retval = ERROR_FAIL;
  325. goto exit;
  326. }
  327. int buf_index = (addr - MIPS32_PRACC_PARAM_OUT) / 4;
  328. buf[buf_index] = buf_get_u32(scan_in[scan_count].scan_32.data, 0, 32);
  329. } else {
  330. if (ejtag_ctrl & EJTAG_CTRL_PRNW) {
  331. LOG_ERROR("Not a fetch/read access, count: %d", scan_count);
  332. retval = ERROR_FAIL;
  333. goto exit;
  334. }
  335. if (addr != fetch_addr) {
  336. LOG_ERROR("Fetch addr mismatch, read: %x expected: %x count: %d", addr, fetch_addr, scan_count);
  337. retval = ERROR_FAIL;
  338. goto exit;
  339. }
  340. fetch_addr += 4;
  341. }
  342. scan_count++;
  343. }
  344. exit:
  345. free(scan_in);
  346. return retval;
  347. }
  348. int mips32_pracc_read_u32(struct mips_ejtag *ejtag_info, uint32_t addr, uint32_t *buf)
  349. {
  350. struct pracc_queue_info ctx = {.max_code = 9};
  351. pracc_queue_init(&ctx);
  352. if (ctx.retval != ERROR_OK)
  353. goto exit;
  354. pracc_add(&ctx, 0, MIPS32_MTC0(15, 31, 0)); /* move $15 to COP0 DeSave */
  355. pracc_add(&ctx, 0, MIPS32_LUI(15, PRACC_UPPER_BASE_ADDR)); /* $15 = MIPS32_PRACC_BASE_ADDR */
  356. pracc_add(&ctx, 0, MIPS32_LUI(8, UPPER16((addr + 0x8000)))); /* load $8 with modified upper address */
  357. pracc_add(&ctx, 0, MIPS32_LW(8, LOWER16(addr), 8)); /* lw $8, LOWER16(addr)($8) */
  358. pracc_add(&ctx, MIPS32_PRACC_PARAM_OUT,
  359. MIPS32_SW(8, PRACC_OUT_OFFSET, 15)); /* sw $8,PRACC_OUT_OFFSET($15) */
  360. pracc_add(&ctx, 0, MIPS32_LUI(8, UPPER16(ejtag_info->reg8))); /* restore upper 16 of $8 */
  361. pracc_add(&ctx, 0, MIPS32_ORI(8, 8, LOWER16(ejtag_info->reg8))); /* restore lower 16 of $8 */
  362. pracc_add(&ctx, 0, MIPS32_B(NEG16(ctx.code_count + 1))); /* jump to start */
  363. pracc_add(&ctx, 0, MIPS32_MFC0(15, 31, 0)); /* move COP0 DeSave to $15 */
  364. ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, buf);
  365. exit:
  366. pracc_queue_free(&ctx);
  367. return ctx.retval;
  368. }
  369. int mips32_pracc_read_mem(struct mips_ejtag *ejtag_info, uint32_t addr, int size, int count, void *buf)
  370. {
  371. if (count == 1 && size == 4)
  372. return mips32_pracc_read_u32(ejtag_info, addr, (uint32_t *)buf);
  373. uint32_t *data = NULL;
  374. struct pracc_queue_info ctx = {.max_code = 256 * 3 + 9 + 1}; /* alloc memory for the worst case */
  375. pracc_queue_init(&ctx);
  376. if (ctx.retval != ERROR_OK)
  377. goto exit;
  378. if (size != 4) {
  379. data = malloc(256 * sizeof(uint32_t));
  380. if (data == NULL) {
  381. LOG_ERROR("Out of memory");
  382. goto exit;
  383. }
  384. }
  385. uint32_t *buf32 = buf;
  386. uint16_t *buf16 = buf;
  387. uint8_t *buf8 = buf;
  388. while (count) {
  389. ctx.code_count = 0;
  390. ctx.store_count = 0;
  391. int this_round_count = (count > 256) ? 256 : count;
  392. uint32_t last_upper_base_addr = UPPER16((addr + 0x8000));
  393. pracc_add(&ctx, 0, MIPS32_MTC0(15, 31, 0)); /* save $15 in DeSave */
  394. pracc_add(&ctx, 0, MIPS32_LUI(15, PRACC_UPPER_BASE_ADDR)); /* $15 = MIPS32_PRACC_BASE_ADDR */
  395. pracc_add(&ctx, 0, MIPS32_LUI(9, last_upper_base_addr)); /* load the upper memory address in $9 */
  396. for (int i = 0; i != this_round_count; i++) { /* Main code loop */
  397. uint32_t upper_base_addr = UPPER16((addr + 0x8000));
  398. if (last_upper_base_addr != upper_base_addr) { /* if needed, change upper address in $9 */
  399. pracc_add(&ctx, 0, MIPS32_LUI(9, upper_base_addr));
  400. last_upper_base_addr = upper_base_addr;
  401. }
  402. if (size == 4)
  403. pracc_add(&ctx, 0, MIPS32_LW(8, LOWER16(addr), 9)); /* load from memory to $8 */
  404. else if (size == 2)
  405. pracc_add(&ctx, 0, MIPS32_LHU(8, LOWER16(addr), 9));
  406. else
  407. pracc_add(&ctx, 0, MIPS32_LBU(8, LOWER16(addr), 9));
  408. pracc_add(&ctx, MIPS32_PRACC_PARAM_OUT + i * 4,
  409. MIPS32_SW(8, PRACC_OUT_OFFSET + i * 4, 15)); /* store $8 at param out */
  410. addr += size;
  411. }
  412. pracc_add(&ctx, 0, MIPS32_LUI(8, UPPER16(ejtag_info->reg8))); /* restore upper 16 bits of reg 8 */
  413. pracc_add(&ctx, 0, MIPS32_ORI(8, 8, LOWER16(ejtag_info->reg8))); /* restore lower 16 bits of reg 8 */
  414. pracc_add(&ctx, 0, MIPS32_LUI(9, UPPER16(ejtag_info->reg9))); /* restore upper 16 bits of reg 9 */
  415. pracc_add(&ctx, 0, MIPS32_ORI(9, 9, LOWER16(ejtag_info->reg9))); /* restore lower 16 bits of reg 9 */
  416. pracc_add(&ctx, 0, MIPS32_B(NEG16(ctx.code_count + 1))); /* jump to start */
  417. pracc_add(&ctx, 0, MIPS32_MFC0(15, 31, 0)); /* restore $15 from DeSave */
  418. if (size == 4) {
  419. ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, buf32);
  420. if (ctx.retval != ERROR_OK)
  421. goto exit;
  422. buf32 += this_round_count;
  423. } else {
  424. ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, data);
  425. if (ctx.retval != ERROR_OK)
  426. goto exit;
  427. uint32_t *data_p = data;
  428. for (int i = 0; i != this_round_count; i++) {
  429. if (size == 2)
  430. *buf16++ = *data_p++;
  431. else
  432. *buf8++ = *data_p++;
  433. }
  434. }
  435. count -= this_round_count;
  436. }
  437. exit:
  438. pracc_queue_free(&ctx);
  439. if (data != NULL)
  440. free(data);
  441. return ctx.retval;
  442. }
  443. int mips32_cp0_read(struct mips_ejtag *ejtag_info, uint32_t *val, uint32_t cp0_reg, uint32_t cp0_sel)
  444. {
  445. struct pracc_queue_info ctx = {.max_code = 8};
  446. pracc_queue_init(&ctx);
  447. if (ctx.retval != ERROR_OK)
  448. goto exit;
  449. pracc_add(&ctx, 0, MIPS32_MTC0(15, 31, 0)); /* move $15 to COP0 DeSave */
  450. pracc_add(&ctx, 0, MIPS32_LUI(15, PRACC_UPPER_BASE_ADDR)); /* $15 = MIPS32_PRACC_BASE_ADDR */
  451. pracc_add(&ctx, 0, MIPS32_MFC0(8, 0, 0) | (cp0_reg << 11) | cp0_sel); /* move COP0 [cp0_reg select] to $8 */
  452. pracc_add(&ctx, MIPS32_PRACC_PARAM_OUT,
  453. MIPS32_SW(8, PRACC_OUT_OFFSET, 15)); /* store $8 to pracc_out */
  454. pracc_add(&ctx, 0, MIPS32_MFC0(15, 31, 0)); /* move COP0 DeSave to $15 */
  455. pracc_add(&ctx, 0, MIPS32_LUI(8, UPPER16(ejtag_info->reg8))); /* restore upper 16 bits of $8 */
  456. pracc_add(&ctx, 0, MIPS32_B(NEG16(ctx.code_count + 1))); /* jump to start */
  457. pracc_add(&ctx, 0, MIPS32_ORI(8, 8, LOWER16(ejtag_info->reg8))); /* restore lower 16 bits of $8 */
  458. ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, val);
  459. exit:
  460. pracc_queue_free(&ctx);
  461. return ctx.retval;
  462. /**
  463. * Note that our input parametes cp0_reg and cp0_sel
  464. * are numbers (not gprs) which make part of mfc0 instruction opcode.
  465. *
  466. * These are not fix, but can be different for each mips32_cp0_read() function call,
  467. * and that is why we must insert them directly into opcode,
  468. * i.e. we can not pass it on EJTAG microprogram stack (via param_in),
  469. * and put them into the gprs later from MIPS32_PRACC_STACK
  470. * because mfc0 do not use gpr as a parameter for the cp0_reg and select part,
  471. * but plain (immediate) number.
  472. *
  473. * MIPS32_MTC0 is implemented via MIPS32_R_INST macro.
  474. * In order to insert our parameters, we must change rd and funct fields.
  475. *
  476. * code[2] |= (cp0_reg << 11) | cp0_sel; change rd and funct of MIPS32_R_INST macro
  477. **/
  478. }
  479. int mips32_cp0_write(struct mips_ejtag *ejtag_info, uint32_t val, uint32_t cp0_reg, uint32_t cp0_sel)
  480. {
  481. struct pracc_queue_info ctx = {.max_code = 6};
  482. pracc_queue_init(&ctx);
  483. if (ctx.retval != ERROR_OK)
  484. goto exit;
  485. pracc_add(&ctx, 0, MIPS32_MTC0(15, 31, 0)); /* move $15 to COP0 DeSave */
  486. pracc_add(&ctx, 0, MIPS32_LUI(15, UPPER16(val))); /* Load val to $15 */
  487. pracc_add(&ctx, 0, MIPS32_ORI(15, 15, LOWER16(val)));
  488. pracc_add(&ctx, 0, MIPS32_MTC0(15, 0, 0) | (cp0_reg << 11) | cp0_sel); /* write cp0 reg / sel */
  489. pracc_add(&ctx, 0, MIPS32_B(NEG16(ctx.code_count + 1))); /* jump to start */
  490. pracc_add(&ctx, 0, MIPS32_MFC0(15, 31, 0)); /* move COP0 DeSave to $15 */
  491. ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, NULL);
  492. exit:
  493. pracc_queue_free(&ctx);
  494. return ctx.retval;
  495. /**
  496. * Note that MIPS32_MTC0 macro is implemented via MIPS32_R_INST macro.
  497. * In order to insert our parameters, we must change rd and funct fields.
  498. * code[3] |= (cp0_reg << 11) | cp0_sel; change rd and funct fields of MIPS32_R_INST macro
  499. **/
  500. }
  501. /**
  502. * \b mips32_pracc_sync_cache
  503. *
  504. * Synchronize Caches to Make Instruction Writes Effective
  505. * (ref. doc. MIPS32 Architecture For Programmers Volume II: The MIPS32 Instruction Set,
  506. * Document Number: MD00086, Revision 2.00, June 9, 2003)
  507. *
  508. * When the instruction stream is written, the SYNCI instruction should be used
  509. * in conjunction with other instructions to make the newly-written instructions effective.
  510. *
  511. * Explanation :
  512. * A program that loads another program into memory is actually writing the D- side cache.
  513. * The instructions it has loaded can't be executed until they reach the I-cache.
  514. *
  515. * After the instructions have been written, the loader should arrange
  516. * to write back any containing D-cache line and invalidate any locations
  517. * already in the I-cache.
  518. *
  519. * You can do that with cache instructions, but those instructions are only available in kernel mode,
  520. * and a loader writing instructions for the use of its own process need not be privileged software.
  521. *
  522. * In the latest MIPS32/64 CPUs, MIPS provides the synci instruction,
  523. * which does the whole job for a cache-line-sized chunk of the memory you just loaded:
  524. * That is, it arranges a D-cache write-back and an I-cache invalidate.
  525. *
  526. * To employ synci at user level, you need to know the size of a cache line,
  527. * and that can be obtained with a rdhwr SYNCI_Step
  528. * from one of the standard “hardware registers”.
  529. */
  530. static int mips32_pracc_sync_cache(struct mips_ejtag *ejtag_info,
  531. uint32_t start_addr, uint32_t end_addr)
  532. {
  533. static const uint32_t code[] = {
  534. /* start: */
  535. MIPS32_MTC0(15, 31, 0), /* move $15 to COP0 DeSave */
  536. MIPS32_LUI(15, UPPER16(MIPS32_PRACC_STACK)), /* $15 = MIPS32_PRACC_STACK */
  537. MIPS32_ORI(15, 15, LOWER16(MIPS32_PRACC_STACK)),
  538. MIPS32_SW(8, 0, 15), /* sw $8,($15) */
  539. MIPS32_SW(9, 0, 15), /* sw $9,($15) */
  540. MIPS32_SW(10, 0, 15), /* sw $10,($15) */
  541. MIPS32_SW(11, 0, 15), /* sw $11,($15) */
  542. MIPS32_LUI(8, UPPER16(MIPS32_PRACC_PARAM_IN)), /* $8 = MIPS32_PRACC_PARAM_IN */
  543. MIPS32_ORI(8, 8, LOWER16(MIPS32_PRACC_PARAM_IN)),
  544. MIPS32_LW(9, 0, 8), /* Load write start_addr to $9 */
  545. MIPS32_LW(10, 4, 8), /* Load write end_addr to $10 */
  546. MIPS32_RDHWR(11, MIPS32_SYNCI_STEP), /* $11 = MIPS32_SYNCI_STEP */
  547. MIPS32_BEQ(11, 0, 6), /* beq $11, $0, end */
  548. MIPS32_NOP,
  549. /* synci_loop : */
  550. MIPS32_SYNCI(0, 9), /* synci 0($9) */
  551. MIPS32_SLTU(8, 10, 9), /* sltu $8, $10, $9 # $8 = $10 < $9 ? 1 : 0 */
  552. MIPS32_BNE(8, 0, NEG16(3)), /* bne $8, $0, synci_loop */
  553. MIPS32_ADDU(9, 9, 11), /* $9 += MIPS32_SYNCI_STEP */
  554. MIPS32_SYNC,
  555. /* end: */
  556. MIPS32_LW(11, 0, 15), /* lw $11,($15) */
  557. MIPS32_LW(10, 0, 15), /* lw $10,($15) */
  558. MIPS32_LW(9, 0, 15), /* lw $9,($15) */
  559. MIPS32_LW(8, 0, 15), /* lw $8,($15) */
  560. MIPS32_B(NEG16(24)), /* b start */
  561. MIPS32_MFC0(15, 31, 0), /* move COP0 DeSave to $15 */
  562. };
  563. /* TODO remove array */
  564. uint32_t *param_in = malloc(2 * sizeof(uint32_t));
  565. int retval;
  566. param_in[0] = start_addr;
  567. param_in[1] = end_addr;
  568. retval = mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code, 2, param_in, 0, NULL, 1);
  569. free(param_in);
  570. return retval;
  571. }
  572. /**
  573. * \b mips32_pracc_clean_invalidate_cache
  574. *
  575. * Writeback D$ and Invalidate I$
  576. * so that the instructions written can be visible to CPU
  577. */
  578. static int mips32_pracc_clean_invalidate_cache(struct mips_ejtag *ejtag_info,
  579. uint32_t start_addr, uint32_t end_addr)
  580. {
  581. static const uint32_t code[] = {
  582. /* start: */
  583. MIPS32_MTC0(15, 31, 0), /* move $15 to COP0 DeSave */
  584. MIPS32_LUI(15, UPPER16(MIPS32_PRACC_STACK)), /* $15 = MIPS32_PRACC_STACK */
  585. MIPS32_ORI(15, 15, LOWER16(MIPS32_PRACC_STACK)),
  586. MIPS32_SW(8, 0, 15), /* sw $8,($15) */
  587. MIPS32_SW(9, 0, 15), /* sw $9,($15) */
  588. MIPS32_SW(10, 0, 15), /* sw $10,($15) */
  589. MIPS32_SW(11, 0, 15), /* sw $11,($15) */
  590. MIPS32_LUI(8, UPPER16(MIPS32_PRACC_PARAM_IN)), /* $8 = MIPS32_PRACC_PARAM_IN */
  591. MIPS32_ORI(8, 8, LOWER16(MIPS32_PRACC_PARAM_IN)),
  592. MIPS32_LW(9, 0, 8), /* Load write start_addr to $9 */
  593. MIPS32_LW(10, 4, 8), /* Load write end_addr to $10 */
  594. MIPS32_LW(11, 8, 8), /* Load write clsiz to $11 */
  595. /* cache_loop: */
  596. MIPS32_SLTU(8, 10, 9), /* sltu $8, $10, $9 : $8 <- $10 < $9 ? */
  597. MIPS32_BGTZ(8, 6), /* bgtz $8, end */
  598. MIPS32_NOP,
  599. MIPS32_CACHE(MIPS32_CACHE_D_HIT_WRITEBACK, 0, 9), /* cache Hit_Writeback_D, 0($9) */
  600. MIPS32_CACHE(MIPS32_CACHE_I_HIT_INVALIDATE, 0, 9), /* cache Hit_Invalidate_I, 0($9) */
  601. MIPS32_ADDU(9, 9, 11), /* $9 += $11 */
  602. MIPS32_B(NEG16(7)), /* b cache_loop */
  603. MIPS32_NOP,
  604. /* end: */
  605. MIPS32_LW(11, 0, 15), /* lw $11,($15) */
  606. MIPS32_LW(10, 0, 15), /* lw $10,($15) */
  607. MIPS32_LW(9, 0, 15), /* lw $9,($15) */
  608. MIPS32_LW(8, 0, 15), /* lw $8,($15) */
  609. MIPS32_B(NEG16(25)), /* b start */
  610. MIPS32_MFC0(15, 31, 0), /* move COP0 DeSave to $15 */
  611. };
  612. /**
  613. * Find cache line size in bytes
  614. */
  615. uint32_t conf;
  616. uint32_t dl, clsiz;
  617. mips32_cp0_read(ejtag_info, &conf, 16, 1);
  618. dl = (conf & MIPS32_CONFIG1_DL_MASK) >> MIPS32_CONFIG1_DL_SHIFT;
  619. /* dl encoding : dl=1 => 4 bytes, dl=2 => 8 bytes, etc... */
  620. clsiz = 0x2 << dl;
  621. /* TODO remove array */
  622. uint32_t *param_in = malloc(3 * sizeof(uint32_t));
  623. int retval;
  624. param_in[0] = start_addr;
  625. param_in[1] = end_addr;
  626. param_in[2] = clsiz;
  627. retval = mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code, 3, param_in, 0, NULL, 1);
  628. free(param_in);
  629. return retval;
  630. }
  631. static int mips32_pracc_write_mem_generic(struct mips_ejtag *ejtag_info, uint32_t addr, int size, int count, void *buf)
  632. {
  633. struct pracc_queue_info ctx = {.max_code = 128 * 3 + 6 + 1}; /* alloc memory for the worst case */
  634. pracc_queue_init(&ctx);
  635. if (ctx.retval != ERROR_OK)
  636. goto exit;
  637. uint32_t *buf32 = buf;
  638. uint16_t *buf16 = buf;
  639. uint8_t *buf8 = buf;
  640. while (count) {
  641. ctx.code_count = 0;
  642. ctx.store_count = 0;
  643. int this_round_count = (count > 128) ? 128 : count;
  644. uint32_t last_upper_base_addr = UPPER16((addr + 0x8000));
  645. pracc_add(&ctx, 0, MIPS32_MTC0(15, 31, 0)); /* save $15 in DeSave */
  646. pracc_add(&ctx, 0, MIPS32_LUI(15, last_upper_base_addr)); /* load $15 with memory base address */
  647. for (int i = 0; i != this_round_count; i++) {
  648. uint32_t upper_base_addr = UPPER16((addr + 0x8000));
  649. if (last_upper_base_addr != upper_base_addr) {
  650. pracc_add(&ctx, 0, MIPS32_LUI(15, upper_base_addr)); /* if needed, change upper address in $15*/
  651. last_upper_base_addr = upper_base_addr;
  652. }
  653. if (size == 4) { /* for word writes check if one half word is 0 and load it accordingly */
  654. if (LOWER16(*buf32) == 0)
  655. pracc_add(&ctx, 0, MIPS32_LUI(8, UPPER16(*buf32))); /* load only upper value */
  656. else if (UPPER16(*buf32) == 0)
  657. pracc_add(&ctx, 0, MIPS32_ORI(8, 0, LOWER16(*buf32))); /* load only lower */
  658. else {
  659. pracc_add(&ctx, 0, MIPS32_LUI(8, UPPER16(*buf32))); /* load upper and lower */
  660. pracc_add(&ctx, 0, MIPS32_ORI(8, 8, LOWER16(*buf32)));
  661. }
  662. pracc_add(&ctx, 0, MIPS32_SW(8, LOWER16(addr), 15)); /* store word to memory */
  663. buf32++;
  664. } else if (size == 2) {
  665. pracc_add(&ctx, 0, MIPS32_ORI(8, 0, *buf16)); /* load lower value */
  666. pracc_add(&ctx, 0, MIPS32_SH(8, LOWER16(addr), 15)); /* store half word to memory */
  667. buf16++;
  668. } else {
  669. pracc_add(&ctx, 0, MIPS32_ORI(8, 0, *buf8)); /* load lower value */
  670. pracc_add(&ctx, 0, MIPS32_SB(8, LOWER16(addr), 15)); /* store byte to memory */
  671. buf8++;
  672. }
  673. addr += size;
  674. }
  675. pracc_add(&ctx, 0, MIPS32_LUI(8, UPPER16(ejtag_info->reg8))); /* restore upper 16 bits of reg 8 */
  676. pracc_add(&ctx, 0, MIPS32_ORI(8, 8, LOWER16(ejtag_info->reg8))); /* restore lower 16 bits of reg 8 */
  677. pracc_add(&ctx, 0, MIPS32_B(NEG16(ctx.code_count + 1))); /* jump to start */
  678. pracc_add(&ctx, 0, MIPS32_MFC0(15, 31, 0)); /* restore $15 from DeSave */
  679. ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, NULL);
  680. if (ctx.retval != ERROR_OK)
  681. goto exit;
  682. count -= this_round_count;
  683. }
  684. exit:
  685. pracc_queue_free(&ctx);
  686. return ctx.retval;
  687. }
  688. int mips32_pracc_write_mem(struct mips_ejtag *ejtag_info, uint32_t addr, int size, int count, void *buf)
  689. {
  690. int retval = mips32_pracc_write_mem_generic(ejtag_info, addr, size, count, buf);
  691. if (retval != ERROR_OK)
  692. return retval;
  693. /**
  694. * If we are in the cachable regoion and cache is activated,
  695. * we must clean D$ + invalidate I$ after we did the write,
  696. * so that changes do not continue to live only in D$, but to be
  697. * replicated in I$ also (maybe we wrote the istructions)
  698. */
  699. uint32_t conf = 0;
  700. int cached = 0;
  701. if ((KSEGX(addr) == KSEG1) || ((addr >= 0xff200000) && (addr <= 0xff3fffff)))
  702. return retval; /*Nothing to do*/
  703. mips32_cp0_read(ejtag_info, &conf, 16, 0);
  704. switch (KSEGX(addr)) {
  705. case KUSEG:
  706. cached = (conf & MIPS32_CONFIG0_KU_MASK) >> MIPS32_CONFIG0_KU_SHIFT;
  707. break;
  708. case KSEG0:
  709. cached = (conf & MIPS32_CONFIG0_K0_MASK) >> MIPS32_CONFIG0_K0_SHIFT;
  710. break;
  711. case KSEG2:
  712. case KSEG3:
  713. cached = (conf & MIPS32_CONFIG0_K23_MASK) >> MIPS32_CONFIG0_K23_SHIFT;
  714. break;
  715. default:
  716. /* what ? */
  717. break;
  718. }
  719. /**
  720. * Check cachablitiy bits coherency algorithm -
  721. * is the region cacheable or uncached.
  722. * If cacheable we have to synchronize the cache
  723. */
  724. if (cached == 0x3) {
  725. uint32_t start_addr, end_addr;
  726. uint32_t rel;
  727. start_addr = addr;
  728. end_addr = addr + count * size;
  729. /** select cache synchronisation mechanism based on Architecture Release */
  730. rel = (conf & MIPS32_CONFIG0_AR_MASK) >> MIPS32_CONFIG0_AR_SHIFT;
  731. switch (rel) {
  732. case MIPS32_ARCH_REL1:
  733. /* MIPS32/64 Release 1 - we must use cache instruction */
  734. mips32_pracc_clean_invalidate_cache(ejtag_info, start_addr, end_addr);
  735. break;
  736. case MIPS32_ARCH_REL2:
  737. /* MIPS32/64 Release 2 - we can use synci instruction */
  738. mips32_pracc_sync_cache(ejtag_info, start_addr, end_addr);
  739. break;
  740. default:
  741. /* what ? */
  742. break;
  743. }
  744. }
  745. return retval;
  746. }
  747. int mips32_pracc_write_regs(struct mips_ejtag *ejtag_info, uint32_t *regs)
  748. {
  749. static const uint32_t cp0_write_code[] = {
  750. MIPS32_MTC0(1, 12, 0), /* move $1 to status */
  751. MIPS32_MTLO(1), /* move $1 to lo */
  752. MIPS32_MTHI(1), /* move $1 to hi */
  753. MIPS32_MTC0(1, 8, 0), /* move $1 to badvaddr */
  754. MIPS32_MTC0(1, 13, 0), /* move $1 to cause*/
  755. MIPS32_MTC0(1, 24, 0), /* move $1 to depc (pc) */
  756. };
  757. struct pracc_queue_info ctx = {.max_code = 37 * 2 + 6 + 1};
  758. pracc_queue_init(&ctx);
  759. if (ctx.retval != ERROR_OK)
  760. goto exit;
  761. /* load registers 2 to 31 with lui and ori instructions, check if some instructions can be saved */
  762. for (int i = 2; i < 32; i++) {
  763. if (LOWER16((regs[i])) == 0) /* if lower half word is 0, lui instruction only */
  764. pracc_add(&ctx, 0, MIPS32_LUI(i, UPPER16((regs[i]))));
  765. else if (UPPER16((regs[i])) == 0) /* if upper half word is 0, ori with $0 only*/
  766. pracc_add(&ctx, 0, MIPS32_ORI(i, 0, LOWER16((regs[i]))));
  767. else { /* default, load with lui and ori instructions */
  768. pracc_add(&ctx, 0, MIPS32_LUI(i, UPPER16((regs[i]))));
  769. pracc_add(&ctx, 0, MIPS32_ORI(i, i, LOWER16((regs[i]))));
  770. }
  771. }
  772. for (int i = 0; i != 6; i++) {
  773. pracc_add(&ctx, 0, MIPS32_LUI(1, UPPER16((regs[i + 32])))); /* load CPO value in $1, with lui and ori */
  774. pracc_add(&ctx, 0, MIPS32_ORI(1, 1, LOWER16((regs[i + 32]))));
  775. pracc_add(&ctx, 0, cp0_write_code[i]); /* write value from $1 to CPO register */
  776. }
  777. pracc_add(&ctx, 0, MIPS32_LUI(1, UPPER16((regs[1])))); /* load upper half word in $1 */
  778. pracc_add(&ctx, 0, MIPS32_B(NEG16(ctx.code_count + 1))); /* jump to start */
  779. pracc_add(&ctx, 0, MIPS32_ORI(1, 1, LOWER16((regs[1])))); /* load lower half word in $1 */
  780. ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, NULL);
  781. ejtag_info->reg8 = regs[8];
  782. ejtag_info->reg9 = regs[9];
  783. exit:
  784. pracc_queue_free(&ctx);
  785. return ctx.retval;
  786. }
  787. int mips32_pracc_read_regs(struct mips_ejtag *ejtag_info, uint32_t *regs)
  788. {
  789. static int cp0_read_code[] = {
  790. MIPS32_MFC0(8, 12, 0), /* move status to $8 */
  791. MIPS32_MFLO(8), /* move lo to $8 */
  792. MIPS32_MFHI(8), /* move hi to $8 */
  793. MIPS32_MFC0(8, 8, 0), /* move badvaddr to $8 */
  794. MIPS32_MFC0(8, 13, 0), /* move cause to $8 */
  795. MIPS32_MFC0(8, 24, 0), /* move depc (pc) to $8 */
  796. };
  797. struct pracc_queue_info ctx = {.max_code = 48};
  798. pracc_queue_init(&ctx);
  799. if (ctx.retval != ERROR_OK)
  800. goto exit;
  801. pracc_add(&ctx, 0, MIPS32_MTC0(1, 31, 0)); /* move $1 to COP0 DeSave */
  802. pracc_add(&ctx, 0, MIPS32_LUI(1, PRACC_UPPER_BASE_ADDR)); /* $1 = MIP32_PRACC_BASE_ADDR */
  803. for (int i = 2; i != 32; i++) /* store GPR's 2 to 31 */
  804. pracc_add(&ctx, MIPS32_PRACC_PARAM_OUT + (i * 4),
  805. MIPS32_SW(i, PRACC_OUT_OFFSET + (i * 4), 1));
  806. for (int i = 0; i != 6; i++) {
  807. pracc_add(&ctx, 0, cp0_read_code[i]); /* load COP0 needed registers to $8 */
  808. pracc_add(&ctx, MIPS32_PRACC_PARAM_OUT + (i + 32) * 4, /* store $8 at PARAM OUT */
  809. MIPS32_SW(8, PRACC_OUT_OFFSET + (i + 32) * 4, 1));
  810. }
  811. pracc_add(&ctx, 0, MIPS32_MFC0(8, 31, 0)); /* move DeSave to $8, reg1 value */
  812. pracc_add(&ctx, MIPS32_PRACC_PARAM_OUT + 4, /* store reg1 value from $8 to param out */
  813. MIPS32_SW(8, PRACC_OUT_OFFSET + 4, 1));
  814. pracc_add(&ctx, 0, MIPS32_B(NEG16(ctx.code_count + 1))); /* jump to start */
  815. pracc_add(&ctx, 0, MIPS32_MFC0(1, 31, 0)); /* move COP0 DeSave to $1, restore reg1 */
  816. if (ejtag_info->mode == 0)
  817. ctx.store_count++; /* Needed by legacy code, due to offset from reg0 */
  818. ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, regs);
  819. ejtag_info->reg8 = regs[8]; /* reg8 is saved but not restored, next called function should restore it */
  820. ejtag_info->reg9 = regs[9];
  821. exit:
  822. pracc_queue_free(&ctx);
  823. return ctx.retval;
  824. }
  825. /* fastdata upload/download requires an initialized working area
  826. * to load the download code; it should not be called otherwise
  827. * fetch order from the fastdata area
  828. * 1. start addr
  829. * 2. end addr
  830. * 3. data ...
  831. */
  832. int mips32_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info, struct working_area *source,
  833. int write_t, uint32_t addr, int count, uint32_t *buf)
  834. {
  835. uint32_t handler_code[] = {
  836. /* caution when editing, table is modified below */
  837. /* r15 points to the start of this code */
  838. MIPS32_SW(8, MIPS32_FASTDATA_HANDLER_SIZE - 4, 15),
  839. MIPS32_SW(9, MIPS32_FASTDATA_HANDLER_SIZE - 8, 15),
  840. MIPS32_SW(10, MIPS32_FASTDATA_HANDLER_SIZE - 12, 15),
  841. MIPS32_SW(11, MIPS32_FASTDATA_HANDLER_SIZE - 16, 15),
  842. /* start of fastdata area in t0 */
  843. MIPS32_LUI(8, UPPER16(MIPS32_PRACC_FASTDATA_AREA)),
  844. MIPS32_ORI(8, 8, LOWER16(MIPS32_PRACC_FASTDATA_AREA)),
  845. MIPS32_LW(9, 0, 8), /* start addr in t1 */
  846. MIPS32_LW(10, 0, 8), /* end addr to t2 */
  847. /* loop: */
  848. /* 8 */ MIPS32_LW(11, 0, 0), /* lw t3,[t8 | r9] */
  849. /* 9 */ MIPS32_SW(11, 0, 0), /* sw t3,[r9 | r8] */
  850. MIPS32_BNE(10, 9, NEG16(3)), /* bne $t2,t1,loop */
  851. MIPS32_ADDI(9, 9, 4), /* addi t1,t1,4 */
  852. MIPS32_LW(8, MIPS32_FASTDATA_HANDLER_SIZE - 4, 15),
  853. MIPS32_LW(9, MIPS32_FASTDATA_HANDLER_SIZE - 8, 15),
  854. MIPS32_LW(10, MIPS32_FASTDATA_HANDLER_SIZE - 12, 15),
  855. MIPS32_LW(11, MIPS32_FASTDATA_HANDLER_SIZE - 16, 15),
  856. MIPS32_LUI(15, UPPER16(MIPS32_PRACC_TEXT)),
  857. MIPS32_ORI(15, 15, LOWER16(MIPS32_PRACC_TEXT)),
  858. MIPS32_JR(15), /* jr start */
  859. MIPS32_MFC0(15, 31, 0), /* move COP0 DeSave to $15 */
  860. };
  861. uint32_t jmp_code[] = {
  862. MIPS32_MTC0(15, 31, 0), /* move $15 to COP0 DeSave */
  863. /* 1 */ MIPS32_LUI(15, 0), /* addr of working area added below */
  864. /* 2 */ MIPS32_ORI(15, 15, 0), /* addr of working area added below */
  865. MIPS32_JR(15), /* jump to ram program */
  866. MIPS32_NOP,
  867. };
  868. int retval, i;
  869. uint32_t val, ejtag_ctrl, address;
  870. if (source->size < MIPS32_FASTDATA_HANDLER_SIZE)
  871. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  872. if (write_t) {
  873. handler_code[8] = MIPS32_LW(11, 0, 8); /* load data from probe at fastdata area */
  874. handler_code[9] = MIPS32_SW(11, 0, 9); /* store data to RAM @ r9 */
  875. } else {
  876. handler_code[8] = MIPS32_LW(11, 0, 9); /* load data from RAM @ r9 */
  877. handler_code[9] = MIPS32_SW(11, 0, 8); /* store data to probe at fastdata area */
  878. }
  879. /* write program into RAM */
  880. if (write_t != ejtag_info->fast_access_save) {
  881. mips32_pracc_write_mem_generic(ejtag_info, source->address, 4, ARRAY_SIZE(handler_code), handler_code);
  882. /* save previous operation to speed to any consecutive read/writes */
  883. ejtag_info->fast_access_save = write_t;
  884. }
  885. LOG_DEBUG("%s using 0x%.8" PRIx32 " for write handler", __func__, source->address);
  886. jmp_code[1] |= UPPER16(source->address);
  887. jmp_code[2] |= LOWER16(source->address);
  888. for (i = 0; i < (int) ARRAY_SIZE(jmp_code); i++) {
  889. retval = wait_for_pracc_rw(ejtag_info, &ejtag_ctrl);
  890. if (retval != ERROR_OK)
  891. return retval;
  892. mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA);
  893. mips_ejtag_drscan_32_out(ejtag_info, jmp_code[i]);
  894. /* Clear the access pending bit (let the processor eat!) */
  895. ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_PRACC;
  896. mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
  897. mips_ejtag_drscan_32_out(ejtag_info, ejtag_ctrl);
  898. }
  899. /* wait PrAcc pending bit for FASTDATA write */
  900. retval = wait_for_pracc_rw(ejtag_info, &ejtag_ctrl);
  901. if (retval != ERROR_OK)
  902. return retval;
  903. /* next fetch to dmseg should be in FASTDATA_AREA, check */
  904. address = 0;
  905. mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS);
  906. retval = mips_ejtag_drscan_32(ejtag_info, &address);
  907. if (retval != ERROR_OK)
  908. return retval;
  909. if (address != MIPS32_PRACC_FASTDATA_AREA)
  910. return ERROR_FAIL;
  911. /* Send the load start address */
  912. val = addr;
  913. mips_ejtag_set_instr(ejtag_info, EJTAG_INST_FASTDATA);
  914. mips_ejtag_fastdata_scan(ejtag_info, 1, &val);
  915. retval = wait_for_pracc_rw(ejtag_info, &ejtag_ctrl);
  916. if (retval != ERROR_OK)
  917. return retval;
  918. /* Send the load end address */
  919. val = addr + (count - 1) * 4;
  920. mips_ejtag_set_instr(ejtag_info, EJTAG_INST_FASTDATA);
  921. mips_ejtag_fastdata_scan(ejtag_info, 1, &val);
  922. unsigned num_clocks = 0; /* like in legacy code */
  923. if (ejtag_info->mode != 0)
  924. num_clocks = ((uint64_t)(ejtag_info->scan_delay) * jtag_get_speed_khz() + 500000) / 1000000;
  925. for (i = 0; i < count; i++) {
  926. jtag_add_clocks(num_clocks);
  927. retval = mips_ejtag_fastdata_scan(ejtag_info, write_t, buf++);
  928. if (retval != ERROR_OK)
  929. return retval;
  930. }
  931. retval = jtag_execute_queue();
  932. if (retval != ERROR_OK) {
  933. LOG_ERROR("fastdata load failed");
  934. return retval;
  935. }
  936. retval = wait_for_pracc_rw(ejtag_info, &ejtag_ctrl);
  937. if (retval != ERROR_OK)
  938. return retval;
  939. address = 0;
  940. mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS);
  941. retval = mips_ejtag_drscan_32(ejtag_info, &address);
  942. if (retval != ERROR_OK)
  943. return retval;
  944. if (address != MIPS32_PRACC_TEXT)
  945. LOG_ERROR("mini program did not return to start");
  946. return retval;
  947. }