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  1. # Cogent CSB337
  2. # http://cogcomp.com/csb_csb337.htm
  3. source [find target/at91rm9200.cfg]
  4. # boots from NOR on CS0: 8 MBytes CFI flash, 16-bit bus
  5. set _FLASHNAME $_CHIPNAME.flash
  6. flash bank $_FLASHNAME cfi 0x10000000 0x00800000 2 2 $_TARGETNAME
  7. # ETM9 trace port connector present on this board, 16 data pins.
  8. if { [info exists ETM_DRIVER] } {
  9. etm config $_TARGETNAME 16 normal half $ETM_DRIVER
  10. # OpenOCD may someday support a real trace port driver...
  11. # system config file would need to configure it.
  12. } else {
  13. etm config $_TARGETNAME 16 normal half dummy
  14. etm_dummy config $_TARGETNAME
  15. }
  16. proc csb337_clk_init { } {
  17. # CPU is in Slow Clock Mode (32KiHz) ... needs slow JTAG clock
  18. adapter_khz 8
  19. # CKGR_MOR: start main oscillator (3.6864 MHz)
  20. mww 0xfffffc20 0xff01
  21. sleep 10
  22. # CKGR_PLLAR: start PLL A for CPU and peripherals (184.32 MHz)
  23. mww 0xfffffc28 0x20313e01
  24. # CKGR_PLLBR: start PLL B for USB timing (96 MHz, with div2)
  25. mww 0xfffffc2c 0x12703e18
  26. # let PLLs lock
  27. sleep 10
  28. # PMC_MCKR: switch to CPU clock = PLLA, master clock = CPU/4
  29. mww 0xfffffc30 0x0302
  30. sleep 20
  31. # CPU is in Normal Mode ... allows faster JTAG clock speed
  32. adapter_khz 40000
  33. }
  34. proc csb337_nor_init { } {
  35. # SMC_CSR0: adjust timings (10 wait states)
  36. mww 0xffffff70 0x1100318a
  37. flash probe 0
  38. }
  39. proc csb337_sdram_init { } {
  40. # enable PIOC clock
  41. mww 0xfffffc10 0x0010
  42. # PC31..PC16 are D31..D16, with internal pullups like D15..D0
  43. mww 0xfffff870 0xffff0000
  44. mww 0xfffff874 0x0
  45. mww 0xfffff804 0xffff0000
  46. # SDRC_CR: set timings
  47. mww 0xffffff98 0x2188b0d5
  48. # SDRC_MR: issue all banks precharge to SDRAM
  49. mww 0xffffff90 2
  50. mww 0x20000000 0
  51. # SDRC_MR: 8 autorefresh cycles
  52. mww 0xffffff90 4
  53. mww 0x20000000 0
  54. mww 0x20000000 0
  55. mww 0x20000000 0
  56. mww 0x20000000 0
  57. mww 0x20000000 0
  58. mww 0x20000000 0
  59. mww 0x20000000 0
  60. mww 0x20000000 0
  61. # SDRC_MR: set SDRAM mode registers (CAS, burst len, etc)
  62. mww 0xffffff90 3
  63. mww 0x20000080 0
  64. # SDRC_TR: set refresh rate
  65. mww 0xffffff94 0x200
  66. mww 0x20000000 0
  67. # SDRC_MR: normal mode, 32 bit bus
  68. mww 0xffffff90 0
  69. mww 0x20000000 0
  70. }
  71. # The rm9200 chip has just been reset. Bring it up far enough
  72. # that we can write flash or run code from SDRAM.
  73. proc csb337_reset_init { } {
  74. csb337_clk_init
  75. # EBI_CSA: CS0 = NOR, CS1 = SDRAM
  76. mww 0xffffff60 0x02
  77. csb337_nor_init
  78. csb337_sdram_init
  79. # Update CP15 control register ... we don't seem to be able to
  80. # read/modify/write its value through a TCL variable, so just
  81. # write it. Fields are zero unless listed here ... and note
  82. # that OpenOCD numbers this register "2", not "1" (!).
  83. #
  84. # - Core to use Async Clocking mode (so it uses 184 MHz most
  85. # of the time instead of limiting to the master clock rate):
  86. # iA(31) = 1, nF(30) = 1
  87. # - Icache on (it's disabled now, slowing i-fetches)
  88. # I(12) = 1
  89. # - Reserved/ones
  90. # 6:3 = 1
  91. arm920t cp15 2 0xc0001078
  92. }
  93. $_TARGETNAME configure -event reset-init {csb337_reset_init}
  94. arm7_9 fast_memory_access enable