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  1. #-------------------------------------------------------------------------
  2. # Mini2440 Samsung s3c2440A Processor with 64MB DRAM, 64MB NAND, 2 MB N0R
  3. # NOTE: Configured for NAND boot (switch S2 in NANDBOOT)
  4. # 64 MB NAND (Samsung K9D1208V0M)
  5. # B Findlay 08/09
  6. #
  7. # ----------- Important notes to help you on your way ----------
  8. # README:
  9. # NOR/NAND Boot Switch - I have not read the vivi source, but from
  10. # what I could tell from reading the registers it appears that vivi
  11. # loads itself into DRAM and then flips NFCONT (0x4E000004) bits
  12. # Mode (bit 0 = 1), and REG_nCE (bit 1 = 0) which maps the NAND
  13. # FLASH at the bottom 64MB of memory. This essentially takes the
  14. # NOR Flash out of the circuit so you can't trash it.
  15. #
  16. # I adapted the samsung_s3c2440.cfg file which is why I did not
  17. # include "source [find target/samsung_s3c2440.cfg]". I believe
  18. # the -work-area-phys 0x200000 is incorrect, but also had to pad
  19. # some additional resets. I didn't modify it as if it is working
  20. # for someone, the work-area-phys is not used by most.
  21. #
  22. # JTAG ADAPTER SPECIFIC
  23. # IMPORTANT! Any JTAG device that uses ADAPTIVE CLOCKING will likely
  24. # FAIL as the pin RTCK on the mini2440 10 pin JTAG Conn doesn't exist.
  25. # This is Pin 11 (RTCK) on 20 pin JTAG connector. Therefore it is
  26. # necessary to FORCE setting the clock. Normally this should be configured
  27. # in the openocd.cfg file, but was placed here as it can be a tough
  28. # problem to figure out. THIS MAY NOT FIX YOUR PROBLEM.. I modified
  29. # the openOCD driver jlink.c and posted it here. It may eventually end
  30. # up changed in openOCD, but its a hack in the driver and really should
  31. # be in the jtag layer (core.c me thinks), but haven't done it yet. My
  32. # hack for jlink.c may be found here.
  33. #
  34. # http://forum.sparkfun.com/viewtopic.php?t=16763&sid=946e65abdd3bab39cc7d90dee33ff135
  35. #
  36. # Note: Also if you have a USB JTAG, you will need the USB library installed
  37. # on your system "libusb-dev" or the make of openocd will fail. I *think*
  38. # it's apt-get install libusb-dev. When I made my config I only included
  39. # --enable-jlink and --enable-usbdevs
  40. #
  41. # I HAVE NOT Tested this throughly, so there could still be problems.
  42. # But it should get you way ahead of the game from where I started.
  43. # If you find problems (and fixes) please post them to
  44. # openocd-development@lists.berlios.de and join the developers and
  45. # check in fixes to this and anything else you find. I do not
  46. # provide support, but if you ask really nice and I see anything
  47. # obvious I will tell you.. mostly just dig, fix, and submit to openocd.
  48. #
  49. # best! brfindla@yahoo.com Nashua, NH USA
  50. #
  51. # Recommended resources:
  52. # - first two are the best Mini2440 resources anywhere
  53. # - maintained by buserror... thanks guy!
  54. #
  55. # http://bliterness.blogspot.com/
  56. # http://code.google.com/p/mini2440/
  57. #
  58. # others....
  59. #
  60. # http://forum.sparkfun.com/viewforum.php?f=18
  61. # http://labs.kernelconcepts.de/Publications/Micro24401/
  62. # http://www.friendlyarm.net/home
  63. # http://www.amontec.com/jtag_pinout.shtml
  64. #
  65. #-------------------------------------------------------------------------
  66. #
  67. #
  68. # Your openocd.cfg file should contain:
  69. # source [find interface/<yourjtag>.cfg]
  70. # source [find board/mini2440.cfg]
  71. #
  72. #
  73. #
  74. # FIXME use some standard target config, maybe create one from this
  75. #
  76. # source [find target/...cfg]
  77. #-------------------------------------------------------------------------
  78. # Target configuration for the Samsung 2440 system on chip
  79. # Tested on a S3C2440 Evaluation board by keesj
  80. # Processor : ARM920Tid(wb) rev 0 (v4l)
  81. # Info: JTAG tap: s3c2440.cpu tap/device found: 0x0032409d
  82. # (Manufacturer: 0x04e, Part: 0x0324, Version: 0x0)
  83. #-------------------------------------------------------------------------
  84. if { [info exists CHIPNAME] } {
  85. set _CHIPNAME $CHIPNAME
  86. } else {
  87. set _CHIPNAME s3c2440
  88. }
  89. if { [info exists ENDIAN] } {
  90. set _ENDIAN $ENDIAN
  91. } else {
  92. # this defaults to a bigendian
  93. set _ENDIAN little
  94. }
  95. if { [info exists CPUTAPID ] } {
  96. set _CPUTAPID $CPUTAPID
  97. } else {
  98. # force an error till we get a good number
  99. set _CPUTAPID 0x0032409d
  100. }
  101. #jtag scan chain
  102. jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_CPUTAPID
  103. set _TARGETNAME $_CHIPNAME.cpu
  104. target create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME
  105. $_TARGETNAME configure -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 1
  106. #reset configuration
  107. jtag_nsrst_delay 100
  108. jtag_ntrst_delay 100
  109. reset_config trst_and_srst
  110. #-------------------------------------------------------------------------
  111. # JTAG ADAPTER SPECIFIC
  112. # IMPORTANT! See README at top of this file.
  113. #-------------------------------------------------------------------------
  114. adapter_khz 12000
  115. jtag interface
  116. #-------------------------------------------------------------------------
  117. # GDB Setup
  118. #-------------------------------------------------------------------------
  119. gdb_breakpoint_override hard
  120. #------------------------------------------------
  121. # ARM SPECIFIC
  122. #------------------------------------------------
  123. targets
  124. # arm7_9 dcc_downloads enable
  125. # arm7_9 fast_memory_access enable
  126. nand device s3c2440 0
  127. jtag_nsrst_delay 100
  128. jtag_ntrst_delay 100
  129. reset_config trst_and_srst
  130. init
  131. echo " "
  132. echo "-------------------------------------------"
  133. echo "--- login with - telnet localhost 4444 ---"
  134. echo "--- then type help_2440 ---"
  135. echo "-------------------------------------------"
  136. echo " "
  137. #------------------------------------------------
  138. # Processor Initialialization
  139. # Note: Processor writes can only occur when
  140. # the state is in SYSTEM. When you call init_2440
  141. # one of the first lines will tell you what state
  142. # you are in. If a linux image is booting
  143. # when you run this, it will not work
  144. # a vivi boot loader will run with this just
  145. # fine. The reg values were obtained by a combination
  146. # of figuring them out fromt the manual, and looking
  147. # at post vivi values with the debugger. Don't
  148. # place too much faith in them, but seem to work.
  149. #------------------------------------------------
  150. proc init_2440 { } {
  151. halt
  152. s3c2440.cpu curstate
  153. #-----------------------------------------------
  154. # Set Processor Clocks - mini2440 xtal=12mHz
  155. # we set main clock for 405mHZ
  156. # we set the USB Clock for 48mHz
  157. # OM2 OM3 pulled to ground so main clock and
  158. # usb clock are off 12mHz xtal
  159. #-----------------------------------------------
  160. mww phys 0x4C000014 0x00000005 # Clock Divider control Reg
  161. mww phys 0x4C000000 0xFFFFFFFF # LOCKTIME count register
  162. mww phys 0x4C000008 0x00038022 # UPPLCON USB clock config Reg
  163. mww phys 0x4C000004 0x0007F021 # MPPLCON Proc clock config Reg
  164. #-----------------------------------------------
  165. # Configure Memory controller
  166. # BWSCON configures all banks, NAND, NOR, DRAM
  167. # DRAM - 64MB - 32 bit bus, uses BANKCON6 BANKCON7
  168. #-----------------------------------------------
  169. mww phys 0x48000000 0x22111112 # BWSCON - Bank and Bus Width
  170. mww phys 0x48000010 0x00001112 # BANKCON4 - ?
  171. mww phys 0x4800001c 0x00018009 # BANKCON6 - DRAM
  172. mww phys 0x48000020 0x00018009 # BANKCON7 - DRAM
  173. mww phys 0x48000024 0x008E04EB # REFRESH - DRAM
  174. mww phys 0x48000028 0x000000B2 # BANKSIZE - DRAM
  175. mww phys 0x4800002C 0x00000030 # MRSRB6 - DRAM
  176. mww phys 0x48000030 0x00000030 # MRSRB7 - DRAM
  177. #-----------------------------------------------
  178. # Now port configuration for enables for memory
  179. # and other stuff.
  180. #-----------------------------------------------
  181. mww phys 0x56000000 0x007FFFFF # GPACON
  182. mww phys 0x56000010 0x00295559 # GPBCON
  183. mww phys 0x56000018 0x000003FF # GPBUP (PULLUP ENABLE)
  184. mww phys 0x56000014 0x000007C2 # GPBDAT
  185. mww phys 0x56000020 0xAAAAA6AA # GPCCON
  186. mww phys 0x56000028 0x0000FFFF # GPCUP
  187. mww phys 0x56000024 0x00000020 # GPCDAT
  188. mww phys 0x56000030 0xAAAAAAAA # GPDCON
  189. mww phys 0x56000038 0x0000FFFF # GPDUP
  190. mww phys 0x56000040 0xAAAAAAAA # GPECON
  191. mww phys 0x56000048 0x0000FFFF # GPEUP
  192. mww phys 0x56000050 0x00001555 # GPFCON
  193. mww phys 0x56000058 0x0000007F # GPFUP
  194. mww phys 0x56000054 0x00000000 # GPFDAT
  195. mww phys 0x56000060 0x00150114 # GPGCON
  196. mww phys 0x56000068 0x0000007F # GPGUP
  197. mww phys 0x56000070 0x0015AAAA # GPHCON
  198. mww phys 0x56000078 0x000003FF # GPGUP
  199. }
  200. proc flash_config { } {
  201. #-----------------------------------------
  202. # Finish Flash Configuration
  203. #-----------------------------------------
  204. halt
  205. #flash configuration (K9D1208V0M: 512Mbit, x8, 3.3V, Mode: Normal, 1st gen)
  206. nand probe 0
  207. nand list
  208. }
  209. proc flash_uboot { } {
  210. # flash the u-Boot binary and reboot into it
  211. init_2440
  212. flash_config
  213. nand erase 0 0x0 0x40000
  214. nand write 0 /tftpboot/u-boot-nand512.bin 0 oob_softecc_kw
  215. resume
  216. }
  217. proc load_uboot { } {
  218. echo " "
  219. echo " "
  220. echo "----------------------------------------------------------"
  221. echo "---- Load U-Boot into RAM and execute it. ---"
  222. echo "---- NOTE: loads, partially runs, and hangs ---"
  223. echo "---- U-Boot is fine, this image runs from vivi. ---"
  224. echo "---- I burned u-boot into NAND so I didn't finish ---"
  225. echo "---- debugging it. I am leaving this here as it is ---"
  226. echo "---- part of the way there if you want to fix it. ---"
  227. echo "---- ---"
  228. echo "---- mini2440 U-boot here: ---"
  229. echo "---- http://repo.or.cz/w/u-boot-openmoko/mini2440.git ---"
  230. echo "---- Also this: ---"
  231. echo "---- http://code.google.com/p/mini2440/wiki/MiniBringup --"
  232. echo "----------------------------------------------------------"
  233. init_2440
  234. echo "Loading /tftpboot/u-boot-nand512.bin"
  235. load_image /tftpboot/u-boot-nand512.bin 0x33f80000 bin
  236. echo "Verifying image...."
  237. verify_image /tftpboot/u-boot-nand512.bin 0x33f80000 bin
  238. echo "jumping to u-boot"
  239. #bp 0x33f80068 4 hw
  240. reg 0 0
  241. reg 1 0
  242. reg 2 0
  243. reg 3 0
  244. reg 4 0x33f80000
  245. resume 0x33f80000
  246. }
  247. # this may help a little bit debugging the load_uboot
  248. proc s {} {
  249. step
  250. reg
  251. arm disassemble 0x33F80068 0x10
  252. }
  253. proc help_2440 {} {
  254. echo " "
  255. echo " "
  256. echo "-----------------------------------------------------------"
  257. echo "---- The following mini2440 funcs are supported ----"
  258. echo "---- init_2440 - initialize clocks, DRAM, IO ----"
  259. echo "---- flash_config - configures nand flash ----"
  260. echo "---- load_uboot - loads uboot into ram ----"
  261. echo "---- flash_uboot - flashes uboot to nand (untested) ----"
  262. echo "---- help_2440 - this help display ----"
  263. echo "-----------------------------------------------------------"
  264. echo " "
  265. echo " "
  266. }
  267. #----------------------------------------------------------------------------
  268. #----------------------------------- END ------------------------------------
  269. #----------------------------------------------------------------------------