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60 lines
1.4 KiB

  1. # PXA255 chip ... originally from Intel, PXA line was sold to Marvell.
  2. # This chip is now at end-of-life. Final orders have been taken.
  3. if { [info exists CHIPNAME] } {
  4. set _CHIPNAME $CHIPNAME
  5. } else {
  6. set _CHIPNAME pxa255
  7. }
  8. if { [info exists ENDIAN] } {
  9. set _ENDIAN $ENDIAN
  10. } else {
  11. set _ENDIAN little
  12. }
  13. if { [info exists CPUTAPID ] } {
  14. set _CPUTAPID $CPUTAPID
  15. } else {
  16. set _CPUTAPID 0x69264013
  17. }
  18. jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $_CPUTAPID
  19. set _TARGETNAME $_CHIPNAME.cpu
  20. target create $_TARGETNAME xscale -endian $_ENDIAN \
  21. -chain-position $_CHIPNAME.cpu
  22. # PXA255 comes out of reset using 3.6864 MHz oscillator.
  23. # Until the PLL kicks in, keep the JTAG clock slow enough
  24. # that we get no errors.
  25. adapter_khz 300
  26. $_TARGETNAME configure -event "reset-start" { adapter_khz 300 }
  27. # both TRST and SRST are *required* for debug
  28. # DCSR is often accessed with SRST active
  29. reset_config trst_and_srst separate srst_nogate
  30. # reset processing that works with PXA
  31. proc init_reset {mode} {
  32. # assert both resets; equivalent to power-on reset
  33. jtag_reset 1 1
  34. # drop TRST after at least 32 cycles
  35. sleep 1
  36. jtag_reset 0 1
  37. # minimum 32 TCK cycles to wake up the controller
  38. runtest 50
  39. # now the TAP will be responsive; validate scanchain
  40. jtag arp_init
  41. # ... and take it out of reset
  42. jtag_reset 0 0
  43. }
  44. proc jtag_init {} {
  45. init_reset startup
  46. }