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  1. # Texas Instruments OMAP 2420
  2. # http://www.ti.com/omap
  3. if { [info exists CHIPNAME] } {
  4. set _CHIPNAME $CHIPNAME
  5. } else {
  6. set _CHIPNAME omap2420
  7. }
  8. # NOTE: likes slowish clock on reset (1.5 MBit/s or less) or use RCLK
  9. reset_config srst_nogate
  10. # Subsidiary TAP: ARM7TDMIr4 plus imaging ... must add via ICEpick (addr 6).
  11. jtag newtap $_CHIPNAME iva -irlen 4 -disable
  12. # Subsidiary TAP: C55x DSP ... must add via ICEpick (addr 2).
  13. jtag newtap $_CHIPNAME dsp -irlen 38 -disable
  14. # Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer
  15. if { [info exists ETB_TAPID ] } {
  16. set _ETB_TAPID $ETB_TAPID
  17. } else {
  18. set _ETB_TAPID 0x2b900f0f
  19. }
  20. jtag newtap $_CHIPNAME etb -irlen 4 -expected-id $_ETB_TAPID
  21. # Subsidiary TAP: ARM1136jf-s with scan chains for ARM Debug, EmbeddedICE-RT, ETM.
  22. if { [info exists CPU_TAPID ] } {
  23. set _CPU_TAPID $CPU_TAPID
  24. } else {
  25. set _CPU_TAPID 0x07b3602f
  26. }
  27. jtag newtap $_CHIPNAME arm -irlen 5 -expected-id $_CPU_TAPID
  28. # Primary TAP: ICEpick-B (JTAG route controller) and boundary scan
  29. if { [info exists JRC_TAPID ] } {
  30. set _JRC_TAPID $JRC_TAPID
  31. } else {
  32. set _JRC_TAPID 0x01ce4801
  33. }
  34. jtag newtap $_CHIPNAME jrc -irlen 2 -expected-id $_JRC_TAPID
  35. # GDB target: the ARM.
  36. set _TARGETNAME $_CHIPNAME.arm
  37. target create $_TARGETNAME arm11 -chain-position $_TARGETNAME
  38. # scratch: framebuffer, may be initially unavailable in some chips
  39. $_TARGETNAME configure -work-area-phys 0x40210000
  40. $_TARGETNAME configure -work-area-size 0x00081000
  41. $_TARGETNAME configure -work-area-backup 0
  42. # trace setup
  43. # REVISIT ... as of 12-June-2009, OpenOCD's ETM code can't talk to ARM11 cores.
  44. #etm config $_TARGETNAME 16 normal full etb
  45. #etb config $_TARGETNAME $_CHIPNAME.etb