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  1. # TI OMAP3530
  2. # http://focus.ti.com/docs/prod/folders/print/omap3530.html
  3. # Other OMAP3 chips remove DSP and/or the OpenGL support
  4. if { [info exists CHIPNAME] } {
  5. set _CHIPNAME $CHIPNAME
  6. } else {
  7. set _CHIPNAME omap3530
  8. }
  9. # ICEpick-C ... used to route Cortex, DSP, and more not shown here
  10. source [find target/icepick.cfg]
  11. # Subsidiary TAP: C64x+ DSP ... must enable via ICEpick
  12. jtag newtap $_CHIPNAME dsp -irlen 38 -ircapture 0x25 -irmask 0x3f -disable
  13. # Subsidiary TAP: CoreSight Debug Access Port (DAP)
  14. if { [info exists DAP_TAPID ] } {
  15. set _DAP_TAPID $DAP_TAPID
  16. } else {
  17. set _DAP_TAPID 0x0b6d602f
  18. }
  19. jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf \
  20. -expected-id $_DAP_TAPID -disable
  21. jtag configure $_CHIPNAME.dap -event tap-enable \
  22. "icepick_c_tapenable $_CHIPNAME.jrc 3"
  23. # Primary TAP: ICEpick-C (JTAG route controller) and boundary scan
  24. if { [info exists JRC_TAPID ] } {
  25. set _JRC_TAPID $JRC_TAPID
  26. } else {
  27. set _JRC_TAPID 0x0b7ae02f
  28. }
  29. jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
  30. -expected-id $_JRC_TAPID
  31. # GDB target: Cortex-A8, using DAP
  32. set _TARGETNAME $_CHIPNAME.cpu
  33. target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.dap
  34. ###################
  35. # the reset sequence is event-driven
  36. # and kind of finicky...
  37. # some TCK tycles are required to activate the DEBUG power domain
  38. jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"
  39. # have the DAP "always" be active
  40. jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap"
  41. proc omap3_dbginit {target} {
  42. # General Cortex A8 debug initialisation
  43. cortex_a8 dbginit
  44. # Enable DBGU signal for OMAP353x
  45. $target mww 0x5401d030 0x00002000
  46. }
  47. # be absolutely certain the JTAG clock will work with the worst-case
  48. # 16.8MHz/2 = 8.4MHz core clock, even before a bootloader kicks in.
  49. # OK to speed up *after* PLL and clock tree setup.
  50. jtag_rclk 1000
  51. $_TARGETNAME configure -event "reset-start" { jtag_rclk 1000 }
  52. # REVISIT This assumes that SRST is unavailable, so we must assert reset
  53. # ourselves using PRM_RSTCTRL. RST_GS (2) is a warm reset, like ICEpick
  54. # would issue. RST_DPLL3 (4) is a cold reset.
  55. set PRM_RSTCTRL 0x48307250
  56. $_TARGETNAME configure -event reset-assert-pre "$_TARGETNAME mww $PRM_RSTCTRL 2"
  57. $_TARGETNAME configure -event reset-assert-post "omap3_dbginit $_TARGETNAME"