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  1. #
  2. # Texas Instruments DaVinci family: TMS320DM365
  3. #
  4. if { [info exists CHIPNAME] } {
  5. set _CHIPNAME $CHIPNAME
  6. } else {
  7. set _CHIPNAME dm365
  8. }
  9. # TI boards default to EMU0/EMU1 *high* -- ARM and ETB are *disabled*
  10. # after JTAG reset until ICEpick is used to route them in.
  11. set EMU01 "-disable"
  12. # With EMU0/EMU1 jumpered *low* ARM and ETB are *enabled* without
  13. # needing any ICEpick interaction.
  14. #set EMU01 "-enable"
  15. source [find target/icepick.cfg]
  16. # Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer
  17. if { [info exists ETB_TAPID ] } {
  18. set _ETB_TAPID $ETB_TAPID
  19. } else {
  20. set _ETB_TAPID 0x2b900f0f
  21. }
  22. jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETB_TAPID $EMU01
  23. jtag configure $_CHIPNAME.etb -event tap-enable \
  24. "icepick_c_tapenable $_CHIPNAME.jrc 1"
  25. # Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM.
  26. if { [info exists CPU_TAPID ] } {
  27. set _CPU_TAPID $CPU_TAPID
  28. } else {
  29. set _CPU_TAPID 0x0792602f
  30. }
  31. jtag newtap $_CHIPNAME arm -irlen 4 -irmask 0xf -expected-id $_CPU_TAPID $EMU01
  32. jtag configure $_CHIPNAME.arm -event tap-enable \
  33. "icepick_c_tapenable $_CHIPNAME.jrc 0"
  34. # Primary TAP: ICEpick (JTAG route controller) and boundary scan
  35. if { [info exists JRC_TAPID ] } {
  36. set _JRC_TAPID $JRC_TAPID
  37. } else {
  38. set _JRC_TAPID 0x0b83e02f
  39. }
  40. jtag newtap $_CHIPNAME jrc -irlen 6 -irmask 0x3f -expected-id $_JRC_TAPID
  41. jtag configure $_CHIPNAME.jrc -event setup \
  42. "jtag tapenable $_CHIPNAME.etb; jtag tapenable $_CHIPNAME.arm"
  43. ################
  44. # various symbol definitions, to avoid hard-wiring addresses
  45. # and enable some sharing of DaVinci-family utility code
  46. global dm365
  47. set dm365 [ dict create ]
  48. # Physical addresses for controllers and memory
  49. # (Some of these are valid for many DaVinci family chips)
  50. dict set dm365 sram0 0x00010000
  51. dict set dm365 sram1 0x00014000
  52. dict set dm365 sysbase 0x01c40000
  53. dict set dm365 pllc1 0x01c40800
  54. dict set dm365 pllc2 0x01c40c00
  55. dict set dm365 psc 0x01c41000
  56. dict set dm365 gpio 0x01c67000
  57. dict set dm365 a_emif 0x01d10000
  58. dict set dm365 a_emif_cs0 0x02000000
  59. dict set dm365 a_emif_cs1 0x04000000
  60. dict set dm365 ddr_emif 0x20000000
  61. dict set dm365 ddr 0x80000000
  62. source [find target/davinci.cfg]
  63. ################
  64. # GDB target: the ARM, using SRAM1 for scratch. SRAM0 (also 16K)
  65. # and the ETB memory (4K) are other options, while trace is unused.
  66. set _TARGETNAME $_CHIPNAME.arm
  67. target create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME
  68. # NOTE that work-area-virt presumes a Linux 2.6.30-rc2+ kernel,
  69. # and that the work area is used only with a kernel mmu context ...
  70. $_TARGETNAME configure \
  71. -work-area-virt [expr 0xfffe0000 + 0x4000] \
  72. -work-area-phys [dict get $dm365 sram1] \
  73. -work-area-size 0x4000 \
  74. -work-area-backup 0
  75. # be absolutely certain the JTAG clock will work with the worst-case
  76. # CLKIN = 19.2 MHz (best case: 36 MHz) even when no bootloader turns
  77. # on the PLL and starts using it. OK to speed up after clock setup.
  78. jtag_rclk 1500
  79. $_TARGETNAME configure -event "reset-start" { jtag_rclk 1500 }
  80. arm7_9 fast_memory_access enable
  81. arm7_9 dcc_downloads enable
  82. # trace setup
  83. etm config $_TARGETNAME 16 normal full etb
  84. etb config $_TARGETNAME $_CHIPNAME.etb