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  1. #
  2. # Texas Instruments DaVinci family: TMS320DM6446
  3. #
  4. if { [info exists CHIPNAME] } {
  5. set _CHIPNAME $CHIPNAME
  6. } else {
  7. set _CHIPNAME dm6446
  8. }
  9. # TI boards default to EMU0/EMU1 *high* -- ARM and ETB are *disabled*
  10. # after JTAG reset until ICEpick is used to route them in.
  11. set EMU01 "-disable"
  12. # With EMU0/EMU1 jumpered *low* ARM and ETB are *enabled* without
  13. # needing any ICEpick interaction.
  14. #set EMU01 "-enable"
  15. source [find target/icepick.cfg]
  16. # Subsidiary TAP: unknown ... must enable via ICEpick
  17. jtag newtap $_CHIPNAME unknown -irlen 8 -disable
  18. jtag configure $_CHIPNAME.unknown -event tap-enable \
  19. "icepick_c_tapenable $_CHIPNAME.jrc 3"
  20. # Subsidiary TAP: C64x+ DSP ... must enable via ICEpick
  21. jtag newtap $_CHIPNAME dsp -irlen 38 -ircapture 0x25 -irmask 0x3f -disable
  22. jtag configure $_CHIPNAME.dsp -event tap-enable \
  23. "icepick_c_tapenable $_CHIPNAME.jrc 2"
  24. # Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer
  25. if { [info exists ETB_TAPID ] } {
  26. set _ETB_TAPID $ETB_TAPID
  27. } else {
  28. set _ETB_TAPID 0x2b900f0f
  29. }
  30. jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETB_TAPID $EMU01
  31. jtag configure $_CHIPNAME.etb -event tap-enable \
  32. "icepick_c_tapenable $_CHIPNAME.jrc 1"
  33. # Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM.
  34. if { [info exists CPU_TAPID ] } {
  35. set _CPU_TAPID $CPU_TAPID
  36. } else {
  37. set _CPU_TAPID 0x07926001
  38. }
  39. jtag newtap $_CHIPNAME arm -irlen 4 -irmask 0xf -expected-id $_CPU_TAPID $EMU01
  40. jtag configure $_CHIPNAME.arm -event tap-enable \
  41. "icepick_c_tapenable $_CHIPNAME.jrc 0"
  42. # Primary TAP: ICEpick-C (JTAG route controller) and boundary scan
  43. if { [info exists JRC_TAPID ] } {
  44. set _JRC_TAPID $JRC_TAPID
  45. } else {
  46. set _JRC_TAPID 0x0b70002f
  47. }
  48. jtag newtap $_CHIPNAME jrc -irlen 6 -irmask 0x3f -expected-id $_JRC_TAPID
  49. jtag configure $_CHIPNAME.jrc -event setup \
  50. "jtag tapenable $_CHIPNAME.etb; jtag tapenable $_CHIPNAME.arm"
  51. ################
  52. # GDB target: the ARM, using SRAM1 for scratch. SRAM0 (also 8K)
  53. # and the ETB memory (4K) are other options, while trace is unused.
  54. # Little-endian; use the OpenOCD default.
  55. set _TARGETNAME $_CHIPNAME.arm
  56. target create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME
  57. $_TARGETNAME configure -work-area-phys 0x0000a000 -work-area-size 0x2000
  58. # be absolutely certain the JTAG clock will work with the worst-case
  59. # CLKIN = 20 MHz (best case: 30 MHz) even when no bootloader turns
  60. # on the PLL and starts using it. OK to speed up after clock setup.
  61. jtag_rclk 1500
  62. $_TARGETNAME configure -event "reset-start" { jtag_rclk 1500 }
  63. arm7_9 fast_memory_access enable
  64. arm7_9 dcc_downloads enable
  65. # trace setup
  66. etm config $_TARGETNAME 16 normal full etb
  67. etb config $_TARGETNAME $_CHIPNAME.etb