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  1. # TI/Luminary Stellaris LM3S chip family
  2. # Some devices have errata in returning their device class.
  3. # DEVICECLASS is provided as a manual override
  4. # Manual setting of a device class of 0xff is not allowed
  5. global _DEVICECLASS
  6. if { [info exists DEVICECLASS] } {
  7. set _DEVICECLASS $DEVICECLASS
  8. } else {
  9. set _DEVICECLASS 0xff
  10. }
  11. # Luminary chips support both JTAG and SWD transports.
  12. # Adapt based on what transport is active.
  13. source [find target/swj-dp.tcl]
  14. # For now we ignore the SPI and UART options, which
  15. # are usable only for ISP style initial flash programming.
  16. if { [info exists CHIPNAME] } {
  17. set _CHIPNAME $CHIPNAME
  18. } else {
  19. set _CHIPNAME lm3s
  20. }
  21. # CPU TAP ID 0x1ba00477 for early Sandstorm parts
  22. # CPU TAP ID 0x2ba00477 for later SandStorm parts, e.g. lm3s811 Rev C2
  23. # CPU TAP ID 0x3ba00477 for Cortex-M3 r1p2 (on Fury, DustDevil)
  24. # CPU TAP ID 0x4ba00477 for Cortex-M3 r2p0 (on Tempest, Firestorm)
  25. # CPU TAP ID 0x4ba00477 for Cortex-M4 r0p1 (on Blizzard)
  26. # ... we'll ignore the JTAG version field, rather than list every
  27. # chip revision that turns up.
  28. if { [info exists CPUTAPID] } {
  29. set _CPUTAPID $CPUTAPID
  30. } else {
  31. set _CPUTAPID 0x0ba00477
  32. }
  33. # SWD DAP, and JTAG TAP, take same params for now;
  34. # ... even though SWD ignores all except TAPID, and
  35. # JTAG shouldn't need anything more then irlen. (and TAPID).
  36. swj_newdap $_CHIPNAME cpu -irlen 4 -irmask 0xf \
  37. -expected-id $_CPUTAPID -ignore-version
  38. if { [info exists WORKAREASIZE] } {
  39. set _WORKAREASIZE $WORKAREASIZE
  40. } else {
  41. # default to 2K working area
  42. set _WORKAREASIZE 0x800
  43. }
  44. set _TARGETNAME $_CHIPNAME.cpu
  45. target create $_TARGETNAME cortex_m3 -chain-position $_CHIPNAME.cpu
  46. # 8K working area at base of ram, not backed up
  47. #
  48. # NOTE: you may need or want to reconfigure the work area;
  49. # some parts have just 6K, and you may want to use other
  50. # addresses (at end of mem not beginning) or back it up.
  51. $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
  52. # JTAG speed ... slow enough to work with a 12 MHz RC oscillator;
  53. # LM3S parts don't support RTCK
  54. #
  55. # NOTE: this may be increased by a reset-init handler, after it
  56. # configures and enables the PLL. Or you might need to decrease
  57. # this, if you're using a slower clock.
  58. adapter_khz 500
  59. source [find mem_helper.tcl]
  60. proc reset_peripherals {family} {
  61. source [find chip/ti/lm3s/lm3s.tcl]
  62. echo "Resetting Core Peripherals"
  63. # Disable the PLL and the system clock divider (nop if disabled)
  64. mmw $SYSCTL_RCC 0 $SYSCTL_RCC_USESYSDIV
  65. mmw $SYSCTL_RCC2 $SYSCTL_RCC2_BYPASS2 0
  66. # RCC and RCC2 to their reset values
  67. mww $SYSCTL_RCC [expr (0x078e3ad0 | ([mrw $SYSCTL_RCC] & $SYSCTL_RCC_MOSCDIS))]
  68. mww $SYSCTL_RCC2 0x07806810
  69. mww $SYSCTL_RCC 0x078e3ad1
  70. # Reset the deep sleep clock configuration register
  71. mww $SYSCTL_DSLPCLKCFG 0x07800000
  72. # Reset the clock gating registers
  73. mww $SYSCTL_RCGC0 0x00000040
  74. mww $SYSCTL_RCGC1 0
  75. mww $SYSCTL_RCGC2 0
  76. mww $SYSCTL_SCGC0 0x00000040
  77. mww $SYSCTL_SCGC1 0
  78. mww $SYSCTL_SCGC2 0
  79. mww $SYSCTL_DCGC0 0x00000040
  80. mww $SYSCTL_DCGC1 0
  81. mww $SYSCTL_DCGC2 0
  82. # Reset the remaining SysCtl registers
  83. mww $SYSCTL_PBORCTL 0
  84. mww $SYSCTL_IMC 0
  85. mww $SYSCTL_GPIOHBCTL 0
  86. mww $SYSCTL_MOSCCTL 0
  87. mww $SYSCTL_PIOSCCAL 0
  88. mww $SYSCTL_I2SMCLKCFG 0
  89. # Reset the peripherals
  90. mww $SYSCTL_SRCR0 0xffffffff
  91. mww $SYSCTL_SRCR1 0xffffffff
  92. mww $SYSCTL_SRCR2 0xffffffff
  93. mww $SYSCTL_SRCR0 0
  94. mww $SYSCTL_SRCR1 0
  95. mww $SYSCTL_SRCR2 0
  96. # Clear any pending SysCtl interrupts
  97. mww $SYSCTL_MISC 0xffffffff
  98. # Wait for any pending flash operations to complete
  99. while {[expr [mrw $FLASH_FMC] & 0xffff] != 0} { sleep 1 }
  100. while {[expr [mrw $FLASH_FMC2] & 0xffff] != 0} { sleep 1 }
  101. # Reset the flash controller registers
  102. mww $FLASH_FMA 0
  103. mww $FLASH_FCIM 0
  104. mww $FLASH_FCMISC 0xffffffff
  105. mww $FLASH_FWBVAL 0
  106. }
  107. $_TARGETNAME configure -event reset-start {
  108. adapter_khz 500
  109. #
  110. # When nRST is asserted on most Stellaris devices, it clears some of
  111. # the debug state. The ARMv7M and Cortex-M3 TRMs say that's wrong;
  112. # and OpenOCD depends on those TRMs. So we won't use SRST on those
  113. # chips. (Only power-on reset should affect debug state, beyond a
  114. # few specified bits; not the chip's nRST input, wired to SRST.)
  115. #
  116. # REVISIT current errata specs don't seem to cover this issue.
  117. # Do we have more details than this email?
  118. # https://lists.berlios.de/pipermail
  119. # /openocd-development/2008-August/003065.html
  120. #
  121. global _DEVICECLASS
  122. if {$_DEVICECLASS != 0xff} {
  123. set device_class $_DEVICECLASS
  124. } else {
  125. set device_class [expr (([mrw 0x400fe000] >> 16) & 0xff)]
  126. }
  127. if {$device_class == 0 || $device_class == 1 ||
  128. $device_class == 3 || $device_class == 5} {
  129. # Sandstorm, Fury, DustDevil and Blizzard are able to use NVIC SYSRESETREQ
  130. cortex_m3 reset_config sysresetreq
  131. } else {
  132. # Tempest and Firestorm default to using NVIC VECTRESET
  133. # peripherals will need reseting manually, see proc reset_peripherals
  134. cortex_m3 reset_config vectreset
  135. # reset peripherals, based on code in
  136. # http://www.ti.com/lit/er/spmz573a/spmz573a.pdf
  137. reset_peripherals $device_class
  138. }
  139. }
  140. # flash configuration ... autodetects sizes, autoprobed
  141. flash bank $_CHIPNAME.flash stellaris 0 0 0 0 $_TARGETNAME