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  1. /***************************************************************************
  2. * Copyright (C) 2007 by Dominic Rath *
  3. * Dominic.Rath@gmx.de *
  4. * *
  5. * Copyright (C) 2009 by √ėyvind Harboe *
  6. * oyvind.harboe@zylin.com *
  7. * *
  8. * This program is free software; you can redistribute it and/or modify *
  9. * it under the terms of the GNU General Public License as published by *
  10. * the Free Software Foundation; either version 2 of the License, or *
  11. * (at your option) any later version. *
  12. * *
  13. * This program is distributed in the hope that it will be useful, *
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  16. * GNU General Public License for more details. *
  17. * *
  18. * You should have received a copy of the GNU General Public License *
  19. * along with this program; if not, write to the *
  20. * Free Software Foundation, Inc., *
  21. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
  22. ***************************************************************************/
  23. #ifdef HAVE_CONFIG_H
  24. #include "config.h"
  25. #endif
  26. #include "arm926ejs.h"
  27. #include "time_support.h"
  28. #include "target_type.h"
  29. #if 0
  30. #define _DEBUG_INSTRUCTION_EXECUTION_
  31. #endif
  32. /* cli handling */
  33. int arm926ejs_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  34. int arm926ejs_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  35. int arm926ejs_handle_virt2phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  36. int arm926ejs_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  37. int arm926ejs_handle_md_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  38. int arm926ejs_handle_mw_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  39. int arm926ejs_handle_read_cache_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  40. int arm926ejs_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  41. /* forward declarations */
  42. int arm926ejs_target_create(struct target_s *target, Jim_Interp *interp);
  43. int arm926ejs_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
  44. int arm926ejs_quit(void);
  45. int arm926ejs_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
  46. static int arm926ejs_virt2phys(struct target_s *target, uint32_t virtual, uint32_t *physical);
  47. static int arm926ejs_mmu(struct target_s *target, int *enabled);
  48. target_type_t arm926ejs_target =
  49. {
  50. .name = "arm926ejs",
  51. .poll = arm7_9_poll,
  52. .arch_state = arm926ejs_arch_state,
  53. .target_request_data = arm7_9_target_request_data,
  54. .halt = arm7_9_halt,
  55. .resume = arm7_9_resume,
  56. .step = arm7_9_step,
  57. .assert_reset = arm7_9_assert_reset,
  58. .deassert_reset = arm7_9_deassert_reset,
  59. .soft_reset_halt = arm926ejs_soft_reset_halt,
  60. .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
  61. .read_memory = arm7_9_read_memory,
  62. .write_memory = arm926ejs_write_memory,
  63. .bulk_write_memory = arm7_9_bulk_write_memory,
  64. .checksum_memory = arm7_9_checksum_memory,
  65. .blank_check_memory = arm7_9_blank_check_memory,
  66. .run_algorithm = armv4_5_run_algorithm,
  67. .add_breakpoint = arm7_9_add_breakpoint,
  68. .remove_breakpoint = arm7_9_remove_breakpoint,
  69. .add_watchpoint = arm7_9_add_watchpoint,
  70. .remove_watchpoint = arm7_9_remove_watchpoint,
  71. .register_commands = arm926ejs_register_commands,
  72. .target_create = arm926ejs_target_create,
  73. .init_target = arm926ejs_init_target,
  74. .examine = arm9tdmi_examine,
  75. .quit = arm926ejs_quit,
  76. .virt2phys = arm926ejs_virt2phys,
  77. .mmu = arm926ejs_mmu
  78. };
  79. int arm926ejs_catch_broken_irscan(uint8_t *captured, void *priv, scan_field_t *field)
  80. {
  81. /* FIX!!!! this code should be reenabled. For now it does not check
  82. * the queue...*/
  83. return 0;
  84. #if 0
  85. /* The ARM926EJ-S' instruction register is 4 bits wide */
  86. uint8_t t = *captured & 0xf;
  87. uint8_t t2 = *field->in_check_value & 0xf;
  88. if (t == t2)
  89. {
  90. return ERROR_OK;
  91. }
  92. else if ((t == 0x0f) || (t == 0x00))
  93. {
  94. LOG_DEBUG("caught ARM926EJ-S invalid Capture-IR result after CP15 access");
  95. return ERROR_OK;
  96. }
  97. return ERROR_JTAG_QUEUE_FAILED;;
  98. #endif
  99. }
  100. #define ARM926EJS_CP15_ADDR(opcode_1, opcode_2, CRn, CRm) ((opcode_1 << 11) | (opcode_2 << 8) | (CRn << 4) | (CRm << 0))
  101. int arm926ejs_cp15_read(target_t *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
  102. {
  103. int retval = ERROR_OK;
  104. armv4_5_common_t *armv4_5 = target->arch_info;
  105. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  106. arm_jtag_t *jtag_info = &arm7_9->jtag_info;
  107. uint32_t address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm);
  108. scan_field_t fields[4];
  109. uint8_t address_buf[2];
  110. uint8_t nr_w_buf = 0;
  111. uint8_t access = 1;
  112. buf_set_u32(address_buf, 0, 14, address);
  113. jtag_set_end_state(TAP_IDLE);
  114. if ((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
  115. {
  116. return retval;
  117. }
  118. arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
  119. fields[0].tap = jtag_info->tap;
  120. fields[0].num_bits = 32;
  121. fields[0].out_value = NULL;
  122. fields[0].in_value = (uint8_t *)value;
  123. fields[1].tap = jtag_info->tap;
  124. fields[1].num_bits = 1;
  125. fields[1].out_value = &access;
  126. fields[1].in_value = &access;
  127. fields[2].tap = jtag_info->tap;
  128. fields[2].num_bits = 14;
  129. fields[2].out_value = address_buf;
  130. fields[2].in_value = NULL;
  131. fields[3].tap = jtag_info->tap;
  132. fields[3].num_bits = 1;
  133. fields[3].out_value = &nr_w_buf;
  134. fields[3].in_value = NULL;
  135. jtag_add_dr_scan(4, fields, jtag_get_end_state());
  136. long long then = timeval_ms();
  137. for (;;)
  138. {
  139. /* rescan with NOP, to wait for the access to complete */
  140. access = 0;
  141. nr_w_buf = 0;
  142. jtag_add_dr_scan(4, fields, jtag_get_end_state());
  143. jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t)value);
  144. if ((retval = jtag_execute_queue()) != ERROR_OK)
  145. {
  146. return retval;
  147. }
  148. if (buf_get_u32(&access, 0, 1) == 1)
  149. {
  150. break;
  151. }
  152. /* 10ms timeout */
  153. if ((timeval_ms()-then)>10)
  154. {
  155. LOG_ERROR("cp15 read operation timed out");
  156. return ERROR_FAIL;
  157. }
  158. }
  159. #ifdef _DEBUG_INSTRUCTION_EXECUTION_
  160. LOG_DEBUG("addr: 0x%x value: %8.8x", address, *value);
  161. #endif
  162. arm_jtag_set_instr(jtag_info, 0xc, &arm926ejs_catch_broken_irscan);
  163. return ERROR_OK;
  164. }
  165. int arm926ejs_cp15_write(target_t *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
  166. {
  167. int retval = ERROR_OK;
  168. armv4_5_common_t *armv4_5 = target->arch_info;
  169. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  170. arm_jtag_t *jtag_info = &arm7_9->jtag_info;
  171. uint32_t address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm);
  172. scan_field_t fields[4];
  173. uint8_t value_buf[4];
  174. uint8_t address_buf[2];
  175. uint8_t nr_w_buf = 1;
  176. uint8_t access = 1;
  177. buf_set_u32(address_buf, 0, 14, address);
  178. buf_set_u32(value_buf, 0, 32, value);
  179. jtag_set_end_state(TAP_IDLE);
  180. if ((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
  181. {
  182. return retval;
  183. }
  184. arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
  185. fields[0].tap = jtag_info->tap;
  186. fields[0].num_bits = 32;
  187. fields[0].out_value = value_buf;
  188. fields[0].in_value = NULL;
  189. fields[1].tap = jtag_info->tap;
  190. fields[1].num_bits = 1;
  191. fields[1].out_value = &access;
  192. fields[1].in_value = &access;
  193. fields[2].tap = jtag_info->tap;
  194. fields[2].num_bits = 14;
  195. fields[2].out_value = address_buf;
  196. fields[2].in_value = NULL;
  197. fields[3].tap = jtag_info->tap;
  198. fields[3].num_bits = 1;
  199. fields[3].out_value = &nr_w_buf;
  200. fields[3].in_value = NULL;
  201. jtag_add_dr_scan(4, fields, jtag_get_end_state());
  202. long long then = timeval_ms();
  203. for (;;)
  204. {
  205. /* rescan with NOP, to wait for the access to complete */
  206. access = 0;
  207. nr_w_buf = 0;
  208. jtag_add_dr_scan(4, fields, jtag_get_end_state());
  209. if ((retval = jtag_execute_queue()) != ERROR_OK)
  210. {
  211. return retval;
  212. }
  213. if (buf_get_u32(&access, 0, 1) == 1)
  214. {
  215. break;
  216. }
  217. /* 10ms timeout */
  218. if ((timeval_ms()-then)>10)
  219. {
  220. LOG_ERROR("cp15 write operation timed out");
  221. return ERROR_FAIL;
  222. }
  223. }
  224. #ifdef _DEBUG_INSTRUCTION_EXECUTION_
  225. LOG_DEBUG("addr: 0x%x value: %8.8x", address, value);
  226. #endif
  227. arm_jtag_set_instr(jtag_info, 0xf, &arm926ejs_catch_broken_irscan);
  228. return ERROR_OK;
  229. }
  230. static int arm926ejs_examine_debug_reason(target_t *target)
  231. {
  232. armv4_5_common_t *armv4_5 = target->arch_info;
  233. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  234. reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
  235. int debug_reason;
  236. int retval;
  237. embeddedice_read_reg(dbg_stat);
  238. if ((retval = jtag_execute_queue()) != ERROR_OK)
  239. return retval;
  240. /* Method-Of-Entry (MOE) field */
  241. debug_reason = buf_get_u32(dbg_stat->value, 6, 4);
  242. switch (debug_reason)
  243. {
  244. case 0:
  245. LOG_DEBUG("no *NEW* debug entry (?missed one?)");
  246. /* ... since last restart or debug reset ... */
  247. target->debug_reason = DBG_REASON_DBGRQ;
  248. break;
  249. case 1:
  250. LOG_DEBUG("breakpoint from EICE unit 0");
  251. target->debug_reason = DBG_REASON_BREAKPOINT;
  252. break;
  253. case 2:
  254. LOG_DEBUG("breakpoint from EICE unit 1");
  255. target->debug_reason = DBG_REASON_BREAKPOINT;
  256. break;
  257. case 3:
  258. LOG_DEBUG("soft breakpoint (BKPT instruction)");
  259. target->debug_reason = DBG_REASON_BREAKPOINT;
  260. break;
  261. case 4:
  262. LOG_DEBUG("vector catch breakpoint");
  263. target->debug_reason = DBG_REASON_BREAKPOINT;
  264. break;
  265. case 5:
  266. LOG_DEBUG("external breakpoint");
  267. target->debug_reason = DBG_REASON_BREAKPOINT;
  268. break;
  269. case 6:
  270. LOG_DEBUG("watchpoint from EICE unit 0");
  271. target->debug_reason = DBG_REASON_WATCHPOINT;
  272. break;
  273. case 7:
  274. LOG_DEBUG("watchpoint from EICE unit 1");
  275. target->debug_reason = DBG_REASON_WATCHPOINT;
  276. break;
  277. case 8:
  278. LOG_DEBUG("external watchpoint");
  279. target->debug_reason = DBG_REASON_WATCHPOINT;
  280. break;
  281. case 9:
  282. LOG_DEBUG("internal debug request");
  283. target->debug_reason = DBG_REASON_DBGRQ;
  284. break;
  285. case 10:
  286. LOG_DEBUG("external debug request");
  287. target->debug_reason = DBG_REASON_DBGRQ;
  288. break;
  289. case 11:
  290. LOG_DEBUG("debug re-entry from system speed access");
  291. /* This is normal when connecting to something that's
  292. * already halted, or in some related code paths, but
  293. * otherwise is surprising (and presumably wrong).
  294. */
  295. switch (target->debug_reason) {
  296. case DBG_REASON_DBGRQ:
  297. break;
  298. default:
  299. LOG_ERROR("unexpected -- debug re-entry");
  300. /* FALLTHROUGH */
  301. case DBG_REASON_UNDEFINED:
  302. target->debug_reason = DBG_REASON_DBGRQ;
  303. break;
  304. }
  305. break;
  306. case 12:
  307. /* FIX!!!! here be dragons!!! We need to fail here so
  308. * the target will interpreted as halted but we won't
  309. * try to talk to it right now... a resume + halt seems
  310. * to sync things up again. Please send an email to
  311. * openocd development mailing list if you have hardware
  312. * to donate to look into this problem....
  313. */
  314. LOG_WARNING("WARNING: mystery debug reason MOE = 0xc. Try issuing a resume + halt.");
  315. target->debug_reason = DBG_REASON_DBGRQ;
  316. break;
  317. default:
  318. LOG_WARNING("WARNING: unknown debug reason: 0x%x", debug_reason);
  319. /* Oh agony! should we interpret this as a halt request or
  320. * that the target stopped on it's own accord?
  321. */
  322. target->debug_reason = DBG_REASON_DBGRQ;
  323. /* if we fail here, we won't talk to the target and it will
  324. * be reported to be in the halted state */
  325. break;
  326. }
  327. return ERROR_OK;
  328. }
  329. uint32_t arm926ejs_get_ttb(target_t *target)
  330. {
  331. armv4_5_common_t *armv4_5 = target->arch_info;
  332. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  333. arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
  334. arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
  335. int retval;
  336. uint32_t ttb = 0x0;
  337. if ((retval = arm926ejs->read_cp15(target, 0, 0, 2, 0, &ttb)) != ERROR_OK)
  338. return retval;
  339. return ttb;
  340. }
  341. void arm926ejs_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
  342. {
  343. armv4_5_common_t *armv4_5 = target->arch_info;
  344. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  345. arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
  346. arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
  347. uint32_t cp15_control;
  348. /* read cp15 control register */
  349. arm926ejs->read_cp15(target, 0, 0, 1, 0, &cp15_control);
  350. jtag_execute_queue();
  351. if (mmu)
  352. {
  353. /* invalidate TLB */
  354. arm926ejs->write_cp15(target, 0, 0, 8, 7, 0x0);
  355. cp15_control &= ~0x1U;
  356. }
  357. if (d_u_cache)
  358. {
  359. uint32_t debug_override;
  360. /* read-modify-write CP15 debug override register
  361. * to enable "test and clean all" */
  362. arm926ejs->read_cp15(target, 0, 0, 15, 0, &debug_override);
  363. debug_override |= 0x80000;
  364. arm926ejs->write_cp15(target, 0, 0, 15, 0, debug_override);
  365. /* clean and invalidate DCache */
  366. arm926ejs->write_cp15(target, 0, 0, 7, 5, 0x0);
  367. /* write CP15 debug override register
  368. * to disable "test and clean all" */
  369. debug_override &= ~0x80000;
  370. arm926ejs->write_cp15(target, 0, 0, 15, 0, debug_override);
  371. cp15_control &= ~0x4U;
  372. }
  373. if (i_cache)
  374. {
  375. /* invalidate ICache */
  376. arm926ejs->write_cp15(target, 0, 0, 7, 5, 0x0);
  377. cp15_control &= ~0x1000U;
  378. }
  379. arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control);
  380. }
  381. void arm926ejs_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
  382. {
  383. armv4_5_common_t *armv4_5 = target->arch_info;
  384. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  385. arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
  386. arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
  387. uint32_t cp15_control;
  388. /* read cp15 control register */
  389. arm926ejs->read_cp15(target, 0, 0, 1, 0, &cp15_control);
  390. jtag_execute_queue();
  391. if (mmu)
  392. cp15_control |= 0x1U;
  393. if (d_u_cache)
  394. cp15_control |= 0x4U;
  395. if (i_cache)
  396. cp15_control |= 0x1000U;
  397. arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control);
  398. }
  399. void arm926ejs_post_debug_entry(target_t *target)
  400. {
  401. armv4_5_common_t *armv4_5 = target->arch_info;
  402. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  403. arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
  404. arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
  405. /* examine cp15 control reg */
  406. arm926ejs->read_cp15(target, 0, 0, 1, 0, &arm926ejs->cp15_control_reg);
  407. jtag_execute_queue();
  408. LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm926ejs->cp15_control_reg);
  409. if (arm926ejs->armv4_5_mmu.armv4_5_cache.ctype == -1)
  410. {
  411. uint32_t cache_type_reg;
  412. /* identify caches */
  413. arm926ejs->read_cp15(target, 0, 1, 0, 0, &cache_type_reg);
  414. jtag_execute_queue();
  415. armv4_5_identify_cache(cache_type_reg, &arm926ejs->armv4_5_mmu.armv4_5_cache);
  416. }
  417. arm926ejs->armv4_5_mmu.mmu_enabled = (arm926ejs->cp15_control_reg & 0x1U) ? 1 : 0;
  418. arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm926ejs->cp15_control_reg & 0x4U) ? 1 : 0;
  419. arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = (arm926ejs->cp15_control_reg & 0x1000U) ? 1 : 0;
  420. /* save i/d fault status and address register */
  421. arm926ejs->read_cp15(target, 0, 0, 5, 0, &arm926ejs->d_fsr);
  422. arm926ejs->read_cp15(target, 0, 1, 5, 0, &arm926ejs->i_fsr);
  423. arm926ejs->read_cp15(target, 0, 0, 6, 0, &arm926ejs->d_far);
  424. LOG_DEBUG("D FSR: 0x%8.8" PRIx32 ", D FAR: 0x%8.8" PRIx32 ", I FSR: 0x%8.8" PRIx32 "",
  425. arm926ejs->d_fsr, arm926ejs->d_far, arm926ejs->i_fsr);
  426. uint32_t cache_dbg_ctrl;
  427. /* read-modify-write CP15 cache debug control register
  428. * to disable I/D-cache linefills and force WT */
  429. arm926ejs->read_cp15(target, 7, 0, 15, 0, &cache_dbg_ctrl);
  430. cache_dbg_ctrl |= 0x7;
  431. arm926ejs->write_cp15(target, 7, 0, 15, 0, cache_dbg_ctrl);
  432. }
  433. void arm926ejs_pre_restore_context(target_t *target)
  434. {
  435. armv4_5_common_t *armv4_5 = target->arch_info;
  436. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  437. arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
  438. arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
  439. /* restore i/d fault status and address register */
  440. arm926ejs->write_cp15(target, 0, 0, 5, 0, arm926ejs->d_fsr);
  441. arm926ejs->write_cp15(target, 0, 1, 5, 0, arm926ejs->i_fsr);
  442. arm926ejs->write_cp15(target, 0, 0, 6, 0, arm926ejs->d_far);
  443. uint32_t cache_dbg_ctrl;
  444. /* read-modify-write CP15 cache debug control register
  445. * to reenable I/D-cache linefills and disable WT */
  446. arm926ejs->read_cp15(target, 7, 0, 15, 0, &cache_dbg_ctrl);
  447. cache_dbg_ctrl &= ~0x7;
  448. arm926ejs->write_cp15(target, 7, 0, 15, 0, cache_dbg_ctrl);
  449. }
  450. int arm926ejs_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm9tdmi_common_t **arm9tdmi_p, arm926ejs_common_t **arm926ejs_p)
  451. {
  452. armv4_5_common_t *armv4_5 = target->arch_info;
  453. arm7_9_common_t *arm7_9;
  454. arm9tdmi_common_t *arm9tdmi;
  455. arm926ejs_common_t *arm926ejs;
  456. if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
  457. {
  458. return -1;
  459. }
  460. arm7_9 = armv4_5->arch_info;
  461. if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
  462. {
  463. return -1;
  464. }
  465. arm9tdmi = arm7_9->arch_info;
  466. if (arm9tdmi->common_magic != ARM9TDMI_COMMON_MAGIC)
  467. {
  468. return -1;
  469. }
  470. arm926ejs = arm9tdmi->arch_info;
  471. if (arm926ejs->common_magic != ARM926EJS_COMMON_MAGIC)
  472. {
  473. return -1;
  474. }
  475. *armv4_5_p = armv4_5;
  476. *arm7_9_p = arm7_9;
  477. *arm9tdmi_p = arm9tdmi;
  478. *arm926ejs_p = arm926ejs;
  479. return ERROR_OK;
  480. }
  481. int arm926ejs_arch_state(struct target_s *target)
  482. {
  483. armv4_5_common_t *armv4_5 = target->arch_info;
  484. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  485. arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
  486. arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
  487. char *state[] =
  488. {
  489. "disabled", "enabled"
  490. };
  491. if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
  492. {
  493. LOG_ERROR("BUG: called for a non-ARMv4/5 target");
  494. exit(-1);
  495. }
  496. LOG_USER(
  497. "target halted in %s state due to %s, current mode: %s\n"
  498. "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
  499. "MMU: %s, D-Cache: %s, I-Cache: %s",
  500. armv4_5_state_strings[armv4_5->core_state],
  501. Jim_Nvp_value2name_simple(nvp_target_debug_reason,target->debug_reason)->name,
  502. armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
  503. buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
  504. buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
  505. state[arm926ejs->armv4_5_mmu.mmu_enabled],
  506. state[arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
  507. state[arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled]);
  508. return ERROR_OK;
  509. }
  510. int arm926ejs_soft_reset_halt(struct target_s *target)
  511. {
  512. int retval = ERROR_OK;
  513. armv4_5_common_t *armv4_5 = target->arch_info;
  514. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  515. arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
  516. arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
  517. reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
  518. if ((retval = target_halt(target)) != ERROR_OK)
  519. {
  520. return retval;
  521. }
  522. long long then = timeval_ms();
  523. int timeout;
  524. while (!(timeout = ((timeval_ms()-then) > 1000)))
  525. {
  526. if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
  527. {
  528. embeddedice_read_reg(dbg_stat);
  529. if ((retval = jtag_execute_queue()) != ERROR_OK)
  530. {
  531. return retval;
  532. }
  533. } else
  534. {
  535. break;
  536. }
  537. if (debug_level >= 1)
  538. {
  539. /* do not eat all CPU, time out after 1 se*/
  540. alive_sleep(100);
  541. } else
  542. {
  543. keep_alive();
  544. }
  545. }
  546. if (timeout)
  547. {
  548. LOG_ERROR("Failed to halt CPU after 1 sec");
  549. return ERROR_TARGET_TIMEOUT;
  550. }
  551. target->state = TARGET_HALTED;
  552. /* SVC, ARM state, IRQ and FIQ disabled */
  553. buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
  554. armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
  555. armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
  556. /* start fetching from 0x0 */
  557. buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
  558. armv4_5->core_cache->reg_list[15].dirty = 1;
  559. armv4_5->core_cache->reg_list[15].valid = 1;
  560. armv4_5->core_mode = ARMV4_5_MODE_SVC;
  561. armv4_5->core_state = ARMV4_5_STATE_ARM;
  562. arm926ejs_disable_mmu_caches(target, 1, 1, 1);
  563. arm926ejs->armv4_5_mmu.mmu_enabled = 0;
  564. arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
  565. arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
  566. return target_call_event_callbacks(target, TARGET_EVENT_HALTED);
  567. }
  568. int arm926ejs_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
  569. {
  570. int retval;
  571. armv4_5_common_t *armv4_5 = target->arch_info;
  572. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  573. arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
  574. arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
  575. /* FIX!!!! this should be cleaned up and made much more general. The
  576. * plan is to write up and test on arm926ejs specifically and
  577. * then generalize and clean up afterwards. */
  578. if ((count == 1) && ((size==2) || (size==4)))
  579. {
  580. /* special case the handling of single word writes to bypass MMU
  581. * to allow implementation of breakpoints in memory marked read only
  582. * by MMU */
  583. if (arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
  584. {
  585. /* flush and invalidate data cache
  586. *
  587. * MCR p15,0,p,c7,c10,1 - clean cache line using virtual address
  588. *
  589. */
  590. retval = arm926ejs->write_cp15(target, 0, 1, 7, 10, address&~0x3);
  591. if (retval != ERROR_OK)
  592. return retval;
  593. }
  594. uint32_t pa;
  595. retval = target->type->virt2phys(target, address, &pa);
  596. if (retval != ERROR_OK)
  597. return retval;
  598. /* write directly to physical memory bypassing any read only MMU bits, etc. */
  599. retval = armv4_5_mmu_write_physical(target, &arm926ejs->armv4_5_mmu, pa, size, count, buffer);
  600. if (retval != ERROR_OK)
  601. return retval;
  602. } else
  603. {
  604. if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK)
  605. return retval;
  606. }
  607. /* If ICache is enabled, we have to invalidate affected ICache lines
  608. * the DCache is forced to write-through, so we don't have to clean it here
  609. */
  610. if (arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
  611. {
  612. if (count <= 1)
  613. {
  614. /* invalidate ICache single entry with MVA */
  615. arm926ejs->write_cp15(target, 0, 1, 7, 5, address);
  616. }
  617. else
  618. {
  619. /* invalidate ICache */
  620. arm926ejs->write_cp15(target, 0, 0, 7, 5, address);
  621. }
  622. }
  623. return retval;
  624. }
  625. int arm926ejs_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
  626. {
  627. arm9tdmi_init_target(cmd_ctx, target);
  628. return ERROR_OK;
  629. }
  630. int arm926ejs_quit(void)
  631. {
  632. return ERROR_OK;
  633. }
  634. int arm926ejs_init_arch_info(target_t *target, arm926ejs_common_t *arm926ejs, jtag_tap_t *tap)
  635. {
  636. arm9tdmi_common_t *arm9tdmi = &arm926ejs->arm9tdmi_common;
  637. arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common;
  638. /* initialize arm9tdmi specific info (including arm7_9 and armv4_5)
  639. */
  640. arm9tdmi_init_arch_info(target, arm9tdmi, tap);
  641. arm9tdmi->arch_info = arm926ejs;
  642. arm926ejs->common_magic = ARM926EJS_COMMON_MAGIC;
  643. arm7_9->post_debug_entry = arm926ejs_post_debug_entry;
  644. arm7_9->pre_restore_context = arm926ejs_pre_restore_context;
  645. arm926ejs->read_cp15 = arm926ejs_cp15_read;
  646. arm926ejs->write_cp15 = arm926ejs_cp15_write;
  647. arm926ejs->armv4_5_mmu.armv4_5_cache.ctype = -1;
  648. arm926ejs->armv4_5_mmu.get_ttb = arm926ejs_get_ttb;
  649. arm926ejs->armv4_5_mmu.read_memory = arm7_9_read_memory;
  650. arm926ejs->armv4_5_mmu.write_memory = arm7_9_write_memory;
  651. arm926ejs->armv4_5_mmu.disable_mmu_caches = arm926ejs_disable_mmu_caches;
  652. arm926ejs->armv4_5_mmu.enable_mmu_caches = arm926ejs_enable_mmu_caches;
  653. arm926ejs->armv4_5_mmu.has_tiny_pages = 1;
  654. arm926ejs->armv4_5_mmu.mmu_enabled = 0;
  655. arm7_9->examine_debug_reason = arm926ejs_examine_debug_reason;
  656. /* The ARM926EJ-S implements the ARMv5TE architecture which
  657. * has the BKPT instruction, so we don't have to use a watchpoint comparator
  658. */
  659. arm7_9->arm_bkpt = ARMV5_BKPT(0x0);
  660. arm7_9->thumb_bkpt = ARMV5_T_BKPT(0x0) & 0xffff;
  661. return ERROR_OK;
  662. }
  663. int arm926ejs_target_create(struct target_s *target, Jim_Interp *interp)
  664. {
  665. arm926ejs_common_t *arm926ejs = calloc(1,sizeof(arm926ejs_common_t));
  666. arm926ejs_init_arch_info(target, arm926ejs, target->tap);
  667. return ERROR_OK;
  668. }
  669. int arm926ejs_register_commands(struct command_context_s *cmd_ctx)
  670. {
  671. int retval;
  672. command_t *arm926ejs_cmd;
  673. retval = arm9tdmi_register_commands(cmd_ctx);
  674. arm926ejs_cmd = register_command(cmd_ctx, NULL, "arm926ejs", NULL, COMMAND_ANY, "arm926ejs specific commands");
  675. register_command(cmd_ctx, arm926ejs_cmd, "cp15", arm926ejs_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register <opcode_1> <opcode_2> <CRn> <CRm> [value]");
  676. register_command(cmd_ctx, arm926ejs_cmd, "cache_info", arm926ejs_handle_cache_info_command, COMMAND_EXEC, "display information about target caches");
  677. register_command(cmd_ctx, arm926ejs_cmd, "virt2phys", arm926ejs_handle_virt2phys_command, COMMAND_EXEC, "translate va to pa <va>");
  678. register_command(cmd_ctx, arm926ejs_cmd, "mdw_phys", arm926ejs_handle_md_phys_command, COMMAND_EXEC, "display memory words <physical addr> [count]");
  679. register_command(cmd_ctx, arm926ejs_cmd, "mdh_phys", arm926ejs_handle_md_phys_command, COMMAND_EXEC, "display memory half-words <physical addr> [count]");
  680. register_command(cmd_ctx, arm926ejs_cmd, "mdb_phys", arm926ejs_handle_md_phys_command, COMMAND_EXEC, "display memory bytes <physical addr> [count]");
  681. register_command(cmd_ctx, arm926ejs_cmd, "mww_phys", arm926ejs_handle_mw_phys_command, COMMAND_EXEC, "write memory word <physical addr> <value>");
  682. register_command(cmd_ctx, arm926ejs_cmd, "mwh_phys", arm926ejs_handle_mw_phys_command, COMMAND_EXEC, "write memory half-word <physical addr> <value>");
  683. register_command(cmd_ctx, arm926ejs_cmd, "mwb_phys", arm926ejs_handle_mw_phys_command, COMMAND_EXEC, "write memory byte <physical addr> <value>");
  684. return retval;
  685. }
  686. int arm926ejs_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
  687. {
  688. int retval;
  689. target_t *target = get_current_target(cmd_ctx);
  690. armv4_5_common_t *armv4_5;
  691. arm7_9_common_t *arm7_9;
  692. arm9tdmi_common_t *arm9tdmi;
  693. arm926ejs_common_t *arm926ejs;
  694. int opcode_1;
  695. int opcode_2;
  696. int CRn;
  697. int CRm;
  698. if ((argc < 4) || (argc > 5))
  699. {
  700. command_print(cmd_ctx, "usage: arm926ejs cp15 <opcode_1> <opcode_2> <CRn> <CRm> [value]");
  701. return ERROR_OK;
  702. }
  703. opcode_1 = strtoul(args[0], NULL, 0);
  704. opcode_2 = strtoul(args[1], NULL, 0);
  705. CRn = strtoul(args[2], NULL, 0);
  706. CRm = strtoul(args[3], NULL, 0);
  707. if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
  708. {
  709. command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
  710. return ERROR_OK;
  711. }
  712. if (target->state != TARGET_HALTED)
  713. {
  714. command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
  715. return ERROR_OK;
  716. }
  717. if (argc == 4)
  718. {
  719. uint32_t value;
  720. if ((retval = arm926ejs->read_cp15(target, opcode_1, opcode_2, CRn, CRm, &value)) != ERROR_OK)
  721. {
  722. command_print(cmd_ctx, "couldn't access register");
  723. return ERROR_OK;
  724. }
  725. if ((retval = jtag_execute_queue()) != ERROR_OK)
  726. {
  727. return retval;
  728. }
  729. command_print(cmd_ctx, "%i %i %i %i: %8.8" PRIx32 "", opcode_1, opcode_2, CRn, CRm, value);
  730. }
  731. else
  732. {
  733. uint32_t value = strtoul(args[4], NULL, 0);
  734. if ((retval = arm926ejs->write_cp15(target, opcode_1, opcode_2, CRn, CRm, value)) != ERROR_OK)
  735. {
  736. command_print(cmd_ctx, "couldn't access register");
  737. return ERROR_OK;
  738. }
  739. command_print(cmd_ctx, "%i %i %i %i: %8.8" PRIx32 "", opcode_1, opcode_2, CRn, CRm, value);
  740. }
  741. return ERROR_OK;
  742. }
  743. int arm926ejs_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
  744. {
  745. target_t *target = get_current_target(cmd_ctx);
  746. armv4_5_common_t *armv4_5;
  747. arm7_9_common_t *arm7_9;
  748. arm9tdmi_common_t *arm9tdmi;
  749. arm926ejs_common_t *arm926ejs;
  750. if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
  751. {
  752. command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
  753. return ERROR_OK;
  754. }
  755. return armv4_5_handle_cache_info_command(cmd_ctx, &arm926ejs->armv4_5_mmu.armv4_5_cache);
  756. }
  757. int arm926ejs_handle_virt2phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
  758. {
  759. target_t *target = get_current_target(cmd_ctx);
  760. armv4_5_common_t *armv4_5;
  761. arm7_9_common_t *arm7_9;
  762. arm9tdmi_common_t *arm9tdmi;
  763. arm926ejs_common_t *arm926ejs;
  764. arm_jtag_t *jtag_info;
  765. if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
  766. {
  767. command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
  768. return ERROR_OK;
  769. }
  770. jtag_info = &arm7_9->jtag_info;
  771. if (target->state != TARGET_HALTED)
  772. {
  773. command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
  774. return ERROR_OK;
  775. }
  776. return armv4_5_mmu_handle_virt2phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu);
  777. }
  778. int arm926ejs_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
  779. {
  780. target_t *target = get_current_target(cmd_ctx);
  781. armv4_5_common_t *armv4_5;
  782. arm7_9_common_t *arm7_9;
  783. arm9tdmi_common_t *arm9tdmi;
  784. arm926ejs_common_t *arm926ejs;
  785. arm_jtag_t *jtag_info;
  786. if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
  787. {
  788. command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
  789. return ERROR_OK;
  790. }
  791. jtag_info = &arm7_9->jtag_info;
  792. if (target->state != TARGET_HALTED)
  793. {
  794. command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
  795. return ERROR_OK;
  796. }
  797. return armv4_5_mmu_handle_md_phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu);
  798. }
  799. int arm926ejs_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
  800. {
  801. target_t *target = get_current_target(cmd_ctx);
  802. armv4_5_common_t *armv4_5;
  803. arm7_9_common_t *arm7_9;
  804. arm9tdmi_common_t *arm9tdmi;
  805. arm926ejs_common_t *arm926ejs;
  806. arm_jtag_t *jtag_info;
  807. if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
  808. {
  809. command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
  810. return ERROR_OK;
  811. }
  812. jtag_info = &arm7_9->jtag_info;
  813. if (target->state != TARGET_HALTED)
  814. {
  815. command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
  816. return ERROR_OK;
  817. }
  818. return armv4_5_mmu_handle_mw_phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu);
  819. }
  820. static int arm926ejs_virt2phys(struct target_s *target, uint32_t virtual, uint32_t *physical)
  821. {
  822. int retval;
  823. int type;
  824. uint32_t cb;
  825. int domain;
  826. uint32_t ap;
  827. armv4_5_common_t *armv4_5;
  828. arm7_9_common_t *arm7_9;
  829. arm9tdmi_common_t *arm9tdmi;
  830. arm926ejs_common_t *arm926ejs;
  831. retval= arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs);
  832. if (retval != ERROR_OK)
  833. {
  834. return retval;
  835. }
  836. uint32_t ret = armv4_5_mmu_translate_va(target, &arm926ejs->armv4_5_mmu, virtual, &type, &cb, &domain, &ap);
  837. if (type == -1)
  838. {
  839. return ret;
  840. }
  841. *physical = ret;
  842. return ERROR_OK;
  843. }
  844. static int arm926ejs_mmu(struct target_s *target, int *enabled)
  845. {
  846. armv4_5_common_t *armv4_5 = target->arch_info;
  847. arm926ejs_common_t *arm926ejs = armv4_5->arch_info;
  848. if (target->state != TARGET_HALTED)
  849. {
  850. LOG_ERROR("Target not halted");
  851. return ERROR_TARGET_INVALID;
  852. }
  853. *enabled = arm926ejs->armv4_5_mmu.mmu_enabled;
  854. return ERROR_OK;
  855. }