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  1. /***************************************************************************
  2. * Copyright (C) 2005 by Dominic Rath *
  3. * Dominic.Rath@gmx.de *
  4. * *
  5. * Copyright (C) 2008 by Spencer Oliver *
  6. * spen@spen-soft.co.uk *
  7. * *
  8. * Copyright (C) 2010 √ėyvind Harboe *
  9. * oyvind.harboe@zylin.com *
  10. * *
  11. * This program is free software; you can redistribute it and/or modify *
  12. * it under the terms of the GNU General Public License as published by *
  13. * the Free Software Foundation; either version 2 of the License, or *
  14. * (at your option) any later version. *
  15. * *
  16. * This program is distributed in the hope that it will be useful, *
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  19. * GNU General Public License for more details. *
  20. * *
  21. * You should have received a copy of the GNU General Public License *
  22. * along with this program; if not, write to the *
  23. * Free Software Foundation, Inc., *
  24. * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
  25. ***************************************************************************/
  26. #ifdef HAVE_CONFIG_H
  27. #include "config.h"
  28. #endif
  29. #include "imp.h"
  30. #include <target/arm.h>
  31. #include <helper/binarybuffer.h>
  32. #include <target/algorithm.h>
  33. /* Flash registers */
  34. #define FLASH_CR0 0x00000000
  35. #define FLASH_CR1 0x00000004
  36. #define FLASH_DR0 0x00000008
  37. #define FLASH_DR1 0x0000000C
  38. #define FLASH_AR 0x00000010
  39. #define FLASH_ER 0x00000014
  40. #define FLASH_NVWPAR 0x0000DFB0
  41. #define FLASH_NVAPR0 0x0000DFB8
  42. #define FLASH_NVAPR1 0x0000DFBC
  43. /* FLASH_CR0 register bits */
  44. #define FLASH_WMS 0x80000000
  45. #define FLASH_SUSP 0x40000000
  46. #define FLASH_WPG 0x20000000
  47. #define FLASH_DWPG 0x10000000
  48. #define FLASH_SER 0x08000000
  49. #define FLASH_SPR 0x01000000
  50. #define FLASH_BER 0x04000000
  51. #define FLASH_MER 0x02000000
  52. #define FLASH_LOCK 0x00000010
  53. #define FLASH_BSYA1 0x00000004
  54. #define FLASH_BSYA0 0x00000002
  55. /* FLASH_CR1 register bits */
  56. #define FLASH_B1S 0x02000000
  57. #define FLASH_B0S 0x01000000
  58. #define FLASH_B1F1 0x00020000
  59. #define FLASH_B1F0 0x00010000
  60. #define FLASH_B0F7 0x00000080
  61. #define FLASH_B0F6 0x00000040
  62. #define FLASH_B0F5 0x00000020
  63. #define FLASH_B0F4 0x00000010
  64. #define FLASH_B0F3 0x00000008
  65. #define FLASH_B0F2 0x00000004
  66. #define FLASH_B0F1 0x00000002
  67. #define FLASH_B0F0 0x00000001
  68. /* FLASH_ER register bits */
  69. #define FLASH_WPF 0x00000100
  70. #define FLASH_RESER 0x00000080
  71. #define FLASH_SEQER 0x00000040
  72. #define FLASH_10ER 0x00000008
  73. #define FLASH_PGER 0x00000004
  74. #define FLASH_ERER 0x00000002
  75. #define FLASH_ERR 0x00000001
  76. struct str7x_flash_bank {
  77. uint32_t *sector_bits;
  78. uint32_t disable_bit;
  79. uint32_t busy_bits;
  80. uint32_t register_base;
  81. };
  82. struct str7x_mem_layout {
  83. uint32_t sector_start;
  84. uint32_t sector_size;
  85. uint32_t sector_bit;
  86. };
  87. enum str7x_status_codes {
  88. STR7X_CMD_SUCCESS = 0,
  89. STR7X_INVALID_COMMAND = 1,
  90. STR7X_SRC_ADDR_ERROR = 2,
  91. STR7X_DST_ADDR_ERROR = 3,
  92. STR7X_SRC_ADDR_NOT_MAPPED = 4,
  93. STR7X_DST_ADDR_NOT_MAPPED = 5,
  94. STR7X_COUNT_ERROR = 6,
  95. STR7X_INVALID_SECTOR = 7,
  96. STR7X_SECTOR_NOT_BLANK = 8,
  97. STR7X_SECTOR_NOT_PREPARED = 9,
  98. STR7X_COMPARE_ERROR = 10,
  99. STR7X_BUSY = 11
  100. };
  101. static const struct str7x_mem_layout mem_layout_str7bank0[] = {
  102. {0x00000000, 0x02000, 0x01},
  103. {0x00002000, 0x02000, 0x02},
  104. {0x00004000, 0x02000, 0x04},
  105. {0x00006000, 0x02000, 0x08},
  106. {0x00008000, 0x08000, 0x10},
  107. {0x00010000, 0x10000, 0x20},
  108. {0x00020000, 0x10000, 0x40},
  109. {0x00030000, 0x10000, 0x80}
  110. };
  111. static const struct str7x_mem_layout mem_layout_str7bank1[] = {
  112. {0x00000000, 0x02000, 0x10000},
  113. {0x00002000, 0x02000, 0x20000}
  114. };
  115. static int str7x_get_flash_adr(struct flash_bank *bank, uint32_t reg)
  116. {
  117. struct str7x_flash_bank *str7x_info = bank->driver_priv;
  118. return str7x_info->register_base | reg;
  119. }
  120. static int str7x_build_block_list(struct flash_bank *bank)
  121. {
  122. struct str7x_flash_bank *str7x_info = bank->driver_priv;
  123. int i;
  124. int num_sectors;
  125. int b0_sectors = 0, b1_sectors = 0;
  126. switch (bank->size) {
  127. case 16 * 1024:
  128. b1_sectors = 2;
  129. break;
  130. case 64 * 1024:
  131. b0_sectors = 5;
  132. break;
  133. case 128 * 1024:
  134. b0_sectors = 6;
  135. break;
  136. case 256 * 1024:
  137. b0_sectors = 8;
  138. break;
  139. default:
  140. LOG_ERROR("BUG: unknown bank->size encountered");
  141. exit(-1);
  142. }
  143. num_sectors = b0_sectors + b1_sectors;
  144. bank->num_sectors = num_sectors;
  145. bank->sectors = malloc(sizeof(struct flash_sector) * num_sectors);
  146. str7x_info->sector_bits = malloc(sizeof(uint32_t) * num_sectors);
  147. num_sectors = 0;
  148. for (i = 0; i < b0_sectors; i++) {
  149. bank->sectors[num_sectors].offset = mem_layout_str7bank0[i].sector_start;
  150. bank->sectors[num_sectors].size = mem_layout_str7bank0[i].sector_size;
  151. bank->sectors[num_sectors].is_erased = -1;
  152. /* the reset_init handler marks all the sectors unprotected,
  153. * matching hardware after reset; keep the driver in sync
  154. */
  155. bank->sectors[num_sectors].is_protected = 0;
  156. str7x_info->sector_bits[num_sectors++] = mem_layout_str7bank0[i].sector_bit;
  157. }
  158. for (i = 0; i < b1_sectors; i++) {
  159. bank->sectors[num_sectors].offset = mem_layout_str7bank1[i].sector_start;
  160. bank->sectors[num_sectors].size = mem_layout_str7bank1[i].sector_size;
  161. bank->sectors[num_sectors].is_erased = -1;
  162. /* the reset_init handler marks all the sectors unprotected,
  163. * matching hardware after reset; keep the driver in sync
  164. */
  165. bank->sectors[num_sectors].is_protected = 0;
  166. str7x_info->sector_bits[num_sectors++] = mem_layout_str7bank1[i].sector_bit;
  167. }
  168. return ERROR_OK;
  169. }
  170. /* flash bank str7x <base> <size> 0 0 <target#> <str71_variant>
  171. */
  172. FLASH_BANK_COMMAND_HANDLER(str7x_flash_bank_command)
  173. {
  174. struct str7x_flash_bank *str7x_info;
  175. if (CMD_ARGC < 7)
  176. return ERROR_COMMAND_SYNTAX_ERROR;
  177. str7x_info = malloc(sizeof(struct str7x_flash_bank));
  178. bank->driver_priv = str7x_info;
  179. /* set default bits for str71x flash */
  180. str7x_info->busy_bits = (FLASH_LOCK | FLASH_BSYA1 | FLASH_BSYA0);
  181. str7x_info->disable_bit = (1 << 1);
  182. if (strcmp(CMD_ARGV[6], "STR71x") == 0)
  183. str7x_info->register_base = 0x40100000;
  184. else if (strcmp(CMD_ARGV[6], "STR73x") == 0) {
  185. str7x_info->register_base = 0x80100000;
  186. str7x_info->busy_bits = (FLASH_LOCK | FLASH_BSYA0);
  187. } else if (strcmp(CMD_ARGV[6], "STR75x") == 0) {
  188. str7x_info->register_base = 0x20100000;
  189. str7x_info->disable_bit = (1 << 0);
  190. } else {
  191. LOG_ERROR("unknown STR7x variant: '%s'", CMD_ARGV[6]);
  192. free(str7x_info);
  193. return ERROR_FLASH_BANK_INVALID;
  194. }
  195. str7x_build_block_list(bank);
  196. return ERROR_OK;
  197. }
  198. /* wait for flash to become idle or report errors.
  199. FIX!!! what's the maximum timeout??? The documentation doesn't
  200. state any maximum time.... by inspection it seems > 1000ms is to be
  201. expected.
  202. 10000ms is long enough that it should cover anything, yet not
  203. quite be equivalent to an infinite loop.
  204. */
  205. static int str7x_waitbusy(struct flash_bank *bank)
  206. {
  207. int err;
  208. int i;
  209. struct target *target = bank->target;
  210. struct str7x_flash_bank *str7x_info = bank->driver_priv;
  211. for (i = 0 ; i < 10000; i++) {
  212. uint32_t retval;
  213. err = target_read_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), &retval);
  214. if (err != ERROR_OK)
  215. return err;
  216. if ((retval & str7x_info->busy_bits) == 0)
  217. return ERROR_OK;
  218. alive_sleep(1);
  219. }
  220. LOG_ERROR("Timed out waiting for str7x flash");
  221. return ERROR_FAIL;
  222. }
  223. static int str7x_result(struct flash_bank *bank)
  224. {
  225. struct target *target = bank->target;
  226. uint32_t flash_flags;
  227. int retval;
  228. retval = target_read_u32(target, str7x_get_flash_adr(bank, FLASH_ER), &flash_flags);
  229. if (retval != ERROR_OK)
  230. return retval;
  231. if (flash_flags & FLASH_WPF) {
  232. LOG_ERROR("str7x hw write protection set");
  233. retval = ERROR_FAIL;
  234. }
  235. if (flash_flags & FLASH_RESER) {
  236. LOG_ERROR("str7x suspended program erase not resumed");
  237. retval = ERROR_FAIL;
  238. }
  239. if (flash_flags & FLASH_10ER) {
  240. LOG_ERROR("str7x trying to set bit to 1 when it is already 0");
  241. retval = ERROR_FAIL;
  242. }
  243. if (flash_flags & FLASH_PGER) {
  244. LOG_ERROR("str7x program error");
  245. retval = ERROR_FAIL;
  246. }
  247. if (flash_flags & FLASH_ERER) {
  248. LOG_ERROR("str7x erase error");
  249. retval = ERROR_FAIL;
  250. }
  251. if (retval == ERROR_OK) {
  252. if (flash_flags & FLASH_ERR) {
  253. /* this should always be set if one of the others are set... */
  254. LOG_ERROR("str7x write operation failed / bad setup");
  255. retval = ERROR_FAIL;
  256. }
  257. }
  258. return retval;
  259. }
  260. static int str7x_protect_check(struct flash_bank *bank)
  261. {
  262. struct str7x_flash_bank *str7x_info = bank->driver_priv;
  263. struct target *target = bank->target;
  264. int i;
  265. uint32_t flash_flags;
  266. if (bank->target->state != TARGET_HALTED) {
  267. LOG_ERROR("Target not halted");
  268. return ERROR_TARGET_NOT_HALTED;
  269. }
  270. int retval;
  271. retval = target_read_u32(target, str7x_get_flash_adr(bank, FLASH_NVWPAR), &flash_flags);
  272. if (retval != ERROR_OK)
  273. return retval;
  274. for (i = 0; i < bank->num_sectors; i++) {
  275. if (flash_flags & str7x_info->sector_bits[i])
  276. bank->sectors[i].is_protected = 0;
  277. else
  278. bank->sectors[i].is_protected = 1;
  279. }
  280. return ERROR_OK;
  281. }
  282. static int str7x_erase(struct flash_bank *bank, int first, int last)
  283. {
  284. struct str7x_flash_bank *str7x_info = bank->driver_priv;
  285. struct target *target = bank->target;
  286. int i;
  287. uint32_t cmd;
  288. uint32_t sectors = 0;
  289. int err;
  290. if (bank->target->state != TARGET_HALTED) {
  291. LOG_ERROR("Target not halted");
  292. return ERROR_TARGET_NOT_HALTED;
  293. }
  294. for (i = first; i <= last; i++)
  295. sectors |= str7x_info->sector_bits[i];
  296. LOG_DEBUG("sectors: 0x%" PRIx32 "", sectors);
  297. /* clear FLASH_ER register */
  298. err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_ER), 0x0);
  299. if (err != ERROR_OK)
  300. return err;
  301. cmd = FLASH_SER;
  302. err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
  303. if (err != ERROR_OK)
  304. return err;
  305. cmd = sectors;
  306. err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR1), cmd);
  307. if (err != ERROR_OK)
  308. return err;
  309. cmd = FLASH_SER | FLASH_WMS;
  310. err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
  311. if (err != ERROR_OK)
  312. return err;
  313. err = str7x_waitbusy(bank);
  314. if (err != ERROR_OK)
  315. return err;
  316. err = str7x_result(bank);
  317. if (err != ERROR_OK)
  318. return err;
  319. for (i = first; i <= last; i++)
  320. bank->sectors[i].is_erased = 1;
  321. return ERROR_OK;
  322. }
  323. static int str7x_protect(struct flash_bank *bank, int set, int first, int last)
  324. {
  325. struct str7x_flash_bank *str7x_info = bank->driver_priv;
  326. struct target *target = bank->target;
  327. int i;
  328. uint32_t cmd;
  329. uint32_t protect_blocks;
  330. if (bank->target->state != TARGET_HALTED) {
  331. LOG_ERROR("Target not halted");
  332. return ERROR_TARGET_NOT_HALTED;
  333. }
  334. protect_blocks = 0xFFFFFFFF;
  335. if (set) {
  336. for (i = first; i <= last; i++)
  337. protect_blocks &= ~(str7x_info->sector_bits[i]);
  338. }
  339. /* clear FLASH_ER register */
  340. int err;
  341. err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_ER), 0x0);
  342. if (err != ERROR_OK)
  343. return err;
  344. cmd = FLASH_SPR;
  345. err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
  346. if (err != ERROR_OK)
  347. return err;
  348. cmd = str7x_get_flash_adr(bank, FLASH_NVWPAR);
  349. err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), cmd);
  350. if (err != ERROR_OK)
  351. return err;
  352. cmd = protect_blocks;
  353. err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_DR0), cmd);
  354. if (err != ERROR_OK)
  355. return err;
  356. cmd = FLASH_SPR | FLASH_WMS;
  357. err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
  358. if (err != ERROR_OK)
  359. return err;
  360. err = str7x_waitbusy(bank);
  361. if (err != ERROR_OK)
  362. return err;
  363. err = str7x_result(bank);
  364. if (err != ERROR_OK)
  365. return err;
  366. return ERROR_OK;
  367. }
  368. static int str7x_write_block(struct flash_bank *bank, const uint8_t *buffer,
  369. uint32_t offset, uint32_t count)
  370. {
  371. struct str7x_flash_bank *str7x_info = bank->driver_priv;
  372. struct target *target = bank->target;
  373. uint32_t buffer_size = 32768;
  374. struct working_area *write_algorithm;
  375. struct working_area *source;
  376. uint32_t address = bank->base + offset;
  377. struct reg_param reg_params[6];
  378. struct arm_algorithm arm_algo;
  379. int retval = ERROR_OK;
  380. /* see contib/loaders/flash/str7x.s for src */
  381. static const uint32_t str7x_flash_write_code[] = {
  382. /* write: */
  383. 0xe3a04201, /* mov r4, #0x10000000 */
  384. 0xe5824000, /* str r4, [r2, #0x0] */
  385. 0xe5821010, /* str r1, [r2, #0x10] */
  386. 0xe4904004, /* ldr r4, [r0], #4 */
  387. 0xe5824008, /* str r4, [r2, #0x8] */
  388. 0xe4904004, /* ldr r4, [r0], #4 */
  389. 0xe582400c, /* str r4, [r2, #0xc] */
  390. 0xe3a04209, /* mov r4, #0x90000000 */
  391. 0xe5824000, /* str r4, [r2, #0x0] */
  392. /* busy: */
  393. 0xe5924000, /* ldr r4, [r2, #0x0] */
  394. 0xe1140005, /* tst r4, r5 */
  395. 0x1afffffc, /* bne busy */
  396. 0xe5924014, /* ldr r4, [r2, #0x14] */
  397. 0xe31400ff, /* tst r4, #0xff */
  398. 0x03140c01, /* tsteq r4, #0x100 */
  399. 0x1a000002, /* bne exit */
  400. 0xe2811008, /* add r1, r1, #0x8 */
  401. 0xe2533001, /* subs r3, r3, #1 */
  402. 0x1affffec, /* bne write */
  403. /* exit: */
  404. 0xeafffffe, /* b exit */
  405. };
  406. /* flash write code */
  407. if (target_alloc_working_area_try(target, sizeof(str7x_flash_write_code),
  408. &write_algorithm) != ERROR_OK) {
  409. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  410. }
  411. uint8_t code[sizeof(str7x_flash_write_code)];
  412. target_buffer_set_u32_array(target, code, ARRAY_SIZE(str7x_flash_write_code),
  413. str7x_flash_write_code);
  414. target_write_buffer(target, write_algorithm->address, sizeof(code), code);
  415. /* memory buffer */
  416. while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
  417. buffer_size /= 2;
  418. if (buffer_size <= 256) {
  419. /* we already allocated the writing code, but failed to get a
  420. * buffer, free the algorithm */
  421. target_free_working_area(target, write_algorithm);
  422. LOG_WARNING("no large enough working area available, can't do block memory writes");
  423. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  424. }
  425. }
  426. arm_algo.common_magic = ARM_COMMON_MAGIC;
  427. arm_algo.core_mode = ARM_MODE_SVC;
  428. arm_algo.core_state = ARM_STATE_ARM;
  429. init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
  430. init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
  431. init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
  432. init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
  433. init_reg_param(&reg_params[4], "r4", 32, PARAM_IN);
  434. init_reg_param(&reg_params[5], "r5", 32, PARAM_OUT);
  435. while (count > 0) {
  436. uint32_t thisrun_count = (count > (buffer_size / 8)) ? (buffer_size / 8) : count;
  437. target_write_buffer(target, source->address, thisrun_count * 8, buffer);
  438. buf_set_u32(reg_params[0].value, 0, 32, source->address);
  439. buf_set_u32(reg_params[1].value, 0, 32, address);
  440. buf_set_u32(reg_params[2].value, 0, 32, str7x_get_flash_adr(bank, FLASH_CR0));
  441. buf_set_u32(reg_params[3].value, 0, 32, thisrun_count);
  442. buf_set_u32(reg_params[5].value, 0, 32, str7x_info->busy_bits);
  443. retval = target_run_algorithm(target, 0, NULL, 6, reg_params,
  444. write_algorithm->address,
  445. write_algorithm->address + (sizeof(str7x_flash_write_code) - 4),
  446. 10000, &arm_algo);
  447. if (retval != ERROR_OK)
  448. break;
  449. if (buf_get_u32(reg_params[4].value, 0, 32) != 0x00) {
  450. retval = str7x_result(bank);
  451. break;
  452. }
  453. buffer += thisrun_count * 8;
  454. address += thisrun_count * 8;
  455. count -= thisrun_count;
  456. }
  457. target_free_working_area(target, source);
  458. target_free_working_area(target, write_algorithm);
  459. destroy_reg_param(&reg_params[0]);
  460. destroy_reg_param(&reg_params[1]);
  461. destroy_reg_param(&reg_params[2]);
  462. destroy_reg_param(&reg_params[3]);
  463. destroy_reg_param(&reg_params[4]);
  464. destroy_reg_param(&reg_params[5]);
  465. return retval;
  466. }
  467. static int str7x_write(struct flash_bank *bank, const uint8_t *buffer,
  468. uint32_t offset, uint32_t count)
  469. {
  470. struct target *target = bank->target;
  471. uint32_t dwords_remaining = (count / 8);
  472. uint32_t bytes_remaining = (count & 0x00000007);
  473. uint32_t address = bank->base + offset;
  474. uint32_t bytes_written = 0;
  475. uint32_t cmd;
  476. int retval;
  477. uint32_t check_address = offset;
  478. int i;
  479. if (bank->target->state != TARGET_HALTED) {
  480. LOG_ERROR("Target not halted");
  481. return ERROR_TARGET_NOT_HALTED;
  482. }
  483. if (offset & 0x7) {
  484. LOG_WARNING("offset 0x%" PRIx32 " breaks required 8-byte alignment", offset);
  485. return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
  486. }
  487. for (i = 0; i < bank->num_sectors; i++) {
  488. uint32_t sec_start = bank->sectors[i].offset;
  489. uint32_t sec_end = sec_start + bank->sectors[i].size;
  490. /* check if destination falls within the current sector */
  491. if ((check_address >= sec_start) && (check_address < sec_end)) {
  492. /* check if destination ends in the current sector */
  493. if (offset + count < sec_end)
  494. check_address = offset + count;
  495. else
  496. check_address = sec_end;
  497. }
  498. }
  499. if (check_address != offset + count)
  500. return ERROR_FLASH_DST_OUT_OF_BANK;
  501. /* clear FLASH_ER register */
  502. target_write_u32(target, str7x_get_flash_adr(bank, FLASH_ER), 0x0);
  503. /* multiple dwords (8-byte) to be programmed? */
  504. if (dwords_remaining > 0) {
  505. /* try using a block write */
  506. retval = str7x_write_block(bank, buffer, offset, dwords_remaining);
  507. if (retval != ERROR_OK) {
  508. if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
  509. /* if block write failed (no sufficient working area),
  510. * we use normal (slow) single dword accesses */
  511. LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
  512. } else {
  513. return retval;
  514. }
  515. } else {
  516. buffer += dwords_remaining * 8;
  517. address += dwords_remaining * 8;
  518. dwords_remaining = 0;
  519. }
  520. }
  521. while (dwords_remaining > 0) {
  522. /* command */
  523. cmd = FLASH_DWPG;
  524. target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
  525. /* address */
  526. target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), address);
  527. /* data word 1 */
  528. target_write_memory(target, str7x_get_flash_adr(bank, FLASH_DR0),
  529. 4, 1, buffer + bytes_written);
  530. bytes_written += 4;
  531. /* data word 2 */
  532. target_write_memory(target, str7x_get_flash_adr(bank, FLASH_DR1),
  533. 4, 1, buffer + bytes_written);
  534. bytes_written += 4;
  535. /* start programming cycle */
  536. cmd = FLASH_DWPG | FLASH_WMS;
  537. target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
  538. int err;
  539. err = str7x_waitbusy(bank);
  540. if (err != ERROR_OK)
  541. return err;
  542. err = str7x_result(bank);
  543. if (err != ERROR_OK)
  544. return err;
  545. dwords_remaining--;
  546. address += 8;
  547. }
  548. if (bytes_remaining) {
  549. uint8_t last_dword[8] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
  550. /* copy the last remaining bytes into the write buffer */
  551. memcpy(last_dword, buffer+bytes_written, bytes_remaining);
  552. /* command */
  553. cmd = FLASH_DWPG;
  554. target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
  555. /* address */
  556. target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), address);
  557. /* data word 1 */
  558. target_write_memory(target, str7x_get_flash_adr(bank, FLASH_DR0),
  559. 4, 1, last_dword);
  560. /* data word 2 */
  561. target_write_memory(target, str7x_get_flash_adr(bank, FLASH_DR1),
  562. 4, 1, last_dword + 4);
  563. /* start programming cycle */
  564. cmd = FLASH_DWPG | FLASH_WMS;
  565. target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
  566. int err;
  567. err = str7x_waitbusy(bank);
  568. if (err != ERROR_OK)
  569. return err;
  570. err = str7x_result(bank);
  571. if (err != ERROR_OK)
  572. return err;
  573. }
  574. return ERROR_OK;
  575. }
  576. static int str7x_probe(struct flash_bank *bank)
  577. {
  578. return ERROR_OK;
  579. }
  580. #if 0
  581. COMMAND_HANDLER(str7x_handle_part_id_command)
  582. {
  583. return ERROR_OK;
  584. }
  585. #endif
  586. static int get_str7x_info(struct flash_bank *bank, char *buf, int buf_size)
  587. {
  588. /* Setting the write protection on a sector is a permanent change but it
  589. * can be disabled temporarily. FLASH_NVWPAR reflects the permanent
  590. * protection state of the sectors, not the temporary.
  591. */
  592. snprintf(buf, buf_size, "STR7x flash protection info is only valid after a power cycle, "
  593. "clearing the protection is only temporary and may not be reflected in the current "
  594. "info returned.");
  595. return ERROR_OK;
  596. }
  597. COMMAND_HANDLER(str7x_handle_disable_jtag_command)
  598. {
  599. struct target *target = NULL;
  600. struct str7x_flash_bank *str7x_info = NULL;
  601. uint32_t flash_cmd;
  602. uint16_t ProtectionLevel = 0;
  603. uint16_t ProtectionRegs;
  604. if (CMD_ARGC < 1)
  605. return ERROR_COMMAND_SYNTAX_ERROR;
  606. struct flash_bank *bank;
  607. int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
  608. if (ERROR_OK != retval)
  609. return retval;
  610. str7x_info = bank->driver_priv;
  611. target = bank->target;
  612. if (target->state != TARGET_HALTED) {
  613. LOG_ERROR("Target not halted");
  614. return ERROR_TARGET_NOT_HALTED;
  615. }
  616. /* first we get protection status */
  617. uint32_t reg;
  618. target_read_u32(target, str7x_get_flash_adr(bank, FLASH_NVAPR0), &reg);
  619. if (!(reg & str7x_info->disable_bit))
  620. ProtectionLevel = 1;
  621. target_read_u32(target, str7x_get_flash_adr(bank, FLASH_NVAPR1), &reg);
  622. ProtectionRegs = ~(reg >> 16);
  623. while (((ProtectionRegs) != 0) && (ProtectionLevel < 16)) {
  624. ProtectionRegs >>= 1;
  625. ProtectionLevel++;
  626. }
  627. if (ProtectionLevel == 0) {
  628. flash_cmd = FLASH_SPR;
  629. target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), flash_cmd);
  630. target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), 0x4010DFB8);
  631. target_write_u32(target, str7x_get_flash_adr(bank, FLASH_DR0), 0xFFFFFFFD);
  632. flash_cmd = FLASH_SPR | FLASH_WMS;
  633. target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), flash_cmd);
  634. } else {
  635. flash_cmd = FLASH_SPR;
  636. target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), flash_cmd);
  637. target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), 0x4010DFBC);
  638. target_write_u32(target, str7x_get_flash_adr(bank, FLASH_DR0),
  639. ~(1 << (15 + ProtectionLevel)));
  640. flash_cmd = FLASH_SPR | FLASH_WMS;
  641. target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), flash_cmd);
  642. }
  643. return ERROR_OK;
  644. }
  645. static const struct command_registration str7x_exec_command_handlers[] = {
  646. {
  647. .name = "disable_jtag",
  648. .usage = "<bank>",
  649. .handler = str7x_handle_disable_jtag_command,
  650. .mode = COMMAND_EXEC,
  651. .help = "disable jtag access",
  652. },
  653. COMMAND_REGISTRATION_DONE
  654. };
  655. static const struct command_registration str7x_command_handlers[] = {
  656. {
  657. .name = "str7x",
  658. .mode = COMMAND_ANY,
  659. .help = "str7x flash command group",
  660. .usage = "",
  661. .chain = str7x_exec_command_handlers,
  662. },
  663. COMMAND_REGISTRATION_DONE
  664. };
  665. struct flash_driver str7x_flash = {
  666. .name = "str7x",
  667. .commands = str7x_command_handlers,
  668. .flash_bank_command = str7x_flash_bank_command,
  669. .erase = str7x_erase,
  670. .protect = str7x_protect,
  671. .write = str7x_write,
  672. .read = default_flash_read,
  673. .probe = str7x_probe,
  674. .auto_probe = str7x_probe,
  675. .erase_check = default_flash_blank_check,
  676. .protect_check = str7x_protect_check,
  677. .info = get_str7x_info,
  678. };