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  1. /***************************************************************************
  2. * Copyright (C) 2005 by Dominic Rath *
  3. * Dominic.Rath@gmx.de *
  4. * *
  5. * Copyright (C) 2008 by Spencer Oliver *
  6. * spen@spen-soft.co.uk *
  7. * *
  8. * This program is free software; you can redistribute it and/or modify *
  9. * it under the terms of the GNU General Public License as published by *
  10. * the Free Software Foundation; either version 2 of the License, or *
  11. * (at your option) any later version. *
  12. * *
  13. * This program is distributed in the hope that it will be useful, *
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  16. * GNU General Public License for more details. *
  17. * *
  18. * You should have received a copy of the GNU General Public License *
  19. * along with this program; if not, write to the *
  20. * Free Software Foundation, Inc., *
  21. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
  22. ***************************************************************************/
  23. #ifdef HAVE_CONFIG_H
  24. #include "config.h"
  25. #endif
  26. #include "replacements.h"
  27. #include "str9xpec.h"
  28. #include "flash.h"
  29. #include "target.h"
  30. #include "log.h"
  31. #include "armv4_5.h"
  32. #include "arm7_9_common.h"
  33. #include "jtag.h"
  34. #include "binarybuffer.h"
  35. #include <stdlib.h>
  36. #include <string.h>
  37. #include <unistd.h>
  38. #include <getopt.h>
  39. int str9xpec_register_commands(struct command_context_s *cmd_ctx);
  40. int str9xpec_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
  41. int str9xpec_erase(struct flash_bank_s *bank, int first, int last);
  42. int str9xpec_protect(struct flash_bank_s *bank, int set, int first, int last);
  43. int str9xpec_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
  44. int str9xpec_probe(struct flash_bank_s *bank);
  45. int str9xpec_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  46. int str9xpec_protect_check(struct flash_bank_s *bank);
  47. int str9xpec_erase_check(struct flash_bank_s *bank);
  48. int str9xpec_info(struct flash_bank_s *bank, char *buf, int buf_size);
  49. int str9xpec_erase_area(struct flash_bank_s *bank, int first, int last);
  50. int str9xpec_set_address(struct flash_bank_s *bank, u8 sector);
  51. int str9xpec_write_options(struct flash_bank_s *bank);
  52. int str9xpec_handle_flash_options_cmap_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  53. int str9xpec_handle_flash_options_lvdthd_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  54. int str9xpec_handle_flash_options_lvdsel_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  55. int str9xpec_handle_flash_options_lvdwarn_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  56. int str9xpec_handle_flash_options_read_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  57. int str9xpec_handle_flash_options_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  58. int str9xpec_handle_flash_lock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  59. int str9xpec_handle_flash_unlock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  60. int str9xpec_handle_flash_enable_turbo_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  61. int str9xpec_handle_flash_disable_turbo_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  62. flash_driver_t str9xpec_flash =
  63. {
  64. .name = "str9xpec",
  65. .register_commands = str9xpec_register_commands,
  66. .flash_bank_command = str9xpec_flash_bank_command,
  67. .erase = str9xpec_erase,
  68. .protect = str9xpec_protect,
  69. .write = str9xpec_write,
  70. .probe = str9xpec_probe,
  71. .auto_probe = str9xpec_probe,
  72. .erase_check = str9xpec_erase_check,
  73. .protect_check = str9xpec_protect_check,
  74. .info = str9xpec_info
  75. };
  76. int str9xpec_register_commands(struct command_context_s *cmd_ctx)
  77. {
  78. command_t *str9xpec_cmd = register_command(cmd_ctx, NULL, "str9xpec", NULL, COMMAND_ANY, "str9xpec flash specific commands");
  79. register_command(cmd_ctx, str9xpec_cmd, "enable_turbo", str9xpec_handle_flash_enable_turbo_command, COMMAND_EXEC,
  80. "enable str9xpec turbo mode");
  81. register_command(cmd_ctx, str9xpec_cmd, "disable_turbo", str9xpec_handle_flash_disable_turbo_command, COMMAND_EXEC,
  82. "disable str9xpec turbo mode");
  83. register_command(cmd_ctx, str9xpec_cmd, "options_cmap", str9xpec_handle_flash_options_cmap_command, COMMAND_EXEC,
  84. "configure str9xpec boot sector");
  85. register_command(cmd_ctx, str9xpec_cmd, "options_lvdthd", str9xpec_handle_flash_options_lvdthd_command, COMMAND_EXEC,
  86. "configure str9xpec lvd threshold");
  87. register_command(cmd_ctx, str9xpec_cmd, "options_lvdsel", str9xpec_handle_flash_options_lvdsel_command, COMMAND_EXEC,
  88. "configure str9xpec lvd selection");
  89. register_command(cmd_ctx, str9xpec_cmd, "options_lvdwarn", str9xpec_handle_flash_options_lvdwarn_command, COMMAND_EXEC,
  90. "configure str9xpec lvd warning");
  91. register_command(cmd_ctx, str9xpec_cmd, "options_read", str9xpec_handle_flash_options_read_command, COMMAND_EXEC,
  92. "read str9xpec options");
  93. register_command(cmd_ctx, str9xpec_cmd, "options_write", str9xpec_handle_flash_options_write_command, COMMAND_EXEC,
  94. "write str9xpec options");
  95. register_command(cmd_ctx, str9xpec_cmd, "lock", str9xpec_handle_flash_lock_command, COMMAND_EXEC,
  96. "lock str9xpec device");
  97. register_command(cmd_ctx, str9xpec_cmd, "unlock", str9xpec_handle_flash_unlock_command, COMMAND_EXEC,
  98. "unlock str9xpec device");
  99. register_command(cmd_ctx, str9xpec_cmd, "part_id", str9xpec_handle_part_id_command, COMMAND_EXEC,
  100. "print part id of str9xpec flash bank <num>");
  101. return ERROR_OK;
  102. }
  103. int str9xpec_set_instr(jtag_tap_t *tap, u32 new_instr, tap_state_t end_state)
  104. {
  105. if( tap == NULL ){
  106. return ERROR_TARGET_INVALID;
  107. }
  108. if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr)
  109. {
  110. scan_field_t field;
  111. field.tap = tap;
  112. field.num_bits = tap->ir_length;
  113. field.out_value = calloc(CEIL(field.num_bits, 8), 1);
  114. buf_set_u32(field.out_value, 0, field.num_bits, new_instr);
  115. field.out_mask = NULL;
  116. field.in_value = NULL;
  117. field.in_check_value = NULL;
  118. field.in_check_mask = NULL;
  119. field.in_handler = NULL;
  120. field.in_handler_priv = NULL;
  121. jtag_add_ir_scan(1, &field, end_state);
  122. free(field.out_value);
  123. }
  124. return ERROR_OK;
  125. }
  126. u8 str9xpec_isc_status(jtag_tap_t *tap)
  127. {
  128. scan_field_t field;
  129. u8 status;
  130. if (str9xpec_set_instr(tap, ISC_NOOP, TAP_IRPAUSE) != ERROR_OK)
  131. return ISC_STATUS_ERROR;
  132. field.tap = tap;
  133. field.num_bits = 8;
  134. field.out_value = NULL;
  135. field.out_mask = NULL;
  136. field.in_value = &status;
  137. field.in_check_value = NULL;
  138. field.in_check_mask = NULL;
  139. field.in_handler = NULL;
  140. field.in_handler_priv = NULL;
  141. jtag_add_dr_scan(1, &field, TAP_IDLE);
  142. jtag_execute_queue();
  143. LOG_DEBUG("status: 0x%2.2x", status);
  144. if (status & ISC_STATUS_SECURITY)
  145. LOG_INFO("Device Security Bit Set");
  146. return status;
  147. }
  148. int str9xpec_isc_enable(struct flash_bank_s *bank)
  149. {
  150. u8 status;
  151. jtag_tap_t *tap;
  152. str9xpec_flash_controller_t *str9xpec_info = bank->driver_priv;
  153. tap = str9xpec_info->tap;
  154. if (str9xpec_info->isc_enable)
  155. return ERROR_OK;
  156. /* enter isc mode */
  157. if (str9xpec_set_instr(tap, ISC_ENABLE, TAP_IDLE) != ERROR_OK)
  158. return ERROR_TARGET_INVALID;
  159. /* check ISC status */
  160. status = str9xpec_isc_status(tap);
  161. if (status & ISC_STATUS_MODE)
  162. {
  163. /* we have entered isc mode */
  164. str9xpec_info->isc_enable = 1;
  165. LOG_DEBUG("ISC_MODE Enabled");
  166. }
  167. return ERROR_OK;
  168. }
  169. int str9xpec_isc_disable(struct flash_bank_s *bank)
  170. {
  171. u8 status;
  172. jtag_tap_t *tap;
  173. str9xpec_flash_controller_t *str9xpec_info = bank->driver_priv;
  174. tap = str9xpec_info->tap;
  175. if (!str9xpec_info->isc_enable)
  176. return ERROR_OK;
  177. if (str9xpec_set_instr(tap, ISC_DISABLE, TAP_IDLE) != ERROR_OK)
  178. return ERROR_TARGET_INVALID;
  179. /* delay to handle aborts */
  180. jtag_add_sleep(50);
  181. /* check ISC status */
  182. status = str9xpec_isc_status(tap);
  183. if (!(status & ISC_STATUS_MODE))
  184. {
  185. /* we have left isc mode */
  186. str9xpec_info->isc_enable = 0;
  187. LOG_DEBUG("ISC_MODE Disabled");
  188. }
  189. return ERROR_OK;
  190. }
  191. int str9xpec_read_config(struct flash_bank_s *bank)
  192. {
  193. scan_field_t field;
  194. u8 status;
  195. jtag_tap_t *tap;
  196. str9xpec_flash_controller_t *str9xpec_info = bank->driver_priv;
  197. tap = str9xpec_info->tap;
  198. LOG_DEBUG("ISC_CONFIGURATION");
  199. /* execute ISC_CONFIGURATION command */
  200. str9xpec_set_instr(tap, ISC_CONFIGURATION, TAP_IRPAUSE);
  201. field.tap = tap;
  202. field.num_bits = 64;
  203. field.out_value = NULL;
  204. field.out_mask = NULL;
  205. field.in_value = str9xpec_info->options;
  206. field.in_check_value = NULL;
  207. field.in_check_mask = NULL;
  208. field.in_handler = NULL;
  209. field.in_handler_priv = NULL;
  210. jtag_add_dr_scan(1, &field, TAP_IDLE);
  211. jtag_execute_queue();
  212. status = str9xpec_isc_status(tap);
  213. return status;
  214. }
  215. int str9xpec_build_block_list(struct flash_bank_s *bank)
  216. {
  217. str9xpec_flash_controller_t *str9xpec_info = bank->driver_priv;
  218. int i;
  219. int num_sectors;
  220. int b0_sectors = 0, b1_sectors = 0;
  221. u32 offset = 0;
  222. int b1_size = 0x2000;
  223. switch (bank->size)
  224. {
  225. case (256 * 1024):
  226. b0_sectors = 4;
  227. break;
  228. case (512 * 1024):
  229. b0_sectors = 8;
  230. break;
  231. case (1024 * 1024):
  232. b0_sectors = 16;
  233. break;
  234. case (2048 * 1024):
  235. b0_sectors = 32;
  236. break;
  237. case (128 * 1024):
  238. b1_size = 0x4000;
  239. b1_sectors = 8;
  240. break;
  241. case (32 * 1024):
  242. b1_sectors = 4;
  243. break;
  244. default:
  245. LOG_ERROR("BUG: unknown bank->size encountered");
  246. exit(-1);
  247. }
  248. num_sectors = b0_sectors + b1_sectors;
  249. bank->num_sectors = num_sectors;
  250. bank->sectors = malloc(sizeof(flash_sector_t) * num_sectors);
  251. str9xpec_info->sector_bits = malloc(sizeof(u32) * num_sectors);
  252. num_sectors = 0;
  253. for (i = 0; i < b0_sectors; i++)
  254. {
  255. bank->sectors[num_sectors].offset = offset;
  256. bank->sectors[num_sectors].size = 0x10000;
  257. offset += bank->sectors[i].size;
  258. bank->sectors[num_sectors].is_erased = -1;
  259. bank->sectors[num_sectors].is_protected = 1;
  260. str9xpec_info->sector_bits[num_sectors++] = i;
  261. }
  262. for (i = 0; i < b1_sectors; i++)
  263. {
  264. bank->sectors[num_sectors].offset = offset;
  265. bank->sectors[num_sectors].size = b1_size;
  266. offset += bank->sectors[i].size;
  267. bank->sectors[num_sectors].is_erased = -1;
  268. bank->sectors[num_sectors].is_protected = 1;
  269. str9xpec_info->sector_bits[num_sectors++] = i + 32;
  270. }
  271. return ERROR_OK;
  272. }
  273. /* flash bank str9x <base> <size> 0 0 <target#>
  274. */
  275. int str9xpec_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
  276. {
  277. str9xpec_flash_controller_t *str9xpec_info;
  278. armv4_5_common_t *armv4_5 = NULL;
  279. arm7_9_common_t *arm7_9 = NULL;
  280. arm_jtag_t *jtag_info = NULL;
  281. if (argc < 6)
  282. {
  283. LOG_WARNING("incomplete flash_bank str9x configuration");
  284. return ERROR_FLASH_BANK_INVALID;
  285. }
  286. str9xpec_info = malloc(sizeof(str9xpec_flash_controller_t));
  287. bank->driver_priv = str9xpec_info;
  288. /* find out jtag position of flash controller
  289. * it is always after the arm966 core */
  290. armv4_5 = bank->target->arch_info;
  291. arm7_9 = armv4_5->arch_info;
  292. jtag_info = &arm7_9->jtag_info;
  293. str9xpec_info->tap = jtag_TapByAbsPosition( jtag_info->tap->abs_chain_position - 1);
  294. str9xpec_info->isc_enable = 0;
  295. str9xpec_build_block_list(bank);
  296. /* clear option byte register */
  297. buf_set_u32(str9xpec_info->options, 0, 64, 0);
  298. return ERROR_OK;
  299. }
  300. int str9xpec_blank_check(struct flash_bank_s *bank, int first, int last)
  301. {
  302. scan_field_t field;
  303. u8 status;
  304. jtag_tap_t *tap;
  305. int i;
  306. u8 *buffer = NULL;
  307. str9xpec_flash_controller_t *str9xpec_info = bank->driver_priv;
  308. tap = str9xpec_info->tap;
  309. if (!str9xpec_info->isc_enable) {
  310. str9xpec_isc_enable( bank );
  311. }
  312. if (!str9xpec_info->isc_enable) {
  313. return ERROR_FLASH_OPERATION_FAILED;
  314. }
  315. buffer = calloc(CEIL(64, 8), 1);
  316. LOG_DEBUG("blank check: first_bank: %i, last_bank: %i", first, last);
  317. for (i = first; i <= last; i++) {
  318. buf_set_u32(buffer, str9xpec_info->sector_bits[i], 1, 1);
  319. }
  320. /* execute ISC_BLANK_CHECK command */
  321. str9xpec_set_instr(tap, ISC_BLANK_CHECK, TAP_IRPAUSE);
  322. field.tap = tap;
  323. field.num_bits = 64;
  324. field.out_value = buffer;
  325. field.out_mask = NULL;
  326. field.in_value = NULL;
  327. field.in_check_value = NULL;
  328. field.in_check_mask = NULL;
  329. field.in_handler = NULL;
  330. field.in_handler_priv = NULL;
  331. jtag_add_dr_scan(1, &field, TAP_IDLE);
  332. jtag_add_sleep(40000);
  333. /* read blank check result */
  334. field.tap = tap;
  335. field.num_bits = 64;
  336. field.out_value = NULL;
  337. field.out_mask = NULL;
  338. field.in_value = buffer;
  339. field.in_check_value = NULL;
  340. field.in_check_mask = NULL;
  341. field.in_handler = NULL;
  342. field.in_handler_priv = NULL;
  343. jtag_add_dr_scan(1, &field, TAP_IRPAUSE);
  344. jtag_execute_queue();
  345. status = str9xpec_isc_status(tap);
  346. for (i = first; i <= last; i++)
  347. {
  348. if (buf_get_u32(buffer, str9xpec_info->sector_bits[i], 1))
  349. bank->sectors[i].is_erased = 0;
  350. else
  351. bank->sectors[i].is_erased = 1;
  352. }
  353. free(buffer);
  354. str9xpec_isc_disable(bank);
  355. if ((status & ISC_STATUS_ERROR) != STR9XPEC_ISC_SUCCESS)
  356. return ERROR_FLASH_OPERATION_FAILED;
  357. return ERROR_OK;
  358. }
  359. int str9xpec_protect_check(struct flash_bank_s *bank)
  360. {
  361. u8 status;
  362. int i;
  363. str9xpec_flash_controller_t *str9xpec_info = bank->driver_priv;
  364. status = str9xpec_read_config(bank);
  365. for (i = 0; i < bank->num_sectors; i++)
  366. {
  367. if (buf_get_u32(str9xpec_info->options, str9xpec_info->sector_bits[i], 1))
  368. bank->sectors[i].is_protected = 1;
  369. else
  370. bank->sectors[i].is_protected = 0;
  371. }
  372. if ((status & ISC_STATUS_ERROR) != STR9XPEC_ISC_SUCCESS)
  373. return ERROR_FLASH_OPERATION_FAILED;
  374. return ERROR_OK;
  375. }
  376. int str9xpec_erase_area(struct flash_bank_s *bank, int first, int last)
  377. {
  378. scan_field_t field;
  379. u8 status;
  380. jtag_tap_t *tap;
  381. int i;
  382. u8 *buffer = NULL;
  383. str9xpec_flash_controller_t *str9xpec_info = bank->driver_priv;
  384. tap = str9xpec_info->tap;
  385. if (!str9xpec_info->isc_enable) {
  386. str9xpec_isc_enable( bank );
  387. }
  388. if (!str9xpec_info->isc_enable) {
  389. return ISC_STATUS_ERROR;
  390. }
  391. buffer = calloc(CEIL(64, 8), 1);
  392. LOG_DEBUG("erase: first_bank: %i, last_bank: %i", first, last);
  393. /* last bank: 0xFF signals a full erase (unlock complete device) */
  394. /* last bank: 0xFE signals a option byte erase */
  395. if (last == 0xFF)
  396. {
  397. for (i = 0; i < 64; i++) {
  398. buf_set_u32(buffer, i, 1, 1);
  399. }
  400. }
  401. else if (last == 0xFE)
  402. {
  403. buf_set_u32(buffer, 49, 1, 1);
  404. }
  405. else
  406. {
  407. for (i = first; i <= last; i++) {
  408. buf_set_u32(buffer, str9xpec_info->sector_bits[i], 1, 1);
  409. }
  410. }
  411. LOG_DEBUG("ISC_ERASE");
  412. /* execute ISC_ERASE command */
  413. str9xpec_set_instr(tap, ISC_ERASE, TAP_IRPAUSE);
  414. field.tap = tap;
  415. field.num_bits = 64;
  416. field.out_value = buffer;
  417. field.out_mask = NULL;
  418. field.in_value = NULL;
  419. field.in_check_value = NULL;
  420. field.in_check_mask = NULL;
  421. field.in_handler = NULL;
  422. field.in_handler_priv = NULL;
  423. jtag_add_dr_scan(1, &field, TAP_IDLE);
  424. jtag_execute_queue();
  425. jtag_add_sleep(10);
  426. /* wait for erase completion */
  427. while (!((status = str9xpec_isc_status(tap)) & ISC_STATUS_BUSY)) {
  428. alive_sleep(1);
  429. }
  430. free(buffer);
  431. str9xpec_isc_disable(bank);
  432. return status;
  433. }
  434. int str9xpec_erase(struct flash_bank_s *bank, int first, int last)
  435. {
  436. int status;
  437. status = str9xpec_erase_area(bank, first, last);
  438. if ((status & ISC_STATUS_ERROR) != STR9XPEC_ISC_SUCCESS)
  439. return ERROR_FLASH_OPERATION_FAILED;
  440. return ERROR_OK;
  441. }
  442. int str9xpec_lock_device(struct flash_bank_s *bank)
  443. {
  444. scan_field_t field;
  445. u8 status;
  446. jtag_tap_t *tap;
  447. str9xpec_flash_controller_t *str9xpec_info = NULL;
  448. str9xpec_info = bank->driver_priv;
  449. tap = str9xpec_info->tap;
  450. if (!str9xpec_info->isc_enable) {
  451. str9xpec_isc_enable( bank );
  452. }
  453. if (!str9xpec_info->isc_enable) {
  454. return ISC_STATUS_ERROR;
  455. }
  456. /* set security address */
  457. str9xpec_set_address(bank, 0x80);
  458. /* execute ISC_PROGRAM command */
  459. str9xpec_set_instr(tap, ISC_PROGRAM_SECURITY, TAP_IDLE);
  460. str9xpec_set_instr(tap, ISC_NOOP, TAP_IRPAUSE);
  461. do {
  462. field.tap = tap;
  463. field.num_bits = 8;
  464. field.out_value = NULL;
  465. field.out_mask = NULL;
  466. field.in_value = &status;
  467. field.in_check_value = NULL;
  468. field.in_check_mask = NULL;
  469. field.in_handler = NULL;
  470. field.in_handler_priv = NULL;
  471. jtag_add_dr_scan(1, &field, -1);
  472. jtag_execute_queue();
  473. } while(!(status & ISC_STATUS_BUSY));
  474. str9xpec_isc_disable(bank);
  475. return status;
  476. }
  477. int str9xpec_unlock_device(struct flash_bank_s *bank)
  478. {
  479. u8 status;
  480. status = str9xpec_erase_area(bank, 0, 255);
  481. return status;
  482. }
  483. int str9xpec_protect(struct flash_bank_s *bank, int set, int first, int last)
  484. {
  485. u8 status;
  486. int i;
  487. str9xpec_flash_controller_t *str9xpec_info = bank->driver_priv;
  488. status = str9xpec_read_config(bank);
  489. if ((status & ISC_STATUS_ERROR) != STR9XPEC_ISC_SUCCESS)
  490. return ERROR_FLASH_OPERATION_FAILED;
  491. LOG_DEBUG("protect: first_bank: %i, last_bank: %i", first, last);
  492. /* last bank: 0xFF signals a full device protect */
  493. if (last == 0xFF)
  494. {
  495. if( set )
  496. {
  497. status = str9xpec_lock_device(bank);
  498. }
  499. else
  500. {
  501. /* perform full erase to unlock device */
  502. status = str9xpec_unlock_device(bank);
  503. }
  504. }
  505. else
  506. {
  507. for (i = first; i <= last; i++)
  508. {
  509. if( set )
  510. buf_set_u32(str9xpec_info->options, str9xpec_info->sector_bits[i], 1, 1);
  511. else
  512. buf_set_u32(str9xpec_info->options, str9xpec_info->sector_bits[i], 1, 0);
  513. }
  514. status = str9xpec_write_options(bank);
  515. }
  516. if ((status & ISC_STATUS_ERROR) != STR9XPEC_ISC_SUCCESS)
  517. return ERROR_FLASH_OPERATION_FAILED;
  518. return ERROR_OK;
  519. }
  520. int str9xpec_set_address(struct flash_bank_s *bank, u8 sector)
  521. {
  522. jtag_tap_t *tap;
  523. scan_field_t field;
  524. str9xpec_flash_controller_t *str9xpec_info = bank->driver_priv;
  525. tap = str9xpec_info->tap;
  526. /* set flash controller address */
  527. str9xpec_set_instr(tap, ISC_ADDRESS_SHIFT, TAP_IRPAUSE);
  528. field.tap = tap;
  529. field.num_bits = 8;
  530. field.out_value = &sector;
  531. field.out_mask = NULL;
  532. field.in_value = NULL;
  533. field.in_check_value = NULL;
  534. field.in_check_mask = NULL;
  535. field.in_handler = NULL;
  536. field.in_handler_priv = NULL;
  537. jtag_add_dr_scan(1, &field, -1);
  538. return ERROR_OK;
  539. }
  540. int str9xpec_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
  541. {
  542. str9xpec_flash_controller_t *str9xpec_info = bank->driver_priv;
  543. u32 dwords_remaining = (count / 8);
  544. u32 bytes_remaining = (count & 0x00000007);
  545. u32 bytes_written = 0;
  546. u8 status;
  547. u32 check_address = offset;
  548. jtag_tap_t *tap;
  549. scan_field_t field;
  550. u8 *scanbuf;
  551. int i;
  552. u32 first_sector = 0;
  553. u32 last_sector = 0;
  554. tap = str9xpec_info->tap;
  555. if (!str9xpec_info->isc_enable) {
  556. str9xpec_isc_enable(bank);
  557. }
  558. if (!str9xpec_info->isc_enable) {
  559. return ERROR_FLASH_OPERATION_FAILED;
  560. }
  561. if (offset & 0x7)
  562. {
  563. LOG_WARNING("offset 0x%x breaks required 8-byte alignment", offset);
  564. return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
  565. }
  566. for (i = 0; i < bank->num_sectors; i++)
  567. {
  568. u32 sec_start = bank->sectors[i].offset;
  569. u32 sec_end = sec_start + bank->sectors[i].size;
  570. /* check if destination falls within the current sector */
  571. if ((check_address >= sec_start) && (check_address < sec_end))
  572. {
  573. /* check if destination ends in the current sector */
  574. if (offset + count < sec_end)
  575. check_address = offset + count;
  576. else
  577. check_address = sec_end;
  578. }
  579. if ((offset >= sec_start) && (offset < sec_end)){
  580. first_sector = i;
  581. }
  582. if ((offset + count >= sec_start) && (offset + count < sec_end)){
  583. last_sector = i;
  584. }
  585. }
  586. if (check_address != offset + count)
  587. return ERROR_FLASH_DST_OUT_OF_BANK;
  588. LOG_DEBUG("first_sector: %i, last_sector: %i", first_sector, last_sector);
  589. scanbuf = calloc(CEIL(64, 8), 1);
  590. LOG_DEBUG("ISC_PROGRAM");
  591. for (i = first_sector; i <= last_sector; i++)
  592. {
  593. str9xpec_set_address(bank, str9xpec_info->sector_bits[i]);
  594. dwords_remaining = dwords_remaining < (bank->sectors[i].size/8) ? dwords_remaining : (bank->sectors[i].size/8);
  595. while (dwords_remaining > 0)
  596. {
  597. str9xpec_set_instr(tap, ISC_PROGRAM, TAP_IRPAUSE);
  598. field.tap = tap;
  599. field.num_bits = 64;
  600. field.out_value = (buffer + bytes_written);
  601. field.out_mask = NULL;
  602. field.in_value = NULL;
  603. field.in_check_value = NULL;
  604. field.in_check_mask = NULL;
  605. field.in_handler = NULL;
  606. field.in_handler_priv = NULL;
  607. jtag_add_dr_scan(1, &field, TAP_IDLE);
  608. /* small delay before polling */
  609. jtag_add_sleep(50);
  610. str9xpec_set_instr(tap, ISC_NOOP, TAP_IRPAUSE);
  611. do {
  612. field.tap = tap;
  613. field.num_bits = 8;
  614. field.out_value = NULL;
  615. field.out_mask = NULL;
  616. field.in_value = scanbuf;
  617. field.in_check_value = NULL;
  618. field.in_check_mask = NULL;
  619. field.in_handler = NULL;
  620. field.in_handler_priv = NULL;
  621. jtag_add_dr_scan(1, &field, -1);
  622. jtag_execute_queue();
  623. status = buf_get_u32(scanbuf, 0, 8);
  624. } while(!(status & ISC_STATUS_BUSY));
  625. if ((status & ISC_STATUS_ERROR) != STR9XPEC_ISC_SUCCESS)
  626. return ERROR_FLASH_OPERATION_FAILED;
  627. /* if ((status & ISC_STATUS_INT_ERROR) != STR9XPEC_ISC_INTFAIL)
  628. return ERROR_FLASH_OPERATION_FAILED; */
  629. dwords_remaining--;
  630. bytes_written += 8;
  631. }
  632. }
  633. if (bytes_remaining)
  634. {
  635. u8 last_dword[8] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
  636. int i = 0;
  637. while(bytes_remaining > 0)
  638. {
  639. last_dword[i++] = *(buffer + bytes_written);
  640. bytes_remaining--;
  641. bytes_written++;
  642. }
  643. str9xpec_set_instr(tap, ISC_PROGRAM, TAP_IRPAUSE);
  644. field.tap = tap;
  645. field.num_bits = 64;
  646. field.out_value = last_dword;
  647. field.out_mask = NULL;
  648. field.in_value = NULL;
  649. field.in_check_value = NULL;
  650. field.in_check_mask = NULL;
  651. field.in_handler = NULL;
  652. field.in_handler_priv = NULL;
  653. jtag_add_dr_scan(1, &field, TAP_IDLE);
  654. /* small delay before polling */
  655. jtag_add_sleep(50);
  656. str9xpec_set_instr(tap, ISC_NOOP, TAP_IRPAUSE);
  657. do {
  658. field.tap = tap;
  659. field.num_bits = 8;
  660. field.out_value = NULL;
  661. field.out_mask = NULL;
  662. field.in_value = scanbuf;
  663. field.in_check_value = NULL;
  664. field.in_check_mask = NULL;
  665. field.in_handler = NULL;
  666. field.in_handler_priv = NULL;
  667. jtag_add_dr_scan(1, &field, -1);
  668. jtag_execute_queue();
  669. status = buf_get_u32(scanbuf, 0, 8);
  670. } while(!(status & ISC_STATUS_BUSY));
  671. if ((status & ISC_STATUS_ERROR) != STR9XPEC_ISC_SUCCESS)
  672. return ERROR_FLASH_OPERATION_FAILED;
  673. /* if ((status & ISC_STATUS_INT_ERROR) != STR9XPEC_ISC_INTFAIL)
  674. return ERROR_FLASH_OPERATION_FAILED; */
  675. }
  676. free(scanbuf);
  677. str9xpec_isc_disable(bank);
  678. return ERROR_OK;
  679. }
  680. int str9xpec_probe(struct flash_bank_s *bank)
  681. {
  682. return ERROR_OK;
  683. }
  684. int str9xpec_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
  685. {
  686. flash_bank_t *bank;
  687. scan_field_t field;
  688. u8 *buffer = NULL;
  689. jtag_tap_t *tap;
  690. u32 idcode;
  691. str9xpec_flash_controller_t *str9xpec_info = NULL;
  692. if (argc < 1)
  693. {
  694. return ERROR_COMMAND_SYNTAX_ERROR;
  695. }
  696. bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
  697. if (!bank)
  698. {
  699. command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
  700. return ERROR_OK;
  701. }
  702. str9xpec_info = bank->driver_priv;
  703. tap = str9xpec_info->tap;
  704. buffer = calloc(CEIL(32, 8), 1);
  705. str9xpec_set_instr(tap, ISC_IDCODE, TAP_IRPAUSE);
  706. field.tap = tap;
  707. field.num_bits = 32;
  708. field.out_value = NULL;
  709. field.out_mask = NULL;
  710. field.in_value = buffer;
  711. field.in_check_value = NULL;
  712. field.in_check_mask = NULL;
  713. field.in_handler = NULL;
  714. field.in_handler_priv = NULL;
  715. jtag_add_dr_scan(1, &field, TAP_IDLE);
  716. jtag_execute_queue();
  717. idcode = buf_get_u32(buffer, 0, 32);
  718. command_print(cmd_ctx, "str9xpec part id: 0x%8.8x", idcode);
  719. free(buffer);
  720. return ERROR_OK;
  721. }
  722. int str9xpec_erase_check(struct flash_bank_s *bank)
  723. {
  724. return str9xpec_blank_check(bank, 0, bank->num_sectors - 1);
  725. }
  726. int str9xpec_info(struct flash_bank_s *bank, char *buf, int buf_size)
  727. {
  728. snprintf(buf, buf_size, "str9xpec flash driver info" );
  729. return ERROR_OK;
  730. }
  731. int str9xpec_handle_flash_options_read_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
  732. {
  733. flash_bank_t *bank;
  734. u8 status;
  735. str9xpec_flash_controller_t *str9xpec_info = NULL;
  736. if (argc < 1)
  737. {
  738. command_print(cmd_ctx, "str9xpec options_read <bank>");
  739. return ERROR_OK;
  740. }
  741. bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
  742. if (!bank)
  743. {
  744. command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
  745. return ERROR_OK;
  746. }
  747. str9xpec_info = bank->driver_priv;
  748. status = str9xpec_read_config(bank);
  749. if ((status & ISC_STATUS_ERROR) != STR9XPEC_ISC_SUCCESS)
  750. return ERROR_FLASH_OPERATION_FAILED;
  751. /* boot bank */
  752. if (buf_get_u32(str9xpec_info->options, STR9XPEC_OPT_CSMAPBIT, 1))
  753. command_print(cmd_ctx, "CS Map: bank1");
  754. else
  755. command_print(cmd_ctx, "CS Map: bank0");
  756. /* OTP lock */
  757. if (buf_get_u32(str9xpec_info->options, STR9XPEC_OPT_OTPBIT, 1))
  758. command_print(cmd_ctx, "OTP Lock: OTP Locked");
  759. else
  760. command_print(cmd_ctx, "OTP Lock: OTP Unlocked");
  761. /* LVD Threshold */
  762. if (buf_get_u32(str9xpec_info->options, STR9XPEC_OPT_LVDTHRESBIT, 1))
  763. command_print(cmd_ctx, "LVD Threshold: 2.7v");
  764. else
  765. command_print(cmd_ctx, "LVD Threshold: 2.4v");
  766. /* LVD reset warning */
  767. if (buf_get_u32(str9xpec_info->options, STR9XPEC_OPT_LVDWARNBIT, 1))
  768. command_print(cmd_ctx, "LVD Reset Warning: VDD or VDDQ Inputs");
  769. else
  770. command_print(cmd_ctx, "LVD Reset Warning: VDD Input Only");
  771. /* LVD reset select */
  772. if (buf_get_u32(str9xpec_info->options, STR9XPEC_OPT_LVDSELBIT, 1))
  773. command_print(cmd_ctx, "LVD Reset Selection: VDD or VDDQ Inputs");
  774. else
  775. command_print(cmd_ctx, "LVD Reset Selection: VDD Input Only");
  776. return ERROR_OK;
  777. }
  778. int str9xpec_write_options(struct flash_bank_s *bank)
  779. {
  780. scan_field_t field;
  781. u8 status;
  782. jtag_tap_t *tap;
  783. str9xpec_flash_controller_t *str9xpec_info = NULL;
  784. str9xpec_info = bank->driver_priv;
  785. tap = str9xpec_info->tap;
  786. /* erase config options first */
  787. status = str9xpec_erase_area( bank, 0xFE, 0xFE );
  788. if ((status & ISC_STATUS_ERROR) != STR9XPEC_ISC_SUCCESS)
  789. return status;
  790. if (!str9xpec_info->isc_enable) {
  791. str9xpec_isc_enable( bank );
  792. }
  793. if (!str9xpec_info->isc_enable) {
  794. return ISC_STATUS_ERROR;
  795. }
  796. /* according to data 64th bit has to be set */
  797. buf_set_u32(str9xpec_info->options, 63, 1, 1);
  798. /* set option byte address */
  799. str9xpec_set_address(bank, 0x50);
  800. /* execute ISC_PROGRAM command */
  801. str9xpec_set_instr(tap, ISC_PROGRAM, TAP_IRPAUSE);
  802. field.tap = tap;
  803. field.num_bits = 64;
  804. field.out_value = str9xpec_info->options;
  805. field.out_mask = NULL;
  806. field.in_value = NULL;
  807. field.in_check_value = NULL;
  808. field.in_check_mask = NULL;
  809. field.in_handler = NULL;
  810. field.in_handler_priv = NULL;
  811. jtag_add_dr_scan(1, &field, TAP_IDLE);
  812. /* small delay before polling */
  813. jtag_add_sleep(50);
  814. str9xpec_set_instr(tap, ISC_NOOP, TAP_IRPAUSE);
  815. do {
  816. field.tap = tap;
  817. field.num_bits = 8;
  818. field.out_value = NULL;
  819. field.out_mask = NULL;
  820. field.in_value = &status;
  821. field.in_check_value = NULL;
  822. field.in_check_mask = NULL;
  823. field.in_handler = NULL;
  824. field.in_handler_priv = NULL;
  825. jtag_add_dr_scan(1, &field, -1);
  826. jtag_execute_queue();
  827. } while(!(status & ISC_STATUS_BUSY));
  828. str9xpec_isc_disable(bank);
  829. return status;
  830. }
  831. int str9xpec_handle_flash_options_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
  832. {
  833. flash_bank_t *bank;
  834. u8 status;
  835. if (argc < 1)
  836. {
  837. command_print(cmd_ctx, "str9xpec options_write <bank>");
  838. return ERROR_OK;
  839. }
  840. bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
  841. if (!bank)
  842. {
  843. command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
  844. return ERROR_OK;
  845. }
  846. status = str9xpec_write_options(bank);
  847. if ((status & ISC_STATUS_ERROR) != STR9XPEC_ISC_SUCCESS)
  848. return ERROR_FLASH_OPERATION_FAILED;
  849. return ERROR_OK;
  850. }
  851. int str9xpec_handle_flash_options_cmap_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
  852. {
  853. flash_bank_t *bank;
  854. str9xpec_flash_controller_t *str9xpec_info = NULL;
  855. if (argc < 2)
  856. {
  857. command_print(cmd_ctx, "str9xpec options_cmap <bank> <bank0|bank1>");
  858. return ERROR_OK;
  859. }
  860. bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
  861. if (!bank)
  862. {
  863. command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
  864. return ERROR_OK;
  865. }
  866. str9xpec_info = bank->driver_priv;
  867. if (strcmp(args[1], "bank1") == 0)
  868. {
  869. buf_set_u32(str9xpec_info->options, STR9XPEC_OPT_CSMAPBIT, 1, 1);
  870. }
  871. else
  872. {
  873. buf_set_u32(str9xpec_info->options, STR9XPEC_OPT_CSMAPBIT, 1, 0);
  874. }
  875. return ERROR_OK;
  876. }
  877. int str9xpec_handle_flash_options_lvdthd_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
  878. {
  879. flash_bank_t *bank;
  880. str9xpec_flash_controller_t *str9xpec_info = NULL;
  881. if (argc < 2)
  882. {
  883. command_print(cmd_ctx, "str9xpec options_lvdthd <bank> <2.4v|2.7v>");
  884. return ERROR_OK;
  885. }
  886. bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
  887. if (!bank)
  888. {
  889. command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
  890. return ERROR_OK;
  891. }
  892. str9xpec_info = bank->driver_priv;
  893. if (strcmp(args[1], "2.7v") == 0)
  894. {
  895. buf_set_u32(str9xpec_info->options, STR9XPEC_OPT_LVDTHRESBIT, 1, 1);
  896. }
  897. else
  898. {
  899. buf_set_u32(str9xpec_info->options, STR9XPEC_OPT_LVDTHRESBIT, 1, 0);
  900. }
  901. return ERROR_OK;
  902. }
  903. int str9xpec_handle_flash_options_lvdsel_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
  904. {
  905. flash_bank_t *bank;
  906. str9xpec_flash_controller_t *str9xpec_info = NULL;
  907. if (argc < 2)
  908. {
  909. command_print(cmd_ctx, "str9xpec options_lvdsel <bank> <vdd|vdd_vddq>");
  910. return ERROR_OK;
  911. }
  912. bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
  913. if (!bank)
  914. {
  915. command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
  916. return ERROR_OK;
  917. }
  918. str9xpec_info = bank->driver_priv;
  919. if (strcmp(args[1], "vdd_vddq") == 0)
  920. {
  921. buf_set_u32(str9xpec_info->options, STR9XPEC_OPT_LVDSELBIT, 1, 1);
  922. }
  923. else
  924. {
  925. buf_set_u32(str9xpec_info->options, STR9XPEC_OPT_LVDSELBIT, 1, 0);
  926. }
  927. return ERROR_OK;
  928. }
  929. int str9xpec_handle_flash_options_lvdwarn_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
  930. {
  931. flash_bank_t *bank;
  932. str9xpec_flash_controller_t *str9xpec_info = NULL;
  933. if (argc < 2)
  934. {
  935. command_print(cmd_ctx, "str9xpec options_lvdwarn <bank> <vdd|vdd_vddq>");
  936. return ERROR_OK;
  937. }
  938. bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
  939. if (!bank)
  940. {
  941. command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
  942. return ERROR_OK;
  943. }
  944. str9xpec_info = bank->driver_priv;
  945. if (strcmp(args[1], "vdd_vddq") == 0)
  946. {
  947. buf_set_u32(str9xpec_info->options, STR9XPEC_OPT_LVDWARNBIT, 1, 1);
  948. }
  949. else
  950. {
  951. buf_set_u32(str9xpec_info->options, STR9XPEC_OPT_LVDWARNBIT, 1, 0);
  952. }
  953. return ERROR_OK;
  954. }
  955. int str9xpec_handle_flash_lock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
  956. {
  957. u8 status;
  958. flash_bank_t *bank;
  959. if (argc < 1)
  960. {
  961. command_print(cmd_ctx, "str9xpec lock <bank>");
  962. return ERROR_OK;
  963. }
  964. bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
  965. if (!bank)
  966. {
  967. command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
  968. return ERROR_OK;
  969. }
  970. status = str9xpec_lock_device(bank);
  971. if ((status & ISC_STATUS_ERROR) != STR9XPEC_ISC_SUCCESS)
  972. return ERROR_FLASH_OPERATION_FAILED;
  973. return ERROR_OK;
  974. }
  975. int str9xpec_handle_flash_unlock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
  976. {
  977. u8 status;
  978. flash_bank_t *bank;
  979. if (argc < 1)
  980. {
  981. command_print(cmd_ctx, "str9xpec unlock <bank>");
  982. return ERROR_OK;
  983. }
  984. bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
  985. if (!bank)
  986. {
  987. command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
  988. return ERROR_OK;
  989. }
  990. status = str9xpec_unlock_device(bank);
  991. if ((status & ISC_STATUS_ERROR) != STR9XPEC_ISC_SUCCESS)
  992. return ERROR_FLASH_OPERATION_FAILED;
  993. return ERROR_OK;
  994. }
  995. int str9xpec_handle_flash_enable_turbo_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
  996. {
  997. int retval;
  998. flash_bank_t *bank;
  999. jtag_tap_t *tap0;
  1000. jtag_tap_t *tap1;
  1001. jtag_tap_t *tap2;
  1002. str9xpec_flash_controller_t *str9xpec_info = NULL;
  1003. if (argc < 1)
  1004. {
  1005. command_print(cmd_ctx, "str9xpec enable_turbo <bank>");
  1006. return ERROR_OK;
  1007. }
  1008. bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
  1009. if (!bank)
  1010. {
  1011. command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
  1012. return ERROR_OK;
  1013. }
  1014. str9xpec_info = bank->driver_priv;
  1015. tap0 = str9xpec_info->tap;
  1016. /* remove arm core from chain - enter turbo mode */
  1017. tap1 = tap0->next_tap;
  1018. if (tap1 == NULL)
  1019. {
  1020. /* things are *WRONG* */
  1021. command_print(cmd_ctx,"**STR9FLASH** (tap1) invalid chain?");
  1022. return ERROR_OK;
  1023. }
  1024. tap2 = tap1->next_tap;
  1025. if (tap2 == NULL)
  1026. {
  1027. /* things are *WRONG* */
  1028. command_print(cmd_ctx,"**STR9FLASH** (tap2) invalid chain?");
  1029. return ERROR_OK;
  1030. }
  1031. /* enable turbo mode - TURBO-PROG-ENABLE */
  1032. str9xpec_set_instr(tap2, 0xD, TAP_IDLE);
  1033. if ((retval = jtag_execute_queue()) != ERROR_OK)
  1034. return retval;
  1035. /* modify scan chain - str9 core has been removed */
  1036. tap1->enabled = 0;
  1037. return ERROR_OK;
  1038. }
  1039. int str9xpec_handle_flash_disable_turbo_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
  1040. {
  1041. flash_bank_t *bank;
  1042. jtag_tap_t *tap;
  1043. str9xpec_flash_controller_t *str9xpec_info = NULL;
  1044. if (argc < 1)
  1045. {
  1046. command_print(cmd_ctx, "str9xpec disable_turbo <bank>");
  1047. return ERROR_OK;
  1048. }
  1049. bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
  1050. if (!bank)
  1051. {
  1052. command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
  1053. return ERROR_OK;
  1054. }
  1055. str9xpec_info = bank->driver_priv;
  1056. tap = str9xpec_info->tap;
  1057. if (tap == NULL)
  1058. return ERROR_FAIL;
  1059. /* exit turbo mode via RESET */
  1060. str9xpec_set_instr(tap, ISC_NOOP, TAP_RESET);
  1061. jtag_execute_queue();
  1062. /* restore previous scan chain */
  1063. if (tap->next_tap) {
  1064. tap->next_tap->enabled = 1;
  1065. }
  1066. return ERROR_OK;
  1067. }