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  1. \input texinfo @c -*-texinfo-*-
  2. @c %**start of header
  3. @setfilename
  4. @settitle OpenOCD User's Guide
  5. @dircategory Development
  6. @direntry
  7. * OpenOCD: (openocd). OpenOCD User's Guide
  8. @end direntry
  9. @paragraphindent 0
  10. @c %**end of header
  11. @include version.texi
  12. @copying
  13. This User's Guide documents
  14. release @value{VERSION},
  15. dated @value{UPDATED},
  16. of the Open On-Chip Debugger (OpenOCD).
  17. @itemize @bullet
  18. @item Copyright @copyright{} 2008 The OpenOCD Project
  19. @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{}
  20. @item Copyright @copyright{} 2008 Oyvind Harboe @email{}
  21. @item Copyright @copyright{} 2008 Duane Ellis @email{}
  22. @item Copyright @copyright{} 2009 David Brownell
  23. @end itemize
  24. @quotation
  25. Permission is granted to copy, distribute and/or modify this document
  26. under the terms of the GNU Free Documentation License, Version 1.2 or
  27. any later version published by the Free Software Foundation; with no
  28. Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
  29. Texts. A copy of the license is included in the section entitled ``GNU
  30. Free Documentation License''.
  31. @end quotation
  32. @end copying
  33. @titlepage
  34. @titlefont{@emph{Open On-Chip Debugger:}}
  35. @sp 1
  36. @title OpenOCD User's Guide
  37. @subtitle for release @value{VERSION}
  38. @subtitle @value{UPDATED}
  39. @page
  40. @vskip 0pt plus 1filll
  41. @insertcopying
  42. @end titlepage
  43. @summarycontents
  44. @contents
  45. @ifnottex
  46. @node Top
  47. @top OpenOCD User's Guide
  48. @insertcopying
  49. @end ifnottex
  50. @menu
  51. * About:: About OpenOCD
  52. * Developers:: OpenOCD Developers
  53. * JTAG Hardware Dongles:: JTAG Hardware Dongles
  54. * About JIM-Tcl:: About JIM-Tcl
  55. * Running:: Running OpenOCD
  56. * OpenOCD Project Setup:: OpenOCD Project Setup
  57. * Config File Guidelines:: Config File Guidelines
  58. * Daemon Configuration:: Daemon Configuration
  59. * Interface - Dongle Configuration:: Interface - Dongle Configuration
  60. * Reset Configuration:: Reset Configuration
  61. * TAP Declaration:: TAP Declaration
  62. * CPU Configuration:: CPU Configuration
  63. * Flash Commands:: Flash Commands
  64. * NAND Flash Commands:: NAND Flash Commands
  65. * PLD/FPGA Commands:: PLD/FPGA Commands
  66. * General Commands:: General Commands
  67. * Architecture and Core Commands:: Architecture and Core Commands
  68. * JTAG Commands:: JTAG Commands
  69. * Boundary Scan Commands:: Boundary Scan Commands
  70. * TFTP:: TFTP
  71. * GDB and OpenOCD:: Using GDB and OpenOCD
  72. * Tcl Scripting API:: Tcl Scripting API
  73. * Upgrading:: Deprecated/Removed Commands
  74. * FAQ:: Frequently Asked Questions
  75. * Tcl Crash Course:: Tcl Crash Course
  76. * License:: GNU Free Documentation License
  77. @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
  78. @comment case issue with ``Index.html'' and ``index.html''
  79. @comment Occurs when creating ``--html --no-split'' output
  80. @comment This fix is based on:
  81. * OpenOCD Concept Index:: Concept Index
  82. * Command and Driver Index:: Command and Driver Index
  83. @end menu
  84. @node About
  85. @unnumbered About
  86. @cindex about
  87. OpenOCD was created by Dominic Rath as part of a diploma thesis written at the
  88. University of Applied Sciences Augsburg (@uref{}).
  89. Since that time, the project has grown into an active open-source project,
  90. supported by a diverse community of software and hardware developers from
  91. around the world.
  92. @section What is OpenOCD?
  93. @cindex TAP
  94. @cindex JTAG
  95. The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
  96. in-system programming and boundary-scan testing for embedded target
  97. devices.
  98. @b{JTAG:} OpenOCD uses a ``hardware interface dongle'' to communicate
  99. with the JTAG (IEEE 1149.1) compliant TAPs on your target board.
  100. A @dfn{TAP} is a ``Test Access Port'', a module which processes
  101. special instructions and data. TAPs are daisy-chained within and
  102. between chips and boards.
  103. @b{Dongles:} OpenOCD currently supports many types of hardware dongles: USB
  104. based, parallel port based, and other standalone boxes that run
  105. OpenOCD internally. @xref{JTAG Hardware Dongles}.
  106. @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
  107. ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x) and
  108. Cortex-M3 (Stellaris LM3 and ST STM32) based cores to be
  109. debugged via the GDB protocol.
  110. @b{Flash Programing:} Flash writing is supported for external CFI
  111. compatible NOR flashes (Intel and AMD/Spansion command set) and several
  112. internal flashes (LPC1700, LPC2000, AT91SAM7, AT91SAM3U, STR7x, STR9x, LM3, and
  113. STM32x). Preliminary support for various NAND flash controllers
  114. (LPC3180, Orion, S3C24xx, more) controller is included.
  115. @section OpenOCD Web Site
  116. The OpenOCD web site provides the latest public news from the community:
  117. @uref{}
  118. @section Latest User's Guide:
  119. The user's guide you are now reading may not be the latest one
  120. available. A version for more recent code may be available.
  121. Its HTML form is published irregularly at:
  122. @uref{}
  123. PDF form is likewise published at:
  124. @uref{}
  125. @section OpenOCD User's Forum
  126. There is an OpenOCD forum (phpBB) hosted by SparkFun:
  127. @uref{}
  128. @node Developers
  129. @chapter OpenOCD Developer Resources
  130. @cindex developers
  131. If you are interested in improving the state of OpenOCD's debugging and
  132. testing support, new contributions will be welcome. Motivated developers
  133. can produce new target, flash or interface drivers, improve the
  134. documentation, as well as more conventional bug fixes and enhancements.
  135. The resources in this chapter are available for developers wishing to explore
  136. or expand the OpenOCD source code.
  137. @section OpenOCD GIT Repository
  138. During the 0.3.x release cycle, OpenOCD switched from Subversion to
  139. a GIT repository hosted at SourceForge. The repository URL is:
  140. @uref{git://}
  141. You may prefer to use a mirror and the HTTP protocol:
  142. @uref{}
  143. With standard GIT tools, use @command{git clone} to initialize
  144. a local repository, and @command{git pull} to update it.
  145. There are also gitweb pages letting you browse the repository
  146. with a web browser, or download arbitrary snapshots without
  147. needing a GIT client:
  148. @uref{}
  149. @uref{}
  150. The @file{README} file contains the instructions for building the project
  151. from the repository or a snapshot.
  152. Developers that want to contribute patches to the OpenOCD system are
  153. @b{strongly} encouraged to work against mainline.
  154. Patches created against older versions may require additional
  155. work from their submitter in order to be updated for newer releases.
  156. @section Doxygen Developer Manual
  157. During the 0.2.x release cycle, the OpenOCD project began
  158. providing a Doxygen reference manual. This document contains more
  159. technical information about the software internals, development
  160. processes, and similar documentation:
  161. @uref{}
  162. This document is a work-in-progress, but contributions would be welcome
  163. to fill in the gaps. All of the source files are provided in-tree,
  164. listed in the Doxyfile configuration in the top of the source tree.
  165. @section OpenOCD Developer Mailing List
  166. The OpenOCD Developer Mailing List provides the primary means of
  167. communication between developers:
  168. @uref{}
  169. Discuss and submit patches to this list.
  170. The @file{PATCHES} file contains basic information about how
  171. to prepare patches.
  172. @node JTAG Hardware Dongles
  173. @chapter JTAG Hardware Dongles
  174. @cindex dongles
  175. @cindex FTDI
  176. @cindex wiggler
  177. @cindex zy1000
  178. @cindex printer port
  179. @cindex USB Adapter
  180. @cindex RTCK
  181. Defined: @b{dongle}: A small device that plugins into a computer and serves as
  182. an adapter .... [snip]
  183. In the OpenOCD case, this generally refers to @b{a small adapater} one
  184. attaches to your computer via USB or the Parallel Printer Port. The
  185. execption being the Zylin ZY1000 which is a small box you attach via
  186. an ethernet cable. The Zylin ZY1000 has the advantage that it does not
  187. require any drivers to be installed on the developer PC. It also has
  188. a built in web interface. It supports RTCK/RCLK or adaptive clocking
  189. and has a built in relay to power cycle targets remotely.
  190. @section Choosing a Dongle
  191. There are several things you should keep in mind when choosing a dongle.
  192. @enumerate
  193. @item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
  194. Does your dongle support it? You might need a level converter.
  195. @item @b{Pinout} What pinout does your target board use?
  196. Does your dongle support it? You may be able to use jumper
  197. wires, or an "octopus" connector, to convert pinouts.
  198. @item @b{Connection} Does your computer have the USB, printer, or
  199. Ethernet port needed?
  200. @item @b{RTCK} Do you require RTCK? Also known as ``adaptive clocking''
  201. @end enumerate
  202. @section Stand alone Systems
  203. @b{ZY1000} See: @url{} Technically, not a
  204. dongle, but a standalone box. The ZY1000 has the advantage that it does
  205. not require any drivers installed on the developer PC. It also has
  206. a built in web interface. It supports RTCK/RCLK or adaptive clocking
  207. and has a built in relay to power cycle targets remotely.
  208. @section USB FT2232 Based
  209. There are many USB JTAG dongles on the market, many of them are based
  210. on a chip from ``Future Technology Devices International'' (FTDI)
  211. known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
  212. See: @url{} for more information.
  213. In summer 2009, USB high speed (480 Mbps) versions of these FTDI
  214. chips are starting to become available in JTAG adapters.
  215. @itemize @bullet
  216. @item @b{usbjtag}
  217. @* Link @url{}
  218. @item @b{jtagkey}
  219. @* See: @url{}
  220. @item @b{jtagkey2}
  221. @* See: @url{}
  222. @item @b{oocdlink}
  223. @* See: @url{} By Joern Kaipf
  224. @item @b{signalyzer}
  225. @* See: @url{}
  226. @item @b{evb_lm3s811}
  227. @* See: @url{} - The Stellaris LM3S811 eval board has an FTD2232C chip built in.
  228. @item @b{luminary_icdi}
  229. @* See: @url{} - Luminary In-Circuit Debug Interface (ICDI) Board, included in the Stellaris LM3S9B90 and LM3S9B92 Evaluation Kits.
  230. @item @b{olimex-jtag}
  231. @* See: @url{}
  232. @item @b{flyswatter}
  233. @* See: @url{}
  234. @item @b{turtelizer2}
  235. @* See:
  236. @uref{, Turtelizer 2}, or
  237. @url{}
  238. @item @b{comstick}
  239. @* Link: @url{}
  240. @item @b{stm32stick}
  241. @* Link @url{}
  242. @item @b{axm0432_jtag}
  243. @* Axiom AXM-0432 Link @url{}
  244. @item @b{cortino}
  245. @* Link @url{}
  246. @end itemize
  247. @section USB JLINK based
  248. There are several OEM versions of the Segger @b{JLINK} adapter. It is
  249. an example of a micro controller based JTAG adapter, it uses an
  250. AT91SAM764 internally.
  251. @itemize @bullet
  252. @item @b{ATMEL SAMICE} Only works with ATMEL chips!
  253. @* Link: @url{}
  254. @item @b{SEGGER JLINK}
  255. @* Link: @url{}
  256. @item @b{IAR J-Link}
  257. @* Link: @url{}
  258. @end itemize
  259. @section USB RLINK based
  260. Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer, permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for SWD and not JTAG, thus not supported.
  261. @itemize @bullet
  262. @item @b{Raisonance RLink}
  263. @* Link: @url{}
  264. @item @b{STM32 Primer}
  265. @* Link: @url{}
  266. @item @b{STM32 Primer2}
  267. @* Link: @url{}
  268. @end itemize
  269. @section USB Other
  270. @itemize @bullet
  271. @item @b{USBprog}
  272. @* Link: @url{} - which uses an Atmel MEGA32 and a UBN9604
  273. @item @b{USB - Presto}
  274. @* Link: @url{}
  275. @item @b{Versaloon-Link}
  276. @* Link: @url{}
  277. @item @b{ARM-JTAG-EW}
  278. @* Link: @url{}
  279. @end itemize
  280. @section IBM PC Parallel Printer Port Based
  281. The two well known ``JTAG Parallel Ports'' cables are the Xilnx DLC5
  282. and the MacGraigor Wiggler. There are many clones and variations of
  283. these on the market.
  284. Note that parallel ports are becoming much less common, so if you
  285. have the choice you should probably avoid these adapters in favor
  286. of USB-based ones.
  287. @itemize @bullet
  288. @item @b{Wiggler} - There are many clones of this.
  289. @* Link: @url{}
  290. @item @b{DLC5} - From XILINX - There are many clones of this
  291. @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
  292. produced, PDF schematics are easily found and it is easy to make.
  293. @item @b{Amontec - JTAG Accelerator}
  294. @* Link: @url{}
  295. @item @b{GW16402}
  296. @* Link: @url{}
  297. @item @b{Wiggler2}
  298. @*@uref{,
  299. Improved parallel-port wiggler-style JTAG adapter}
  300. @item @b{Wiggler_ntrst_inverted}
  301. @* Yet another variation - See the source code, src/jtag/parport.c
  302. @item @b{old_amt_wiggler}
  303. @* Unknown - probably not on the market today
  304. @item @b{arm-jtag}
  305. @* Link: Most likely @url{} [another wiggler clone]
  306. @item @b{chameleon}
  307. @* Link: @url{}
  308. @item @b{Triton}
  309. @* Unknown.
  310. @item @b{Lattice}
  311. @* ispDownload from Lattice Semiconductor
  312. @url{}
  313. @item @b{flashlink}
  314. @* From ST Microsystems;
  315. @uref{,
  316. FlashLINK JTAG programing cable for PSD and uPSD}
  317. @end itemize
  318. @section Other...
  319. @itemize @bullet
  320. @item @b{ep93xx}
  321. @* An EP93xx based Linux machine using the GPIO pins directly.
  322. @item @b{at91rm9200}
  323. @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
  324. @end itemize
  325. @node About JIM-Tcl
  326. @chapter About JIM-Tcl
  327. @cindex JIM Tcl
  328. @cindex tcl
  329. OpenOCD includes a small ``Tcl Interpreter'' known as JIM-Tcl.
  330. This programming language provides a simple and extensible
  331. command interpreter.
  332. All commands presented in this Guide are extensions to JIM-Tcl.
  333. You can use them as simple commands, without needing to learn
  334. much of anything about Tcl.
  335. Alternatively, can write Tcl programs with them.
  336. You can learn more about JIM at its website, @url{}.
  337. @itemize @bullet
  338. @item @b{JIM vs. Tcl}
  339. @* JIM-TCL is a stripped down version of the well known Tcl language,
  340. which can be found here: @url{}. JIM-Tcl has far
  341. fewer features. JIM-Tcl is a single .C file and a single .H file and
  342. implements the basic Tcl command set. In contrast: Tcl 8.6 is a
  343. 4.2 MB .zip file containing 1540 files.
  344. @item @b{Missing Features}
  345. @* Our practice has been: Add/clone the real Tcl feature if/when
  346. needed. We welcome JIM Tcl improvements, not bloat.
  347. @item @b{Scripts}
  348. @* OpenOCD configuration scripts are JIM Tcl Scripts. OpenOCD's
  349. command interpreter today is a mixture of (newer)
  350. JIM-Tcl commands, and (older) the orginal command interpreter.
  351. @item @b{Commands}
  352. @* At the OpenOCD telnet command line (or via the GDB mon command) one
  353. can type a Tcl for() loop, set variables, etc.
  354. Some of the commands documented in this guide are implemented
  355. as Tcl scripts, from a @file{startup.tcl} file internal to the server.
  356. @item @b{Historical Note}
  357. @* JIM-Tcl was introduced to OpenOCD in spring 2008.
  358. @item @b{Need a crash course in Tcl?}
  359. @*@xref{Tcl Crash Course}.
  360. @end itemize
  361. @node Running
  362. @chapter Running
  363. @cindex command line options
  364. @cindex logfile
  365. @cindex directory search
  366. The @option{--help} option shows:
  367. @verbatim
  368. bash$ openocd --help
  369. --help | -h display this help
  370. --version | -v display OpenOCD version
  371. --file | -f use configuration file <name>
  372. --search | -s dir to search for config files and scripts
  373. --debug | -d set debug level <0-3>
  374. --log_output | -l redirect log output to file <name>
  375. --command | -c run <command>
  376. --pipe | -p use pipes when talking to gdb
  377. @end verbatim
  378. By default OpenOCD reads the file configuration file @file{openocd.cfg}
  379. in the current directory. To specify a different (or multiple)
  380. configuration file, you can use the ``-f'' option. For example:
  381. @example
  382. openocd -f config1.cfg -f config2.cfg -f config3.cfg
  383. @end example
  384. OpenOCD starts by processing the configuration commands provided
  385. on the command line or in @file{openocd.cfg}.
  386. @xref{Configuration Stage}.
  387. At the end of the configuration stage it verifies the JTAG scan
  388. chain defined using those commands; your configuration should
  389. ensure that this always succeeds.
  390. Normally, OpenOCD then starts running as a daemon.
  391. Alternatively, commands may be used to terminate the configuration
  392. stage early, perform work (such as updating some flash memory),
  393. and then shut down without acting as a daemon.
  394. Once OpenOCD starts running as a daemon, it waits for connections from
  395. clients (Telnet, GDB, Other) and processes the commands issued through
  396. those channels.
  397. If you are having problems, you can enable internal debug messages via
  398. the ``-d'' option.
  399. Also it is possible to interleave JIM-Tcl commands w/config scripts using the
  400. @option{-c} command line switch.
  401. To enable debug output (when reporting problems or working on OpenOCD
  402. itself), use the @option{-d} command line switch. This sets the
  403. @option{debug_level} to "3", outputting the most information,
  404. including debug messages. The default setting is "2", outputting only
  405. informational messages, warnings and errors. You can also change this
  406. setting from within a telnet or gdb session using @command{debug_level
  407. <n>} (@pxref{debug_level}).
  408. You can redirect all output from the daemon to a file using the
  409. @option{-l <logfile>} switch.
  410. Search paths for config/script files can be added to OpenOCD by using
  411. the @option{-s <search>} switch. The current directory and the OpenOCD
  412. target library is in the search path by default.
  413. For details on the @option{-p} option. @xref{Connecting to GDB}.
  414. Note! OpenOCD will launch the GDB & telnet server even if it can not
  415. establish a connection with the target. In general, it is possible for
  416. the JTAG controller to be unresponsive until the target is set up
  417. correctly via e.g. GDB monitor commands in a GDB init script.
  418. @node OpenOCD Project Setup
  419. @chapter OpenOCD Project Setup
  420. To use OpenOCD with your development projects, you need to do more than
  421. just connecting the JTAG adapter hardware (dongle) to your development board
  422. and then starting the OpenOCD server.
  423. You also need to configure that server so that it knows
  424. about that adapter and board, and helps your work.
  425. @section Hooking up the JTAG Adapter
  426. Today's most common case is a dongle with a JTAG cable on one side
  427. (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
  428. and a USB cable on the other.
  429. Instead of USB, some cables use Ethernet;
  430. older ones may use a PC parallel port, or even a serial port.
  431. @enumerate
  432. @item @emph{Start with power to your target board turned off},
  433. and nothing connected to your JTAG adapter.
  434. If you're particularly paranoid, unplug power to the board.
  435. It's important to have the ground signal properly set up,
  436. unless you are using a JTAG adapter which provides
  437. galvanic isolation between the target board and the
  438. debugging host.
  439. @item @emph{Be sure it's the right kind of JTAG connector.}
  440. If your dongle has a 20-pin ARM connector, you need some kind
  441. of adapter (or octopus, see below) to hook it up to
  442. boards using 14-pin or 10-pin connectors ... or to 20-pin
  443. connectors which don't use ARM's pinout.
  444. In the same vein, make sure the voltage levels are compatible.
  445. Not all JTAG adapters have the level shifters needed to work
  446. with 1.2 Volt boards.
  447. @item @emph{Be certain the cable is properly oriented} or you might
  448. damage your board. In most cases there are only two possible
  449. ways to connect the cable.
  450. Connect the JTAG cable from your adapter to the board.
  451. Be sure it's firmly connected.
  452. In the best case, the connector is keyed to physically
  453. prevent you from inserting it wrong.
  454. This is most often done using a slot on the board's male connector
  455. housing, which must match a key on the JTAG cable's female connector.
  456. If there's no housing, then you must look carefully and
  457. make sure pin 1 on the cable hooks up to pin 1 on the board.
  458. Ribbon cables are frequently all grey except for a wire on one
  459. edge, which is red. The red wire is pin 1.
  460. Sometimes dongles provide cables where one end is an ``octopus'' of
  461. color coded single-wire connectors, instead of a connector block.
  462. These are great when converting from one JTAG pinout to another,
  463. but are tedious to set up.
  464. Use these with connector pinout diagrams to help you match up the
  465. adapter signals to the right board pins.
  466. @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
  467. A USB, parallel, or serial port connector will go to the host which
  468. you are using to run OpenOCD.
  469. For Ethernet, consult the documentation and your network administrator.
  470. For USB based JTAG adapters you have an easy sanity check at this point:
  471. does the host operating system see the JTAG adapter?
  472. @item @emph{Connect the adapter's power supply, if needed.}
  473. This step is primarily for non-USB adapters,
  474. but sometimes USB adapters need extra power.
  475. @item @emph{Power up the target board.}
  476. Unless you just let the magic smoke escape,
  477. you're now ready to set up the OpenOCD server
  478. so you can use JTAG to work with that board.
  479. @end enumerate
  480. Talk with the OpenOCD server using
  481. telnet (@code{telnet localhost 4444} on many systems) or GDB.
  482. @xref{GDB and OpenOCD}.
  483. @section Project Directory
  484. There are many ways you can configure OpenOCD and start it up.
  485. A simple way to organize them all involves keeping a
  486. single directory for your work with a given board.
  487. When you start OpenOCD from that directory,
  488. it searches there first for configuration files, scripts,
  489. and for code you upload to the target board.
  490. It is also the natural place to write files,
  491. such as log files and data you download from the board.
  492. @section Configuration Basics
  493. There are two basic ways of configuring OpenOCD, and
  494. a variety of ways you can mix them.
  495. Think of the difference as just being how you start the server:
  496. @itemize
  497. @item Many @option{-f file} or @option{-c command} options on the command line
  498. @item No options, but a @dfn{user config file}
  499. in the current directory named @file{openocd.cfg}
  500. @end itemize
  501. Here is an example @file{openocd.cfg} file for a setup
  502. using a Signalyzer FT2232-based JTAG adapter to talk to
  503. a board with an Atmel AT91SAM7X256 microcontroller:
  504. @example
  505. source [find interface/signalyzer.cfg]
  506. # GDB can also flash my flash!
  507. gdb_memory_map enable
  508. gdb_flash_program enable
  509. source [find target/sam7x256.cfg]
  510. @end example
  511. Here is the command line equivalent of that configuration:
  512. @example
  513. openocd -f interface/signalyzer.cfg \
  514. -c "gdb_memory_map enable" \
  515. -c "gdb_flash_program enable" \
  516. -f target/sam7x256.cfg
  517. @end example
  518. You could wrap such long command lines in shell scripts,
  519. each supporting a different development task.
  520. One might re-flash the board with a specific firmware version.
  521. Another might set up a particular debugging or run-time environment.
  522. @quotation Important
  523. At this writing (October 2009) the command line method has
  524. problems with how it treats variables.
  525. For example, after @option{-c "set VAR value"}, or doing the
  526. same in a script, the variable @var{VAR} will have no value
  527. that can be tested in a later script.
  528. @end quotation
  529. Here we will focus on the simpler solution: one user config
  530. file, including basic configuration plus any TCL procedures
  531. to simplify your work.
  532. @section User Config Files
  533. @cindex config file, user
  534. @cindex user config file
  535. @cindex config file, overview
  536. A user configuration file ties together all the parts of a project
  537. in one place.
  538. One of the following will match your situation best:
  539. @itemize
  540. @item Ideally almost everything comes from configuration files
  541. provided by someone else.
  542. For example, OpenOCD distributes a @file{scripts} directory
  543. (probably in @file{/usr/share/openocd/scripts} on Linux).
  544. Board and tool vendors can provide these too, as can individual
  545. user sites; the @option{-s} command line option lets you say
  546. where to find these files. (@xref{Running}.)
  547. The AT91SAM7X256 example above works this way.
  548. Three main types of non-user configuration file each have their
  549. own subdirectory in the @file{scripts} directory:
  550. @enumerate
  551. @item @b{interface} -- one for each kind of JTAG adapter/dongle
  552. @item @b{board} -- one for each different board
  553. @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
  554. @end enumerate
  555. Best case: include just two files, and they handle everything else.
  556. The first is an interface config file.
  557. The second is board-specific, and it sets up the JTAG TAPs and
  558. their GDB targets (by deferring to some @file{target.cfg} file),
  559. declares all flash memory, and leaves you nothing to do except
  560. meet your deadline:
  561. @example
  562. source [find interface/olimex-jtag-tiny.cfg]
  563. source [find board/csb337.cfg]
  564. @end example
  565. Boards with a single microcontroller often won't need more
  566. than the target config file, as in the AT91SAM7X256 example.
  567. That's because there is no external memory (flash, DDR RAM), and
  568. the board differences are encapsulated by application code.
  569. @item You can often reuse some standard config files but
  570. need to write a few new ones, probably a @file{board.cfg} file.
  571. You will be using commands described later in this User's Guide,
  572. and working with the guidelines in the next chapter.
  573. For example, there may be configuration files for your JTAG adapter
  574. and target chip, but you need a new board-specific config file
  575. giving access to your particular flash chips.
  576. Or you might need to write another target chip configuration file
  577. for a new chip built around the Cortex M3 core.
  578. @quotation Note
  579. When you write new configuration files, please submit
  580. them for inclusion in the next OpenOCD release.
  581. For example, a @file{board/newboard.cfg} file will help the
  582. next users of that board, and a @file{target/newcpu.cfg}
  583. will help support users of any board using that chip.
  584. @end quotation
  585. @item
  586. You may may need to write some C code.
  587. It may be as simple as a supporting a new ft2232 or parport
  588. based dongle; a bit more involved, like a NAND or NOR flash
  589. controller driver; or a big piece of work like supporting
  590. a new chip architecture.
  591. @end itemize
  592. Reuse the existing config files when you can.
  593. Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
  594. You may find a board configuration that's a good example to follow.
  595. When you write config files, separate the reusable parts
  596. (things every user of that interface, chip, or board needs)
  597. from ones specific to your environment and debugging approach.
  598. @itemize
  599. @item
  600. For example, a @code{gdb-attach} event handler that invokes
  601. the @command{reset init} command will interfere with debugging
  602. early boot code, which performs some of the same actions
  603. that the @code{reset-init} event handler does.
  604. @item
  605. Likewise, the @command{arm9tdmi vector_catch} command (or
  606. @cindex vector_catch
  607. its siblings @command{xscale vector_catch}
  608. and @command{cortex_m3 vector_catch}) can be a timesaver
  609. during some debug sessions, but don't make everyone use that either.
  610. Keep those kinds of debugging aids in your user config file,
  611. along with messaging and tracing setup.
  612. (@xref{Software Debug Messages and Tracing}.)
  613. @item
  614. You might need to override some defaults.
  615. For example, you might need to move, shrink, or back up the target's
  616. work area if your application needs much SRAM.
  617. @item
  618. TCP/IP port configuration is another example of something which
  619. is environment-specific, and should only appear in
  620. a user config file. @xref{TCP/IP Ports}.
  621. @end itemize
  622. @section Project-Specific Utilities
  623. A few project-specific utility
  624. routines may well speed up your work.
  625. Write them, and keep them in your project's user config file.
  626. For example, if you are making a boot loader work on a
  627. board, it's nice to be able to debug the ``after it's
  628. loaded to RAM'' parts separately from the finicky early
  629. code which sets up the DDR RAM controller and clocks.
  630. A script like this one, or a more GDB-aware sibling,
  631. may help:
  632. @example
  633. proc ramboot @{ @} @{
  634. # Reset, running the target's "reset-init" scripts
  635. # to initialize clocks and the DDR RAM controller.
  636. # Leave the CPU halted.
  637. reset init
  638. # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
  639. load_image u-boot.bin 0x20000000
  640. # Start running.
  641. resume 0x20000000
  642. @}
  643. @end example
  644. Then once that code is working you will need to make it
  645. boot from NOR flash; a different utility would help.
  646. Alternatively, some developers write to flash using GDB.
  647. (You might use a similar script if you're working with a flash
  648. based microcontroller application instead of a boot loader.)
  649. @example
  650. proc newboot @{ @} @{
  651. # Reset, leaving the CPU halted. The "reset-init" event
  652. # proc gives faster access to the CPU and to NOR flash;
  653. # "reset halt" would be slower.
  654. reset init
  655. # Write standard version of U-Boot into the first two
  656. # sectors of NOR flash ... the standard version should
  657. # do the same lowlevel init as "reset-init".
  658. flash protect 0 0 1 off
  659. flash erase_sector 0 0 1
  660. flash write_bank 0 u-boot.bin 0x0
  661. flash protect 0 0 1 on
  662. # Reboot from scratch using that new boot loader.
  663. reset run
  664. @}
  665. @end example
  666. You may need more complicated utility procedures when booting
  667. from NAND.
  668. That often involves an extra bootloader stage,
  669. running from on-chip SRAM to perform DDR RAM setup so it can load
  670. the main bootloader code (which won't fit into that SRAM).
  671. Other helper scripts might be used to write production system images,
  672. involving considerably more than just a three stage bootloader.
  673. @section Target Software Changes
  674. Sometimes you may want to make some small changes to the software
  675. you're developing, to help make JTAG debugging work better.
  676. For example, in C or assembly language code you might
  677. use @code{#ifdef JTAG_DEBUG} (or its converse) around code
  678. handling issues like:
  679. @itemize @bullet
  680. @item @b{ARM Wait-For-Interrupt}...
  681. Many ARM chips synchronize the JTAG clock using the core clock.
  682. Low power states which stop that core clock thus prevent JTAG access.
  683. Idle loops in tasking environments often enter those low power states
  684. via the @code{WFI} instruction (or its coprocessor equivalent, before ARMv7).
  685. You may want to @emph{disable that instruction} in source code,
  686. or otherwise prevent using that state,
  687. to ensure you can get JTAG access at any time.
  688. For example, the OpenOCD @command{halt} command may not
  689. work for an idle processor otherwise.
  690. @item @b{Delay after reset}...
  691. Not all chips have good support for debugger access
  692. right after reset; many LPC2xxx chips have issues here.
  693. Similarly, applications that reconfigure pins used for
  694. JTAG access as they start will also block debugger access.
  695. To work with boards like this, @emph{enable a short delay loop}
  696. the first thing after reset, before "real" startup activities.
  697. For example, one second's delay is usually more than enough
  698. time for a JTAG debugger to attach, so that
  699. early code execution can be debugged
  700. or firmware can be replaced.
  701. @item @b{Debug Communications Channel (DCC)}...
  702. Some processors include mechanisms to send messages over JTAG.
  703. Many ARM cores support these, as do some cores from other vendors.
  704. (OpenOCD may be able to use this DCC internally, speeding up some
  705. operations like writing to memory.)
  706. Your application may want to deliver various debugging messages
  707. over JTAG, by @emph{linking with a small library of code}
  708. provided with OpenOCD and using the utilities there to send
  709. various kinds of message.
  710. @xref{Software Debug Messages and Tracing}.
  711. @end itemize
  712. @node Config File Guidelines
  713. @chapter Config File Guidelines
  714. This chapter is aimed at any user who needs to write a config file,
  715. including developers and integrators of OpenOCD and any user who
  716. needs to get a new board working smoothly.
  717. It provides guidelines for creating those files.
  718. You should find the following directories under @t{$(INSTALLDIR)/scripts},
  719. with files including the ones listed here.
  720. Use them as-is where you can; or as models for new files.
  721. @itemize @bullet
  722. @item @file{interface} ...
  723. think JTAG Dongle. Files that configure JTAG adapters go here.
  724. @example
  725. $ ls interface
  726. arm-jtag-ew.cfg hitex_str9-comstick.cfg oocdlink.cfg
  727. arm-usb-ocd.cfg icebear.cfg openocd-usb.cfg
  728. at91rm9200.cfg jlink.cfg parport.cfg
  729. axm0432.cfg jtagkey2.cfg parport_dlc5.cfg
  730. calao-usb-a9260-c01.cfg jtagkey.cfg rlink.cfg
  731. calao-usb-a9260-c02.cfg jtagkey-tiny.cfg sheevaplug.cfg
  732. calao-usb-a9260.cfg luminary.cfg signalyzer.cfg
  733. chameleon.cfg luminary-icdi.cfg stm32-stick.cfg
  734. cortino.cfg luminary-lm3s811.cfg turtelizer2.cfg
  735. dummy.cfg olimex-arm-usb-ocd.cfg usbprog.cfg
  736. flyswatter.cfg olimex-jtag-tiny.cfg vsllink.cfg
  737. $
  738. @end example
  739. @item @file{board} ...
  740. think Circuit Board, PWA, PCB, they go by many names. Board files
  741. contain initialization items that are specific to a board.
  742. They reuse target configuration files, since the same
  743. microprocessor chips are used on many boards,
  744. but support for external parts varies widely. For
  745. example, the SDRAM initialization sequence for the board, or the type
  746. of external flash and what address it uses. Any initialization
  747. sequence to enable that external flash or SDRAM should be found in the
  748. board file. Boards may also contain multiple targets: two CPUs; or
  749. a CPU and an FPGA.
  750. @example
  751. $ ls board
  752. arm_evaluator7t.cfg keil_mcb1700.cfg
  753. at91rm9200-dk.cfg keil_mcb2140.cfg
  754. at91sam9g20-ek.cfg linksys_nslu2.cfg
  755. atmel_at91sam7s-ek.cfg logicpd_imx27.cfg
  756. atmel_at91sam9260-ek.cfg mini2440.cfg
  757. atmel_sam3u_ek.cfg olimex_LPC2378STK.cfg
  758. crossbow_tech_imote2.cfg olimex_lpc_h2148.cfg
  759. csb337.cfg olimex_sam7_ex256.cfg
  760. csb732.cfg olimex_sam9_l9260.cfg
  761. digi_connectcore_wi-9c.cfg olimex_stm32_h103.cfg
  762. dm355evm.cfg omap2420_h4.cfg
  763. dm365evm.cfg osk5912.cfg
  764. dm6446evm.cfg pic-p32mx.cfg
  765. eir.cfg propox_mmnet1001.cfg
  766. ek-lm3s1968.cfg pxa255_sst.cfg
  767. ek-lm3s3748.cfg sheevaplug.cfg
  768. ek-lm3s811.cfg stm3210e_eval.cfg
  769. ek-lm3s9b9x.cfg stm32f10x_128k_eval.cfg
  770. hammer.cfg str910-eval.cfg
  771. hitex_lpc2929.cfg telo.cfg
  772. hitex_stm32-performancestick.cfg ti_beagleboard.cfg
  773. hitex_str9-comstick.cfg topas910.cfg
  774. iar_str912_sk.cfg topasa900.cfg
  775. imx27ads.cfg unknown_at91sam9260.cfg
  776. imx27lnst.cfg x300t.cfg
  777. imx31pdk.cfg zy1000.cfg
  778. $
  779. @end example
  780. @item @file{target} ...
  781. think chip. The ``target'' directory represents the JTAG TAPs
  782. on a chip
  783. which OpenOCD should control, not a board. Two common types of targets
  784. are ARM chips and FPGA or CPLD chips.
  785. When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
  786. the target config file defines all of them.
  787. @example
  788. $ ls target
  789. aduc702x.cfg imx27.cfg pxa255.cfg
  790. ar71xx.cfg imx31.cfg pxa270.cfg
  791. at91eb40a.cfg imx35.cfg readme.txt
  792. at91r40008.cfg is5114.cfg sam7se512.cfg
  793. at91rm9200.cfg ixp42x.cfg sam7x256.cfg
  794. at91sam3u1c.cfg lm3s1968.cfg samsung_s3c2410.cfg
  795. at91sam3u1e.cfg lm3s3748.cfg samsung_s3c2440.cfg
  796. at91sam3u2c.cfg lm3s6965.cfg samsung_s3c2450.cfg
  797. at91sam3u2e.cfg lm3s811.cfg samsung_s3c4510.cfg
  798. at91sam3u4c.cfg lm3s9b9x.cfg samsung_s3c6410.cfg
  799. at91sam3u4e.cfg lpc1768.cfg sharp_lh79532.cfg
  800. at91sam3uXX.cfg lpc2103.cfg smdk6410.cfg
  801. at91sam7sx.cfg lpc2124.cfg smp8634.cfg
  802. at91sam9260.cfg lpc2129.cfg stm32.cfg
  803. c100.cfg lpc2148.cfg str710.cfg
  804. c100config.tcl lpc2294.cfg str730.cfg
  805. c100helper.tcl lpc2378.cfg str750.cfg
  806. c100regs.tcl lpc2478.cfg str912.cfg
  807. cs351x.cfg lpc2900.cfg telo.cfg
  808. davinci.cfg mega128.cfg ti_dm355.cfg
  809. dragonite.cfg netx500.cfg ti_dm365.cfg
  810. epc9301.cfg omap2420.cfg ti_dm6446.cfg
  811. feroceon.cfg omap3530.cfg tmpa900.cfg
  812. icepick.cfg omap5912.cfg tmpa910.cfg
  813. imx21.cfg pic32mx.cfg xba_revA3.cfg
  814. $
  815. @end example
  816. @item @emph{more} ... browse for other library files which may be useful.
  817. For example, there are various generic and CPU-specific utilities.
  818. @end itemize
  819. The @file{openocd.cfg} user config
  820. file may override features in any of the above files by
  821. setting variables before sourcing the target file, or by adding
  822. commands specific to their situation.
  823. @section Interface Config Files
  824. The user config file
  825. should be able to source one of these files with a command like this:
  826. @example
  827. source [find interface/FOOBAR.cfg]
  828. @end example
  829. A preconfigured interface file should exist for every interface in use
  830. today, that said, perhaps some interfaces have only been used by the
  831. sole developer who created it.
  832. A separate chapter gives information about how to set these up.
  833. @xref{Interface - Dongle Configuration}.
  834. Read the OpenOCD source code if you have a new kind of hardware interface
  835. and need to provide a driver for it.
  836. @section Board Config Files
  837. @cindex config file, board
  838. @cindex board config file
  839. The user config file
  840. should be able to source one of these files with a command like this:
  841. @example
  842. source [find board/FOOBAR.cfg]
  843. @end example
  844. The point of a board config file is to package everything
  845. about a given board that user config files need to know.
  846. In summary the board files should contain (if present)
  847. @enumerate
  848. @item One or more @command{source [target/...cfg]} statements
  849. @item NOR flash configuration (@pxref{NOR Configuration})
  850. @item NAND flash configuration (@pxref{NAND Configuration})
  851. @item Target @code{reset} handlers for SDRAM and I/O configuration
  852. @item JTAG adapter reset configuration (@pxref{Reset Configuration})
  853. @item All things that are not ``inside a chip''
  854. @end enumerate
  855. Generic things inside target chips belong in target config files,
  856. not board config files. So for example a @code{reset-init} event
  857. handler should know board-specific oscillator and PLL parameters,
  858. which it passes to target-specific utility code.
  859. The most complex task of a board config file is creating such a
  860. @code{reset-init} event handler.
  861. Define those handlers last, after you verify the rest of the board
  862. configuration works.
  863. @subsection Communication Between Config files
  864. In addition to target-specific utility code, another way that
  865. board and target config files communicate is by following a
  866. convention on how to use certain variables.
  867. The full Tcl/Tk language supports ``namespaces'', but JIM-Tcl does not.
  868. Thus the rule we follow in OpenOCD is this: Variables that begin with
  869. a leading underscore are temporary in nature, and can be modified and
  870. used at will within a target configuration file.
  871. Complex board config files can do the things like this,
  872. for a board with three chips:
  873. @example
  874. # Chip #1: PXA270 for network side, big endian
  875. set CHIPNAME network
  876. set ENDIAN big
  877. source [find target/pxa270.cfg]
  878. # on return: _TARGETNAME = network.cpu
  879. # other commands can refer to the "network.cpu" target.
  880. $_TARGETNAME configure .... events for this CPU..
  881. # Chip #2: PXA270 for video side, little endian
  882. set CHIPNAME video
  883. set ENDIAN little
  884. source [find target/pxa270.cfg]
  885. # on return: _TARGETNAME = video.cpu
  886. # other commands can refer to the "video.cpu" target.
  887. $_TARGETNAME configure .... events for this CPU..
  888. # Chip #3: Xilinx FPGA for glue logic
  889. set CHIPNAME xilinx
  890. unset ENDIAN
  891. source [find target/spartan3.cfg]
  892. @end example
  893. That example is oversimplified because it doesn't show any flash memory,
  894. or the @code{reset-init} event handlers to initialize external DRAM
  895. or (assuming it needs it) load a configuration into the FPGA.
  896. Such features are usually needed for low-level work with many boards,
  897. where ``low level'' implies that the board initialization software may
  898. not be working. (That's a common reason to need JTAG tools. Another
  899. is to enable working with microcontroller-based systems, which often
  900. have no debugging support except a JTAG connector.)
  901. Target config files may also export utility functions to board and user
  902. config files. Such functions should use name prefixes, to help avoid
  903. naming collisions.
  904. Board files could also accept input variables from user config files.
  905. For example, there might be a @code{J4_JUMPER} setting used to identify
  906. what kind of flash memory a development board is using, or how to set
  907. up other clocks and peripherals.
  908. @subsection Variable Naming Convention
  909. @cindex variable names
  910. Most boards have only one instance of a chip.
  911. However, it should be easy to create a board with more than
  912. one such chip (as shown above).
  913. Accordingly, we encourage these conventions for naming
  914. variables associated with different @file{target.cfg} files,
  915. to promote consistency and
  916. so that board files can override target defaults.
  917. Inputs to target config files include:
  918. @itemize @bullet
  919. @item @code{CHIPNAME} ...
  920. This gives a name to the overall chip, and is used as part of
  921. tap identifier dotted names.
  922. While the default is normally provided by the chip manufacturer,
  923. board files may need to distinguish between instances of a chip.
  924. @item @code{ENDIAN} ...
  925. By default @option{little} - although chips may hard-wire @option{big}.
  926. Chips that can't change endianness don't need to use this variable.
  927. @item @code{CPUTAPID} ...
  928. When OpenOCD examines the JTAG chain, it can be told verify the
  929. chips against the JTAG IDCODE register.
  930. The target file will hold one or more defaults, but sometimes the
  931. chip in a board will use a different ID (perhaps a newer revision).
  932. @end itemize
  933. Outputs from target config files include:
  934. @itemize @bullet
  935. @item @code{_TARGETNAME} ...
  936. By convention, this variable is created by the target configuration
  937. script. The board configuration file may make use of this variable to
  938. configure things like a ``reset init'' script, or other things
  939. specific to that board and that target.
  940. If the chip has 2 targets, the names are @code{_TARGETNAME0},
  941. @code{_TARGETNAME1}, ... etc.
  942. @end itemize
  943. @subsection The reset-init Event Handler
  944. @cindex event, reset-init
  945. @cindex reset-init handler
  946. Board config files run in the OpenOCD configuration stage;
  947. they can't use TAPs or targets, since they haven't been
  948. fully set up yet.
  949. This means you can't write memory or access chip registers;
  950. you can't even verify that a flash chip is present.
  951. That's done later in event handlers, of which the target @code{reset-init}
  952. handler is one of the most important.
  953. Except on microcontrollers, the basic job of @code{reset-init} event
  954. handlers is setting up flash and DRAM, as normally handled by boot loaders.
  955. Microcontrollers rarely use boot loaders; they run right out of their
  956. on-chip flash and SRAM memory. But they may want to use one of these
  957. handlers too, if just for developer convenience.
  958. @quotation Note
  959. Because this is so very board-specific, and chip-specific, no examples
  960. are included here.
  961. Instead, look at the board config files distributed with OpenOCD.
  962. If you have a boot loader, its source code will help; so will
  963. configuration files for other JTAG tools
  964. (@pxref{Translating Configuration Files}).
  965. @end quotation
  966. Some of this code could probably be shared between different boards.
  967. For example, setting up a DRAM controller often doesn't differ by
  968. much except the bus width (16 bits or 32?) and memory timings, so a
  969. reusable TCL procedure loaded by the @file{target.cfg} file might take
  970. those as parameters.
  971. Similarly with oscillator, PLL, and clock setup;
  972. and disabling the watchdog.
  973. Structure the code cleanly, and provide comments to help
  974. the next developer doing such work.
  975. (@emph{You might be that next person} trying to reuse init code!)
  976. The last thing normally done in a @code{reset-init} handler is probing
  977. whatever flash memory was configured. For most chips that needs to be
  978. done while the associated target is halted, either because JTAG memory
  979. access uses the CPU or to prevent conflicting CPU access.
  980. @subsection JTAG Clock Rate
  981. Before your @code{reset-init} handler has set up
  982. the PLLs and clocking, you may need to run with
  983. a low JTAG clock rate.
  984. @xref{JTAG Speed}.
  985. Then you'd increase that rate after your handler has
  986. made it possible to use the faster JTAG clock.
  987. When the initial low speed is board-specific, for example
  988. because it depends on a board-specific oscillator speed, then
  989. you should probably set it up in the board config file;
  990. if it's target-specific, it belongs in the target config file.
  991. For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
  992. @uref{} gives details.}
  993. is one sixth of the CPU clock; or one eighth for ARM11 cores.
  994. Consult chip documentation to determine the peak JTAG clock rate,
  995. which might be less than that.
  996. @quotation Warning
  997. On most ARMs, JTAG clock detection is coupled to the core clock, so
  998. software using a @option{wait for interrupt} operation blocks JTAG access.
  999. Adaptive clocking provides a partial workaround, but a more complete
  1000. solution just avoids using that instruction with JTAG debuggers.
  1001. @end quotation
  1002. If the board supports adaptive clocking, use the @command{jtag_rclk}
  1003. command, in case your board is used with JTAG adapter which
  1004. also supports it. Otherwise use @command{jtag_khz}.
  1005. Set the slow rate at the beginning of the reset sequence,
  1006. and the faster rate as soon as the clocks are at full speed.
  1007. @section Target Config Files
  1008. @cindex config file, target
  1009. @cindex target config file
  1010. Board config files communicate with target config files using
  1011. naming conventions as described above, and may source one or
  1012. more target config files like this:
  1013. @example
  1014. source [find target/FOOBAR.cfg]
  1015. @end example
  1016. The point of a target config file is to package everything
  1017. about a given chip that board config files need to know.
  1018. In summary the target files should contain
  1019. @enumerate
  1020. @item Set defaults
  1021. @item Add TAPs to the scan chain
  1022. @item Add CPU targets (includes GDB support)
  1023. @item CPU/Chip/CPU-Core specific features
  1024. @item On-Chip flash
  1025. @end enumerate
  1026. As a rule of thumb, a target file sets up only one chip.
  1027. For a microcontroller, that will often include a single TAP,
  1028. which is a CPU needing a GDB target, and its on-chip flash.
  1029. More complex chips may include multiple TAPs, and the target
  1030. config file may need to define them all before OpenOCD
  1031. can talk to the chip.
  1032. For example, some phone chips have JTAG scan chains that include
  1033. an ARM core for operating system use, a DSP,
  1034. another ARM core embedded in an image processing engine,
  1035. and other processing engines.
  1036. @subsection Default Value Boiler Plate Code
  1037. All target configuration files should start with code like this,
  1038. letting board config files express environment-specific
  1039. differences in how things should be set up.
  1040. @example
  1041. # Boards may override chip names, perhaps based on role,
  1042. # but the default should match what the vendor uses
  1043. if @{ [info exists CHIPNAME] @} @{
  1045. @} else @{
  1046. set _CHIPNAME sam7x256
  1047. @}
  1048. # ONLY use ENDIAN with targets that can change it.
  1049. if @{ [info exists ENDIAN] @} @{
  1050. set _ENDIAN $ENDIAN
  1051. @} else @{
  1052. set _ENDIAN little
  1053. @}
  1054. # TAP identifiers may change as chips mature, for example with
  1055. # new revision fields (the "3" here). Pick a good default; you
  1056. # can pass several such identifiers to the "jtag newtap" command.
  1057. if @{ [info exists CPUTAPID ] @} @{
  1059. @} else @{
  1060. set _CPUTAPID 0x3f0f0f0f
  1061. @}
  1062. @end example
  1063. @c but 0x3f0f0f0f is for an str73x part ...
  1064. @emph{Remember:} Board config files may include multiple target
  1065. config files, or the same target file multiple times
  1066. (changing at least @code{CHIPNAME}).
  1067. Likewise, the target configuration file should define
  1068. @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
  1069. use it later on when defining debug targets:
  1070. @example
  1071. set _TARGETNAME $_CHIPNAME.cpu
  1072. target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
  1073. @end example
  1074. @subsection Adding TAPs to the Scan Chain
  1075. After the ``defaults'' are set up,
  1076. add the TAPs on each chip to the JTAG scan chain.
  1077. @xref{TAP Declaration}, and the naming convention
  1078. for taps.
  1079. In the simplest case the chip has only one TAP,
  1080. probably for a CPU or FPGA.
  1081. The config file for the Atmel AT91SAM7X256
  1082. looks (in part) like this:
  1083. @example
  1084. jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \
  1085. -expected-id $_CPUTAPID
  1086. @end example
  1087. A board with two such at91sam7 chips would be able
  1088. to source such a config file twice, with different
  1089. values for @code{CHIPNAME}, so
  1090. it adds a different TAP each time.
  1091. If there are nonzero @option{-expected-id} values,
  1092. OpenOCD attempts to verify the actual tap id against those values.
  1093. It will issue error messages if there is mismatch, which
  1094. can help to pinpoint problems in OpenOCD configurations.
  1095. @example
  1096. JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
  1097. (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
  1098. ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
  1099. ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
  1100. ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
  1101. @end example
  1102. There are more complex examples too, with chips that have
  1103. multiple TAPs. Ones worth looking at include:
  1104. @itemize
  1105. @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
  1106. plus a JRC to enable them
  1107. @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
  1108. @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
  1109. is not currently used)
  1110. @end itemize
  1111. @subsection Add CPU targets
  1112. After adding a TAP for a CPU, you should set it up so that
  1113. GDB and other commands can use it.
  1114. @xref{CPU Configuration}.
  1115. For the at91sam7 example above, the command can look like this;
  1116. note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
  1117. to little endian, and this chip doesn't support changing that.
  1118. @example
  1119. set _TARGETNAME $_CHIPNAME.cpu
  1120. target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
  1121. @end example
  1122. Work areas are small RAM areas associated with CPU targets.
  1123. They are used by OpenOCD to speed up downloads,
  1124. and to download small snippets of code to program flash chips.
  1125. If the chip includes a form of ``on-chip-ram'' - and many do - define
  1126. a work area if you can.
  1127. Again using the at91sam7 as an example, this can look like:
  1128. @example
  1129. $_TARGETNAME configure -work-area-phys 0x00200000 \
  1130. -work-area-size 0x4000 -work-area-backup 0
  1131. @end example
  1132. @subsection Chip Reset Setup
  1133. As a rule, you should put the @command{reset_config} command
  1134. into the board file. Most things you think you know about a
  1135. chip can be tweaked by the board.
  1136. Some chips have specific ways the TRST and SRST signals are
  1137. managed. In the unusual case that these are @emph{chip specific}
  1138. and can never be changed by board wiring, they could go here.
  1139. Some chips need special attention during reset handling if
  1140. they're going to be used with JTAG.
  1141. An example might be needing to send some commands right
  1142. after the target's TAP has been reset, providing a
  1143. @code{reset-deassert-post} event handler that writes a chip
  1144. register to report that JTAG debugging is being done.
  1145. JTAG clocking constraints often change during reset, and in
  1146. some cases target config files (rather than board config files)
  1147. are the right places to handle some of those issues.
  1148. For example, immediately after reset most chips run using a
  1149. slower clock than they will use later.
  1150. That means that after reset (and potentially, as OpenOCD
  1151. first starts up) they must use a slower JTAG clock rate
  1152. than they will use later.
  1153. @xref{JTAG Speed}.
  1154. @quotation Important
  1155. When you are debugging code that runs right after chip
  1156. reset, getting these issues right is critical.
  1157. In particular, if you see intermittent failures when
  1158. OpenOCD verifies the scan chain after reset,
  1159. look at how you are setting up JTAG clocking.
  1160. @end quotation
  1161. @subsection ARM Core Specific Hacks
  1162. If the chip has a DCC, enable it. If the chip is an ARM9 with some
  1163. special high speed download features - enable it.
  1164. If present, the MMU, the MPU and the CACHE should be disabled.
  1165. Some ARM cores are equipped with trace support, which permits
  1166. examination of the instruction and data bus activity. Trace
  1167. activity is controlled through an ``Embedded Trace Module'' (ETM)
  1168. on one of the core's scan chains. The ETM emits voluminous data
  1169. through a ``trace port''. (@xref{ARM Hardware Tracing}.)
  1170. If you are using an external trace port,
  1171. configure it in your board config file.
  1172. If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
  1173. configure it in your target config file.
  1174. @example
  1175. etm config $_TARGETNAME 16 normal full etb
  1176. etb config $_TARGETNAME $_CHIPNAME.etb
  1177. @end example
  1178. @subsection Internal Flash Configuration
  1179. This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
  1180. @b{Never ever} in the ``target configuration file'' define any type of
  1181. flash that is external to the chip. (For example a BOOT flash on
  1182. Chip Select 0.) Such flash information goes in a board file - not
  1183. the TARGET (chip) file.
  1184. Examples:
  1185. @itemize @bullet
  1186. @item at91sam7x256 - has 256K flash YES enable it.
  1187. @item str912 - has flash internal YES enable it.
  1188. @item imx27 - uses boot flash on CS0 - it goes in the board file.
  1189. @item pxa270 - again - CS0 flash - it goes in the board file.
  1190. @end itemize
  1191. @anchor{Translating Configuration Files}
  1192. @section Translating Configuration Files
  1193. @cindex translation
  1194. If you have a configuration file for another hardware debugger
  1195. or toolset (Abatron, BDI2000, BDI3000, CCS,
  1196. Lauterbach, Segger, Macraigor, etc.), translating
  1197. it into OpenOCD syntax is often quite straightforward. The most tricky
  1198. part of creating a configuration script is oftentimes the reset init
  1199. sequence where e.g. PLLs, DRAM and the like is set up.
  1200. One trick that you can use when translating is to write small
  1201. Tcl procedures to translate the syntax into OpenOCD syntax. This
  1202. can avoid manual translation errors and make it easier to
  1203. convert other scripts later on.
  1204. Example of transforming quirky arguments to a simple search and
  1205. replace job:
  1206. @example
  1207. # Lauterbach syntax(?)
  1208. #
  1209. # Data.Set c15:0x042f %long 0x40000015
  1210. #
  1211. # OpenOCD syntax when using procedure below.
  1212. #
  1213. # setc15 0x01 0x00050078
  1214. proc setc15 @{regs value@} @{
  1215. global TARGETNAME
  1216. echo [format "set p15 0x%04x, 0x%08x" $regs $value]
  1217. arm11 mcr $TARGETNAME 15 [expr ($regs>>12)&0x7] \
  1218. [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] \
  1219. [expr ($regs>>8)&0x7] $value
  1220. @}
  1221. @end example
  1222. @node Daemon Configuration
  1223. @chapter Daemon Configuration
  1224. @cindex initialization
  1225. The commands here are commonly found in the openocd.cfg file and are
  1226. used to specify what TCP/IP ports are used, and how GDB should be
  1227. supported.
  1228. @anchor{Configuration Stage}
  1229. @section Configuration Stage
  1230. @cindex configuration stage
  1231. @cindex config command
  1232. When the OpenOCD server process starts up, it enters a
  1233. @emph{configuration stage} which is the only time that
  1234. certain commands, @emph{configuration commands}, may be issued.
  1235. In this manual, the definition of a configuration command is
  1236. presented as a @emph{Config Command}, not as a @emph{Command}
  1237. which may be issued interactively.
  1238. Those configuration commands include declaration of TAPs,
  1239. flash banks,
  1240. the interface used for JTAG communication,
  1241. and other basic setup.
  1242. The server must leave the configuration stage before it
  1243. may access or activate TAPs.
  1244. After it leaves this stage, configuration commands may no
  1245. longer be issued.
  1246. The first thing OpenOCD does after leaving the configuration
  1247. stage is to verify that it can talk to the scan chain
  1248. (list of TAPs) which has been configured.
  1249. It will warn if it doesn't find TAPs it expects to find,
  1250. or finds TAPs that aren't supposed to be there.
  1251. You should see no errors at this point.
  1252. If you see errors, resolve them by correcting the
  1253. commands you used to configure the server.
  1254. Common errors include using an initial JTAG speed that's too
  1255. fast, and not providing the right IDCODE values for the TAPs
  1256. on the scan chain.
  1257. @deffn {Config Command} init
  1258. This command terminates the configuration stage and
  1259. enters the normal command mode. This can be useful to add commands to
  1260. the startup scripts and commands such as resetting the target,
  1261. programming flash, etc. To reset the CPU upon startup, add "init" and
  1262. "reset" at the end of the config script or at the end of the OpenOCD
  1263. command line using the @option{-c} command line switch.
  1264. If this command does not appear in any startup/configuration file
  1265. OpenOCD executes the command for you after processing all
  1266. configuration files and/or command line options.
  1267. @b{NOTE:} This command normally occurs at or near the end of your
  1268. openocd.cfg file to force OpenOCD to ``initialize'' and make the
  1269. targets ready. For example: If your openocd.cfg file needs to
  1270. read/write memory on your target, @command{init} must occur before
  1271. the memory read/write commands. This includes @command{nand probe}.
  1272. @end deffn
  1273. @deffn {Overridable Procedure} jtag_init
  1274. This is invoked at server startup to verify that it can talk
  1275. to the scan chain (list of TAPs) which has been configured.
  1276. The default implementation first tries @command{jtag arp_init},
  1277. which uses only a lightweight JTAG reset before examining the
  1278. scan chain.
  1279. If that fails, it tries again, using a harder reset
  1280. from the overridable procedure @command{init_reset}.
  1281. Implementations must have verified the JTAG scan chain before
  1282. they return.
  1283. This is done by calling @command{jtag arp_init}
  1284. (or @command{jtag arp_init-reset}).
  1285. @end deffn
  1286. @anchor{TCP/IP Ports}
  1287. @section TCP/IP Ports
  1288. @cindex TCP port
  1289. @cindex server
  1290. @cindex port
  1291. @cindex security
  1292. The OpenOCD server accepts remote commands in several syntaxes.
  1293. Each syntax uses a different TCP/IP port, which you may specify
  1294. only during configuration (before those ports are opened).
  1295. For reasons including security, you may wish to prevent remote
  1296. access using one or more of these ports.
  1297. In such cases, just specify the relevant port number as zero.
  1298. If you disable all access through TCP/IP, you will need to
  1299. use the command line @option{-pipe} option.
  1300. @deffn {Command} gdb_port (number)
  1301. @cindex GDB server
  1302. Specify or query the first port used for incoming GDB connections.
  1303. The GDB port for the
  1304. first target will be gdb_port, the second target will listen on gdb_port + 1, and so on.
  1305. When not specified during the configuration stage,
  1306. the port @var{number} defaults to 3333.
  1307. When specified as zero, this port is not activated.
  1308. @end deffn
  1309. @deffn {Command} tcl_port (number)
  1310. Specify or query the port used for a simplified RPC
  1311. connection that can be used by clients to issue TCL commands and get the
  1312. output from the Tcl engine.
  1313. Intended as a machine interface.
  1314. When not specified during the configuration stage,
  1315. the port @var{number} defaults to 6666.
  1316. When specified as zero, this port is not activated.
  1317. @end deffn
  1318. @deffn {Command} telnet_port (number)
  1319. Specify or query the
  1320. port on which to listen for incoming telnet connections.
  1321. This port is intended for interaction with one human through TCL commands.
  1322. When not specified during the configuration stage,
  1323. the port @var{number} defaults to 4444.
  1324. When specified as zero, this port is not activated.
  1325. @end deffn
  1326. @anchor{GDB Configuration}
  1327. @section GDB Configuration
  1328. @cindex GDB
  1329. @cindex GDB configuration
  1330. You can reconfigure some GDB behaviors if needed.
  1331. The ones listed here are static and global.
  1332. @xref{Target Configuration}, about configuring individual targets.
  1333. @xref{Target Events}, about configuring target-specific event handling.
  1334. @anchor{gdb_breakpoint_override}
  1335. @deffn {Command} gdb_breakpoint_override [@option{hard}|@option{soft}|@option{disable}]
  1336. Force breakpoint type for gdb @command{break} commands.
  1337. This option supports GDB GUIs which don't
  1338. distinguish hard versus soft breakpoints, if the default OpenOCD and
  1339. GDB behaviour is not sufficient. GDB normally uses hardware
  1340. breakpoints if the memory map has been set up for flash regions.
  1341. @end deffn
  1342. @anchor{gdb_flash_program}
  1343. @deffn {Config Command} gdb_flash_program (@option{enable}|@option{disable})
  1344. Set to @option{enable} to cause OpenOCD to program the flash memory when a
  1345. vFlash packet is received.
  1346. The default behaviour is @option{enable}.
  1347. @end deffn
  1348. @deffn {Config Command} gdb_memory_map (@option{enable}|@option{disable})
  1349. Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
  1350. requested. GDB will then know when to set hardware breakpoints, and program flash
  1351. using the GDB load command. @command{gdb_flash_program enable} must also be enabled
  1352. for flash programming to work.
  1353. Default behaviour is @option{enable}.
  1354. @xref{gdb_flash_program}.
  1355. @end deffn
  1356. @deffn {Config Command} gdb_report_data_abort (@option{enable}|@option{disable})
  1357. Specifies whether data aborts cause an error to be reported
  1358. by GDB memory read packets.
  1359. The default behaviour is @option{disable};
  1360. use @option{enable} see these errors reported.
  1361. @end deffn
  1362. @anchor{Event Polling}
  1363. @section Event Polling
  1364. Hardware debuggers are parts of asynchronous systems,
  1365. where significant events can happen at any time.
  1366. The OpenOCD server needs to detect some of these events,
  1367. so it can report them to through TCL command line
  1368. or to GDB.
  1369. Examples of such events include:
  1370. @itemize
  1371. @item One of the targets can stop running ... maybe it triggers
  1372. a code breakpoint or data watchpoint, or halts itself.
  1373. @item Messages may be sent over ``debug message'' channels ... many
  1374. targets support such messages sent over JTAG,
  1375. for receipt by the person debugging or tools.
  1376. @item Loss of power ... some adapters can detect these events.
  1377. @item Resets not issued through JTAG ... such reset sources
  1378. can include button presses or other system hardware, sometimes
  1379. including the target itself (perhaps through a watchdog).
  1380. @item Debug instrumentation sometimes supports event triggering
  1381. such as ``trace buffer full'' (so it can quickly be emptied)
  1382. or other signals (to correlate with code behavior).
  1383. @end itemize
  1384. None of those events are signaled through standard JTAG signals.
  1385. However, most conventions for JTAG connectors include voltage
  1386. level and system reset (SRST) signal detection.
  1387. Some connectors also include instrumentation signals, which
  1388. can imply events when those signals are inputs.
  1389. In general, OpenOCD needs to periodically check for those events,
  1390. either by looking at the status of signals on the JTAG connector
  1391. or by sending synchronous ``tell me your status'' JTAG requests
  1392. to the various active targets.
  1393. There is a command to manage and monitor that polling,
  1394. which is normally done in the background.
  1395. @deffn Command poll [@option{on}|@option{off}]
  1396. Poll the current target for its current state.
  1397. (Also, @pxref{target curstate}.)
  1398. If that target is in debug mode, architecture
  1399. specific information about the current state is printed.
  1400. An optional parameter
  1401. allows background polling to be enabled and disabled.
  1402. You could use this from the TCL command shell, or
  1403. from GDB using @command{monitor poll} command.
  1404. @example
  1405. > poll
  1406. background polling: on
  1407. target state: halted
  1408. target halted in ARM state due to debug-request, \
  1409. current mode: Supervisor
  1410. cpsr: 0x800000d3 pc: 0x11081bfc
  1411. MMU: disabled, D-Cache: disabled, I-Cache: enabled
  1412. >
  1413. @end example
  1414. @end deffn
  1415. @node Interface - Dongle Configuration
  1416. @chapter Interface - Dongle Configuration
  1417. @cindex config file, interface
  1418. @cindex interface config file
  1419. JTAG Adapters/Interfaces/Dongles are normally configured
  1420. through commands in an interface configuration
  1421. file which is sourced by your @file{openocd.cfg} file, or
  1422. through a command line @option{-f interface/....cfg} option.
  1423. @example
  1424. source [find interface/olimex-jtag-tiny.cfg]
  1425. @end example
  1426. These commands tell
  1427. OpenOCD what type of JTAG adapter you have, and how to talk to it.
  1428. A few cases are so simple that you only need to say what driver to use:
  1429. @example
  1430. # jlink interface
  1431. interface jlink
  1432. @end example
  1433. Most adapters need a bit more configuration than that.
  1434. @section Interface Configuration
  1435. The interface command tells OpenOCD what type of JTAG dongle you are
  1436. using. Depending on the type of dongle, you may need to have one or
  1437. more additional commands.
  1438. @deffn {Config Command} {interface} name
  1439. Use the interface driver @var{name} to connect to the
  1440. target.
  1441. @end deffn
  1442. @deffn Command {interface_list}
  1443. List the interface drivers that have been built into
  1444. the running copy of OpenOCD.
  1445. @end deffn
  1446. @deffn Command {jtag interface}
  1447. Returns the name of the interface driver being used.
  1448. @end deffn
  1449. @section Interface Drivers
  1450. Each of the interface drivers listed here must be explicitly
  1451. enabled when OpenOCD is configured, in order to be made
  1452. available at run time.
  1453. @deffn {Interface Driver} {amt_jtagaccel}
  1454. Amontec Chameleon in its JTAG Accelerator configuration,
  1455. connected to a PC's EPP mode parallel port.
  1456. This defines some driver-specific commands:
  1457. @deffn {Config Command} {parport_port} number
  1458. Specifies either the address of the I/O port (default: 0x378 for LPT1) or
  1459. the number of the @file{/dev/parport} device.
  1460. @end deffn
  1461. @deffn {Config Command} rtck [@option{enable}|@option{disable}]
  1462. Displays status of RTCK option.
  1463. Optionally sets that option first.
  1464. @end deffn
  1465. @end deffn
  1466. @deffn {Interface Driver} {arm-jtag-ew}
  1467. Olimex ARM-JTAG-EW USB adapter
  1468. This has one driver-specific command:
  1469. @deffn Command {armjtagew_info}
  1470. Logs some status
  1471. @end deffn
  1472. @end deffn
  1473. @deffn {Interface Driver} {at91rm9200}
  1474. Supports bitbanged JTAG from the local system,
  1475. presuming that system is an Atmel AT91rm9200
  1476. and a specific set of GPIOs is used.
  1477. @c command: at91rm9200_device NAME
  1478. @c chooses among list of bit configs ... only one option
  1479. @end deffn
  1480. @deffn {Interface Driver} {dummy}
  1481. A dummy software-only driver for debugging.
  1482. @end deffn
  1483. @deffn {Interface Driver} {ep93xx}
  1484. Cirrus Logic EP93xx based single-board computer bit-banging (in development)
  1485. @end deffn
  1486. @deffn {Interface Driver} {ft2232}
  1487. FTDI FT2232 (USB) based devices over one of the userspace libraries.
  1488. These interfaces have several commands, used to configure the driver
  1489. before initializing the JTAG scan chain:
  1490. @deffn {Config Command} {ft2232_device_desc} description
  1491. Provides the USB device description (the @emph{iProduct string})
  1492. of the FTDI FT2232 device. If not
  1493. specified, the FTDI default value is used. This setting is only valid
  1494. if compiled with FTD2XX support.
  1495. @end deffn
  1496. @deffn {Config Command} {ft2232_serial} serial-number
  1497. Specifies the @var{serial-number} of the FTDI FT2232 device to use,
  1498. in case the vendor provides unique IDs and more than one FT2232 device
  1499. is connected to the host.
  1500. If not specified, serial numbers are not considered.
  1501. (Note that USB serial numbers can be arbitrary Unicode strings,
  1502. and are not restricted to containing only decimal digits.)
  1503. @end deffn
  1504. @deffn {Config Command} {ft2232_layout} name
  1505. Each vendor's FT2232 device can use different GPIO signals
  1506. to control output-enables, reset signals, and LEDs.
  1507. Currently valid layout @var{name} values include:
  1508. @itemize @minus
  1509. @item @b{axm0432_jtag} Axiom AXM-0432
  1510. @item @b{comstick} Hitex STR9 comstick
  1511. @item @b{cortino} Hitex Cortino JTAG interface
  1512. @item @b{evb_lm3s811} Luminary Micro EVB_LM3S811 as a JTAG interface,
  1513. either for the local Cortex-M3 (SRST only)
  1514. or in a passthrough mode (neither SRST nor TRST)
  1515. @item @b{luminary_icdi} Luminary In-Circuit Debug Interface (ICDI) Board
  1516. @item @b{flyswatter} Tin Can Tools Flyswatter
  1517. @item @b{icebear} ICEbear JTAG adapter from Section 5
  1518. @item @b{jtagkey} Amontec JTAGkey and JTAGkey-Tiny (and compatibles)
  1519. @item @b{jtagkey2} Amontec JTAGkey2 (and compatibles)
  1520. @item @b{m5960} American Microsystems M5960
  1521. @item @b{olimex-jtag} Olimex ARM-USB-OCD and ARM-USB-Tiny
  1522. @item @b{oocdlink} OOCDLink
  1523. @c oocdlink ~= jtagkey_prototype_v1
  1524. @item @b{sheevaplug} Marvell Sheevaplug development kit
  1525. @item @b{signalyzer} Xverve Signalyzer
  1526. @item @b{stm32stick} Hitex STM32 Performance Stick
  1527. @item @b{turtelizer2} egnite Software turtelizer2
  1528. @item @b{usbjtag} "USBJTAG-1" layout described in the OpenOCD diploma thesis
  1529. @end itemize
  1530. @end deffn
  1531. @deffn {Config Command} {ft2232_vid_pid} [vid pid]+
  1532. The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
  1533. default values are used.
  1534. Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
  1535. @example
  1536. ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
  1537. @end example
  1538. @end deffn
  1539. @deffn {Config Command} {ft2232_latency} ms
  1540. On some systems using FT2232 based JTAG interfaces the FT_Read function call in
  1541. ft2232_read() fails to return the expected number of bytes. This can be caused by
  1542. USB communication delays and has proved hard to reproduce and debug. Setting the
  1543. FT2232 latency timer to a larger value increases delays for short USB packets but it
  1544. also reduces the risk of timeouts before receiving the expected number of bytes.
  1545. The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
  1546. @end deffn
  1547. For example, the interface config file for a
  1548. Turtelizer JTAG Adapter looks something like this:
  1549. @example
  1550. interface ft2232
  1551. ft2232_device_desc "Turtelizer JTAG/RS232 Adapter"
  1552. ft2232_layout turtelizer2
  1553. ft2232_vid_pid 0x0403 0xbdc8
  1554. @end example
  1555. @end deffn
  1556. @deffn {Interface Driver} {gw16012}
  1557. Gateworks GW16012 JTAG programmer.
  1558. This has one driver-specific command:
  1559. @deffn {Config Command} {parport_port} number
  1560. Specifies either the address of the I/O port (default: 0x378 for LPT1) or
  1561. the number of the @file{/dev/parport} device.
  1562. @end deffn
  1563. @end deffn
  1564. @deffn {Interface Driver} {jlink}
  1565. Segger jlink USB adapter
  1566. @c command: jlink_info
  1567. @c dumps status
  1568. @c command: jlink_hw_jtag (2|3)
  1569. @c sets version 2 or 3
  1570. @end deffn
  1571. @deffn {Interface Driver} {parport}
  1572. Supports PC parallel port bit-banging cables:
  1573. Wigglers, PLD download cable, and more.
  1574. These interfaces have several commands, used to configure the driver
  1575. before initializing the JTAG scan chain:
  1576. @deffn {Config Command} {parport_cable} name
  1577. The layout of the parallel port cable used to connect to the target.
  1578. Currently valid cable @var{name} values include:
  1579. @itemize @minus
  1580. @item @b{altium} Altium Universal JTAG cable.
  1581. @item @b{arm-jtag} Same as original wiggler except SRST and
  1582. TRST connections reversed and TRST is also inverted.
  1583. @item @b{chameleon} The Amontec Chameleon's CPLD when operated
  1584. in configuration mode. This is only used to
  1585. program the Chameleon itself, not a connected target.
  1586. @item @b{dlc5} The Xilinx Parallel cable III.
  1587. @item @b{flashlink} The ST Parallel cable.
  1588. @item @b{lattice} Lattice ispDOWNLOAD Cable
  1589. @item @b{old_amt_wiggler} The Wiggler configuration that comes with
  1590. some versions of
  1591. Amontec's Chameleon Programmer. The new version available from
  1592. the website uses the original Wiggler layout ('@var{wiggler}')
  1593. @item @b{triton} The parallel port adapter found on the
  1594. ``Karo Triton 1 Development Board''.
  1595. This is also the layout used by the HollyGates design
  1596. (see @uref{}).
  1597. @item @b{wiggler} The original Wiggler layout, also supported by
  1598. several clones, such as the Olimex ARM-JTAG
  1599. @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
  1600. @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
  1601. @end itemize
  1602. @end deffn
  1603. @deffn {Config Command} {parport_port} number
  1604. Either the address of the I/O port (default: 0x378 for LPT1) or the number of
  1605. the @file{/dev/parport} device
  1606. When using PPDEV to access the parallel port, use the number of the parallel port:
  1607. @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
  1608. you may encounter a problem.
  1609. @end deffn
  1610. @deffn {Config Command} {parport_write_on_exit} (on|off)
  1611. This will configure the parallel driver to write a known
  1612. cable-specific value to the parallel interface on exiting OpenOCD
  1613. @end deffn
  1614. For example, the interface configuration file for a
  1615. classic ``Wiggler'' cable might look something like this:
  1616. @example
  1617. interface parport
  1618. parport_port 0xc8b8
  1619. parport_cable wiggler
  1620. @end example
  1621. @end deffn
  1622. @deffn {Interface Driver} {presto}
  1623. ASIX PRESTO USB JTAG programmer.
  1624. @c command: presto_serial str
  1625. @c sets serial number
  1626. @end deffn
  1627. @deffn {Interface Driver} {rlink}
  1628. Raisonance RLink USB adapter
  1629. @end deffn
  1630. @deffn {Interface Driver} {usbprog}
  1631. usbprog is a freely programmable USB adapter.
  1632. @end deffn
  1633. @deffn {Interface Driver} {vsllink}
  1634. vsllink is part of Versaloon which is a versatile USB programmer.
  1635. @quotation Note
  1636. This defines quite a few driver-specific commands,
  1637. which are not currently documented here.
  1638. @end quotation
  1639. @end deffn
  1640. @deffn {Interface Driver} {ZY1000}
  1641. This is the Zylin ZY1000 JTAG debugger.
  1642. @quotation Note
  1643. This defines some driver-specific commands,
  1644. which are not currently documented here.
  1645. @end quotation
  1646. @deffn Command power [@option{on}|@option{off}]
  1647. Turn power switch to target on/off.
  1648. No arguments: print status.
  1649. @end deffn
  1650. @end deffn
  1651. @anchor{JTAG Speed}
  1652. @section JTAG Speed
  1653. JTAG clock setup is part of system setup.
  1654. It @emph{does not belong with interface setup} since any interface
  1655. only knows a few of the constraints for the JTAG clock speed.
  1656. Sometimes the JTAG speed is
  1657. changed during the target initialization process: (1) slow at
  1658. reset, (2) program the CPU clocks, (3) run fast.
  1659. Both the "slow" and "fast" clock rates are functions of the
  1660. oscillators used, the chip, the board design, and sometimes
  1661. power management software that may be active.
  1662. The speed used during reset, and the scan chain verification which
  1663. follows reset, can be adjusted using a @code{reset-start}
  1664. target event handler.
  1665. It can then be reconfigured to a faster speed by a
  1666. @code{reset-init} target event handler after it reprograms those
  1667. CPU clocks, or manually (if something else, such as a boot loader,
  1668. sets up those clocks).
  1669. @xref{Target Events}.
  1670. When the initial low JTAG speed is a chip characteristic, perhaps
  1671. because of a required oscillator speed, provide such a handler
  1672. in the target config file.
  1673. When that speed is a function of a board-specific characteristic
  1674. such as which speed oscillator is used, it belongs in the board
  1675. config file instead.
  1676. In both cases it's safest to also set the initial JTAG clock rate
  1677. to that same slow speed, so that OpenOCD never starts up using a
  1678. clock speed that's faster than the scan chain can support.
  1679. @example
  1680. jtag_rclk 3000
  1681. $_TARGET.cpu configure -event reset-start @{ jtag_rclk 3000 @}
  1682. @end example
  1683. If your system supports adaptive clocking (RTCK), configuring
  1684. JTAG to use that is probably the most robust approach.
  1685. However, it introduces delays to synchronize clocks; so it
  1686. may not be the fastest solution.
  1687. @b{NOTE:} Script writers should consider using @command{jtag_rclk}
  1688. instead of @command{jtag_khz}.
  1689. @deffn {Command} jtag_khz max_speed_kHz
  1690. A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
  1691. JTAG interfaces usually support a limited number of
  1692. speeds. The speed actually used won't be faster
  1693. than the speed specified.
  1694. Chip data sheets generally include a top JTAG clock rate.
  1695. The actual rate is often a function of a CPU core clock,
  1696. and is normally less than that peak rate.
  1697. For example, most ARM cores accept at most one sixth of the CPU clock.
  1698. Speed 0 (khz) selects RTCK method.
  1699. @xref{FAQ RTCK}.
  1700. If your system uses RTCK, you won't need to change the
  1701. JTAG clocking after setup.
  1702. Not all interfaces, boards, or targets support ``rtck''.
  1703. If the interface device can not
  1704. support it, an error is returned when you try to use RTCK.
  1705. @end deffn
  1706. @defun jtag_rclk fallback_speed_kHz
  1707. @cindex adaptive clocking
  1708. @cindex RTCK
  1709. This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
  1710. If that fails (maybe the interface, board, or target doesn't
  1711. support it), falls back to the specified frequency.
  1712. @example
  1713. # Fall back to 3mhz if RTCK is not supported
  1714. jtag_rclk 3000
  1715. @end example
  1716. @end defun
  1717. @node Reset Configuration
  1718. @chapter Reset Configuration
  1719. @cindex Reset Configuration
  1720. Every system configuration may require a different reset
  1721. configuration. This can also be quite confusing.
  1722. Resets also interact with @var{reset-init} event handlers,
  1723. which do things like setting up clocks and DRAM, and
  1724. JTAG clock rates. (@xref{JTAG Speed}.)
  1725. They can also interact with JTAG routers.
  1726. Please see the various board files for examples.
  1727. @quotation Note
  1728. To maintainers and integrators:
  1729. Reset configuration touches several things at once.
  1730. Normally the board configuration file
  1731. should define it and assume that the JTAG adapter supports
  1732. everything that's wired up to the board's JTAG connector.
  1733. However, the target configuration file could also make note
  1734. of something the silicon vendor has done inside the chip,
  1735. which will be true for most (or all) boards using that chip.
  1736. And when the JTAG adapter doesn't support everything, the
  1737. user configuration file will need to override parts of
  1738. the reset configuration provided by other files.
  1739. @end quotation
  1740. @section Types of Reset
  1741. There are many kinds of reset possible through JTAG, but
  1742. they may not all work with a given board and adapter.
  1743. That's part of why reset configuration can be error prone.
  1744. @itemize @bullet
  1745. @item
  1746. @emph{System Reset} ... the @emph{SRST} hardware signal
  1747. resets all chips connected to the JTAG adapter, such as processors,
  1748. power management chips, and I/O controllers. Normally resets triggered
  1749. with this signal behave exactly like pressing a RESET button.
  1750. @item
  1751. @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
  1752. just the TAP controllers connected to the JTAG adapter.
  1753. Such resets should not be visible to the rest of the system; resetting a
  1754. device's the TAP controller just puts that controller into a known state.
  1755. @item
  1756. @emph{Emulation Reset} ... many devices can be reset through JTAG
  1757. commands. These resets are often distinguishable from system
  1758. resets, either explicitly (a "reset reason" register says so)
  1759. or implicitly (not all parts of the chip get reset).
  1760. @item
  1761. @emph{Other Resets} ... system-on-chip devices often support
  1762. several other types of reset.
  1763. You may need to arrange that a watchdog timer stops
  1764. while debugging, preventing a watchdog reset.
  1765. There may be individual module resets.
  1766. @end itemize
  1767. In the best case, OpenOCD can hold SRST, then reset
  1768. the TAPs via TRST and send commands through JTAG to halt the
  1769. CPU at the reset vector before the 1st instruction is executed.
  1770. Then when it finally releases the SRST signal, the system is
  1771. halted under debugger control before any code has executed.
  1772. This is the behavior required to support the @command{reset halt}
  1773. and @command{reset init} commands; after @command{reset init} a
  1774. board-specific script might do things like setting up DRAM.
  1775. (@xref{Reset Command}.)
  1776. @anchor{SRST and TRST Issues}
  1777. @section SRST and TRST Issues
  1778. Because SRST and TRST are hardware signals, they can have a
  1779. variety of system-specific constraints. Some of the most
  1780. common issues are:
  1781. @itemize @bullet
  1782. @item @emph{Signal not available} ... Some boards don't wire
  1783. SRST or TRST to the JTAG connector. Some JTAG adapters don't
  1784. support such signals even if they are wired up.
  1785. Use the @command{reset_config} @var{signals} options to say
  1786. when either of those signals is not connected.
  1787. When SRST is not available, your code might not be able to rely
  1788. on controllers having been fully reset during code startup.
  1789. Missing TRST is not a problem, since JTAG level resets can
  1790. be triggered using with TMS signaling.
  1791. @item @emph{Signals shorted} ... Sometimes a chip, board, or
  1792. adapter will connect SRST to TRST, instead of keeping them separate.
  1793. Use the @command{reset_config} @var{combination} options to say
  1794. when those signals aren't properly independent.
  1795. @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
  1796. delay circuit, reset supervisor, or on-chip features can extend
  1797. the effect of a JTAG adapter's reset for some time after the adapter
  1798. stops issuing the reset. For example, there may be chip or board
  1799. requirements that all reset pulses last for at least a
  1800. certain amount of time; and reset buttons commonly have
  1801. hardware debouncing.
  1802. Use the @command{jtag_nsrst_delay} and @command{jtag_ntrst_delay}
  1803. commands to say when extra delays are needed.
  1804. @item @emph{Drive type} ... Reset lines often have a pullup
  1805. resistor, letting the JTAG interface treat them as open-drain
  1806. signals. But that's not a requirement, so the adapter may need
  1807. to use push/pull output drivers.
  1808. Also, with weak pullups it may be advisable to drive
  1809. signals to both levels (push/pull) to minimize rise times.
  1810. Use the @command{reset_config} @var{trst_type} and
  1811. @var{srst_type} parameters to say how to drive reset signals.
  1812. @item @emph{Special initialization} ... Targets sometimes need
  1813. special JTAG initialization sequences to handle chip-specific
  1814. issues (not limited to errata).
  1815. For example, certain JTAG commands might need to be issued while
  1816. the system as a whole is in a reset state (SRST active)
  1817. but the JTAG scan chain is usable (TRST inactive).
  1818. Many systems treat combined assertion of SRST and TRST as a
  1819. trigger for a harder reset than SRST alone.
  1820. Such custom reset handling is discussed later in this chapter.
  1821. @end itemize
  1822. There can also be other issues.
  1823. Some devices don't fully conform to the JTAG specifications.
  1824. Trivial system-specific differences are common, such as
  1825. SRST and TRST using slightly different names.
  1826. There are also vendors who distribute key JTAG documentation for
  1827. their chips only to developers who have signed a Non-Disclosure
  1828. Agreement (NDA).
  1829. Sometimes there are chip-specific extensions like a requirement to use
  1830. the normally-optional TRST signal (precluding use of JTAG adapters which
  1831. don't pass TRST through), or needing extra steps to complete a TAP reset.
  1832. In short, SRST and especially TRST handling may be very finicky,
  1833. needing to cope with both architecture and board specific constraints.
  1834. @section Commands for Handling Resets
  1835. @deffn {Command} jtag_nsrst_assert_width milliseconds
  1836. Minimum amount of time (in milliseconds) OpenOCD should wait
  1837. after asserting nSRST (active-low system reset) before
  1838. allowing it to be deasserted.
  1839. @end deffn
  1840. @deffn {Command} jtag_nsrst_delay milliseconds
  1841. How long (in milliseconds) OpenOCD should wait after deasserting
  1842. nSRST (active-low system reset) before starting new JTAG operations.
  1843. When a board has a reset button connected to SRST line it will
  1844. probably have hardware debouncing, implying you should use this.
  1845. @end deffn
  1846. @deffn {Command} jtag_ntrst_assert_width milliseconds
  1847. Minimum amount of time (in milliseconds) OpenOCD should wait
  1848. after asserting nTRST (active-low JTAG TAP reset) before
  1849. allowing it to be deasserted.
  1850. @end deffn
  1851. @deffn {Command} jtag_ntrst_delay milliseconds
  1852. How long (in milliseconds) OpenOCD should wait after deasserting
  1853. nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
  1854. @end deffn
  1855. @deffn {Command} reset_config mode_flag ...
  1856. This command displays or modifies the reset configuration
  1857. of your combination of JTAG board and target in target
  1858. configuration scripts.
  1859. Information earlier in this section describes the kind of problems
  1860. the command is intended to address (@pxref{SRST and TRST Issues}).
  1861. As a rule this command belongs only in board config files,
  1862. describing issues like @emph{board doesn't connect TRST};
  1863. or in user config files, addressing limitations derived
  1864. from a particular combination of interface and board.
  1865. (An unlikely example would be using a TRST-only adapter
  1866. with a board that only wires up SRST.)
  1867. The @var{mode_flag} options can be specified in any order, but only one
  1868. of each type -- @var{signals}, @var{combination},
  1869. @var{gates},
  1870. @var{trst_type},
  1871. and @var{srst_type} -- may be specified at a time.
  1872. If you don't provide a new value for a given type, its previous
  1873. value (perhaps the default) is unchanged.
  1874. For example, this means that you don't need to say anything at all about
  1875. TRST just to declare that if the JTAG adapter should want to drive SRST,
  1876. it must explicitly be driven high (@option{srst_push_pull}).
  1877. @itemize
  1878. @item
  1879. @var{signals} can specify which of the reset signals are connected.
  1880. For example, If the JTAG interface provides SRST, but the board doesn't
  1881. connect that signal properly, then OpenOCD can't use it.
  1882. Possible values are @option{none} (the default), @option{trst_only},
  1883. @option{srst_only} and @option{trst_and_srst}.
  1884. @quotation Tip
  1885. If your board provides SRST and/or TRST through the JTAG connector,
  1886. you must declare that so those signals can be used.
  1887. @end quotation
  1888. @item
  1889. The @var{combination} is an optional value specifying broken reset
  1890. signal implementations.
  1891. The default behaviour if no option given is @option{separate},
  1892. indicating everything behaves normally.
  1893. @option{srst_pulls_trst} states that the
  1894. test logic is reset together with the reset of the system (e.g. Philips
  1895. LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
  1896. the system is reset together with the test logic (only hypothetical, I
  1897. haven't seen hardware with such a bug, and can be worked around).
  1898. @option{combined} implies both @option{srst_pulls_trst} and
  1899. @option{trst_pulls_srst}.
  1900. @item
  1901. The @var{gates} tokens control flags that describe some cases where
  1902. JTAG may be unvailable during reset.
  1903. @option{srst_gates_jtag} (default)
  1904. indicates that asserting SRST gates the
  1905. JTAG clock. This means that no communication can happen on JTAG
  1906. while SRST is asserted.
  1907. Its converse is @option{srst_nogate}, indicating that JTAG commands
  1908. can safely be issued while SRST is active.
  1909. @end itemize
  1910. The optional @var{trst_type} and @var{srst_type} parameters allow the
  1911. driver mode of each reset line to be specified. These values only affect
  1912. JTAG interfaces with support for different driver modes, like the Amontec
  1913. JTAGkey and JTAG Accelerator. Also, they are necessarily ignored if the
  1914. relevant signal (TRST or SRST) is not connected.
  1915. @itemize
  1916. @item
  1917. Possible @var{trst_type} driver modes for the test reset signal (TRST)
  1918. are the default @option{trst_push_pull}, and @option{trst_open_drain}.
  1919. Most boards connect this signal to a pulldown, so the JTAG TAPs
  1920. never leave reset unless they are hooked up to a JTAG adapter.
  1921. @item
  1922. Possible @var{srst_type} driver modes for the system reset signal (SRST)
  1923. are the default @option{srst_open_drain}, and @option{srst_push_pull}.
  1924. Most boards connect this signal to a pullup, and allow the
  1925. signal to be pulled low by various events including system
  1926. powerup and pressing a reset button.
  1927. @end itemize
  1928. @end deffn
  1929. @section Custom Reset Handling
  1930. @cindex events
  1931. OpenOCD has several ways to help support the various reset
  1932. mechanisms provided by chip and board vendors.
  1933. The commands shown in the previous section give standard parameters.
  1934. There are also @emph{event handlers} associated with TAPs or Targets.
  1935. Those handlers are Tcl procedures you can provide, which are invoked
  1936. at particular points in the reset sequence.
  1937. After configuring those mechanisms, you might still
  1938. find your board doesn't start up or reset correctly.
  1939. For example, maybe it needs a slightly different sequence
  1940. of SRST and/or TRST manipulations, because of quirks that
  1941. the @command{reset_config} mechanism doesn't address;
  1942. or asserting both might trigger a stronger reset, which
  1943. needs special attention.
  1944. Experiment with lower level operations, such as @command{jtag_reset}
  1945. and the @command{jtag arp_*} operations shown here,
  1946. to find a sequence of operations that works.
  1947. @xref{JTAG Commands}.
  1948. When you find a working sequence, it can be used to override
  1949. @command{jtag_init}, which fires during OpenOCD startup
  1950. (@pxref{Configuration Stage});
  1951. or @command{init_reset}, which fires during reset processing.
  1952. You might also want to provide some project-specific reset
  1953. schemes. For example, on a multi-target board the standard
  1954. @command{reset} command would reset all targets, but you
  1955. may need the ability to reset only one target at time and
  1956. thus want to avoid using the board-wide SRST signal.
  1957. @deffn {Overridable Procedure} init_reset mode
  1958. This is invoked near the beginning of the @command{reset} command,
  1959. usually to provide as much of a cold (power-up) reset as practical.
  1960. By default it is also invoked from @command{jtag_init} if
  1961. the scan chain does not respond to pure JTAG operations.
  1962. The @var{mode} parameter is the parameter given to the
  1963. low level reset command (@option{halt},
  1964. @option{init}, or @option{run}), @option{setup},
  1965. or potentially some other value.
  1966. The default implementation just invokes @command{jtag arp_init-reset}.
  1967. Replacements will normally build on low level JTAG
  1968. operations such as @command{jtag_reset}.
  1969. Operations here must not address individual TAPs
  1970. (or their associated targets)
  1971. until the JTAG scan chain has first been verified to work.
  1972. Implementations must have verified the JTAG scan chain before
  1973. they return.
  1974. This is done by calling @command{jtag arp_init}
  1975. (or @command{jtag arp_init-reset}).
  1976. @end deffn
  1977. @deffn Command {jtag arp_init}
  1978. This validates the scan chain using just the four
  1979. standard JTAG signals (TMS, TCK, TDI, TDO).
  1980. It starts by issuing a JTAG-only reset.
  1981. Then it performs checks to verify that the scan chain configuration
  1982. matches the TAPs it can observe.
  1983. Those checks include checking IDCODE values for each active TAP,
  1984. and verifying the length of their instruction registers using
  1985. TAP @code{-ircapture} and @code{-irmask} values.
  1986. If these tests all pass, TAP @code{setup} events are
  1987. issued to all TAPs with handlers for that event.
  1988. @end deffn
  1989. @deffn Command {jtag arp_init-reset}
  1990. This uses TRST and SRST to try resetting
  1991. everything on the JTAG scan chain
  1992. (and anything else connected to SRST).
  1993. It then invokes the logic of @command{jtag arp_init}.
  1994. @end deffn
  1995. @node TAP Declaration
  1996. @chapter TAP Declaration
  1997. @cindex TAP declaration
  1998. @cindex TAP configuration
  1999. @emph{Test Access Ports} (TAPs) are the core of JTAG.
  2000. TAPs serve many roles, including:
  2001. @itemize @bullet
  2002. @item @b{Debug Target} A CPU TAP can be used as a GDB debug target
  2003. @item @b{Flash Programing} Some chips program the flash directly via JTAG.
  2004. Others do it indirectly, making a CPU do it.
  2005. @item @b{Program Download} Using the same CPU support GDB uses,
  2006. you can initialize a DRAM controller, download code to DRAM, and then
  2007. start running that code.
  2008. @item @b{Boundary Scan} Most chips support boundary scan, which
  2009. helps test for board assembly problems like solder bridges
  2010. and missing connections
  2011. @end itemize
  2012. OpenOCD must know about the active TAPs on your board(s).
  2013. Setting up the TAPs is the core task of your configuration files.
  2014. Once those TAPs are set up, you can pass their names to code
  2015. which sets up CPUs and exports them as GDB targets,
  2016. probes flash memory, performs low-level JTAG operations, and more.
  2017. @section Scan Chains
  2018. @cindex scan chain
  2019. TAPs are part of a hardware @dfn{scan chain},
  2020. which is daisy chain of TAPs.
  2021. They also need to be added to
  2022. OpenOCD's software mirror of that hardware list,
  2023. giving each member a name and associating other data with it.
  2024. Simple scan chains, with a single TAP, are common in
  2025. systems with a single microcontroller or microprocessor.
  2026. More complex chips may have several TAPs internally.
  2027. Very complex scan chains might have a dozen or more TAPs:
  2028. several in one chip, more in the next, and connecting
  2029. to other boards with their own chips and TAPs.
  2030. You can display the list with the @command{scan_chain} command.
  2031. (Don't confuse this with the list displayed by the @command{targets}
  2032. command, presented in the next chapter.
  2033. That only displays TAPs for CPUs which are configured as
  2034. debugging targets.)
  2035. Here's what the scan chain might look like for a chip more than one TAP:
  2036. @verbatim
  2037. TapName Enabled IdCode Expected IrLen IrCap IrMask Instr
  2038. -- ------------------ ------- ---------- ---------- ----- ----- ------ -----
  2039. 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0 0 0x...
  2040. 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x1 0 0xc
  2041. 2 omap5912.unknown Y 0x00000000 0x00000000 8 0 0 0xff
  2042. @end verbatim
  2043. Unfortunately those TAPs can't always be autoconfigured,
  2044. because not all devices provide good support for that.
  2045. JTAG doesn't require supporting IDCODE instructions, and
  2046. chips with JTAG routers may not link TAPs into the chain
  2047. until they are told to do so.
  2048. The configuration mechanism currently supported by OpenOCD
  2049. requires explicit configuration of all TAP devices using
  2050. @command{jtag newtap} commands, as detailed later in this chapter.
  2051. A command like this would declare one tap and name it @code{chip1.cpu}:
  2052. @example
  2053. jtag newtap chip1 cpu -irlen 7 -ircapture 0x01 -irmask 0x55
  2054. @end example
  2055. Each target configuration file lists the TAPs provided
  2056. by a given chip.
  2057. Board configuration files combine all the targets on a board,
  2058. and so forth.
  2059. Note that @emph{the order in which TAPs are declared is very important.}
  2060. It must match the order in the JTAG scan chain, both inside
  2061. a single chip and between them.
  2062. @xref{FAQ TAP Order}.
  2063. For example, the ST Microsystems STR912 chip has
  2064. three separate TAPs@footnote{See the ST
  2065. document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
  2066. 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
  2067. @url{}}.
  2068. To configure those taps, @file{target/str912.cfg}
  2069. includes commands something like this:
  2070. @example
  2071. jtag newtap str912 flash ... params ...
  2072. jtag newtap str912 cpu ... params ...
  2073. jtag newtap str912 bs ... params ...
  2074. @end example
  2075. Actual config files use a variable instead of literals like
  2076. @option{str912}, to support more than one chip of each type.
  2077. @xref{Config File Guidelines}.
  2078. @deffn Command {jtag names}
  2079. Returns the names of all current TAPs in the scan chain.
  2080. Use @command{jtag cget} or @command{jtag tapisenabled}
  2081. to examine attributes and state of each TAP.
  2082. @example
  2083. foreach t [jtag names] @{
  2084. puts [format "TAP: %s\n" $t]
  2085. @}
  2086. @end example
  2087. @end deffn
  2088. @deffn Command {scan_chain}
  2089. Displays the TAPs in the scan chain configuration,
  2090. and their status.
  2091. The set of TAPs listed by this command is fixed by
  2092. exiting the OpenOCD configuration stage,
  2093. but systems with a JTAG router can
  2094. enable or disable TAPs dynamically.
  2095. In addition to the enable/disable status, the contents of
  2096. each TAP's instruction register can also change.
  2097. @end deffn
  2098. @c FIXME! "jtag cget" should be able to return all TAP
  2099. @c attributes, like "$target_name cget" does for targets.
  2100. @c Probably want "jtag eventlist", and a "tap-reset" event
  2101. @c (on entry to RESET state).
  2102. @section TAP Names
  2103. @cindex dotted name
  2104. When TAP objects are declared with @command{jtag newtap},
  2105. a @dfn{} is created for the TAP, combining the
  2106. name of a module (usually a chip) and a label for the TAP.
  2107. For example: @code{xilinx.tap}, @code{str912.flash},
  2108. @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
  2109. Many other commands use that to manipulate or
  2110. refer to the TAP. For example, CPU configuration uses the
  2111. name, as does declaration of NAND or NOR flash banks.
  2112. The components of a dotted name should follow ``C'' symbol
  2113. name rules: start with an alphabetic character, then numbers
  2114. and underscores are OK; while others (including dots!) are not.
  2115. @quotation Tip
  2116. In older code, JTAG TAPs were numbered from 0..N.
  2117. This feature is still present.
  2118. However its use is highly discouraged, and
  2119. should not be relied on; it will be removed by mid-2010.
  2120. Update all of your scripts to use TAP names rather than numbers,
  2121. by paying attention to the runtime warnings they trigger.
  2122. Using TAP numbers in target configuration scripts prevents
  2123. reusing those scripts on boards with multiple targets.
  2124. @end quotation
  2125. @section TAP Declaration Commands
  2126. @c shouldn't this be(come) a {Config Command}?
  2127. @anchor{jtag newtap}
  2128. @deffn Command {jtag newtap} chipname tapname configparams...
  2129. Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
  2130. and configured according to the various @var{configparams}.
  2131. The @var{chipname} is a symbolic name for the chip.
  2132. Conventionally target config files use @code{$_CHIPNAME},
  2133. defaulting to the model name given by the chip vendor but
  2134. overridable.
  2135. @cindex TAP naming convention
  2136. The @var{tapname} reflects the role of that TAP,
  2137. and should follow this convention:
  2138. @itemize @bullet
  2139. @item @code{bs} -- For boundary scan if this is a seperate TAP;
  2140. @item @code{cpu} -- The main CPU of the chip, alternatively
  2141. @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
  2142. @code{arm1} and @code{arm2} on chips two ARMs, and so forth;
  2143. @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
  2144. @item @code{flash} -- If the chip has a flash TAP, like the str912;
  2145. @item @code{jrc} -- For JTAG route controller (example: the ICEpick modules
  2146. on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
  2147. @item @code{tap} -- Should be used only FPGA or CPLD like devices
  2148. with a single TAP;
  2149. @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
  2150. @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
  2151. For example, the Freescale IMX31 has a SDMA (Smart DMA) with
  2152. a JTAG TAP; that TAP should be named @code{sdma}.
  2153. @end itemize
  2154. Every TAP requires at least the following @var{configparams}:
  2155. @itemize @bullet
  2156. @item @code{-irlen} @var{NUMBER}
  2157. @*The length in bits of the
  2158. instruction register, such as 4 or 5 bits.
  2159. @end itemize
  2160. A TAP may also provide optional @var{configparams}:
  2161. @itemize @bullet
  2162. @item @code{-disable} (or @code{-enable})
  2163. @*Use the @code{-disable} parameter to flag a TAP which is not
  2164. linked in to the scan chain after a reset using either TRST
  2165. or the JTAG state machine's @sc{reset} state.
  2166. You may use @code{-enable} to highlight the default state
  2167. (the TAP is linked in).
  2168. @xref{Enabling and Disabling TAPs}.
  2169. @item @code{-expected-id} @var{number}
  2170. @*A non-zero @var{number} represents a 32-bit IDCODE
  2171. which you expect to find when the scan chain is examined.
  2172. These codes are not required by all JTAG devices.
  2173. @emph{Repeat the option} as many times as required if more than one
  2174. ID code could appear (for example, multiple versions).
  2175. Specify @var{number} as zero to suppress warnings about IDCODE
  2176. values that were found but not included in the list.
  2177. @item @code{-ircapture} @var{NUMBER}
  2178. @*The bit pattern loaded by the TAP into the JTAG shift register
  2179. on entry to the @sc{ircapture} state, such as 0x01.
  2180. JTAG requires the two LSBs of this value to be 01.
  2181. By default, @code{-ircapture} and @code{-irmask} are set
  2182. up to verify that two-bit value; but you may provide
  2183. additional bits, if you know them.
  2184. @item @code{-irmask} @var{NUMBER}
  2185. @*A mask used with @code{-ircapture}
  2186. to verify that instruction scans work correctly.
  2187. Such scans are not used by OpenOCD except to verify that
  2188. there seems to be no problems with JTAG scan chain operations.
  2189. @end itemize
  2190. @end deffn
  2191. @section Other TAP commands
  2192. @deffn Command {jtag cget} @option{-event} name
  2193. @deffnx Command {jtag configure} @option{-event} name string
  2194. At this writing this TAP attribute
  2195. mechanism is used only for event handling.
  2196. (It is not a direct analogue of the @code{cget}/@code{configure}
  2197. mechanism for debugger targets.)
  2198. See the next section for information about the available events.
  2199. The @code{configure} subcommand assigns an event handler,
  2200. a TCL string which is evaluated when the event is triggered.
  2201. The @code{cget} subcommand returns that handler.
  2202. @end deffn
  2203. @anchor{TAP Events}
  2204. @section TAP Events
  2205. @cindex events
  2206. @cindex TAP events
  2207. OpenOCD includes two event mechanisms.
  2208. The one presented here applies to all JTAG TAPs.
  2209. The other applies to debugger targets,
  2210. which are associated with certain TAPs.
  2211. The TAP events currently defined are:
  2212. @itemize @bullet
  2213. @item @b{post-reset}
  2214. @* The TAP has just completed a JTAG reset.
  2215. The tap may still be in the JTAG @sc{reset} state.
  2216. Handlers for these events might perform initialization sequences
  2217. such as issuing TCK cycles, TMS sequences to ensure
  2218. exit from the ARM SWD mode, and more.
  2219. Because the scan chain has not yet been verified, handlers for these events
  2220. @emph{should not issue commands which scan the JTAG IR or DR registers}
  2221. of any particular target.
  2222. @b{NOTE:} As this is written (September 2009), nothing prevents such access.
  2223. @item @b{setup}
  2224. @* The scan chain has been reset and verified.
  2225. This handler may enable TAPs as needed.
  2226. @item @b{tap-disable}
  2227. @* The TAP needs to be disabled. This handler should
  2228. implement @command{jtag tapdisable}
  2229. by issuing the relevant JTAG commands.
  2230. @item @b{tap-enable}
  2231. @* The TAP needs to be enabled. This handler should
  2232. implement @command{jtag tapenable}
  2233. by issuing the relevant JTAG commands.
  2234. @end itemize
  2235. If you need some action after each JTAG reset, which isn't actually
  2236. specific to any TAP (since you can't yet trust the scan chain's
  2237. contents to be accurate), you might:
  2238. @example
  2239. jtag configure CHIP.jrc -event post-reset @{
  2240. echo "JTAG Reset done"
  2241. ... non-scan jtag operations to be done after reset
  2242. @}
  2243. @end example
  2244. @anchor{Enabling and Disabling TAPs}
  2245. @section Enabling and Disabling TAPs
  2246. @cindex JTAG Route Controller
  2247. @cindex jrc
  2248. In some systems, a @dfn{JTAG Route Controller} (JRC)
  2249. is used to enable and/or disable specific JTAG TAPs.
  2250. Many ARM based chips from Texas Instruments include
  2251. an ``ICEpick'' module, which is a JRC.
  2252. Such chips include DaVinci and OMAP3 processors.
  2253. A given TAP may not be visible until the JRC has been
  2254. told to link it into the scan chain; and if the JRC
  2255. has been told to unlink that TAP, it will no longer
  2256. be visible.
  2257. Such routers address problems that JTAG ``bypass mode''
  2258. ignores, such as:
  2259. @itemize
  2260. @item The scan chain can only go as fast as its slowest TAP.
  2261. @item Having many TAPs slows instruction scans, since all
  2262. TAPs receive new instructions.
  2263. @item TAPs in the scan chain must be powered up, which wastes
  2264. power and prevents debugging some power management mechanisms.
  2265. @end itemize
  2266. The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
  2267. as implied by the existence of JTAG routers.
  2268. However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
  2269. does include a kind of JTAG router functionality.
  2270. @c (a) currently the event handlers don't seem to be able to
  2271. @c fail in a way that could lead to no-change-of-state.
  2272. In OpenOCD, tap enabling/disabling is invoked by the Tcl commands
  2273. shown below, and is implemented using TAP event handlers.
  2274. So for example, when defining a TAP for a CPU connected to
  2275. a JTAG router, your @file{target.cfg} file
  2276. should define TAP event handlers using
  2277. code that looks something like this:
  2278. @example
  2279. jtag configure CHIP.cpu -event tap-enable @{
  2280. ... jtag operations using CHIP.jrc
  2281. @}
  2282. jtag configure CHIP.cpu -event tap-disable @{
  2283. ... jtag operations using CHIP.jrc
  2284. @}
  2285. @end example
  2286. Then you might want that CPU's TAP enabled almost all the time:
  2287. @example
  2288. jtag configure $CHIP.jrc -event setup "jtag tapenable $CHIP.cpu"
  2289. @end example
  2290. Note how that particular setup event handler declaration
  2291. uses quotes to evaluate @code{$CHIP} when the event is configured.
  2292. Using brackets @{ @} would cause it to be evaluated later,
  2293. at runtime, when it might have a different value.
  2294. @deffn Command {jtag tapdisable}
  2295. If necessary, disables the tap
  2296. by sending it a @option{tap-disable} event.
  2297. Returns the string "1" if the tap
  2298. specified by @var{} is enabled,
  2299. and "0" if it is disabled.
  2300. @end deffn
  2301. @deffn Command {jtag tapenable}
  2302. If necessary, enables the tap
  2303. by sending it a @option{tap-enable} event.
  2304. Returns the string "1" if the tap
  2305. specified by @var{} is enabled,
  2306. and "0" if it is disabled.
  2307. @end deffn
  2308. @deffn Command {jtag tapisenabled}
  2309. Returns the string "1" if the tap
  2310. specified by @var{} is enabled,
  2311. and "0" if it is disabled.
  2312. @quotation Note
  2313. Humans will find the @command{scan_chain} command more helpful
  2314. for querying the state of the JTAG taps.
  2315. @end quotation
  2316. @end deffn
  2317. @node CPU Configuration
  2318. @chapter CPU Configuration
  2319. @cindex GDB target
  2320. This chapter discusses how to set up GDB debug targets for CPUs.
  2321. You can also access these targets without GDB
  2322. (@pxref{Architecture and Core Commands},
  2323. and @ref{Target State handling}) and
  2324. through various kinds of NAND and NOR flash commands.
  2325. If you have multiple CPUs you can have multiple such targets.
  2326. We'll start by looking at how to examine the targets you have,
  2327. then look at how to add one more target and how to configure it.
  2328. @section Target List
  2329. @cindex target, current
  2330. @cindex target, list
  2331. All targets that have been set up are part of a list,
  2332. where each member has a name.
  2333. That name should normally be the same as the TAP name.
  2334. You can display the list with the @command{targets}
  2335. (plural!) command.
  2336. This display often has only one CPU; here's what it might
  2337. look like with more than one:
  2338. @verbatim
  2339. TargetName Type Endian TapName State
  2340. -- ------------------ ---------- ------ ------------------ ------------
  2341. 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
  2342. 1 MyTarget cortex_m3 little tap-disabled
  2343. @end verbatim
  2344. One member of that list is the @dfn{current target}, which
  2345. is implicitly referenced by many commands.
  2346. It's the one marked with a @code{*} near the target name.
  2347. In particular, memory addresses often refer to the address
  2348. space seen by that current target.
  2349. Commands like @command{mdw} (memory display words)
  2350. and @command{flash erase_address} (erase NOR flash blocks)
  2351. are examples; and there are many more.
  2352. Several commands let you examine the list of targets:
  2353. @deffn Command {target count}
  2354. @emph{Note: target numbers are deprecated; don't use them.
  2355. They will be removed shortly after August 2010, including this command.
  2356. Iterate target using @command{target names}, not by counting.}
  2357. Returns the number of targets, @math{N}.
  2358. The highest numbered target is @math{N - 1}.
  2359. @example
  2360. set c [target count]
  2361. for @{ set x 0 @} @{ $x < $c @} @{ incr x @} @{
  2362. # Assuming you have created this function
  2363. print_target_details $x
  2364. @}
  2365. @end example
  2366. @end deffn
  2367. @deffn Command {target current}
  2368. Returns the name of the current target.
  2369. @end deffn
  2370. @deffn Command {target names}
  2371. Lists the names of all current targets in the list.
  2372. @example
  2373. foreach t [target names] @{
  2374. puts [format "Target: %s\n" $t]
  2375. @}
  2376. @end example
  2377. @end deffn
  2378. @deffn Command {target number} number
  2379. @emph{Note: target numbers are deprecated; don't use them.
  2380. They will be removed shortly after August 2010, including this command.}
  2381. The list of targets is numbered starting at zero.
  2382. This command returns the name of the target at index @var{number}.
  2383. @example
  2384. set thename [target number $x]
  2385. puts [format "Target %d is: %s\n" $x $thename]
  2386. @end example
  2387. @end deffn
  2388. @c yep, "target list" would have been better.
  2389. @c plus maybe "target setdefault".
  2390. @deffn Command targets [name]
  2391. @emph{Note: the name of this command is plural. Other target
  2392. command names are singular.}
  2393. With no parameter, this command displays a table of all known
  2394. targets in a user friendly form.
  2395. With a parameter, this command sets the current target to
  2396. the given target with the given @var{name}; this is
  2397. only relevant on boards which have more than one target.
  2398. @end deffn
  2399. @section Target CPU Types and Variants
  2400. @cindex target type
  2401. @cindex CPU type
  2402. @cindex CPU variant
  2403. Each target has a @dfn{CPU type}, as shown in the output of
  2404. the @command{targets} command. You need to specify that type
  2405. when calling @command{target create}.
  2406. The CPU type indicates more than just the instruction set.
  2407. It also indicates how that instruction set is implemented,
  2408. what kind of debug support it integrates,
  2409. whether it has an MMU (and if so, what kind),
  2410. what core-specific commands may be available
  2411. (@pxref{Architecture and Core Commands}),
  2412. and more.
  2413. For some CPU types, OpenOCD also defines @dfn{variants} which
  2414. indicate differences that affect their handling.
  2415. For example, a particular implementation bug might need to be
  2416. worked around in some chip versions.
  2417. It's easy to see what target types are supported,
  2418. since there's a command to list them.
  2419. However, there is currently no way to list what target variants
  2420. are supported (other than by reading the OpenOCD source code).
  2421. @anchor{target types}
  2422. @deffn Command {target types}
  2423. Lists all supported target types.
  2424. At this writing, the supported CPU types and variants are:
  2425. @itemize @bullet
  2426. @item @code{arm11} -- this is a generation of ARMv6 cores
  2427. @item @code{arm720t} -- this is an ARMv4 core
  2428. @item @code{arm7tdmi} -- this is an ARMv4 core
  2429. @item @code{arm920t} -- this is an ARMv5 core
  2430. @item @code{arm926ejs} -- this is an ARMv5 core
  2431. @item @code{arm966e} -- this is an ARMv5 core
  2432. @item @code{arm9tdmi} -- this is an ARMv4 core
  2433. @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
  2434. (Support for this is preliminary and incomplete.)
  2435. @item @code{cortex_a8} -- this is an ARMv7 core
  2436. @item @code{cortex_m3} -- this is an ARMv7 core, supporting only the
  2437. compact Thumb2 instruction set. It supports one variant:
  2438. @itemize @minus
  2439. @item @code{lm3s} ... Use this when debugging older Stellaris LM3S targets.
  2440. This will cause OpenOCD to use a software reset rather than asserting
  2441. SRST, to avoid a issue with clearing the debug registers.
  2442. This is fixed in Fury Rev B, DustDevil Rev B, Tempest; these revisions will
  2443. be detected and the normal reset behaviour used.
  2444. @end itemize
  2445. @item @code{fa526} -- resembles arm920 (w/o Thumb)
  2446. @item @code{feroceon} -- resembles arm926
  2447. @item @code{mips_m4k} -- a MIPS core. This supports one variant:
  2448. @itemize @minus
  2449. @item @code{ejtag_srst} ... Use this when debugging targets that do not
  2450. provide a functional SRST line on the EJTAG connector. This causes
  2451. OpenOCD to instead use an EJTAG software reset command to reset the
  2452. processor.
  2453. You still need to enable @option{srst} on the @command{reset_config}
  2454. command to enable OpenOCD hardware reset functionality.
  2455. @end itemize
  2456. @item @code{xscale} -- this is actually an architecture,
  2457. not a CPU type. It is based on the ARMv5 architecture.
  2458. There are several variants defined:
  2459. @itemize @minus
  2460. @item @code{ixp42x}, @code{ixp45x}, @code{ixp46x},
  2461. @code{pxa27x} ... instruction register length is 7 bits
  2462. @item @code{pxa250}, @code{pxa255},
  2463. @code{pxa26x} ... instruction register length is 5 bits
  2464. @end itemize
  2465. @end itemize
  2466. @end deffn
  2467. To avoid being confused by the variety of ARM based cores, remember
  2468. this key point: @emph{ARM is a technology licencing company}.
  2469. (See: @url{}.)
  2470. The CPU name used by OpenOCD will reflect the CPU design that was
  2471. licenced, not a vendor brand which incorporates that design.
  2472. Name prefixes like arm7, arm9, arm11, and cortex
  2473. reflect design generations;
  2474. while names like ARMv4, ARMv5, ARMv6, and ARMv7
  2475. reflect an architecture version implemented by a CPU design.
  2476. @anchor{Target Configuration}
  2477. @section Target Configuration
  2478. Before creating a ``target'', you must have added its TAP to the scan chain.
  2479. When you've added that TAP, you will have a @code{}
  2480. which is used to set up the CPU support.
  2481. The chip-specific configuration file will normally configure its CPU(s)
  2482. right after it adds all of the chip's TAPs to the scan chain.
  2483. Although you can set up a target in one step, it's often clearer if you
  2484. use shorter commands and do it in two steps: create it, then configure
  2485. optional parts.
  2486. All operations on the target after it's created will use a new
  2487. command, created as part of target creation.
  2488. The two main things to configure after target creation are
  2489. a work area, which usually has target-specific defaults even
  2490. if the board setup code overrides them later;
  2491. and event handlers (@pxref{Target Events}), which tend
  2492. to be much more board-specific.
  2493. The key steps you use might look something like this
  2494. @example
  2495. target create MyTarget cortex_m3 -chain-position mychip.cpu
  2496. $MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
  2497. $MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
  2498. $MyTarget configure -event reset-init @{ myboard_reinit @}
  2499. @end example
  2500. You should specify a working area if you can; typically it uses some
  2501. on-chip SRAM.
  2502. Such a working area can speed up many things, including bulk
  2503. writes to target memory;
  2504. flash operations like checking to see if memory needs to be erased;
  2505. GDB memory checksumming;
  2506. and more.
  2507. @quotation Warning
  2508. On more complex chips, the work area can become
  2509. inaccessible when application code
  2510. (such as an operating system)
  2511. enables or disables the MMU.
  2512. For example, the particular MMU context used to acess the virtual
  2513. address will probably matter ... and that context might not have
  2514. easy access to other addresses needed.
  2515. At this writing, OpenOCD doesn't have much MMU intelligence.
  2516. @end quotation
  2517. It's often very useful to define a @code{reset-init} event handler.
  2518. For systems that are normally used with a boot loader,
  2519. common tasks include updating clocks and initializing memory
  2520. controllers.
  2521. That may be needed to let you write the boot loader into flash,
  2522. in order to ``de-brick'' your board; or to load programs into
  2523. external DDR memory without having run the boot loader.
  2524. @deffn Command {target create} target_name type configparams...
  2525. This command creates a GDB debug target that refers to a specific JTAG tap.
  2526. It enters that target into a list, and creates a new
  2527. command (@command{@var{target_name}}) which is used for various
  2528. purposes including additional configuration.
  2529. @itemize @bullet
  2530. @item @var{target_name} ... is the name of the debug target.
  2531. By convention this should be the same as the @emph{}
  2532. of the TAP associated with this target, which must be specified here
  2533. using the @code{-chain-position @var{}} configparam.
  2534. This name is also used to create the target object command,
  2535. referred to here as @command{$target_name},
  2536. and in other places the target needs to be identified.
  2537. @item @var{type} ... specifies the target type. @xref{target types}.
  2538. @item @var{configparams} ... all parameters accepted by
  2539. @command{$target_name configure} are permitted.
  2540. If the target is big-endian, set it here with @code{-endian big}.
  2541. If the variant matters, set it here with @code{-variant}.
  2542. You @emph{must} set the @code{-chain-position @var{}} here.
  2543. @end itemize
  2544. @end deffn
  2545. @deffn Command {$target_name configure} configparams...
  2546. The options accepted by this command may also be
  2547. specified as parameters to @command{target create}.
  2548. Their values can later be queried one at a time by
  2549. using the @command{$target_name cget} command.
  2550. @emph{Warning:} changing some of these after setup is dangerous.
  2551. For example, moving a target from one TAP to another;
  2552. and changing its endianness or variant.
  2553. @itemize @bullet
  2554. @item @code{-chain-position} @var{} -- names the TAP
  2555. used to access this target.
  2556. @item @code{-endian} (@option{big}|@option{little}) -- specifies
  2557. whether the CPU uses big or little endian conventions
  2558. @item @code{-event} @var{event_name} @var{event_body} --
  2559. @xref{Target Events}.
  2560. Note that this updates a list of named event handlers.
  2561. Calling this twice with two different event names assigns
  2562. two different handlers, but calling it twice with the
  2563. same event name assigns only one handler.
  2564. @item @code{-variant} @var{name} -- specifies a variant of the target,
  2565. which OpenOCD needs to know about.
  2566. @item @code{-work-area-backup} (@option{0}|@option{1}) -- says
  2567. whether the work area gets backed up; by default,
  2568. @emph{it is not backed up.}
  2569. When possible, use a working_area that doesn't need to be backed up,
  2570. since performing a backup slows down operations.
  2571. For example, the beginning of an SRAM block is likely to
  2572. be used by most build systems, but the end is often unused.
  2573. @item @code{-work-area-size} @var{size} -- specify/set the work area
  2574. @item @code{-work-area-phys} @var{address} -- set the work area
  2575. base @var{address} to be used when no MMU is active.
  2576. @item @code{-work-area-virt} @var{address} -- set the work area
  2577. base @var{address} to be used when an MMU is active.
  2578. @end itemize
  2579. @end deffn
  2580. @section Other $target_name Commands
  2581. @cindex object command
  2582. The Tcl/Tk language has the concept of object commands,
  2583. and OpenOCD adopts that same model for targets.
  2584. A good Tk example is a on screen button.
  2585. Once a button is created a button
  2586. has a name (a path in Tk terms) and that name is useable as a first
  2587. class command. For example in Tk, one can create a button and later
  2588. configure it like this:
  2589. @example
  2590. # Create
  2591. button .foobar -background red -command @{ foo @}
  2592. # Modify
  2593. .foobar configure -foreground blue
  2594. # Query
  2595. set x [.foobar cget -background]
  2596. # Report
  2597. puts [format "The button is %s" $x]
  2598. @end example
  2599. In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
  2600. button, and its object commands are invoked the same way.
  2601. @example
  2602. str912.cpu mww 0x1234 0x42
  2603. omap3530.cpu mww 0x5555 123
  2604. @end example
  2605. The commands supported by OpenOCD target objects are:
  2606. @deffn Command {$target_name arp_examine}
  2607. @deffnx Command {$target_name arp_halt}
  2608. @deffnx Command {$target_name arp_poll}
  2609. @deffnx Command {$target_name arp_reset}
  2610. @deffnx Command {$target_name arp_waitstate}
  2611. Internal OpenOCD scripts (most notably @file{startup.tcl})
  2612. use these to deal with specific reset cases.
  2613. They are not otherwise documented here.
  2614. @end deffn
  2615. @deffn Command {$target_name array2mem} arrayname width address count
  2616. @deffnx Command {$target_name mem2array} arrayname width address count
  2617. These provide an efficient script-oriented interface to memory.
  2618. The @code{array2mem} primitive writes bytes, halfwords, or words;
  2619. while @code{mem2array} reads them.
  2620. In both cases, the TCL side uses an array, and
  2621. the target side uses raw memory.
  2622. The efficiency comes from enabling the use of
  2623. bulk JTAG data transfer operations.
  2624. The script orientation comes from working with data
  2625. values that are packaged for use by TCL scripts;
  2626. @command{mdw} type primitives only print data they retrieve,
  2627. and neither store nor return those values.
  2628. @itemize
  2629. @item @var{arrayname} ... is the name of an array variable
  2630. @item @var{width} ... is 8/16/32 - indicating the memory access size
  2631. @item @var{address} ... is the target memory address
  2632. @item @var{count} ... is the number of elements to process
  2633. @end itemize
  2634. @end deffn
  2635. @deffn Command {$target_name cget} queryparm
  2636. Each configuration parameter accepted by
  2637. @command{$target_name configure}
  2638. can be individually queried, to return its current value.
  2639. The @var{queryparm} is a parameter name
  2640. accepted by that command, such as @code{-work-area-phys}.
  2641. There are a few special cases:
  2642. @itemize @bullet
  2643. @item @code{-event} @var{event_name} -- returns the handler for the
  2644. event named @var{event_name}.
  2645. This is a special case because setting a handler requires
  2646. two parameters.
  2647. @item @code{-type} -- returns the target type.
  2648. This is a special case because this is set using
  2649. @command{target create} and can't be changed
  2650. using @command{$target_name configure}.
  2651. @end itemize
  2652. For example, if you wanted to summarize information about
  2653. all the targets you might use something like this:
  2654. @example
  2655. foreach name [target names] @{
  2656. set y [$name cget -endian]
  2657. set z [$name cget -type]
  2658. puts [format "Chip %d is %s, Endian: %s, type: %s" \
  2659. $x $name $y $z]
  2660. @}
  2661. @end example
  2662. @end deffn
  2663. @anchor{target curstate}
  2664. @deffn Command {$target_name curstate}
  2665. Displays the current target state:
  2666. @code{debug-running},
  2667. @code{halted},
  2668. @code{reset},
  2669. @code{running}, or @code{unknown}.
  2670. (Also, @pxref{Event Polling}.)
  2671. @end deffn
  2672. @deffn Command {$target_name eventlist}
  2673. Displays a table listing all event handlers
  2674. currently associated with this target.
  2675. @xref{Target Events}.
  2676. @end deffn
  2677. @deffn Command {$target_name invoke-event} event_name
  2678. Invokes the handler for the event named @var{event_name}.
  2679. (This is primarily intended for use by OpenOCD framework
  2680. code, for example by the reset code in @file{startup.tcl}.)
  2681. @end deffn
  2682. @deffn Command {$target_name mdw} addr [count]
  2683. @deffnx Command {$target_name mdh} addr [count]
  2684. @deffnx Command {$target_name mdb} addr [count]
  2685. Display contents of address @var{addr}, as
  2686. 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
  2687. or 8-bit bytes (@command{mdb}).
  2688. If @var{count} is specified, displays that many units.
  2689. (If you want to manipulate the data instead of displaying it,
  2690. see the @code{mem2array} primitives.)
  2691. @end deffn
  2692. @deffn Command {$target_name mww} addr word
  2693. @deffnx Command {$target_name mwh} addr halfword
  2694. @deffnx Command {$target_name mwb} addr byte
  2695. Writes the specified @var{word} (32 bits),
  2696. @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
  2697. at the specified address @var{addr}.
  2698. @end deffn
  2699. @anchor{Target Events}
  2700. @section Target Events
  2701. @cindex target events
  2702. @cindex events
  2703. At various times, certain things can happen, or you want them to happen.
  2704. For example:
  2705. @itemize @bullet
  2706. @item What should happen when GDB connects? Should your target reset?
  2707. @item When GDB tries to flash the target, do you need to enable the flash via a special command?
  2708. @item During reset, do you need to write to certain memory locations
  2709. to set up system clocks or
  2710. to reconfigure the SDRAM?
  2711. @end itemize
  2712. All of the above items can be addressed by target event handlers.
  2713. These are set up by @command{$target_name configure -event} or
  2714. @command{target create ... -event}.
  2715. The programmer's model matches the @code{-command} option used in Tcl/Tk
  2716. buttons and events. The two examples below act the same, but one creates
  2717. and invokes a small procedure while the other inlines it.
  2718. @example
  2719. proc my_attach_proc @{ @} @{
  2720. echo "Reset..."
  2721. reset halt
  2722. @}
  2723. mychip.cpu configure -event gdb-attach my_attach_proc
  2724. mychip.cpu configure -event gdb-attach @{
  2725. echo "Reset..."
  2726. reset halt
  2727. @}
  2728. @end example
  2729. The following target events are defined:
  2730. @itemize @bullet
  2731. @item @b{debug-halted}
  2732. @* The target has halted for debug reasons (i.e.: breakpoint)
  2733. @item @b{debug-resumed}
  2734. @* The target has resumed (i.e.: gdb said run)
  2735. @item @b{early-halted}
  2736. @* Occurs early in the halt process
  2737. @ignore
  2738. @item @b{examine-end}
  2739. @* Currently not used (goal: when JTAG examine completes)
  2740. @item @b{examine-start}
  2741. @* Currently not used (goal: when JTAG examine starts)
  2742. @end ignore
  2743. @item @b{gdb-attach}
  2744. @* When GDB connects
  2745. @item @b{gdb-detach}
  2746. @* When GDB disconnects
  2747. @item @b{gdb-end}
  2748. @* When the target has halted and GDB is not doing anything (see early halt)
  2749. @item @b{gdb-flash-erase-start}
  2750. @* Before the GDB flash process tries to erase the flash
  2751. @item @b{gdb-flash-erase-end}
  2752. @* After the GDB flash process has finished erasing the flash
  2753. @item @b{gdb-flash-write-start}
  2754. @* Before GDB writes to the flash
  2755. @item @b{gdb-flash-write-end}
  2756. @* After GDB writes to the flash
  2757. @item @b{gdb-start}
  2758. @* Before the target steps, gdb is trying to start/resume the target
  2759. @item @b{halted}
  2760. @* The target has halted
  2761. @ignore
  2762. @item @b{old-gdb_program_config}
  2763. @* DO NOT USE THIS: Used internally
  2764. @item @b{old-pre_resume}
  2765. @* DO NOT USE THIS: Used internally
  2766. @end ignore
  2767. @item @b{reset-assert-pre}
  2768. @* Issued as part of @command{reset} processing
  2769. after @command{reset_init} was triggered
  2770. but before SRST alone is re-asserted on the tap.
  2771. @item @b{reset-assert-post}
  2772. @* Issued as part of @command{reset} processing
  2773. when SRST is asserted on the tap.
  2774. @item @b{reset-deassert-pre}
  2775. @* Issued as part of @command{reset} processing
  2776. when SRST is about to be released on the tap.
  2777. @item @b{reset-deassert-post}
  2778. @* Issued as part of @command{reset} processing
  2779. when SRST has been released on the tap.
  2780. @item @b{reset-end}
  2781. @* Issued as the final step in @command{reset} processing.
  2782. @ignore
  2783. @item @b{reset-halt-post}
  2784. @* Currently not used
  2785. @item @b{reset-halt-pre}
  2786. @* Currently not used
  2787. @end ignore
  2788. @item @b{reset-init}
  2789. @* Used by @b{reset init} command for board-specific initialization.
  2790. This event fires after @emph{reset-deassert-post}.
  2791. This is where you would configure PLLs and clocking, set up DRAM so
  2792. you can download programs that don't fit in on-chip SRAM, set up pin
  2793. multiplexing, and so on.
  2794. (You may be able to switch to a fast JTAG clock rate here, after
  2795. the target clocks are fully set up.)
  2796. @item @b{reset-start}
  2797. @* Issued as part of @command{reset} processing
  2798. before @command{reset_init} is called.
  2799. This is the most robust place to use @command{jtag_rclk}
  2800. or @command{jtag_khz} to switch to a low JTAG clock rate,
  2801. when reset disables PLLs needed to use a fast clock.
  2802. @ignore
  2803. @item @b{reset-wait-pos}
  2804. @* Currently not used
  2805. @item @b{reset-wait-pre}
  2806. @* Currently not used
  2807. @end ignore
  2808. @item @b{resume-start}
  2809. @* Before any target is resumed
  2810. @item @b{resume-end}
  2811. @* After all targets have resumed
  2812. @item @b{resume-ok}
  2813. @* Success
  2814. @item @b{resumed}
  2815. @* Target has resumed
  2816. @end itemize
  2817. @node Flash Commands
  2818. @chapter Flash Commands
  2819. OpenOCD has different commands for NOR and NAND flash;
  2820. the ``flash'' command works with NOR flash, while
  2821. the ``nand'' command works with NAND flash.
  2822. This partially reflects different hardware technologies:
  2823. NOR flash usually supports direct CPU instruction and data bus access,
  2824. while data from a NAND flash must be copied to memory before it can be
  2825. used. (SPI flash must also be copied to memory before use.)
  2826. However, the documentation also uses ``flash'' as a generic term;
  2827. for example, ``Put flash configuration in board-specific files''.
  2828. Flash Steps:
  2829. @enumerate
  2830. @item Configure via the command @command{flash bank}
  2831. @* Do this in a board-specific configuration file,
  2832. passing parameters as needed by the driver.
  2833. @item Operate on the flash via @command{flash subcommand}
  2834. @* Often commands to manipulate the flash are typed by a human, or run
  2835. via a script in some automated way. Common tasks include writing a
  2836. boot loader, operating system, or other data.
  2837. @item GDB Flashing
  2838. @* Flashing via GDB requires the flash be configured via ``flash
  2839. bank'', and the GDB flash features be enabled.
  2840. @xref{GDB Configuration}.
  2841. @end enumerate
  2842. Many CPUs have the ablity to ``boot'' from the first flash bank.
  2843. This means that misprogramming that bank can ``brick'' a system,
  2844. so that it can't boot.
  2845. JTAG tools, like OpenOCD, are often then used to ``de-brick'' the
  2846. board by (re)installing working boot firmware.
  2847. @anchor{NOR Configuration}
  2848. @section Flash Configuration Commands
  2849. @cindex flash configuration
  2850. @deffn {Config Command} {flash bank} driver base size chip_width bus_width target [driver_options]
  2851. Configures a flash bank which provides persistent storage
  2852. for addresses from @math{base} to @math{base + size - 1}.
  2853. These banks will often be visible to GDB through the target's memory map.
  2854. In some cases, configuring a flash bank will activate extra commands;
  2855. see the driver-specific documentation.
  2856. @itemize @bullet
  2857. @item @var{driver} ... identifies the controller driver
  2858. associated with the flash bank being declared.
  2859. This is usually @code{cfi} for external flash, or else
  2860. the name of a microcontroller with embedded flash memory.
  2861. @xref{Flash Driver List}.
  2862. @item @var{base} ... Base address of the flash chip.
  2863. @item @var{size} ... Size of the chip, in bytes.
  2864. For some drivers, this value is detected from the hardware.
  2865. @item @var{chip_width} ... Width of the flash chip, in bytes;
  2866. ignored for most microcontroller drivers.
  2867. @item @var{bus_width} ... Width of the data bus used to access the
  2868. chip, in bytes; ignored for most microcontroller drivers.
  2869. @item @var{target} ... Names the target used to issue
  2870. commands to the flash controller.
  2871. @comment Actually, it's currently a controller-specific parameter...
  2872. @item @var{driver_options} ... drivers may support, or require,
  2873. additional parameters. See the driver-specific documentation
  2874. for more information.
  2875. @end itemize
  2876. @quotation Note
  2877. This command is not available after OpenOCD initialization has completed.
  2878. Use it in board specific configuration files, not interactively.
  2879. @end quotation
  2880. @end deffn
  2881. @comment the REAL name for this command is "ocd_flash_banks"
  2882. @comment less confusing would be: "flash list" (like "nand list")
  2883. @deffn Command {flash banks}
  2884. Prints a one-line summary of each device declared
  2885. using @command{flash bank}, numbered from zero.
  2886. Note that this is the @emph{plural} form;
  2887. the @emph{singular} form is a very different command.
  2888. @end deffn
  2889. @deffn Command {flash probe} num
  2890. Identify the flash, or validate the parameters of the configured flash. Operation
  2891. depends on the flash type.
  2892. The @var{num} parameter is a value shown by @command{flash banks}.
  2893. Most flash commands will implicitly @emph{autoprobe} the bank;
  2894. flash drivers can distinguish between probing and autoprobing,
  2895. but most don't bother.
  2896. @end deffn
  2897. @section Erasing, Reading, Writing to Flash
  2898. @cindex flash erasing
  2899. @cindex flash reading
  2900. @cindex flash writing
  2901. @cindex flash programming
  2902. One feature distinguishing NOR flash from NAND or serial flash technologies
  2903. is that for read access, it acts exactly like any other addressible memory.
  2904. This means you can use normal memory read commands like @command{mdw} or
  2905. @command{dump_image} with it, with no special @command{flash} subcommands.
  2906. @xref{Memory access}, and @ref{Image access}.
  2907. Write access works differently. Flash memory normally needs to be erased
  2908. before it's written. Erasing a sector turns all of its bits to ones, and
  2909. writing can turn ones into zeroes. This is why there are special commands
  2910. for interactive erasing and writing, and why GDB needs to know which parts
  2911. of the address space hold NOR flash memory.
  2912. @quotation Note
  2913. Most of these erase and write commands leverage the fact that NOR flash
  2914. chips consume target address space. They implicitly refer to the current
  2915. JTAG target, and map from an address in that target's address space
  2916. back to a flash bank.
  2917. @comment In May 2009, those mappings may fail if any bank associated
  2918. @comment with that target doesn't succesfuly autoprobe ... bug worth fixing?
  2919. A few commands use abstract addressing based on bank and sector numbers,
  2920. and don't depend on searching the current target and its address space.
  2921. Avoid confusing the two command models.
  2922. @end quotation
  2923. Some flash chips implement software protection against accidental writes,
  2924. since such buggy writes could in some cases ``brick'' a system.
  2925. For such systems, erasing and writing may require sector protection to be
  2926. disabled first.
  2927. Examples include CFI flash such as ``Intel Advanced Bootblock flash'',
  2928. and AT91SAM7 on-chip flash.
  2929. @xref{flash protect}.
  2930. @anchor{flash erase_sector}
  2931. @deffn Command {flash erase_sector} num first last
  2932. Erase sectors in bank @var{num}, starting at sector @var{first}
  2933. up to and including @var{last}.
  2934. Sector numbering starts at 0.
  2935. Providing a @var{last} sector of @option{last}
  2936. specifies "to the end of the flash bank".
  2937. The @var{num} parameter is a value shown by @command{flash banks}.
  2938. @end deffn
  2939. @deffn Command {flash erase_address} address length
  2940. Erase sectors starting at @var{address} for @var{length} bytes.
  2941. The flash bank to use is inferred from the @var{address}, and
  2942. the specified length must stay within that bank.
  2943. As a special case, when @var{length} is zero and @var{address} is
  2944. the start of the bank, the whole flash is erased.
  2945. @end deffn
  2946. @deffn Command {flash fillw} address word length
  2947. @deffnx Command {flash fillh} address halfword length
  2948. @deffnx Command {flash fillb} address byte length
  2949. Fills flash memory with the specified @var{word} (32 bits),
  2950. @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
  2951. starting at @var{address} and continuing
  2952. for @var{length} units (word/halfword/byte).
  2953. No erasure is done before writing; when needed, that must be done
  2954. before issuing this command.
  2955. Writes are done in blocks of up to 1024 bytes, and each write is
  2956. verified by reading back the data and comparing it to what was written.
  2957. The flash bank to use is inferred from the @var{address} of
  2958. each block, and the specified length must stay within that bank.
  2959. @end deffn
  2960. @comment no current checks for errors if fill blocks touch multiple banks!
  2961. @anchor{flash write_bank}
  2962. @deffn Command {flash write_bank} num filename offset
  2963. Write the binary @file{filename} to flash bank @var{num},
  2964. starting at @var{offset} bytes from the beginning of the bank.
  2965. The @var{num} parameter is a value shown by @command{flash banks}.
  2966. @end deffn
  2967. @anchor{flash write_image}
  2968. @deffn Command {flash write_image} [erase] [unlock] filename [offset] [type]
  2969. Write the image @file{filename} to the current target's flash bank(s).
  2970. A relocation @var{offset} may be specified, in which case it is added
  2971. to the base address for each section in the image.
  2972. The file [@var{type}] can be specified
  2973. explicitly as @option{bin} (binary), @option{ihex} (Intel hex),
  2974. @option{elf} (ELF file), @option{s19} (Motorola s19).
  2975. @option{mem}, or @option{builder}.
  2976. The relevant flash sectors will be erased prior to programming
  2977. if the @option{erase} parameter is given. If @option{unlock} is
  2978. provided, then the flash banks are unlocked before erase and
  2979. program. The flash bank to use is inferred from the @var{address} of
  2980. each image segment.
  2981. @end deffn
  2982. @section Other Flash commands
  2983. @cindex flash protection
  2984. @deffn Command {flash erase_check} num
  2985. Check erase state of sectors in flash bank @var{num},
  2986. and display that status.
  2987. The @var{num} parameter is a value shown by @command{flash banks}.
  2988. This is the only operation that
  2989. updates the erase state information displayed by @option{flash info}. That means you have
  2990. to issue a @command{flash erase_check} command after erasing or programming the device
  2991. to get updated information.
  2992. (Code execution may have invalidated any state records kept by OpenOCD.)
  2993. @end deffn
  2994. @deffn Command {flash info} num
  2995. Print info about flash bank @var{num}
  2996. The @var{num} parameter is a value shown by @command{flash banks}.
  2997. The information includes per-sector protect status.
  2998. @end deffn
  2999. @anchor{flash protect}
  3000. @deffn Command {flash protect} num first last (@option{on}|@option{off})
  3001. Enable (@option{on}) or disable (@option{off}) protection of flash sectors
  3002. in flash bank @var{num}, starting at sector @var{first}
  3003. and continuing up to and including @var{last}.
  3004. Providing a @var{last} sector of @option{last}
  3005. specifies "to the end of the flash bank".
  3006. The @var{num} parameter is a value shown by @command{flash banks}.
  3007. @end deffn
  3008. @deffn Command {flash protect_check} num
  3009. Check protection state of sectors in flash bank @var{num}.
  3010. The @var{num} parameter is a value shown by @command{flash banks}.
  3011. @comment @option{flash erase_sector} using the same syntax.
  3012. @end deffn
  3013. @anchor{Flash Driver List}
  3014. @section Flash Drivers, Options, and Commands
  3015. As noted above, the @command{flash bank} command requires a driver name,
  3016. and allows driver-specific options and behaviors.
  3017. Some drivers also activate driver-specific commands.
  3018. @subsection External Flash
  3019. @deffn {Flash Driver} cfi
  3020. @cindex Common Flash Interface
  3021. @cindex CFI
  3022. The ``Common Flash Interface'' (CFI) is the main standard for
  3023. external NOR flash chips, each of which connects to a
  3024. specific external chip select on the CPU.
  3025. Frequently the first such chip is used to boot the system.
  3026. Your board's @code{reset-init} handler might need to
  3027. configure additional chip selects using other commands (like: @command{mww} to
  3028. configure a bus and its timings) , or
  3029. perhaps configure a GPIO pin that controls the ``write protect'' pin
  3030. on the flash chip.
  3031. The CFI driver can use a target-specific working area to significantly
  3032. speed up operation.
  3033. The CFI driver can accept the following optional parameters, in any order:
  3034. @itemize
  3035. @item @var{jedec_probe} ... is used to detect certain non-CFI flash ROMs,
  3036. like AM29LV010 and similar types.
  3037. @item @var{x16_as_x8} ... when a 16-bit flash is hooked up to an 8-bit bus.
  3038. @end itemize
  3039. To configure two adjacent banks of 16 MBytes each, both sixteen bits (two bytes)
  3040. wide on a sixteen bit bus:
  3041. @example
  3042. flash bank cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
  3043. flash bank cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
  3044. @end example
  3045. @c "cfi part_id" disabled
  3046. @end deffn
  3047. @subsection Internal Flash (Microcontrollers)
  3048. @deffn {Flash Driver} aduc702x
  3049. The ADUC702x analog microcontrollers from Analog Devices
  3050. include internal flash and use ARM7TDMI cores.
  3051. The aduc702x flash driver works with models ADUC7019 through ADUC7028.
  3052. The setup command only requires the @var{target} argument
  3053. since all devices in this family have the same memory layout.
  3054. @example
  3055. flash bank aduc702x 0 0 0 0 $_TARGETNAME
  3056. @end example
  3057. @end deffn
  3058. @deffn {Flash Driver} at91sam3
  3059. @cindex at91sam3
  3060. All members of the AT91SAM3 microcontroller family from
  3061. Atmel include internal flash and use ARM's Cortex-M3 core. The driver
  3062. currently (6/22/09) recognizes the AT91SAM3U[1/2/4][C/E] chips. Note
  3063. that the driver was orginaly developed and tested using the
  3064. AT91SAM3U4E, using a SAM3U-EK eval board. Support for other chips in
  3065. the family was cribbed from the data sheet. @emph{Note to future
  3066. readers/updaters: Please remove this worrysome comment after other
  3067. chips are confirmed.}
  3068. The AT91SAM3U4[E/C] (256K) chips have two flash banks; most other chips
  3069. have one flash bank. In all cases the flash banks are at
  3070. the following fixed locations:
  3071. @example
  3072. # Flash bank 0 - all chips
  3073. flash bank at91sam3 0x00080000 0 1 1 $_TARGETNAME
  3074. # Flash bank 1 - only 256K chips
  3075. flash bank at91sam3 0x00100000 0 1 1 $_TARGETNAME
  3076. @end example
  3077. Internally, the AT91SAM3 flash memory is organized as follows.
  3078. Unlike the AT91SAM7 chips, these are not used as parameters
  3079. to the @command{flash bank} command:
  3080. @itemize
  3081. @item @emph{N-Banks:} 256K chips have 2 banks, others have 1 bank.
  3082. @item @emph{Bank Size:} 128K/64K Per flash bank
  3083. @item @emph{Sectors:} 16 or 8 per bank
  3084. @item @emph{SectorSize:} 8K Per Sector
  3085. @item @emph{PageSize:} 256 bytes per page. Note that OpenOCD operates on 'sector' sizes, not page sizes.
  3086. @end itemize
  3087. The AT91SAM3 driver adds some additional commands:
  3088. @deffn Command {at91sam3 gpnvm}
  3089. @deffnx Command {at91sam3 gpnvm clear} number
  3090. @deffnx Command {at91sam3 gpnvm set} number
  3091. @deffnx Command {at91sam3 gpnvm show} [@option{all}|number]
  3092. With no parameters, @command{show} or @command{show all},
  3093. shows the status of all GPNVM bits.
  3094. With @command{show} @var{number}, displays that bit.
  3095. With @command{set} @var{number} or @command{clear} @var{number},
  3096. modifies that GPNVM bit.
  3097. @end deffn
  3098. @deffn Command {at91sam3 info}
  3099. This command attempts to display information about the AT91SAM3
  3100. chip. @emph{First} it read the @code{CHIPID_CIDR} [address 0x400e0740, see
  3101. Section 28.2.1, page 505 of the AT91SAM3U 29/may/2009 datasheet,
  3102. document id: doc6430A] and decodes the values. @emph{Second} it reads the
  3103. various clock configuration registers and attempts to display how it
  3104. believes the chip is configured. By default, the SLOWCLK is assumed to
  3105. be 32768 Hz, see the command @command{at91sam3 slowclk}.
  3106. @end deffn
  3107. @deffn Command {at91sam3 slowclk} [value]
  3108. This command shows/sets the slow clock frequency used in the
  3109. @command{at91sam3 info} command calculations above.
  3110. @end deffn
  3111. @end deffn
  3112. @deffn {Flash Driver} at91sam7
  3113. All members of the AT91SAM7 microcontroller family from Atmel include
  3114. internal flash and use ARM7TDMI cores. The driver automatically
  3115. recognizes a number of these chips using the chip identification
  3116. register, and autoconfigures itself.
  3117. @example
  3118. flash bank at91sam7 0 0 0 0 $_TARGETNAME
  3119. @end example
  3120. For chips which are not recognized by the controller driver, you must
  3121. provide additional parameters in the following order:
  3122. @itemize
  3123. @item @var{chip_model} ... label used with @command{flash info}
  3124. @item @var{banks}
  3125. @item @var{sectors_per_bank}
  3126. @item @var{pages_per_sector}
  3127. @item @var{pages_size}
  3128. @item @var{num_nvm_bits}
  3129. @item @var{freq_khz} ... required if an external clock is provided,
  3130. optional (but recommended) when the oscillator frequency is known
  3131. @end itemize
  3132. It is recommended that you provide zeroes for all of those values
  3133. except the clock frequency, so that everything except that frequency
  3134. will be autoconfigured.
  3135. Knowing the frequency helps ensure correct timings for flash access.
  3136. The flash controller handles erases automatically on a page (128/256 byte)
  3137. basis, so explicit erase commands are not necessary for flash programming.
  3138. However, there is an ``EraseAll`` command that can erase an entire flash
  3139. plane (of up to 256KB), and it will be used automatically when you issue
  3140. @command{flash erase_sector} or @command{flash erase_address} commands.
  3141. @deffn Command {at91sam7 gpnvm} bitnum (@option{set}|@option{clear})
  3142. Set or clear a ``General Purpose Non-Volatle Memory'' (GPNVM)
  3143. bit for the processor. Each processor has a number of such bits,
  3144. used for controlling features such as brownout detection (so they
  3145. are not truly general purpose).
  3146. @quotation Note
  3147. This assumes that the first flash bank (number 0) is associated with
  3148. the appropriate at91sam7 target.
  3149. @end quotation
  3150. @end deffn
  3151. @end deffn
  3152. @deffn {Flash Driver} avr
  3153. The AVR 8-bit microcontrollers from Atmel integrate flash memory.
  3154. @emph{The current implementation is incomplete.}
  3155. @comment - defines mass_erase ... pointless given flash_erase_address
  3156. @end deffn
  3157. @deffn {Flash Driver} ecosflash
  3158. @emph{No idea what this is...}
  3159. The @var{ecosflash} driver defines one mandatory parameter,
  3160. the name of a modules of target code which is downloaded
  3161. and executed.
  3162. @end deffn
  3163. @deffn {Flash Driver} lpc2000
  3164. Most members of the LPC1700 and LPC2000 microcontroller families from NXP
  3165. include internal flash and use Cortex-M3 (LPC1700) or ARM7TDMI (LPC2000) cores.
  3166. @quotation Note
  3167. There are LPC2000 devices which are not supported by the @var{lpc2000}
  3168. driver:
  3169. The LPC2888 is supported by the @var{lpc288x} driver.
  3170. The LPC29xx family is supported by the @var{lpc2900} driver.
  3171. @end quotation
  3172. The @var{lpc2000} driver defines two mandatory and one optional parameters,
  3173. which must appear in the following order:
  3174. @itemize
  3175. @item @var{variant} ... required, may be
  3176. @var{lpc2000_v1} (older LPC21xx and LPC22xx)
  3177. @var{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx)
  3178. or @var{lpc1700} (LPC175x and LPC176x)
  3179. @item @var{clock_kHz} ... the frequency, in kiloHertz,
  3180. at which the core is running
  3181. @item @var{calc_checksum} ... optional (but you probably want to provide this!),
  3182. telling the driver to calculate a valid checksum for the exception vector table.
  3183. @end itemize
  3184. LPC flashes don't require the chip and bus width to be specified.
  3185. @example
  3186. flash bank lpc2000 0x0 0x7d000 0 0 $_TARGETNAME \
  3187. lpc2000_v2 14765 calc_checksum
  3188. @end example
  3189. @deffn {Command} {lpc2000 part_id} bank
  3190. Displays the four byte part identifier associated with
  3191. the specified flash @var{bank}.
  3192. @end deffn
  3193. @end deffn
  3194. @deffn {Flash Driver} lpc288x
  3195. The LPC2888 microcontroller from NXP needs slightly different flash
  3196. support from its lpc2000 siblings.
  3197. The @var{lpc288x} driver defines one mandatory parameter,
  3198. the programming clock rate in Hz.
  3199. LPC flashes don't require the chip and bus width to be specified.
  3200. @example
  3201. flash bank lpc288x 0 0 0 0 $_TARGETNAME 12000000
  3202. @end example
  3203. @end deffn
  3204. @deffn {Flash Driver} lpc2900
  3205. This driver supports the LPC29xx ARM968E based microcontroller family
  3206. from NXP.
  3207. The predefined parameters @var{base}, @var{size}, @var{chip_width} and
  3208. @var{bus_width} of the @code{flash bank} command are ignored. Flash size and
  3209. sector layout are auto-configured by the driver.
  3210. The driver has one additional mandatory parameter: The CPU clock rate
  3211. (in kHz) at the time the flash operations will take place. Most of the time this
  3212. will not be the crystal frequency, but a higher PLL frequency. The
  3213. @code{reset-init} event handler in the board script is usually the place where
  3214. you start the PLL.
  3215. The driver rejects flashless devices (currently the LPC2930).
  3216. The EEPROM in LPC2900 devices is not mapped directly into the address space.
  3217. It must be handled much more like NAND flash memory, and will therefore be
  3218. handled by a separate @code{lpc2900_eeprom} driver (not yet available).
  3219. Sector protection in terms of the LPC2900 is handled transparently. Every time a
  3220. sector needs to be erased or programmed, it is automatically unprotected.
  3221. What is shown as protection status in the @code{flash info} command, is
  3222. actually the LPC2900 @emph{sector security}. This is a mechanism to prevent a
  3223. sector from ever being erased or programmed again. As this is an irreversible
  3224. mechanism, it is handled by a special command (@code{lpc2900 secure_sector}),
  3225. and not by the standard @code{flash protect} command.
  3226. Example for a 125 MHz clock frequency:
  3227. @example
  3228. flash bank lpc2900 0 0 0 0 $_TARGETNAME 125000
  3229. @end example
  3230. Some @code{lpc2900}-specific commands are defined. In the following command list,
  3231. the @var{bank} parameter is the bank number as obtained by the
  3232. @code{flash banks} command.
  3233. @deffn Command {lpc2900 signature} bank
  3234. Calculates a 128-bit hash value, the @emph{signature}, from the whole flash
  3235. content. This is a hardware feature of the flash block, hence the calculation is
  3236. very fast. You may use this to verify the content of a programmed device against
  3237. a known signature.
  3238. Example:
  3239. @example
  3240. lpc2900 signature 0
  3241. signature: 0x5f40cdc8:0xc64e592e:0x10490f89:0x32a0f317
  3242. @end example
  3243. @end deffn
  3244. @deffn Command {lpc2900 read_custom} bank filename
  3245. Reads the 912 bytes of customer information from the flash index sector, and
  3246. saves it to a file in binary format.
  3247. Example:
  3248. @example
  3249. lpc2900 read_custom 0 /path_to/customer_info.bin
  3250. @end example
  3251. @end deffn
  3252. The index sector of the flash is a @emph{write-only} sector. It cannot be
  3253. erased! In order to guard against unintentional write access, all following
  3254. commands need to be preceeded by a successful call to the @code{password}
  3255. command:
  3256. @deffn Command {lpc2900 password} bank password
  3257. You need to use this command right before each of the following commands:
  3258. @code{lpc2900 write_custom}, @code{lpc2900 secure_sector},
  3259. @code{lpc2900 secure_jtag}.
  3260. The password string is fixed to "I_know_what_I_am_doing".
  3261. Example:
  3262. @example
  3263. lpc2900 password 0 I_know_what_I_am_doing
  3264. Potentially dangerous operation allowed in next command!
  3265. @end example
  3266. @end deffn
  3267. @deffn Command {lpc2900 write_custom} bank filename type
  3268. Writes the content of the file into the customer info space of the flash index
  3269. sector. The filetype can be specified with the @var{type} field. Possible values
  3270. for @var{type} are: @var{bin} (binary), @var{ihex} (Intel hex format),
  3271. @var{elf} (ELF binary) or @var{s19} (Motorola S-records). The file must
  3272. contain a single section, and the contained data length must be exactly
  3273. 912 bytes.
  3274. @quotation Attention
  3275. This cannot be reverted! Be careful!
  3276. @end quotation
  3277. Example:
  3278. @example
  3279. lpc2900 write_custom 0 /path_to/customer_info.bin bin
  3280. @end example
  3281. @end deffn
  3282. @deffn Command {lpc2900 secure_sector} bank first last
  3283. Secures the sector range from @var{first} to @var{last} (including) against
  3284. further program and erase operations. The sector security will be effective
  3285. after the next power cycle.
  3286. @quotation Attention
  3287. This cannot be reverted! Be careful!
  3288. @end quotation
  3289. Secured sectors appear as @emph{protected} in the @code{flash info} command.
  3290. Example:
  3291. @example
  3292. lpc2900 secure_sector 0 1 1
  3293. flash info 0
  3294. #0 : lpc2900 at 0x20000000, size 0x000c0000, (...)
  3295. # 0: 0x00000000 (0x2000 8kB) not protected
  3296. # 1: 0x00002000 (0x2000 8kB) protected
  3297. # 2: 0x00004000 (0x2000 8kB) not protected
  3298. @end example
  3299. @end deffn
  3300. @deffn Command {lpc2900 secure_jtag} bank
  3301. Irreversibly disable the JTAG port. The new JTAG security setting will be
  3302. effective after the next power cycle.
  3303. @quotation Attention
  3304. This cannot be reverted! Be careful!
  3305. @end quotation
  3306. Examples:
  3307. @example
  3308. lpc2900 secure_jtag 0
  3309. @end example
  3310. @end deffn
  3311. @end deffn
  3312. @deffn {Flash Driver} ocl
  3313. @emph{No idea what this is, other than using some arm7/arm9 core.}
  3314. @example
  3315. flash bank ocl 0 0 0 0 $_TARGETNAME
  3316. @end example
  3317. @end deffn
  3318. @deffn {Flash Driver} pic32mx
  3319. The PIC32MX microcontrollers are based on the MIPS 4K cores,
  3320. and integrate flash memory.
  3321. @emph{The current implementation is incomplete.}
  3322. @example
  3323. flash bank pix32mx 0 0 0 0 $_TARGETNAME
  3324. @end example
  3325. @comment numerous *disabled* commands are defined:
  3326. @comment - chip_erase ... pointless given flash_erase_address
  3327. @comment - lock, unlock ... pointless given protect on/off (yes?)
  3328. @comment - pgm_word ... shouldn't bank be deduced from address??
  3329. Some pic32mx-specific commands are defined:
  3330. @deffn Command {pic32mx pgm_word} address value bank
  3331. Programs the specified 32-bit @var{value} at the given @var{address}
  3332. in the specified chip @var{bank}.
  3333. @end deffn
  3334. @end deffn
  3335. @deffn {Flash Driver} stellaris
  3336. All members of the Stellaris LM3Sxxx microcontroller family from
  3337. Texas Instruments
  3338. include internal flash and use ARM Cortex M3 cores.
  3339. The driver automatically recognizes a number of these chips using
  3340. the chip identification register, and autoconfigures itself.
  3341. @footnote{Currently there is a @command{stellaris mass_erase} command.
  3342. That seems pointless since the same effect can be had using the
  3343. standard @command{flash erase_address} command.}
  3344. @example
  3345. flash bank stellaris 0 0 0 0 $_TARGETNAME
  3346. @end example
  3347. @end deffn
  3348. @deffn {Flash Driver} stm32x
  3349. All members of the STM32 microcontroller family from ST Microelectronics
  3350. include internal flash and use ARM Cortex M3 cores.
  3351. The driver automatically recognizes a number of these chips using
  3352. the chip identification register, and autoconfigures itself.
  3353. @example
  3354. flash bank stm32x 0 0 0 0 $_TARGETNAME
  3355. @end example
  3356. Some stm32x-specific commands
  3357. @footnote{Currently there is a @command{stm32x mass_erase} command.
  3358. That seems pointless since the same effect can be had using the
  3359. standard @command{flash erase_address} command.}
  3360. are defined:
  3361. @deffn Command {stm32x lock} num
  3362. Locks the entire stm32 device.
  3363. The @var{num} parameter is a value shown by @command{flash banks}.
  3364. @end deffn
  3365. @deffn Command {stm32x unlock} num
  3366. Unlocks the entire stm32 device.
  3367. The @var{num} parameter is a value shown by @command{flash banks}.
  3368. @end deffn
  3369. @deffn Command {stm32x options_read} num
  3370. Read and display the stm32 option bytes written by
  3371. the @command{stm32x options_write} command.
  3372. The @var{num} parameter is a value shown by @command{flash banks}.
  3373. @end deffn
  3374. @deffn Command {stm32x options_write} num (@option{SWWDG}|@option{HWWDG}) (@option{RSTSTNDBY}|@option{NORSTSTNDBY}) (@option{RSTSTOP}|@option{NORSTSTOP})
  3375. Writes the stm32 option byte with the specified values.
  3376. The @var{num} parameter is a value shown by @command{flash banks}.
  3377. @end deffn
  3378. @end deffn
  3379. @deffn {Flash Driver} str7x
  3380. All members of the STR7 microcontroller family from ST Microelectronics
  3381. include internal flash and use ARM7TDMI cores.
  3382. The @var{str7x} driver defines one mandatory parameter, @var{variant},
  3383. which is either @code{STR71x}, @code{STR73x} or @code{STR75x}.
  3384. @example
  3385. flash bank str7x 0x40000000 0x00040000 0 0 $_TARGETNAME STR71x
  3386. @end example
  3387. @deffn Command {str7x disable_jtag} bank
  3388. Activate the Debug/Readout protection mechanism
  3389. for the specified flash bank.
  3390. @end deffn
  3391. @end deffn
  3392. @deffn {Flash Driver} str9x
  3393. Most members of the STR9 microcontroller family from ST Microelectronics
  3394. include internal flash and use ARM966E cores.
  3395. The str9 needs the flash controller to be configured using
  3396. the @command{str9x flash_config} command prior to Flash programming.
  3397. @example
  3398. flash bank str9x 0x40000000 0x00040000 0 0 $_TARGETNAME
  3399. str9x flash_config 0 4 2 0 0x80000
  3400. @end example
  3401. @deffn Command {str9x flash_config} num bbsr nbbsr bbadr nbbadr
  3402. Configures the str9 flash controller.
  3403. The @var{num} parameter is a value shown by @command{flash banks}.
  3404. @itemize @bullet
  3405. @item @var{bbsr} - Boot Bank Size register
  3406. @item @var{nbbsr} - Non Boot Bank Size register
  3407. @item @var{bbadr} - Boot Bank Start Address register
  3408. @item @var{nbbadr} - Boot Bank Start Address register
  3409. @end itemize
  3410. @end deffn
  3411. @end deffn
  3412. @deffn {Flash Driver} tms470
  3413. Most members of the TMS470 microcontroller family from Texas Instruments
  3414. include internal flash and use ARM7TDMI cores.
  3415. This driver doesn't require the chip and bus width to be specified.
  3416. Some tms470-specific commands are defined:
  3417. @deffn Command {tms470 flash_keyset} key0 key1 key2 key3
  3418. Saves programming keys in a register, to enable flash erase and write commands.
  3419. @end deffn
  3420. @deffn Command {tms470 osc_mhz} clock_mhz
  3421. Reports the clock speed, which is used to calculate timings.
  3422. @end deffn
  3423. @deffn Command {tms470 plldis} (0|1)
  3424. Disables (@var{1}) or enables (@var{0}) use of the PLL to speed up
  3425. the flash clock.
  3426. @end deffn
  3427. @end deffn
  3428. @subsection str9xpec driver
  3429. @cindex str9xpec
  3430. Here is some background info to help
  3431. you better understand how this driver works. OpenOCD has two flash drivers for
  3432. the str9:
  3433. @enumerate
  3434. @item
  3435. Standard driver @option{str9x} programmed via the str9 core. Normally used for
  3436. flash programming as it is faster than the @option{str9xpec} driver.
  3437. @item
  3438. Direct programming @option{str9xpec} using the flash controller. This is an
  3439. ISC compilant (IEEE 1532) tap connected in series with the str9 core. The str9
  3440. core does not need to be running to program using this flash driver. Typical use
  3441. for this driver is locking/unlocking the target and programming the option bytes.
  3442. @end enumerate
  3443. Before we run any commands using the @option{str9xpec} driver we must first disable
  3444. the str9 core. This example assumes the @option{str9xpec} driver has been
  3445. configured for flash bank 0.
  3446. @example
  3447. # assert srst, we do not want core running
  3448. # while accessing str9xpec flash driver
  3449. jtag_reset 0 1
  3450. # turn off target polling
  3451. poll off
  3452. # disable str9 core
  3453. str9xpec enable_turbo 0
  3454. # read option bytes
  3455. str9xpec options_read 0
  3456. # re-enable str9 core
  3457. str9xpec disable_turbo 0
  3458. poll on
  3459. reset halt
  3460. @end example
  3461. The above example will read the str9 option bytes.
  3462. When performing a unlock remember that you will not be able to halt the str9 - it
  3463. has been locked. Halting the core is not required for the @option{str9xpec} driver
  3464. as mentioned above, just issue the commands above manually or from a telnet prompt.
  3465. @deffn {Flash Driver} str9xpec
  3466. Only use this driver for locking/unlocking the device or configuring the option bytes.
  3467. Use the standard str9 driver for programming.
  3468. Before using the flash commands the turbo mode must be enabled using the
  3469. @command{str9xpec enable_turbo} command.
  3470. Several str9xpec-specific commands are defined:
  3471. @deffn Command {str9xpec disable_turbo} num
  3472. Restore the str9 into JTAG chain.
  3473. @end deffn
  3474. @deffn Command {str9xpec enable_turbo} num
  3475. Enable turbo mode, will simply remove the str9 from the chain and talk
  3476. directly to the embedded flash controller.
  3477. @end deffn
  3478. @deffn Command {str9xpec lock} num
  3479. Lock str9 device. The str9 will only respond to an unlock command that will
  3480. erase the device.
  3481. @end deffn
  3482. @deffn Command {str9xpec part_id} num
  3483. Prints the part identifier for bank @var{num}.
  3484. @end deffn
  3485. @deffn Command {str9xpec options_cmap} num (@option{bank0}|@option{bank1})
  3486. Configure str9 boot bank.
  3487. @end deffn
  3488. @deffn Command {str9xpec options_lvdsel} num (@option{vdd}|@option{vdd_vddq})
  3489. Configure str9 lvd source.
  3490. @end deffn
  3491. @deffn Command {str9xpec options_lvdthd} num (@option{2.4v}|@option{2.7v})
  3492. Configure str9 lvd threshold.
  3493. @end deffn
  3494. @deffn Command {str9xpec options_lvdwarn} bank (@option{vdd}|@option{vdd_vddq})
  3495. Configure str9 lvd reset warning source.
  3496. @end deffn
  3497. @deffn Command {str9xpec options_read} num
  3498. Read str9 option bytes.
  3499. @end deffn
  3500. @deffn Command {str9xpec options_write} num
  3501. Write str9 option bytes.
  3502. @end deffn
  3503. @deffn Command {str9xpec unlock} num
  3504. unlock str9 device.
  3505. @end deffn
  3506. @end deffn
  3507. @section mFlash
  3508. @subsection mFlash Configuration
  3509. @cindex mFlash Configuration
  3510. @deffn {Config Command} {mflash bank} soc base RST_pin target
  3511. Configures a mflash for @var{soc} host bank at
  3512. address @var{base}.
  3513. The pin number format depends on the host GPIO naming convention.
  3514. Currently, the mflash driver supports s3c2440 and pxa270.
  3515. Example for s3c2440 mflash where @var{RST pin} is GPIO B1:
  3516. @example
  3517. mflash bank s3c2440 0x10000000 1b 0
  3518. @end example
  3519. Example for pxa270 mflash where @var{RST pin} is GPIO 43:
  3520. @example
  3521. mflash bank pxa270 0x08000000 43 0
  3522. @end example
  3523. @end deffn
  3524. @subsection mFlash commands
  3525. @cindex mFlash commands
  3526. @deffn Command {mflash config pll} frequency
  3527. Configure mflash PLL.
  3528. The @var{frequency} is the mflash input frequency, in Hz.
  3529. Issuing this command will erase mflash's whole internal nand and write new pll.
  3530. After this command, mflash needs power-on-reset for normal operation.
  3531. If pll was newly configured, storage and boot(optional) info also need to be update.
  3532. @end deffn
  3533. @deffn Command {mflash config boot}
  3534. Configure bootable option.
  3535. If bootable option is set, mflash offer the first 8 sectors
  3536. (4kB) for boot.
  3537. @end deffn
  3538. @deffn Command {mflash config storage}
  3539. Configure storage information.
  3540. For the normal storage operation, this information must be
  3541. written.
  3542. @end deffn
  3543. @deffn Command {mflash dump} num filename offset size
  3544. Dump @var{size} bytes, starting at @var{offset} bytes from the
  3545. beginning of the bank @var{num}, to the file named @var{filename}.
  3546. @end deffn
  3547. @deffn Command {mflash probe}
  3548. Probe mflash.
  3549. @end deffn
  3550. @deffn Command {mflash write} num filename offset
  3551. Write the binary file @var{filename} to mflash bank @var{num}, starting at
  3552. @var{offset} bytes from the beginning of the bank.
  3553. @end deffn
  3554. @node NAND Flash Commands
  3555. @chapter NAND Flash Commands
  3556. @cindex NAND
  3557. Compared to NOR or SPI flash, NAND devices are inexpensive
  3558. and high density. Today's NAND chips, and multi-chip modules,
  3559. commonly hold multiple GigaBytes of data.
  3560. NAND chips consist of a number of ``erase blocks'' of a given
  3561. size (such as 128 KBytes), each of which is divided into a
  3562. number of pages (of perhaps 512 or 2048 bytes each). Each
  3563. page of a NAND flash has an ``out of band'' (OOB) area to hold
  3564. Error Correcting Code (ECC) and other metadata, usually 16 bytes
  3565. of OOB for every 512 bytes of page data.
  3566. One key characteristic of NAND flash is that its error rate
  3567. is higher than that of NOR flash. In normal operation, that
  3568. ECC is used to correct and detect errors. However, NAND
  3569. blocks can also wear out and become unusable; those blocks
  3570. are then marked "bad". NAND chips are even shipped from the
  3571. manufacturer with a few bad blocks. The highest density chips
  3572. use a technology (MLC) that wears out more quickly, so ECC
  3573. support is increasingly important as a way to detect blocks
  3574. that have begun to fail, and help to preserve data integrity
  3575. with techniques such as wear leveling.
  3576. Software is used to manage the ECC. Some controllers don't
  3577. support ECC directly; in those cases, software ECC is used.
  3578. Other controllers speed up the ECC calculations with hardware.
  3579. Single-bit error correction hardware is routine. Controllers
  3580. geared for newer MLC chips may correct 4 or more errors for
  3581. every 512 bytes of data.
  3582. You will need to make sure that any data you write using
  3583. OpenOCD includes the apppropriate kind of ECC. For example,
  3584. that may mean passing the @code{oob_softecc} flag when
  3585. writing NAND data, or ensuring that the correct hardware
  3586. ECC mode is used.
  3587. The basic steps for using NAND devices include:
  3588. @enumerate
  3589. @item Declare via the command @command{nand device}
  3590. @* Do this in a board-specific configuration file,
  3591. passing parameters as needed by the controller.
  3592. @item Configure each device using @command{nand probe}.
  3593. @* Do this only after the associated target is set up,
  3594. such as in its reset-init script or in procures defined
  3595. to access that device.
  3596. @item Operate on the flash via @command{nand subcommand}
  3597. @* Often commands to manipulate the flash are typed by a human, or run
  3598. via a script in some automated way. Common task include writing a
  3599. boot loader, operating system, or other data needed to initialize or
  3600. de-brick a board.
  3601. @end enumerate
  3602. @b{NOTE:} At the time this text was written, the largest NAND
  3603. flash fully supported by OpenOCD is 2 GiBytes (16 GiBits).
  3604. This is because the variables used to hold offsets and lengths
  3605. are only 32 bits wide.
  3606. (Larger chips may work in some cases, unless an offset or length
  3607. is larger than 0xffffffff, the largest 32-bit unsigned integer.)
  3608. Some larger devices will work, since they are actually multi-chip
  3609. modules with two smaller chips and individual chipselect lines.
  3610. @anchor{NAND Configuration}
  3611. @section NAND Configuration Commands
  3612. @cindex NAND configuration
  3613. NAND chips must be declared in configuration scripts,
  3614. plus some additional configuration that's done after
  3615. OpenOCD has initialized.
  3616. @deffn {Config Command} {nand device} controller target [configparams...]
  3617. Declares a NAND device, which can be read and written to
  3618. after it has been configured through @command{nand probe}.
  3619. In OpenOCD, devices are single chips; this is unlike some
  3620. operating systems, which may manage multiple chips as if
  3621. they were a single (larger) device.
  3622. In some cases, configuring a device will activate extra
  3623. commands; see the controller-specific documentation.
  3624. @b{NOTE:} This command is not available after OpenOCD
  3625. initialization has completed. Use it in board specific
  3626. configuration files, not interactively.
  3627. @itemize @bullet
  3628. @item @var{controller} ... identifies the controller driver
  3629. associated with the NAND device being declared.
  3630. @xref{NAND Driver List}.
  3631. @item @var{target} ... names the target used when issuing
  3632. commands to the NAND controller.
  3633. @comment Actually, it's currently a controller-specific parameter...
  3634. @item @var{configparams} ... controllers may support, or require,
  3635. additional parameters. See the controller-specific documentation
  3636. for more information.
  3637. @end itemize
  3638. @end deffn
  3639. @deffn Command {nand list}
  3640. Prints a summary of each device declared
  3641. using @command{nand device}, numbered from zero.
  3642. Note that un-probed devices show no details.
  3643. @example
  3644. > nand list
  3645. #0: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
  3646. blocksize: 131072, blocks: 8192
  3647. #1: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
  3648. blocksize: 131072, blocks: 8192
  3649. >
  3650. @end example
  3651. @end deffn
  3652. @deffn Command {nand probe} num
  3653. Probes the specified device to determine key characteristics
  3654. like its page and block sizes, and how many blocks it has.
  3655. The @var{num} parameter is the value shown by @command{nand list}.
  3656. You must (successfully) probe a device before you can use
  3657. it with most other NAND commands.
  3658. @end deffn
  3659. @section Erasing, Reading, Writing to NAND Flash
  3660. @deffn Command {nand dump} num filename offset length [oob_option]
  3661. @cindex NAND reading
  3662. Reads binary data from the NAND device and writes it to the file,
  3663. starting at the specified offset.
  3664. The @var{num} parameter is the value shown by @command{nand list}.
  3665. Use a complete path name for @var{filename}, so you don't depend
  3666. on the directory used to start the OpenOCD server.
  3667. The @var{offset} and @var{length} must be exact multiples of the
  3668. device's page size. They describe a data region; the OOB data
  3669. associated with each such page may also be accessed.
  3670. @b{NOTE:} At the time this text was written, no error correction
  3671. was done on the data that's read, unless raw access was disabled
  3672. and the underlying NAND controller driver had a @code{read_page}
  3673. method which handled that error correction.
  3674. By default, only page data is saved to the specified file.
  3675. Use an @var{oob_option} parameter to save OOB data:
  3676. @itemize @bullet
  3677. @item no oob_* parameter
  3678. @*Output file holds only page data; OOB is discarded.
  3679. @item @code{oob_raw}
  3680. @*Output file interleaves page data and OOB data;
  3681. the file will be longer than "length" by the size of the
  3682. spare areas associated with each data page.
  3683. Note that this kind of "raw" access is different from
  3684. what's implied by @command{nand raw_access}, which just
  3685. controls whether a hardware-aware access method is used.
  3686. @item @code{oob_only}
  3687. @*Output file has only raw OOB data, and will
  3688. be smaller than "length" since it will contain only the
  3689. spare areas associated with each data page.
  3690. @end itemize
  3691. @end deffn
  3692. @deffn Command {nand erase} num [offset length]
  3693. @cindex NAND erasing
  3694. @cindex NAND programming
  3695. Erases blocks on the specified NAND device, starting at the
  3696. specified @var{offset} and continuing for @var{length} bytes.
  3697. Both of those values must be exact multiples of the device's
  3698. block size, and the region they specify must fit entirely in the chip.
  3699. If those parameters are not specified,
  3700. the whole NAND chip will be erased.
  3701. The @var{num} parameter is the value shown by @command{nand list}.
  3702. @b{NOTE:} This command will try to erase bad blocks, when told
  3703. to do so, which will probably invalidate the manufacturer's bad
  3704. block marker.
  3705. For the remainder of the current server session, @command{nand info}
  3706. will still report that the block ``is'' bad.
  3707. @end deffn
  3708. @deffn Command {nand write} num filename offset [option...]
  3709. @cindex NAND writing
  3710. @cindex NAND programming
  3711. Writes binary data from the file into the specified NAND device,
  3712. starting at the specified offset. Those pages should already
  3713. have been erased; you can't change zero bits to one bits.
  3714. The @var{num} parameter is the value shown by @command{nand list}.
  3715. Use a complete path name for @var{filename}, so you don't depend
  3716. on the directory used to start the OpenOCD server.
  3717. The @var{offset} must be an exact multiple of the device's page size.
  3718. All data in the file will be written, assuming it doesn't run
  3719. past the end of the device.
  3720. Only full pages are written, and any extra space in the last
  3721. page will be filled with 0xff bytes. (That includes OOB data,
  3722. if that's being written.)
  3723. @b{NOTE:} At the time this text was written, bad blocks are
  3724. ignored. That is, this routine will not skip bad blocks,
  3725. but will instead try to write them. This can cause problems.
  3726. Provide at most one @var{option} parameter. With some
  3727. NAND drivers, the meanings of these parameters may change
  3728. if @command{nand raw_access} was used to disable hardware ECC.
  3729. @itemize @bullet
  3730. @item no oob_* parameter
  3731. @*File has only page data, which is written.
  3732. If raw acccess is in use, the OOB area will not be written.
  3733. Otherwise, if the underlying NAND controller driver has
  3734. a @code{write_page} routine, that routine may write the OOB
  3735. with hardware-computed ECC data.
  3736. @item @code{oob_only}
  3737. @*File has only raw OOB data, which is written to the OOB area.
  3738. Each page's data area stays untouched. @i{This can be a dangerous
  3739. option}, since it can invalidate the ECC data.
  3740. You may need to force raw access to use this mode.
  3741. @item @code{oob_raw}
  3742. @*File interleaves data and OOB data, both of which are written
  3743. If raw access is enabled, the data is written first, then the
  3744. un-altered OOB.
  3745. Otherwise, if the underlying NAND controller driver has
  3746. a @code{write_page} routine, that routine may modify the OOB
  3747. before it's written, to include hardware-computed ECC data.
  3748. @item @code{oob_softecc}
  3749. @*File has only page data, which is written.
  3750. The OOB area is filled with 0xff, except for a standard 1-bit
  3751. software ECC code stored in conventional locations.
  3752. You might need to force raw access to use this mode, to prevent
  3753. the underlying driver from applying hardware ECC.
  3754. @item @code{oob_softecc_kw}
  3755. @*File has only page data, which is written.
  3756. The OOB area is filled with 0xff, except for a 4-bit software ECC
  3757. specific to the boot ROM in Marvell Kirkwood SoCs.
  3758. You might need to force raw access to use this mode, to prevent
  3759. the underlying driver from applying hardware ECC.
  3760. @end itemize
  3761. @end deffn
  3762. @section Other NAND commands
  3763. @cindex NAND other commands
  3764. @deffn Command {nand check_bad_blocks} [offset length]
  3765. Checks for manufacturer bad block markers on the specified NAND
  3766. device. If no parameters are provided, checks the whole
  3767. device; otherwise, starts at the specified @var{offset} and
  3768. continues for @var{length} bytes.
  3769. Both of those values must be exact multiples of the device's
  3770. block size, and the region they specify must fit entirely in the chip.
  3771. The @var{num} parameter is the value shown by @command{nand list}.
  3772. @b{NOTE:} Before using this command you should force raw access
  3773. with @command{nand raw_access enable} to ensure that the underlying
  3774. driver will not try to apply hardware ECC.
  3775. @end deffn
  3776. @deffn Command {nand info} num
  3777. The @var{num} parameter is the value shown by @command{nand list}.
  3778. This prints the one-line summary from "nand list", plus for
  3779. devices which have been probed this also prints any known
  3780. status for each block.
  3781. @end deffn
  3782. @deffn Command {nand raw_access} num (@option{enable}|@option{disable})
  3783. Sets or clears an flag affecting how page I/O is done.
  3784. The @var{num} parameter is the value shown by @command{nand list}.
  3785. This flag is cleared (disabled) by default, but changing that
  3786. value won't affect all NAND devices. The key factor is whether
  3787. the underlying driver provides @code{read_page} or @code{write_page}
  3788. methods. If it doesn't provide those methods, the setting of
  3789. this flag is irrelevant; all access is effectively ``raw''.
  3790. When those methods exist, they are normally used when reading
  3791. data (@command{nand dump} or reading bad block markers) or
  3792. writing it (@command{nand write}). However, enabling
  3793. raw access (setting the flag) prevents use of those methods,
  3794. bypassing hardware ECC logic.
  3795. @i{This can be a dangerous option}, since writing blocks
  3796. with the wrong ECC data can cause them to be marked as bad.
  3797. @end deffn
  3798. @anchor{NAND Driver List}
  3799. @section NAND Drivers, Options, and Commands
  3800. As noted above, the @command{nand device} command allows
  3801. driver-specific options and behaviors.
  3802. Some controllers also activate controller-specific commands.
  3803. @deffn {NAND Driver} davinci
  3804. This driver handles the NAND controllers found on DaVinci family
  3805. chips from Texas Instruments.
  3806. It takes three extra parameters:
  3807. address of the NAND chip;
  3808. hardware ECC mode to use (@option{hwecc1},
  3809. @option{hwecc4}, @option{hwecc4_infix});
  3810. address of the AEMIF controller on this processor.
  3811. @example
  3812. nand device davinci dm355.arm 0x02000000 hwecc4 0x01e10000
  3813. @end example
  3814. All DaVinci processors support the single-bit ECC hardware,
  3815. and newer ones also support the four-bit ECC hardware.
  3816. The @code{write_page} and @code{read_page} methods are used
  3817. to implement those ECC modes, unless they are disabled using
  3818. the @command{nand raw_access} command.
  3819. @end deffn
  3820. @deffn {NAND Driver} lpc3180
  3821. These controllers require an extra @command{nand device}
  3822. parameter: the clock rate used by the controller.
  3823. @deffn Command {lpc3180 select} num [mlc|slc]
  3824. Configures use of the MLC or SLC controller mode.
  3825. MLC implies use of hardware ECC.
  3826. The @var{num} parameter is the value shown by @command{nand list}.
  3827. @end deffn
  3828. At this writing, this driver includes @code{write_page}
  3829. and @code{read_page} methods. Using @command{nand raw_access}
  3830. to disable those methods will prevent use of hardware ECC
  3831. in the MLC controller mode, but won't change SLC behavior.
  3832. @end deffn
  3833. @comment current lpc3180 code won't issue 5-byte address cycles
  3834. @deffn {NAND Driver} orion
  3835. These controllers require an extra @command{nand device}
  3836. parameter: the address of the controller.
  3837. @example
  3838. nand device orion 0xd8000000
  3839. @end example
  3840. These controllers don't define any specialized commands.
  3841. At this writing, their drivers don't include @code{write_page}
  3842. or @code{read_page} methods, so @command{nand raw_access} won't
  3843. change any behavior.
  3844. @end deffn
  3845. @deffn {NAND Driver} s3c2410
  3846. @deffnx {NAND Driver} s3c2412
  3847. @deffnx {NAND Driver} s3c2440
  3848. @deffnx {NAND Driver} s3c2443
  3849. These S3C24xx family controllers don't have any special
  3850. @command{nand device} options, and don't define any
  3851. specialized commands.
  3852. At this writing, their drivers don't include @code{write_page}
  3853. or @code{read_page} methods, so @command{nand raw_access} won't
  3854. change any behavior.
  3855. @end deffn
  3856. @node PLD/FPGA Commands
  3857. @chapter PLD/FPGA Commands
  3858. @cindex PLD
  3859. @cindex FPGA
  3860. Programmable Logic Devices (PLDs) and the more flexible
  3861. Field Programmable Gate Arrays (FPGAs) are both types of programmable hardware.
  3862. OpenOCD can support programming them.
  3863. Although PLDs are generally restrictive (cells are less functional, and
  3864. there are no special purpose cells for memory or computational tasks),
  3865. they share the same OpenOCD infrastructure.
  3866. Accordingly, both are called PLDs here.
  3867. @section PLD/FPGA Configuration and Commands
  3868. As it does for JTAG TAPs, debug targets, and flash chips (both NOR and NAND),
  3869. OpenOCD maintains a list of PLDs available for use in various commands.
  3870. Also, each such PLD requires a driver.
  3871. They are referenced by the number shown by the @command{pld devices} command,
  3872. and new PLDs are defined by @command{pld device driver_name}.
  3873. @deffn {Config Command} {pld device} driver_name tap_name [driver_options]
  3874. Defines a new PLD device, supported by driver @var{driver_name},
  3875. using the TAP named @var{tap_name}.
  3876. The driver may make use of any @var{driver_options} to configure its
  3877. behavior.
  3878. @end deffn
  3879. @deffn {Command} {pld devices}
  3880. Lists the PLDs and their numbers.
  3881. @end deffn
  3882. @deffn {Command} {pld load} num filename
  3883. Loads the file @file{filename} into the PLD identified by @var{num}.
  3884. The file format must be inferred by the driver.
  3885. @end deffn
  3886. @section PLD/FPGA Drivers, Options, and Commands
  3887. Drivers may support PLD-specific options to the @command{pld device}
  3888. definition command, and may also define commands usable only with
  3889. that particular type of PLD.
  3890. @deffn {FPGA Driver} virtex2
  3891. Virtex-II is a family of FPGAs sold by Xilinx.
  3892. It supports the IEEE 1532 standard for In-System Configuration (ISC).
  3893. No driver-specific PLD definition options are used,
  3894. and one driver-specific command is defined.
  3895. @deffn {Command} {virtex2 read_stat} num
  3896. Reads and displays the Virtex-II status register (STAT)
  3897. for FPGA @var{num}.
  3898. @end deffn
  3899. @end deffn
  3900. @node General Commands
  3901. @chapter General Commands
  3902. @cindex commands
  3903. The commands documented in this chapter here are common commands that
  3904. you, as a human, may want to type and see the output of. Configuration type
  3905. commands are documented elsewhere.
  3906. Intent:
  3907. @itemize @bullet
  3908. @item @b{Source Of Commands}
  3909. @* OpenOCD commands can occur in a configuration script (discussed
  3910. elsewhere) or typed manually by a human or supplied programatically,
  3911. or via one of several TCP/IP Ports.
  3912. @item @b{From the human}
  3913. @* A human should interact with the telnet interface (default port: 4444)
  3914. or via GDB (default port 3333).
  3915. To issue commands from within a GDB session, use the @option{monitor}
  3916. command, e.g. use @option{monitor poll} to issue the @option{poll}
  3917. command. All output is relayed through the GDB session.
  3918. @item @b{Machine Interface}
  3919. The Tcl interface's intent is to be a machine interface. The default Tcl
  3920. port is 5555.
  3921. @end itemize
  3922. @section Daemon Commands
  3923. @deffn {Command} exit
  3924. Exits the current telnet session.
  3925. @end deffn
  3926. @c note EXTREMELY ANNOYING word wrap at column 75
  3927. @c even when lines are e.g. 100+ columns ...
  3928. @c coded in startup.tcl
  3929. @deffn {Command} help [string]
  3930. With no parameters, prints help text for all commands.
  3931. Otherwise, prints each helptext containing @var{string}.
  3932. Not every command provides helptext.
  3933. @end deffn
  3934. @deffn Command sleep msec [@option{busy}]
  3935. Wait for at least @var{msec} milliseconds before resuming.
  3936. If @option{busy} is passed, busy-wait instead of sleeping.
  3937. (This option is strongly discouraged.)
  3938. Useful in connection with script files
  3939. (@command{script} command and @command{target_name} configuration).
  3940. @end deffn
  3941. @deffn Command shutdown
  3942. Close the OpenOCD daemon, disconnecting all clients (GDB, telnet, other).
  3943. @end deffn
  3944. @anchor{debug_level}
  3945. @deffn Command debug_level [n]
  3946. @cindex message level
  3947. Display debug level.
  3948. If @var{n} (from 0..3) is provided, then set it to that level.
  3949. This affects the kind of messages sent to the server log.
  3950. Level 0 is error messages only;
  3951. level 1 adds warnings;
  3952. level 2 adds informational messages;
  3953. and level 3 adds debugging messages.
  3954. The default is level 2, but that can be overridden on
  3955. the command line along with the location of that log
  3956. file (which is normally the server's standard output).
  3957. @xref{Running}.
  3958. @end deffn
  3959. @deffn Command fast (@option{enable}|@option{disable})
  3960. Default disabled.
  3961. Set default behaviour of OpenOCD to be "fast and dangerous".
  3962. At this writing, this only affects the defaults for two ARM7/ARM9 parameters:
  3963. fast memory access, and DCC downloads. Those parameters may still be
  3964. individually overridden.
  3965. The target specific "dangerous" optimisation tweaking options may come and go
  3966. as more robust and user friendly ways are found to ensure maximum throughput
  3967. and robustness with a minimum of configuration.
  3968. Typically the "fast enable" is specified first on the command line:
  3969. @example
  3970. openocd -c "fast enable" -c "interface dummy" -f target/str710.cfg
  3971. @end example
  3972. @end deffn
  3973. @deffn Command echo message
  3974. Logs a message at "user" priority.
  3975. Output @var{message} to stdout.
  3976. @example
  3977. echo "Downloading kernel -- please wait"
  3978. @end example
  3979. @end deffn
  3980. @deffn Command log_output [filename]
  3981. Redirect logging to @var{filename};
  3982. the initial log output channel is stderr.
  3983. @end deffn
  3984. @anchor{Target State handling}
  3985. @section Target State handling
  3986. @cindex reset
  3987. @cindex halt
  3988. @cindex target initialization
  3989. In this section ``target'' refers to a CPU configured as
  3990. shown earlier (@pxref{CPU Configuration}).
  3991. These commands, like many, implicitly refer to
  3992. a current target which is used to perform the
  3993. various operations. The current target may be changed
  3994. by using @command{targets} command with the name of the
  3995. target which should become current.
  3996. @deffn Command reg [(number|name) [value]]
  3997. Access a single register by @var{number} or by its @var{name}.
  3998. @emph{With no arguments}:
  3999. list all available registers for the current target,
  4000. showing number, name, size, value, and cache status.
  4001. @emph{With number/name}: display that register's value.
  4002. @emph{With both number/name and value}: set register's value.
  4003. Cores may have surprisingly many registers in their
  4004. Debug and trace infrastructure:
  4005. @example
  4006. > reg
  4007. (0) r0 (/32): 0x0000D3C2 (dirty: 1, valid: 1)
  4008. (1) r1 (/32): 0xFD61F31C (dirty: 0, valid: 1)
  4009. (2) r2 (/32): 0x00022551 (dirty: 0, valid: 1)
  4010. ...
  4011. (164) ETM_CONTEXTID_COMPARATOR_MASK (/32): \
  4012. 0x00000000 (dirty: 0, valid: 0)
  4013. >
  4014. @end example
  4015. @end deffn
  4016. @deffn Command halt [ms]
  4017. @deffnx Command wait_halt [ms]
  4018. The @command{halt} command first sends a halt request to the target,
  4019. which @command{wait_halt} doesn't.
  4020. Otherwise these behave the same: wait up to @var{ms} milliseconds,
  4021. or 5 seconds if there is no parameter, for the target to halt
  4022. (and enter debug mode).
  4023. Using 0 as the @var{ms} parameter prevents OpenOCD from waiting.
  4024. @quotation Warning
  4025. On ARM cores, software using the @emph{wait for interrupt} operation
  4026. often blocks the JTAG access needed by a @command{halt} command.
  4027. This is because that operation also puts the core into a low
  4028. power mode by gating the core clock;
  4029. but the core clock is needed to detect JTAG clock transitions.
  4030. One partial workaround uses adaptive clocking: when the core is
  4031. interrupted the operation completes, then JTAG clocks are accepted
  4032. at least until the interrupt handler completes.
  4033. However, this workaround is often unusable since the processor, board,
  4034. and JTAG adapter must all support adaptive JTAG clocking.
  4035. Also, it can't work until an interrupt is issued.
  4036. A more complete workaround is to not use that operation while you
  4037. work with a JTAG debugger.
  4038. Tasking environments generaly have idle loops where the body is the
  4039. @emph{wait for interrupt} operation.
  4040. (On older cores, it is a coprocessor action;
  4041. newer cores have a @option{wfi} instruction.)
  4042. Such loops can just remove that operation, at the cost of higher
  4043. power consumption (because the CPU is needlessly clocked).
  4044. @end quotation
  4045. @end deffn
  4046. @deffn Command resume [address]
  4047. Resume the target at its current code position,
  4048. or the optional @var{address} if it is provided.
  4049. OpenOCD will wait 5 seconds for the target to resume.
  4050. @end deffn
  4051. @deffn Command step [address]
  4052. Single-step the target at its current code position,
  4053. or the optional @var{address} if it is provided.
  4054. @end deffn
  4055. @anchor{Reset Command}
  4056. @deffn Command reset
  4057. @deffnx Command {reset run}
  4058. @deffnx Command {reset halt}
  4059. @deffnx Command {reset init}
  4060. Perform as hard a reset as possible, using SRST if possible.
  4061. @emph{All defined targets will be reset, and target
  4062. events will fire during the reset sequence.}
  4063. The optional parameter specifies what should
  4064. happen after the reset.
  4065. If there is no parameter, a @command{reset run} is executed.
  4066. The other options will not work on all systems.
  4067. @xref{Reset Configuration}.
  4068. @itemize @minus
  4069. @item @b{run} Let the target run
  4070. @item @b{halt} Immediately halt the target
  4071. @item @b{init} Immediately halt the target, and execute the reset-init script
  4072. @end itemize
  4073. @end deffn
  4074. @deffn Command soft_reset_halt
  4075. Requesting target halt and executing a soft reset. This is often used
  4076. when a target cannot be reset and halted. The target, after reset is
  4077. released begins to execute code. OpenOCD attempts to stop the CPU and
  4078. then sets the program counter back to the reset vector. Unfortunately
  4079. the code that was executed may have left the hardware in an unknown
  4080. state.
  4081. @end deffn
  4082. @section I/O Utilities
  4083. These commands are available when
  4084. OpenOCD is built with @option{--enable-ioutil}.
  4085. They are mainly useful on embedded targets,
  4086. notably the ZY1000.
  4087. Hosts with operating systems have complementary tools.
  4088. @emph{Note:} there are several more such commands.
  4089. @deffn Command append_file filename [string]*
  4090. Appends the @var{string} parameters to
  4091. the text file @file{filename}.
  4092. Each string except the last one is followed by one space.
  4093. The last string is followed by a newline.
  4094. @end deffn
  4095. @deffn Command cat filename
  4096. Reads and displays the text file @file{filename}.
  4097. @end deffn
  4098. @deffn Command cp src_filename dest_filename
  4099. Copies contents from the file @file{src_filename}
  4100. into @file{dest_filename}.
  4101. @end deffn
  4102. @deffn Command ip
  4103. @emph{No description provided.}
  4104. @end deffn
  4105. @deffn Command ls
  4106. @emph{No description provided.}
  4107. @end deffn
  4108. @deffn Command mac
  4109. @emph{No description provided.}
  4110. @end deffn
  4111. @deffn Command meminfo
  4112. Display available RAM memory on OpenOCD host.
  4113. Used in OpenOCD regression testing scripts.
  4114. @end deffn
  4115. @deffn Command peek
  4116. @emph{No description provided.}
  4117. @end deffn
  4118. @deffn Command poke
  4119. @emph{No description provided.}
  4120. @end deffn
  4121. @deffn Command rm filename
  4122. @c "rm" has both normal and Jim-level versions??
  4123. Unlinks the file @file{filename}.
  4124. @end deffn
  4125. @deffn Command trunc filename
  4126. Removes all data in the file @file{filename}.
  4127. @end deffn
  4128. @anchor{Memory access}
  4129. @section Memory access commands
  4130. @cindex memory access
  4131. These commands allow accesses of a specific size to the memory
  4132. system. Often these are used to configure the current target in some
  4133. special way. For example - one may need to write certain values to the
  4134. SDRAM controller to enable SDRAM.
  4135. @enumerate
  4136. @item Use the @command{targets} (plural) command
  4137. to change the current target.
  4138. @item In system level scripts these commands are deprecated.
  4139. Please use their TARGET object siblings to avoid making assumptions
  4140. about what TAP is the current target, or about MMU configuration.
  4141. @end enumerate
  4142. @deffn Command mdw addr [count]
  4143. @deffnx Command mdh addr [count]
  4144. @deffnx Command mdb addr [count]
  4145. Display contents of address @var{addr}, as
  4146. 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
  4147. or 8-bit bytes (@command{mdb}).
  4148. If @var{count} is specified, displays that many units.
  4149. (If you want to manipulate the data instead of displaying it,
  4150. see the @code{mem2array} primitives.)
  4151. @end deffn
  4152. @deffn Command mww addr word
  4153. @deffnx Command mwh addr halfword
  4154. @deffnx Command mwb addr byte
  4155. Writes the specified @var{word} (32 bits),
  4156. @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
  4157. at the specified address @var{addr}.
  4158. @end deffn
  4159. @anchor{Image access}
  4160. @section Image loading commands
  4161. @cindex image loading
  4162. @cindex image dumping
  4163. @anchor{dump_image}
  4164. @deffn Command {dump_image} filename address size
  4165. Dump @var{size} bytes of target memory starting at @var{address} to the
  4166. binary file named @var{filename}.
  4167. @end deffn
  4168. @deffn Command {fast_load}
  4169. Loads an image stored in memory by @command{fast_load_image} to the
  4170. current target. Must be preceeded by fast_load_image.
  4171. @end deffn
  4172. @deffn Command {fast_load_image} filename address [@option{bin}|@option{ihex}|@option{elf}]
  4173. Normally you should be using @command{load_image} or GDB load. However, for
  4174. testing purposes or when I/O overhead is significant(OpenOCD running on an embedded
  4175. host), storing the image in memory and uploading the image to the target
  4176. can be a way to upload e.g. multiple debug sessions when the binary does not change.
  4177. Arguments are the same as @command{load_image}, but the image is stored in OpenOCD host
  4178. memory, i.e. does not affect target. This approach is also useful when profiling
  4179. target programming performance as I/O and target programming can easily be profiled
  4180. separately.
  4181. @end deffn
  4182. @anchor{load_image}
  4183. @deffn Command {load_image} filename address [@option{bin}|@option{ihex}|@option{elf}]
  4184. Load image from file @var{filename} to target memory at @var{address}.
  4185. The file format may optionally be specified
  4186. (@option{bin}, @option{ihex}, or @option{elf})
  4187. @end deffn
  4188. @deffn Command {test_image} filename [address [@option{bin}|@option{ihex}|@option{elf}]]
  4189. Displays image section sizes and addresses
  4190. as if @var{filename} were loaded into target memory
  4191. starting at @var{address} (defaults to zero).
  4192. The file format may optionally be specified
  4193. (@option{bin}, @option{ihex}, or @option{elf})
  4194. @end deffn
  4195. @deffn Command {verify_image} filename address [@option{bin}|@option{ihex}|@option{elf}]
  4196. Verify @var{filename} against target memory starting at @var{address}.
  4197. The file format may optionally be specified
  4198. (@option{bin}, @option{ihex}, or @option{elf})
  4199. This will first attempt a comparison using a CRC checksum, if this fails it will try a binary compare.
  4200. @end deffn
  4201. @section Breakpoint and Watchpoint commands
  4202. @cindex breakpoint
  4203. @cindex watchpoint
  4204. CPUs often make debug modules accessible through JTAG, with
  4205. hardware support for a handful of code breakpoints and data
  4206. watchpoints.
  4207. In addition, CPUs almost always support software breakpoints.
  4208. @deffn Command {bp} [address len [@option{hw}]]
  4209. With no parameters, lists all active breakpoints.
  4210. Else sets a breakpoint on code execution starting
  4211. at @var{address} for @var{length} bytes.
  4212. This is a software breakpoint, unless @option{hw} is specified
  4213. in which case it will be a hardware breakpoint.
  4214. (@xref{arm9tdmi vector_catch}, or @pxref{xscale vector_catch},
  4215. for similar mechanisms that do not consume hardware breakpoints.)
  4216. @end deffn
  4217. @deffn Command {rbp} address
  4218. Remove the breakpoint at @var{address}.
  4219. @end deffn
  4220. @deffn Command {rwp} address
  4221. Remove data watchpoint on @var{address}
  4222. @end deffn
  4223. @deffn Command {wp} [address len [(@option{r}|@option{w}|@option{a}) [value [mask]]]]
  4224. With no parameters, lists all active watchpoints.
  4225. Else sets a data watchpoint on data from @var{address} for @var{length} bytes.
  4226. The watch point is an "access" watchpoint unless
  4227. the @option{r} or @option{w} parameter is provided,
  4228. defining it as respectively a read or write watchpoint.
  4229. If a @var{value} is provided, that value is used when determining if
  4230. the watchpoint should trigger. The value may be first be masked
  4231. using @var{mask} to mark ``don't care'' fields.
  4232. @end deffn
  4233. @section Misc Commands
  4234. @cindex profiling
  4235. @deffn Command {profile} seconds filename
  4236. Profiling samples the CPU's program counter as quickly as possible,
  4237. which is useful for non-intrusive stochastic profiling.
  4238. Saves up to 10000 sampines in @file{filename} using ``gmon.out'' format.
  4239. @end deffn
  4240. @deffn Command {version}
  4241. Displays a string identifying the version of this OpenOCD server.
  4242. @end deffn
  4243. @deffn Command {virt2phys} virtual_address
  4244. Requests the current target to map the specified @var{virtual_address}
  4245. to its corresponding physical address, and displays the result.
  4246. @end deffn
  4247. @node Architecture and Core Commands
  4248. @chapter Architecture and Core Commands
  4249. @cindex Architecture Specific Commands
  4250. @cindex Core Specific Commands
  4251. Most CPUs have specialized JTAG operations to support debugging.
  4252. OpenOCD packages most such operations in its standard command framework.
  4253. Some of those operations don't fit well in that framework, so they are
  4254. exposed here as architecture or implementation (core) specific commands.
  4255. @anchor{ARM Hardware Tracing}
  4256. @section ARM Hardware Tracing
  4257. @cindex tracing
  4258. @cindex ETM
  4259. @cindex ETB
  4260. CPUs based on ARM cores may include standard tracing interfaces,
  4261. based on an ``Embedded Trace Module'' (ETM) which sends voluminous
  4262. address and data bus trace records to a ``Trace Port''.
  4263. @itemize
  4264. @item
  4265. Development-oriented boards will sometimes provide a high speed
  4266. trace connector for collecting that data, when the particular CPU
  4267. supports such an interface.
  4268. (The standard connector is a 38-pin Mictor, with both JTAG
  4269. and trace port support.)
  4270. Those trace connectors are supported by higher end JTAG adapters
  4271. and some logic analyzer modules; frequently those modules can
  4272. buffer several megabytes of trace data.
  4273. Configuring an ETM coupled to such an external trace port belongs
  4274. in the board-specific configuration file.
  4275. @item
  4276. If the CPU doesn't provide an external interface, it probably
  4277. has an ``Embedded Trace Buffer'' (ETB) on the chip, which is a
  4278. dedicated SRAM. 4KBytes is one common ETB size.
  4279. Configuring an ETM coupled only to an ETB belongs in the CPU-specific
  4280. (target) configuration file, since it works the same on all boards.
  4281. @end itemize
  4282. ETM support in OpenOCD doesn't seem to be widely used yet.
  4283. @quotation Issues
  4284. ETM support may be buggy, and at least some @command{etm config}
  4285. parameters should be detected by asking the ETM for them.
  4286. It seems like a GDB hookup should be possible,
  4287. as well as triggering trace on specific events
  4288. (perhaps @emph{handling IRQ 23} or @emph{calls foo()}).
  4289. There should be GUI tools to manipulate saved trace data and help
  4290. analyse it in conjunction with the source code.
  4291. It's unclear how much of a common interface is shared
  4292. with the current XScale trace support, or should be
  4293. shared with eventual Nexus-style trace module support.
  4294. At this writing (September 2009) only ARM7 and ARM9 support
  4295. for ETM modules is available. The code should be able to
  4296. work with some newer cores; but not all of them support
  4297. this original style of JTAG access.
  4298. @end quotation
  4299. @subsection ETM Configuration
  4300. ETM setup is coupled with the trace port driver configuration.
  4301. @deffn {Config Command} {etm config} target width mode clocking driver
  4302. Declares the ETM associated with @var{target}, and associates it
  4303. with a given trace port @var{driver}. @xref{Trace Port Drivers}.
  4304. Several of the parameters must reflect the trace port configuration.
  4305. The @var{width} must be either 4, 8, or 16.
  4306. The @var{mode} must be @option{normal}, @option{multiplexted},
  4307. or @option{demultiplexted}.
  4308. The @var{clocking} must be @option{half} or @option{full}.
  4309. @quotation Note
  4310. You can see the ETM registers using the @command{reg} command.
  4311. Not all possible registers are present in every ETM.
  4312. Most of the registers are write-only, and are used to configure
  4313. what CPU activities are traced.
  4314. @end quotation
  4315. @end deffn
  4316. @deffn Command {etm info}
  4317. Displays information about the current target's ETM.
  4318. @end deffn
  4319. @deffn Command {etm status}
  4320. Displays status of the current target's ETM and trace port driver:
  4321. is the ETM idle, or is it collecting data?
  4322. Did trace data overflow?
  4323. Was it triggered?
  4324. @end deffn
  4325. @deffn Command {etm tracemode} [type context_id_bits cycle_accurate branch_output]
  4326. Displays what data that ETM will collect.
  4327. If arguments are provided, first configures that data.
  4328. When the configuration changes, tracing is stopped
  4329. and any buffered trace data is invalidated.
  4330. @itemize
  4331. @item @var{type} ... describing how data accesses are traced,
  4332. when they pass any ViewData filtering that that was set up.
  4333. The value is one of
  4334. @option{none} (save nothing),
  4335. @option{data} (save data),
  4336. @option{address} (save addresses),
  4337. @option{all} (save data and addresses)
  4338. @item @var{context_id_bits} ... 0, 8, 16, or 32
  4339. @item @var{cycle_accurate} ... @option{enable} or @option{disable}
  4340. cycle-accurate instruction tracing.
  4341. Before ETMv3, enabling this causes much extra data to be recorded.
  4342. @item @var{branch_output} ... @option{enable} or @option{disable}.
  4343. Disable this unless you need to try reconstructing the instruction
  4344. trace stream without an image of the code.
  4345. @end itemize
  4346. @end deffn
  4347. @deffn Command {etm trigger_percent} [percent]
  4348. This displays, or optionally changes, the trace port driver's
  4349. behavior after the ETM's configured @emph{trigger} event fires.
  4350. It controls how much more trace data is saved after the (single)
  4351. trace trigger becomes active.
  4352. @itemize
  4353. @item The default corresponds to @emph{trace around} usage,
  4354. recording 50 percent data before the event and the rest
  4355. afterwards.
  4356. @item The minimum value of @var{percent} is 2 percent,
  4357. recording almost exclusively data before the trigger.
  4358. Such extreme @emph{trace before} usage can help figure out
  4359. what caused that event to happen.
  4360. @item The maximum value of @var{percent} is 100 percent,
  4361. recording data almost exclusively after the event.
  4362. This extreme @emph{trace after} usage might help sort out
  4363. how the event caused trouble.
  4364. @end itemize
  4365. @c REVISIT allow "break" too -- enter debug mode.
  4366. @end deffn
  4367. @subsection ETM Trace Operation
  4368. After setting up the ETM, you can use it to collect data.
  4369. That data can be exported to files for later analysis.
  4370. It can also be parsed with OpenOCD, for basic sanity checking.
  4371. To configure what is being traced, you will need to write
  4372. various trace registers using @command{reg ETM_*} commands.
  4373. For the definitions of these registers, read ARM publication
  4374. @emph{IHI 0014, ``Embedded Trace Macrocell, Architecture Specification''}.
  4375. Be aware that most of the relevant registers are write-only,
  4376. and that ETM resources are limited. There are only a handful
  4377. of address comparators, data comparators, counters, and so on.
  4378. Examples of scenarios you might arrange to trace include:
  4379. @itemize
  4380. @item Code flow within a function, @emph{excluding} subroutines
  4381. it calls. Use address range comparators to enable tracing
  4382. for instruction access within that function's body.
  4383. @item Code flow within a function, @emph{including} subroutines
  4384. it calls. Use the sequencer and address comparators to activate
  4385. tracing on an ``entered function'' state, then deactivate it by
  4386. exiting that state when the function's exit code is invoked.
  4387. @item Code flow starting at the fifth invocation of a function,
  4388. combining one of the above models with a counter.
  4389. @item CPU data accesses to the registers for a particular device,
  4390. using address range comparators and the ViewData logic.
  4391. @item Such data accesses only during IRQ handling, combining the above
  4392. model with sequencer triggers which on entry and exit to the IRQ handler.
  4393. @item @emph{... more}
  4394. @end itemize
  4395. At this writing, September 2009, there are no Tcl utility
  4396. procedures to help set up any common tracing scenarios.
  4397. @deffn Command {etm analyze}
  4398. Reads trace data into memory, if it wasn't already present.
  4399. Decodes and prints the data that was collected.
  4400. @end deffn
  4401. @deffn Command {etm dump} filename
  4402. Stores the captured trace data in @file{filename}.
  4403. @end deffn
  4404. @deffn Command {etm image} filename [base_address] [type]
  4405. Opens an image file.
  4406. @end deffn
  4407. @deffn Command {etm load} filename
  4408. Loads captured trace data from @file{filename}.
  4409. @end deffn
  4410. @deffn Command {etm start}
  4411. Starts trace data collection.
  4412. @end deffn
  4413. @deffn Command {etm stop}
  4414. Stops trace data collection.
  4415. @end deffn
  4416. @anchor{Trace Port Drivers}
  4417. @subsection Trace Port Drivers
  4418. To use an ETM trace port it must be associated with a driver.
  4419. @deffn {Trace Port Driver} dummy
  4420. Use the @option{dummy} driver if you are configuring an ETM that's
  4421. not connected to anything (on-chip ETB or off-chip trace connector).
  4422. @emph{This driver lets OpenOCD talk to the ETM, but it does not expose
  4423. any trace data collection.}
  4424. @deffn {Config Command} {etm_dummy config} target
  4425. Associates the ETM for @var{target} with a dummy driver.
  4426. @end deffn
  4427. @end deffn
  4428. @deffn {Trace Port Driver} etb
  4429. Use the @option{etb} driver if you are configuring an ETM
  4430. to use on-chip ETB memory.
  4431. @deffn {Config Command} {etb config} target etb_tap
  4432. Associates the ETM for @var{target} with the ETB at @var{etb_tap}.
  4433. You can see the ETB registers using the @command{reg} command.
  4434. @end deffn
  4435. @end deffn
  4436. @deffn {Trace Port Driver} oocd_trace
  4437. This driver isn't available unless OpenOCD was explicitly configured
  4438. with the @option{--enable-oocd_trace} option. You probably don't want
  4439. to configure it unless you've built the appropriate prototype hardware;
  4440. it's @emph{proof-of-concept} software.
  4441. Use the @option{oocd_trace} driver if you are configuring an ETM that's
  4442. connected to an off-chip trace connector.
  4443. @deffn {Config Command} {oocd_trace config} target tty
  4444. Associates the ETM for @var{target} with a trace driver which
  4445. collects data through the serial port @var{tty}.
  4446. @end deffn
  4447. @deffn Command {oocd_trace resync}
  4448. Re-synchronizes with the capture clock.
  4449. @end deffn
  4450. @deffn Command {oocd_trace status}
  4451. Reports whether the capture clock is locked or not.
  4452. @end deffn
  4453. @end deffn
  4454. @section ARMv4 and ARMv5 Architecture
  4455. @cindex ARMv4
  4456. @cindex ARMv5
  4457. These commands are specific to ARM architecture v4 and v5,
  4458. including all ARM7 or ARM9 systems and Intel XScale.
  4459. They are available in addition to other core-specific
  4460. commands that may be available.
  4461. @deffn Command {armv4_5 core_state} [@option{arm}|@option{thumb}]
  4462. Displays the core_state, optionally changing it to process
  4463. either @option{arm} or @option{thumb} instructions.
  4464. The target may later be resumed in the currently set core_state.
  4465. (Processors may also support the Jazelle state, but
  4466. that is not currently supported in OpenOCD.)
  4467. @end deffn
  4468. @deffn Command {armv4_5 disassemble} address [count [@option{thumb}]]
  4469. @cindex disassemble
  4470. Disassembles @var{count} instructions starting at @var{address}.
  4471. If @var{count} is not specified, a single instruction is disassembled.
  4472. If @option{thumb} is specified, or the low bit of the address is set,
  4473. Thumb (16-bit) instructions are used;
  4474. else ARM (32-bit) instructions are used.
  4475. (Processors may also support the Jazelle state, but
  4476. those instructions are not currently understood by OpenOCD.)
  4477. @end deffn
  4478. @deffn Command {armv4_5 reg}
  4479. Display a table of all banked core registers, fetching the current value from every
  4480. core mode if necessary. OpenOCD versions before rev. 60 didn't fetch the current
  4481. register value.
  4482. @end deffn
  4483. @subsection ARM7 and ARM9 specific commands
  4484. @cindex ARM7
  4485. @cindex ARM9
  4486. These commands are specific to ARM7 and ARM9 cores, like ARM7TDMI, ARM720T,
  4487. ARM9TDMI, ARM920T or ARM926EJ-S.
  4488. They are available in addition to the ARMv4/5 commands,
  4489. and any other core-specific commands that may be available.
  4490. @deffn Command {arm7_9 dbgrq} (@option{enable}|@option{disable})
  4491. Control use of the EmbeddedIce DBGRQ signal to force entry into debug mode,
  4492. instead of breakpoints. This should be
  4493. safe for all but ARM7TDMI--S cores (like Philips LPC).
  4494. This feature is enabled by default on most ARM9 cores,
  4495. including ARM9TDMI, ARM920T, and ARM926EJ-S.
  4496. @end deffn
  4497. @deffn Command {arm7_9 dcc_downloads} (@option{enable}|@option{disable})
  4498. @cindex DCC
  4499. Control the use of the debug communications channel (DCC) to write larger (>128 byte)
  4500. amounts of memory. DCC downloads offer a huge speed increase, but might be
  4501. unsafe, especially with targets running at very low speeds. This command was introduced
  4502. with OpenOCD rev. 60, and requires a few bytes of working area.
  4503. @end deffn
  4504. @anchor{arm7_9 fast_memory_access}
  4505. @deffn Command {arm7_9 fast_memory_access} (@option{enable}|@option{disable})
  4506. Enable or disable memory writes and reads that don't check completion of
  4507. the operation. This provides a huge speed increase, especially with USB JTAG
  4508. cables (FT2232), but might be unsafe if used with targets running at very low
  4509. speeds, like the 32kHz startup clock of an AT91RM9200.
  4510. @end deffn
  4511. @deffn {Debug Command} {arm7_9 write_core_reg} num mode word
  4512. @emph{This is intended for use while debugging OpenOCD; you probably
  4513. shouldn't use it.}
  4514. Writes a 32-bit @var{word} to register @var{num} (from 0 to 16)
  4515. as used in the specified @var{mode}
  4516. (where e.g. mode 16 is "user" and mode 19 is "supervisor";
  4517. the M4..M0 bits of the PSR).
  4518. Registers 0..15 are the normal CPU registers such as r0(0), r1(1) ... pc(15).
  4519. Register 16 is the mode-specific SPSR,
  4520. unless the specified mode is 0xffffffff (32-bit all-ones)
  4521. in which case register 16 is the CPSR.
  4522. The write goes directly to the CPU, bypassing the register cache.
  4523. @end deffn
  4524. @deffn {Debug Command} {arm7_9 write_xpsr} word (@option{0}|@option{1})
  4525. @emph{This is intended for use while debugging OpenOCD; you probably
  4526. shouldn't use it.}
  4527. If the second parameter is zero, writes @var{word} to the
  4528. Current Program Status register (CPSR).
  4529. Else writes @var{word} to the current mode's Saved PSR (SPSR).
  4530. In both cases, this bypasses the register cache.
  4531. @end deffn
  4532. @deffn {Debug Command} {arm7_9 write_xpsr_im8} byte rotate (@option{0}|@option{1})
  4533. @emph{This is intended for use while debugging OpenOCD; you probably
  4534. shouldn't use it.}
  4535. Writes eight bits to the CPSR or SPSR,
  4536. first rotating them by @math{2*rotate} bits,
  4537. and bypassing the register cache.
  4538. This has lower JTAG overhead than writing the entire CPSR or SPSR
  4539. with @command{arm7_9 write_xpsr}.
  4540. @end deffn
  4541. @subsection ARM720T specific commands
  4542. @cindex ARM720T
  4543. These commands are available to ARM720T based CPUs,
  4544. which are implementations of the ARMv4T architecture
  4545. based on the ARM7TDMI-S integer core.
  4546. They are available in addition to the ARMv4/5 and ARM7/ARM9 commands.
  4547. @deffn Command {arm720t cp15} regnum [value]
  4548. Display cp15 register @var{regnum};
  4549. else if a @var{value} is provided, that value is written to that register.
  4550. @end deffn
  4551. @deffn Command {arm720t mdw_phys} addr [count]
  4552. @deffnx Command {arm720t mdh_phys} addr [count]
  4553. @deffnx Command {arm720t mdb_phys} addr [count]
  4554. Display contents of physical address @var{addr}, as
  4555. 32-bit words (@command{mdw_phys}), 16-bit halfwords (@command{mdh_phys}),
  4556. or 8-bit bytes (@command{mdb_phys}).
  4557. If @var{count} is specified, displays that many units.
  4558. @end deffn
  4559. @deffn Command {arm720t mww_phys} addr word
  4560. @deffnx Command {arm720t mwh_phys} addr halfword
  4561. @deffnx Command {arm720t mwb_phys} addr byte
  4562. Writes the specified @var{word} (32 bits),
  4563. @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
  4564. at the specified physical address @var{addr}.
  4565. @end deffn
  4566. @deffn Command {arm720t virt2phys} va
  4567. Translate a virtual address @var{va} to a physical address
  4568. and display the result.
  4569. @end deffn
  4570. @subsection ARM9 specific commands
  4571. @cindex ARM9
  4572. ARM9-family cores are built around ARM9TDMI or ARM9E (including ARM9EJS)
  4573. integer processors.
  4574. Such cores include the ARM920T, ARM926EJ-S, and ARM966.
  4575. For historical reasons, one command shared by these cores starts
  4576. with the @command{arm9tdmi} prefix.
  4577. This is true even for ARM9E based processors, which implement the
  4578. ARMv5TE architecture instead of ARMv4T.
  4579. @c 9-june-2009: tried this on arm920t, it didn't work.
  4580. @c no-params always lists nothing caught, and that's how it acts.
  4581. @anchor{arm9tdmi vector_catch}
  4582. @deffn Command {arm9tdmi vector_catch} [@option{all}|@option{none}|list]
  4583. @cindex vector_catch
  4584. Vector Catch hardware provides a sort of dedicated breakpoint
  4585. for hardware events such as reset, interrupt, and abort.
  4586. You can use this to conserve normal breakpoint resources,
  4587. so long as you're not concerned with code that branches directly
  4588. to those hardware vectors.
  4589. This always finishes by listing the current configuration.
  4590. If parameters are provided, it first reconfigures the
  4591. vector catch hardware to intercept
  4592. @option{all} of the hardware vectors,
  4593. @option{none} of them,
  4594. or a list with one or more of the following:
  4595. @option{reset} @option{undef} @option{swi} @option{pabt} @option{dabt} @option{reserved}
  4596. @option{irq} @option{fiq}.
  4597. @end deffn
  4598. @subsection ARM920T specific commands
  4599. @cindex ARM920T
  4600. These commands are available to ARM920T based CPUs,
  4601. which are implementations of the ARMv4T architecture
  4602. built using the ARM9TDMI integer core.
  4603. They are available in addition to the ARMv4/5, ARM7/ARM9,
  4604. and ARM9TDMI commands.
  4605. @deffn Command {arm920t cache_info}
  4606. Print information about the caches found. This allows to see whether your target
  4607. is an ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
  4608. @end deffn
  4609. @deffn Command {arm920t cp15} regnum [value]
  4610. Display cp15 register @var{regnum};
  4611. else if a @var{value} is provided, that value is written to that register.
  4612. @end deffn
  4613. @deffn Command {arm920t cp15i} opcode [value [address]]
  4614. Interpreted access using cp15 @var{opcode}.
  4615. If no @var{value} is provided, the result is displayed.
  4616. Else if that value is written using the specified @var{address},
  4617. or using zero if no other address is not provided.
  4618. @end deffn
  4619. @deffn Command {arm920t mdw_phys} addr [count]
  4620. @deffnx Command {arm920t mdh_phys} addr [count]
  4621. @deffnx Command {arm920t mdb_phys} addr [count]
  4622. Display contents of physical address @var{addr}, as
  4623. 32-bit words (@command{mdw_phys}), 16-bit halfwords (@command{mdh_phys}),
  4624. or 8-bit bytes (@command{mdb_phys}).
  4625. If @var{count} is specified, displays that many units.
  4626. @end deffn
  4627. @deffn Command {arm920t mww_phys} addr word
  4628. @deffnx Command {arm920t mwh_phys} addr halfword
  4629. @deffnx Command {arm920t mwb_phys} addr byte
  4630. Writes the specified @var{word} (32 bits),
  4631. @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
  4632. at the specified physical address @var{addr}.
  4633. @end deffn
  4634. @deffn Command {arm920t read_cache} filename
  4635. Dump the content of ICache and DCache to a file named @file{filename}.
  4636. @end deffn
  4637. @deffn Command {arm920t read_mmu} filename
  4638. Dump the content of the ITLB and DTLB to a file named @file{filename}.
  4639. @end deffn
  4640. @deffn Command {arm920t virt2phys} va
  4641. Translate a virtual address @var{va} to a physical address
  4642. and display the result.
  4643. @end deffn
  4644. @subsection ARM926ej-s specific commands
  4645. @cindex ARM926ej-s
  4646. These commands are available to ARM926ej-s based CPUs,
  4647. which are implementations of the ARMv5TEJ architecture
  4648. based on the ARM9EJ-S integer core.
  4649. They are available in addition to the ARMv4/5, ARM7/ARM9,
  4650. and ARM9TDMI commands.
  4651. The Feroceon cores also support these commands, although
  4652. they are not built from ARM926ej-s designs.
  4653. @deffn Command {arm926ejs cache_info}
  4654. Print information about the caches found.
  4655. @end deffn
  4656. @deffn Command {arm926ejs cp15} opcode1 opcode2 CRn CRm regnum [value]
  4657. Accesses cp15 register @var{regnum} using
  4658. @var{opcode1}, @var{opcode2}, @var{CRn}, and @var{CRm}.
  4659. If a @var{value} is provided, that value is written to that register.
  4660. Else that register is read and displayed.
  4661. @end deffn
  4662. @deffn Command {arm926ejs mdw_phys} addr [count]
  4663. @deffnx Command {arm926ejs mdh_phys} addr [count]
  4664. @deffnx Command {arm926ejs mdb_phys} addr [count]
  4665. Display contents of physical address @var{addr}, as
  4666. 32-bit words (@command{mdw_phys}), 16-bit halfwords (@command{mdh_phys}),
  4667. or 8-bit bytes (@command{mdb_phys}).
  4668. If @var{count} is specified, displays that many units.
  4669. @end deffn
  4670. @deffn Command {arm926ejs mww_phys} addr word
  4671. @deffnx Command {arm926ejs mwh_phys} addr halfword
  4672. @deffnx Command {arm926ejs mwb_phys} addr byte
  4673. Writes the specified @var{word} (32 bits),
  4674. @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
  4675. at the specified physical address @var{addr}.
  4676. @end deffn
  4677. @deffn Command {arm926ejs virt2phys} va
  4678. Translate a virtual address @var{va} to a physical address
  4679. and display the result.
  4680. @end deffn
  4681. @subsection ARM966E specific commands
  4682. @cindex ARM966E
  4683. These commands are available to ARM966 based CPUs,
  4684. which are implementations of the ARMv5TE architecture.
  4685. They are available in addition to the ARMv4/5, ARM7/ARM9,
  4686. and ARM9TDMI commands.
  4687. @deffn Command {arm966e cp15} regnum [value]
  4688. Display cp15 register @var{regnum};
  4689. else if a @var{value} is provided, that value is written to that register.
  4690. @end deffn
  4691. @subsection XScale specific commands
  4692. @cindex XScale
  4693. Some notes about the debug implementation on the XScale CPUs:
  4694. The XScale CPU provides a special debug-only mini-instruction cache
  4695. (mini-IC) in which exception vectors and target-resident debug handler
  4696. code are placed by OpenOCD. In order to get access to the CPU, OpenOCD
  4697. must point vector 0 (the reset vector) to the entry of the debug
  4698. handler. However, this means that the complete first cacheline in the
  4699. mini-IC is marked valid, which makes the CPU fetch all exception
  4700. handlers from the mini-IC, ignoring the code in RAM.
  4701. OpenOCD currently does not sync the mini-IC entries with the RAM
  4702. contents (which would fail anyway while the target is running), so
  4703. the user must provide appropriate values using the @code{xscale
  4704. vector_table} command.
  4705. It is recommended to place a pc-relative indirect branch in the vector
  4706. table, and put the branch destination somewhere in memory. Doing so
  4707. makes sure the code in the vector table stays constant regardless of
  4708. code layout in memory:
  4709. @example
  4710. _vectors:
  4711. ldr pc,[pc,#0x100-8]
  4712. ldr pc,[pc,#0x100-8]
  4713. ldr pc,[pc,#0x100-8]
  4714. ldr pc,[pc,#0x100-8]
  4715. ldr pc,[pc,#0x100-8]
  4716. ldr pc,[pc,#0x100-8]
  4717. ldr pc,[pc,#0x100-8]
  4718. ldr pc,[pc,#0x100-8]
  4719. .org 0x100
  4720. .long real_reset_vector
  4721. .long real_ui_handler
  4722. .long real_swi_handler
  4723. .long real_pf_abort
  4724. .long real_data_abort
  4725. .long 0 /* unused */
  4726. .long real_irq_handler
  4727. .long real_fiq_handler
  4728. @end example
  4729. The debug handler must be placed somewhere in the address space using
  4730. the @code{xscale debug_handler} command. The allowed locations for the
  4731. debug handler are either (0x800 - 0x1fef800) or (0xfe000800 -
  4732. 0xfffff800). The default value is 0xfe000800.
  4733. These commands are available to XScale based CPUs,
  4734. which are implementations of the ARMv5TE architecture.
  4735. @deffn Command {xscale analyze_trace}
  4736. Displays the contents of the trace buffer.
  4737. @end deffn
  4738. @deffn Command {xscale cache_clean_address} address
  4739. Changes the address used when cleaning the data cache.
  4740. @end deffn
  4741. @deffn Command {xscale cache_info}
  4742. Displays information about the CPU caches.
  4743. @end deffn
  4744. @deffn Command {xscale cp15} regnum [value]
  4745. Display cp15 register @var{regnum};
  4746. else if a @var{value} is provided, that value is written to that register.
  4747. @end deffn
  4748. @deffn Command {xscale debug_handler} target address
  4749. Changes the address used for the specified target's debug handler.
  4750. @end deffn
  4751. @deffn Command {xscale dcache} (@option{enable}|@option{disable})
  4752. Enables or disable the CPU's data cache.
  4753. @end deffn
  4754. @deffn Command {xscale dump_trace} filename
  4755. Dumps the raw contents of the trace buffer to @file{filename}.
  4756. @end deffn
  4757. @deffn Command {xscale icache} (@option{enable}|@option{disable})
  4758. Enables or disable the CPU's instruction cache.
  4759. @end deffn
  4760. @deffn Command {xscale mmu} (@option{enable}|@option{disable})
  4761. Enables or disable the CPU's memory management unit.
  4762. @end deffn
  4763. @deffn Command {xscale trace_buffer} (@option{enable}|@option{disable}) [@option{fill} [n] | @option{wrap}]
  4764. Enables or disables the trace buffer,
  4765. and controls how it is emptied.
  4766. @end deffn
  4767. @deffn Command {xscale trace_image} filename [offset [type]]
  4768. Opens a trace image from @file{filename}, optionally rebasing
  4769. its segment addresses by @var{offset}.
  4770. The image @var{type} may be one of
  4771. @option{bin} (binary), @option{ihex} (Intel hex),
  4772. @option{elf} (ELF file), @option{s19} (Motorola s19),
  4773. @option{mem}, or @option{builder}.
  4774. @end deffn
  4775. @anchor{xscale vector_catch}
  4776. @deffn Command {xscale vector_catch} [mask]
  4777. @cindex vector_catch
  4778. Display a bitmask showing the hardware vectors to catch.
  4779. If the optional parameter is provided, first set the bitmask to that value.
  4780. The mask bits correspond with bit 16..23 in the DCSR:
  4781. @example
  4782. 0x01 Trap Reset
  4783. 0x02 Trap Undefined Instructions
  4784. 0x04 Trap Software Interrupt
  4785. 0x08 Trap Prefetch Abort
  4786. 0x10 Trap Data Abort
  4787. 0x20 reserved
  4788. 0x40 Trap IRQ
  4789. 0x80 Trap FIQ
  4790. @end example
  4791. @end deffn
  4792. @anchor{xscale vector_table}
  4793. @deffn Command {xscale vector_table} [<low|high> <index> <value>]
  4794. @cindex vector_table
  4795. Set an entry in the mini-IC vector table. There are two tables: one for
  4796. low vectors (at 0x00000000), and one for high vectors (0xFFFF0000), each
  4797. holding the 8 exception vectors. @var{index} can be 1-7, because vector 0
  4798. points to the debug handler entry and can not be overwritten.
  4799. @var{value} holds the 32-bit opcode that is placed in the mini-IC.
  4800. Without arguments, the current settings are displayed.
  4801. @end deffn
  4802. @section ARMv6 Architecture
  4803. @cindex ARMv6
  4804. @subsection ARM11 specific commands
  4805. @cindex ARM11
  4806. @deffn Command {arm11 mcr} pX opc1 CRn CRm opc2 value
  4807. Write @var{value} to a coprocessor @var{pX} register
  4808. passing parameters @var{CRn},
  4809. @var{CRm}, opcodes @var{opc1} and @var{opc2},
  4810. and the MCR instruction.
  4811. (The difference beween this and the MCR2 instruction is
  4812. one bit in the encoding, effecively a fifth parameter.)
  4813. @end deffn
  4814. @deffn Command {arm11 memwrite burst} [value]
  4815. Displays the value of the memwrite burst-enable flag,
  4816. which is enabled by default. Burst writes are only used
  4817. for memory writes larger than 1 word. Single word writes
  4818. are likely to be from reset init scripts and those writes
  4819. are often to non-memory locations which could easily have
  4820. many wait states, which could easily break burst writes.
  4821. If @var{value} is defined, first assigns that.
  4822. @end deffn
  4823. @deffn Command {arm11 memwrite error_fatal} [value]
  4824. Displays the value of the memwrite error_fatal flag,
  4825. which is enabled by default.
  4826. If @var{value} is defined, first assigns that.
  4827. @end deffn
  4828. @deffn Command {arm11 mrc} pX opc1 CRn CRm opc2
  4829. Read a coprocessor @var{pX} register passing parameters @var{CRn},
  4830. @var{CRm}, opcodes @var{opc1} and @var{opc2},
  4831. and the MRC instruction.
  4832. (The difference beween this and the MRC2 instruction is
  4833. one bit in the encoding, effecively a fifth parameter.)
  4834. Displays the result.
  4835. @end deffn
  4836. @deffn Command {arm11 step_irq_enable} [value]
  4837. Displays the value of the flag controlling whether
  4838. IRQs are enabled during single stepping;
  4839. they are disabled by default.
  4840. If @var{value} is defined, first assigns that.
  4841. @end deffn
  4842. @deffn Command {arm11 vcr} [value]
  4843. @cindex vector_catch
  4844. Displays the value of the @emph{Vector Catch Register (VCR)},
  4845. coprocessor 14 register 7.
  4846. If @var{value} is defined, first assigns that.
  4847. Vector Catch hardware provides dedicated breakpoints
  4848. for certain hardware events.
  4849. The specific bit values are core-specific (as in fact is using
  4850. coprocessor 14 register 7 itself) but all current ARM11
  4851. cores @emph{except the ARM1176} use the same six bits.
  4852. @end deffn
  4853. @section ARMv7 Architecture
  4854. @cindex ARMv7
  4855. @subsection ARMv7 Debug Access Port (DAP) specific commands
  4856. @cindex Debug Access Port
  4857. @cindex DAP
  4858. These commands are specific to ARM architecture v7 Debug Access Port (DAP),
  4859. included on cortex-m3 and cortex-a8 systems.
  4860. They are available in addition to other core-specific commands that may be available.
  4861. @deffn Command {dap info} [num]
  4862. Displays dap info for ap @var{num}, defaulting to the currently selected AP.
  4863. @end deffn
  4864. @deffn Command {dap apsel} [num]
  4865. Select AP @var{num}, defaulting to 0.
  4866. @end deffn
  4867. @deffn Command {dap apid} [num]
  4868. Displays id register from AP @var{num},
  4869. defaulting to the currently selected AP.
  4870. @end deffn
  4871. @deffn Command {dap baseaddr} [num]
  4872. Displays debug base address from AP @var{num},
  4873. defaulting to the currently selected AP.
  4874. @end deffn
  4875. @deffn Command {dap memaccess} [value]
  4876. Displays the number of extra tck for mem-ap memory bus access [0-255].
  4877. If @var{value} is defined, first assigns that.
  4878. @end deffn
  4879. @subsection ARMv7-A specific commands
  4880. @cindex ARMv7-A
  4881. @deffn Command {armv7a disassemble} address [count [@option{thumb}]]
  4882. @cindex disassemble
  4883. Disassembles @var{count} instructions starting at @var{address}.
  4884. If @var{count} is not specified, a single instruction is disassembled.
  4885. If @option{thumb} is specified, or the low bit of the address is set,
  4886. Thumb2 (mixed 16/32-bit) instructions are used;
  4887. else ARM (32-bit) instructions are used.
  4888. With a handful of exceptions, ThumbEE instructions are the same as Thumb2;
  4889. ThumbEE disassembly currently has no explicit support.
  4890. (Processors may also support the Jazelle state, but
  4891. those instructions are not currently understood by OpenOCD.)
  4892. @end deffn
  4893. @subsection Cortex-M3 specific commands
  4894. @cindex Cortex-M3
  4895. @deffn Command {cortex_m3 disassemble} address [count]
  4896. @cindex disassemble
  4897. Disassembles @var{count} Thumb2 instructions starting at @var{address}.
  4898. If @var{count} is not specified, a single instruction is disassembled.
  4899. @end deffn
  4900. @deffn Command {cortex_m3 maskisr} (@option{on}|@option{off})
  4901. Control masking (disabling) interrupts during target step/resume.
  4902. @end deffn
  4903. @deffn Command {cortex_m3 vector_catch} [@option{all}|@option{none}|list]
  4904. @cindex vector_catch
  4905. Vector Catch hardware provides dedicated breakpoints
  4906. for certain hardware events.
  4907. Parameters request interception of
  4908. @option{all} of these hardware event vectors,
  4909. @option{none} of them,
  4910. or one or more of the following:
  4911. @option{hard_err} for a HardFault exception;
  4912. @option{mm_err} for a MemManage exception;
  4913. @option{bus_err} for a BusFault exception;
  4914. @option{irq_err},
  4915. @option{state_err},
  4916. @option{chk_err}, or
  4917. @option{nocp_err} for various UsageFault exceptions; or
  4918. @option{reset}.
  4919. If NVIC setup code does not enable them,
  4920. MemManage, BusFault, and UsageFault exceptions
  4921. are mapped to HardFault.
  4922. UsageFault checks for
  4923. divide-by-zero and unaligned access
  4924. must also be explicitly enabled.
  4925. This finishes by listing the current vector catch configuration.
  4926. @end deffn
  4927. @anchor{Software Debug Messages and Tracing}
  4928. @section Software Debug Messages and Tracing
  4929. @cindex Linux-ARM DCC support
  4930. @cindex tracing
  4931. @cindex libdcc
  4932. @cindex DCC
  4933. OpenOCD can process certain requests from target software. Currently
  4934. @command{target_request debugmsgs}
  4935. is supported only for @option{arm7_9} and @option{cortex_m3} cores.
  4936. These messages are received as part of target polling, so
  4937. you need to have @command{poll on} active to receive them.
  4938. They are intrusive in that they will affect program execution
  4939. times. If that is a problem, @pxref{ARM Hardware Tracing}.
  4940. See @file{libdcc} in the contrib dir for more details.
  4941. In addition to sending strings, characters, and
  4942. arrays of various size integers from the target,
  4943. @file{libdcc} also exports a software trace point mechanism.
  4944. The target being debugged may
  4945. issue trace messages which include a 24-bit @dfn{trace point} number.
  4946. Trace point support includes two distinct mechanisms,
  4947. each supported by a command:
  4948. @itemize
  4949. @item @emph{History} ... A circular buffer of trace points
  4950. can be set up, and then displayed at any time.
  4951. This tracks where code has been, which can be invaluable in
  4952. finding out how some fault was triggered.
  4953. The buffer may overflow, since it collects records continuously.
  4954. It may be useful to use some of the 24 bits to represent a
  4955. particular event, and other bits to hold data.
  4956. @item @emph{Counting} ... An array of counters can be set up,
  4957. and then displayed at any time.
  4958. This can help establish code coverage and identify hot spots.
  4959. The array of counters is directly indexed by the trace point
  4960. number, so trace points with higher numbers are not counted.
  4961. @end itemize
  4962. Linux-ARM kernels have a ``Kernel low-level debugging
  4963. via EmbeddedICE DCC channel'' option (CONFIG_DEBUG_ICEDCC,
  4964. depends on CONFIG_DEBUG_LL) which uses this mechanism to
  4965. deliver messages before a serial console can be activated.
  4966. This is not the same format used by @file{libdcc}.
  4967. Other software, such as the U-Boot boot loader, sometimes
  4968. does the same thing.
  4969. @deffn Command {target_request debugmsgs} [@option{enable}|@option{disable}|@option{charmsg}]
  4970. Displays current handling of target DCC message requests.
  4971. These messages may be sent to the debugger while the target is running.
  4972. The optional @option{enable} and @option{charmsg} parameters
  4973. both enable the messages, while @option{disable} disables them.
  4974. With @option{charmsg} the DCC words each contain one character,
  4975. as used by Linux with CONFIG_DEBUG_ICEDCC;
  4976. otherwise the libdcc format is used.
  4977. @end deffn
  4978. @deffn Command {trace history} [@option{clear}|count]
  4979. With no parameter, displays all the trace points that have triggered
  4980. in the order they triggered.
  4981. With the parameter @option{clear}, erases all current trace history records.
  4982. With a @var{count} parameter, allocates space for that many
  4983. history records.
  4984. @end deffn
  4985. @deffn Command {trace point} [@option{clear}|identifier]
  4986. With no parameter, displays all trace point identifiers and how many times
  4987. they have been triggered.
  4988. With the parameter @option{clear}, erases all current trace point counters.
  4989. With a numeric @var{identifier} parameter, creates a new a trace point counter
  4990. and associates it with that identifier.
  4991. @emph{Important:} The identifier and the trace point number
  4992. are not related except by this command.
  4993. These trace point numbers always start at zero (from server startup,
  4994. or after @command{trace point clear}) and count up from there.
  4995. @end deffn
  4996. @node JTAG Commands
  4997. @chapter JTAG Commands
  4998. @cindex JTAG Commands
  4999. Most general purpose JTAG commands have been presented earlier.
  5000. (@xref{JTAG Speed}, @ref{Reset Configuration}, and @ref{TAP Declaration}.)
  5001. Lower level JTAG commands, as presented here,
  5002. may be needed to work with targets which require special
  5003. attention during operations such as reset or initialization.
  5004. To use these commands you will need to understand some
  5005. of the basics of JTAG, including:
  5006. @itemize @bullet
  5007. @item A JTAG scan chain consists of a sequence of individual TAP
  5008. devices such as a CPUs.
  5009. @item Control operations involve moving each TAP through the same
  5010. standard state machine (in parallel)
  5011. using their shared TMS and clock signals.
  5012. @item Data transfer involves shifting data through the chain of
  5013. instruction or data registers of each TAP, writing new register values
  5014. while the reading previous ones.
  5015. @item Data register sizes are a function of the instruction active in
  5016. a given TAP, while instruction register sizes are fixed for each TAP.
  5017. All TAPs support a BYPASS instruction with a single bit data register.
  5018. @item The way OpenOCD differentiates between TAP devices is by
  5019. shifting different instructions into (and out of) their instruction
  5020. registers.
  5021. @end itemize
  5022. @section Low Level JTAG Commands
  5023. These commands are used by developers who need to access
  5024. JTAG instruction or data registers, possibly controlling
  5025. the order of TAP state transitions.
  5026. If you're not debugging OpenOCD internals, or bringing up a
  5027. new JTAG adapter or a new type of TAP device (like a CPU or
  5028. JTAG router), you probably won't need to use these commands.
  5029. @deffn Command {drscan} tap [numbits value]+ [@option{-endstate} tap_state]
  5030. Loads the data register of @var{tap} with a series of bit fields
  5031. that specify the entire register.
  5032. Each field is @var{numbits} bits long with
  5033. a numeric @var{value} (hexadecimal encouraged).
  5034. The return value holds the original value of each
  5035. of those fields.
  5036. For example, a 38 bit number might be specified as one
  5037. field of 32 bits then one of 6 bits.
  5038. @emph{For portability, never pass fields which are more
  5039. than 32 bits long. Many OpenOCD implementations do not
  5040. support 64-bit (or larger) integer values.}
  5041. All TAPs other than @var{tap} must be in BYPASS mode.
  5042. The single bit in their data registers does not matter.
  5043. When @var{tap_state} is specified, the JTAG state machine is left
  5044. in that state.
  5045. For example @sc{drpause} might be specified, so that more
  5046. instructions can be issued before re-entering the @sc{run/idle} state.
  5047. If the end state is not specified, the @sc{run/idle} state is entered.
  5048. @quotation Warning
  5049. OpenOCD does not record information about data register lengths,
  5050. so @emph{it is important that you get the bit field lengths right}.
  5051. Remember that different JTAG instructions refer to different
  5052. data registers, which may have different lengths.
  5053. Moreover, those lengths may not be fixed;
  5054. the SCAN_N instruction can change the length of
  5055. the register accessed by the INTEST instruction
  5056. (by connecting a different scan chain).
  5057. @end quotation
  5058. @end deffn
  5059. @deffn Command {flush_count}
  5060. Returns the number of times the JTAG queue has been flushed.
  5061. This may be used for performance tuning.
  5062. For example, flushing a queue over USB involves a
  5063. minimum latency, often several milliseconds, which does
  5064. not change with the amount of data which is written.
  5065. You may be able to identify performance problems by finding
  5066. tasks which waste bandwidth by flushing small transfers too often,
  5067. instead of batching them into larger operations.
  5068. @end deffn
  5069. @deffn Command {irscan} [tap instruction]+ [@option{-endstate} tap_state]
  5070. For each @var{tap} listed, loads the instruction register
  5071. with its associated numeric @var{instruction}.
  5072. (The number of bits in that instruction may be displayed
  5073. using the @command{scan_chain} command.)
  5074. For other TAPs, a BYPASS instruction is loaded.
  5075. When @var{tap_state} is specified, the JTAG state machine is left
  5076. in that state.
  5077. For example @sc{irpause} might be specified, so the data register
  5078. can be loaded before re-entering the @sc{run/idle} state.
  5079. If the end state is not specified, the @sc{run/idle} state is entered.
  5080. @quotation Note
  5081. OpenOCD currently supports only a single field for instruction
  5082. register values, unlike data register values.
  5083. For TAPs where the instruction register length is more than 32 bits,
  5084. portable scripts currently must issue only BYPASS instructions.
  5085. @end quotation
  5086. @end deffn
  5087. @deffn Command {jtag_reset} trst srst
  5088. Set values of reset signals.
  5089. The @var{trst} and @var{srst} parameter values may be
  5090. @option{0}, indicating that reset is inactive (pulled or driven high),
  5091. or @option{1}, indicating it is active (pulled or driven low).
  5092. The @command{reset_config} command should already have been used
  5093. to configure how the board and JTAG adapter treat these two
  5094. signals, and to say if either signal is even present.
  5095. @xref{Reset Configuration}.
  5096. Note that TRST is specially handled.
  5097. It actually signifies JTAG's @sc{reset} state.
  5098. So if the board doesn't support the optional TRST signal,
  5099. or it doesn't support it along with the specified SRST value,
  5100. JTAG reset is triggered with TMS and TCK signals
  5101. instead of the TRST signal.
  5102. And no matter how that JTAG reset is triggered, once
  5103. the scan chain enters @sc{reset} with TRST inactive,
  5104. TAP @code{post-reset} events are delivered to all TAPs
  5105. with handlers for that event.
  5106. @end deffn
  5107. @deffn Command {pathmove} start_state [next_state ...]
  5108. Start by moving to @var{start_state}, which
  5109. must be one of the @emph{stable} states.
  5110. Then, in a series of single state transitions
  5111. (conforming to the JTAG state machine) shift to
  5112. each @var{next_state} in sequence, one per TCK cycle.
  5113. The final state must also be stable.
  5114. @end deffn
  5115. @deffn Command {runtest} @var{num_cycles}
  5116. Move to the @sc{run/idle} state, and execute at least
  5117. @var{num_cycles} of the JTAG clock (TCK).
  5118. Instructions often need some time
  5119. to execute before they take effect.
  5120. @end deffn
  5121. @c tms_sequence (short|long)
  5122. @c ... temporary, debug-only, probably gone before 0.2 ships
  5123. @deffn Command {verify_ircapture} (@option{enable}|@option{disable})
  5124. Verify values captured during @sc{ircapture} and returned
  5125. during IR scans. Default is enabled, but this can be
  5126. overridden by @command{verify_jtag}.
  5127. @end deffn
  5128. @deffn Command {verify_jtag} (@option{enable}|@option{disable})
  5129. Enables verification of DR and IR scans, to help detect
  5130. programming errors. For IR scans, @command{verify_ircapture}
  5131. must also be enabled.
  5132. Default is enabled.
  5133. @end deffn
  5134. @section TAP state names
  5135. @cindex TAP state names
  5136. The @var{tap_state} names used by OpenOCD in the @command{drscan},
  5137. @command{irscan}, and @command{pathmove} commands are the same
  5138. as those used in SVF boundary scan documents, except that some
  5139. versions of SVF use @sc{idle} instead of @sc{run/idle}.
  5140. @itemize @bullet
  5141. @item @b{RESET} ... @emph{stable} (with TMS high);
  5142. acts as if TRST were pulsed
  5143. @item @b{RUN/IDLE} ... @emph{stable}; don't assume this always means IDLE
  5144. @item @b{DRSELECT}
  5145. @item @b{DRCAPTURE}
  5146. @item @b{DRSHIFT} ... @emph{stable}; TDI/TDO shifting
  5147. through the data register
  5148. @item @b{DREXIT1}
  5149. @item @b{DRPAUSE} ... @emph{stable}; data register ready
  5150. for update or more shifting
  5151. @item @b{DREXIT2}
  5152. @item @b{DRUPDATE}
  5153. @item @b{IRSELECT}
  5154. @item @b{IRCAPTURE}
  5155. @item @b{IRSHIFT} ... @emph{stable}; TDI/TDO shifting
  5156. through the instruction register
  5157. @item @b{IREXIT1}
  5158. @item @b{IRPAUSE} ... @emph{stable}; instruction register ready
  5159. for update or more shifting
  5160. @item @b{IREXIT2}
  5161. @item @b{IRUPDATE}
  5162. @end itemize
  5163. Note that only six of those states are fully ``stable'' in the
  5164. face of TMS fixed (low except for @sc{reset})
  5165. and a free-running JTAG clock. For all the
  5166. others, the next TCK transition changes to a new state.
  5167. @itemize @bullet
  5168. @item From @sc{drshift} and @sc{irshift}, clock transitions will
  5169. produce side effects by changing register contents. The values
  5170. to be latched in upcoming @sc{drupdate} or @sc{irupdate} states
  5171. may not be as expected.
  5172. @item @sc{run/idle}, @sc{drpause}, and @sc{irpause} are reasonable
  5173. choices after @command{drscan} or @command{irscan} commands,
  5174. since they are free of JTAG side effects.
  5175. @item @sc{run/idle} may have side effects that appear at non-JTAG
  5176. levels, such as advancing the ARM9E-S instruction pipeline.
  5177. Consult the documentation for the TAP(s) you are working with.
  5178. @end itemize
  5179. @node Boundary Scan Commands
  5180. @chapter Boundary Scan Commands
  5181. One of the original purposes of JTAG was to support
  5182. boundary scan based hardware testing.
  5183. Although its primary focus is to support On-Chip Debugging,
  5184. OpenOCD also includes some boundary scan commands.
  5185. @section SVF: Serial Vector Format
  5186. @cindex Serial Vector Format
  5187. @cindex SVF
  5188. The Serial Vector Format, better known as @dfn{SVF}, is a
  5189. way to represent JTAG test patterns in text files.
  5190. OpenOCD supports running such test files.
  5191. @deffn Command {svf} filename [@option{quiet}]
  5192. This issues a JTAG reset (Test-Logic-Reset) and then
  5193. runs the SVF script from @file{filename}.
  5194. Unless the @option{quiet} option is specified,
  5195. each command is logged before it is executed.
  5196. @end deffn
  5197. @section XSVF: Xilinx Serial Vector Format
  5198. @cindex Xilinx Serial Vector Format
  5199. @cindex XSVF
  5200. The Xilinx Serial Vector Format, better known as @dfn{XSVF}, is a
  5201. binary representation of SVF which is optimized for use with
  5202. Xilinx devices.
  5203. OpenOCD supports running such test files.
  5204. @quotation Important
  5205. Not all XSVF commands are supported.
  5206. @end quotation
  5207. @deffn Command {xsvf} (tapname|@option{plain}) filename [@option{virt2}] [@option{quiet}]
  5208. This issues a JTAG reset (Test-Logic-Reset) and then
  5209. runs the XSVF script from @file{filename}.
  5210. When a @var{tapname} is specified, the commands are directed at
  5211. that TAP.
  5212. When @option{virt2} is specified, the @sc{xruntest} command counts
  5213. are interpreted as TCK cycles instead of microseconds.
  5214. Unless the @option{quiet} option is specified,
  5215. messages are logged for comments and some retries.
  5216. @end deffn
  5217. @node TFTP
  5218. @chapter TFTP
  5219. @cindex TFTP
  5220. If OpenOCD runs on an embedded host(as ZY1000 does), then TFTP can
  5221. be used to access files on PCs (either the developer's PC or some other PC).
  5222. The way this works on the ZY1000 is to prefix a filename by
  5223. "/tftp/ip/" and append the TFTP path on the TFTP
  5224. server (tftpd). For example,
  5225. @example
  5226. load_image /tftp/\temp\abc.elf
  5227. @end example
  5228. will load c:\temp\abc.elf from the developer pc ( into memory as
  5229. if the file was hosted on the embedded host.
  5230. In order to achieve decent performance, you must choose a TFTP server
  5231. that supports a packet size bigger than the default packet size (512 bytes). There
  5232. are numerous TFTP servers out there (free and commercial) and you will have to do
  5233. a bit of googling to find something that fits your requirements.
  5234. @node GDB and OpenOCD
  5235. @chapter GDB and OpenOCD
  5236. @cindex GDB
  5237. OpenOCD complies with the remote gdbserver protocol, and as such can be used
  5238. to debug remote targets.
  5239. @anchor{Connecting to GDB}
  5240. @section Connecting to GDB
  5241. @cindex Connecting to GDB
  5242. Use GDB 6.7 or newer with OpenOCD if you run into trouble. For
  5243. instance GDB 6.3 has a known bug that produces bogus memory access
  5244. errors, which has since been fixed: look up 1836 in
  5245. @url{}
  5246. OpenOCD can communicate with GDB in two ways:
  5247. @enumerate
  5248. @item
  5249. A socket (TCP/IP) connection is typically started as follows:
  5250. @example
  5251. target remote localhost:3333
  5252. @end example
  5253. This would cause GDB to connect to the gdbserver on the local pc using port 3333.
  5254. @item
  5255. A pipe connection is typically started as follows:
  5256. @example
  5257. target remote | openocd --pipe
  5258. @end example
  5259. This would cause GDB to run OpenOCD and communicate using pipes (stdin/stdout).
  5260. Using this method has the advantage of GDB starting/stopping OpenOCD for the debug
  5261. session.
  5262. @end enumerate
  5263. To list the available OpenOCD commands type @command{monitor help} on the
  5264. GDB command line.
  5265. OpenOCD supports the gdb @option{qSupported} packet, this enables information
  5266. to be sent by the GDB remote server (i.e. OpenOCD) to GDB. Typical information includes
  5267. packet size and the device's memory map.
  5268. Previous versions of OpenOCD required the following GDB options to increase
  5269. the packet size and speed up GDB communication:
  5270. @example
  5271. set remote memory-write-packet-size 1024
  5272. set remote memory-write-packet-size fixed
  5273. set remote memory-read-packet-size 1024
  5274. set remote memory-read-packet-size fixed
  5275. @end example
  5276. This is now handled in the @option{qSupported} PacketSize and should not be required.
  5277. @section Programming using GDB
  5278. @cindex Programming using GDB
  5279. By default the target memory map is sent to GDB. This can be disabled by
  5280. the following OpenOCD configuration option:
  5281. @example
  5282. gdb_memory_map disable
  5283. @end example
  5284. For this to function correctly a valid flash configuration must also be set
  5285. in OpenOCD. For faster performance you should also configure a valid
  5286. working area.
  5287. Informing GDB of the memory map of the target will enable GDB to protect any
  5288. flash areas of the target and use hardware breakpoints by default. This means
  5289. that the OpenOCD option @command{gdb_breakpoint_override} is not required when
  5290. using a memory map. @xref{gdb_breakpoint_override}.
  5291. To view the configured memory map in GDB, use the GDB command @option{info mem}
  5292. All other unassigned addresses within GDB are treated as RAM.
  5293. GDB 6.8 and higher set any memory area not in the memory map as inaccessible.
  5294. This can be changed to the old behaviour by using the following GDB command
  5295. @example
  5296. set mem inaccessible-by-default off
  5297. @end example
  5298. If @command{gdb_flash_program enable} is also used, GDB will be able to
  5299. program any flash memory using the vFlash interface.
  5300. GDB will look at the target memory map when a load command is given, if any
  5301. areas to be programmed lie within the target flash area the vFlash packets
  5302. will be used.
  5303. If the target needs configuring before GDB programming, an event
  5304. script can be executed:
  5305. @example
  5306. $_TARGETNAME configure -event EVENTNAME BODY
  5307. @end example
  5308. To verify any flash programming the GDB command @option{compare-sections}
  5309. can be used.
  5310. @node Tcl Scripting API
  5311. @chapter Tcl Scripting API
  5312. @cindex Tcl Scripting API
  5313. @cindex Tcl scripts
  5314. @section API rules
  5315. The commands are stateless. E.g. the telnet command line has a concept
  5316. of currently active target, the Tcl API proc's take this sort of state
  5317. information as an argument to each proc.
  5318. There are three main types of return values: single value, name value
  5319. pair list and lists.
  5320. Name value pair. The proc 'foo' below returns a name/value pair
  5321. list.
  5322. @verbatim
  5323. > set foo(me) Duane
  5324. > set foo(you) Oyvind
  5325. > set foo(mouse) Micky
  5326. > set foo(duck) Donald
  5327. If one does this:
  5328. > set foo
  5329. The result is:
  5330. me Duane you Oyvind mouse Micky duck Donald
  5331. Thus, to get the names of the associative array is easy:
  5332. foreach { name value } [set foo] {
  5333. puts "Name: $name, Value: $value"
  5334. }
  5335. @end verbatim
  5336. Lists returned must be relatively small. Otherwise a range
  5337. should be passed in to the proc in question.
  5338. @section Internal low-level Commands
  5339. By low-level, the intent is a human would not directly use these commands.
  5340. Low-level commands are (should be) prefixed with "ocd_", e.g.
  5341. @command{ocd_flash_banks}
  5342. is the low level API upon which @command{flash banks} is implemented.
  5343. @itemize @bullet
  5344. @item @b{ocd_mem2array} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
  5345. Read memory and return as a Tcl array for script processing
  5346. @item @b{ocd_array2mem} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
  5347. Convert a Tcl array to memory locations and write the values
  5348. @item @b{ocd_flash_banks} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}> <@var{target}> [@option{driver options} ...]
  5349. Return information about the flash banks
  5350. @end itemize
  5351. OpenOCD commands can consist of two words, e.g. "flash banks". The
  5352. @file{startup.tcl} "unknown" proc will translate this into a Tcl proc
  5353. called "flash_banks".
  5354. @section OpenOCD specific Global Variables
  5355. @subsection HostOS
  5356. Real Tcl has ::tcl_platform(), and platform::identify, and many other
  5357. variables. JimTCL, as implemented in OpenOCD creates $HostOS which
  5358. holds one of the following values:
  5359. @itemize @bullet
  5360. @item @b{winxx} Built using Microsoft Visual Studio
  5361. @item @b{linux} Linux is the underlying operating sytem
  5362. @item @b{darwin} Darwin (mac-os) is the underlying operating sytem.
  5363. @item @b{cygwin} Running under Cygwin
  5364. @item @b{mingw32} Running under MingW32
  5365. @item @b{other} Unknown, none of the above.
  5366. @end itemize
  5367. Note: 'winxx' was choosen because today (March-2009) no distinction is made between Win32 and Win64.
  5368. @quotation Note
  5369. We should add support for a variable like Tcl variable
  5370. @code{tcl_platform(platform)}, it should be called
  5371. @code{jim_platform} (because it
  5372. is jim, not real tcl).
  5373. @end quotation
  5374. @node Upgrading
  5375. @chapter Deprecated/Removed Commands
  5376. @cindex Deprecated/Removed Commands
  5377. Certain OpenOCD commands have been deprecated or
  5378. removed during the various revisions.
  5379. Upgrade your scripts as soon as possible.
  5380. These descriptions for old commands may be removed
  5381. a year after the command itself was removed.
  5382. This means that in January 2010 this chapter may
  5383. become much shorter.
  5384. @itemize @bullet
  5385. @item @b{arm7_9 fast_writes}
  5386. @cindex arm7_9 fast_writes
  5387. @*Use @command{arm7_9 fast_memory_access} instead.
  5388. @xref{arm7_9 fast_memory_access}.
  5389. @item @b{endstate}
  5390. @cindex endstate
  5391. @*An buggy old command that would not really work since background polling would wipe out the global endstate
  5392. @item @b{arm7_9 force_hw_bkpts}
  5393. @*Use @command{gdb_breakpoint_override} instead. Note that GDB will use hardware breakpoints
  5394. for flash if the GDB memory map has been set up(default when flash is declared in
  5395. target configuration). @xref{gdb_breakpoint_override}.
  5396. @item @b{arm7_9 sw_bkpts}
  5397. @*On by default. @xref{gdb_breakpoint_override}.
  5398. @item @b{daemon_startup}
  5399. @*this config option has been removed, simply adding @option{init} and @option{reset halt} to
  5400. the end of your config script will give the same behaviour as using @option{daemon_startup reset}
  5401. and @option{target cortex_m3 little reset_halt 0}.
  5402. @item @b{dump_binary}
  5403. @*use @option{dump_image} command with same args. @xref{dump_image}.
  5404. @item @b{flash erase}
  5405. @*use @option{flash erase_sector} command with same args. @xref{flash erase_sector}.
  5406. @item @b{flash write}
  5407. @*use @option{flash write_bank} command with same args. @xref{flash write_bank}.
  5408. @item @b{flash write_binary}
  5409. @*use @option{flash write_bank} command with same args. @xref{flash write_bank}.
  5410. @item @b{flash auto_erase}
  5411. @*use @option{flash write_image} command passing @option{erase} as the first parameter. @xref{flash write_image}.
  5412. @item @b{jtag_device}
  5413. @*use the @command{jtag newtap} command, converting from positional syntax
  5414. to named prefixes, and naming the TAP.
  5415. @xref{jtag newtap}.
  5416. Note that if you try to use the old command, a message will tell you the
  5417. right new command to use; and that the fourth parameter in the old syntax
  5418. was never actually used.
  5419. @example
  5420. OLD: jtag_device 8 0x01 0xe3 0xfe
  5421. NEW: jtag newtap CHIPNAME TAPNAME \
  5422. -irlen 8 -ircapture 0x01 -irmask 0xe3
  5423. @end example
  5424. @item @b{jtag_speed} value
  5425. @*@xref{JTAG Speed}.
  5426. Usually, a value of zero means maximum
  5427. speed. The actual effect of this option depends on the JTAG interface used.
  5428. @itemize @minus
  5429. @item wiggler: maximum speed / @var{number}
  5430. @item ft2232: 6MHz / (@var{number}+1)
  5431. @item amt jtagaccel: 8 / 2**@var{number}
  5432. @item jlink: maximum speed in kHz (0-12000), 0 will use RTCK
  5433. @item rlink: 24MHz / @var{number}, but only for certain values of @var{number}
  5434. @comment end speed list.
  5435. @end itemize
  5436. @item @b{load_binary}
  5437. @*use @option{load_image} command with same args. @xref{load_image}.
  5438. @item @b{run_and_halt_time}
  5439. @*This command has been removed for simpler reset behaviour, it can be simulated with the
  5440. following commands:
  5441. @smallexample
  5442. reset run
  5443. sleep 100
  5444. halt
  5445. @end smallexample
  5446. @item @b{target} <@var{type}> <@var{endian}> <@var{jtag-position}>
  5447. @*use the create subcommand of @option{target}.
  5448. @item @b{target_script} <@var{target#}> <@var{eventname}> <@var{scriptname}>
  5449. @*use <@var{target_name}> configure -event <@var{eventname}> "script <@var{scriptname}>"
  5450. @item @b{working_area}
  5451. @*use the @option{configure} subcommand of @option{target} to set the work-area-virt, work-area-phy, work-area-size, and work-area-backup properties of the target.
  5452. @end itemize
  5453. @node FAQ
  5454. @chapter FAQ
  5455. @cindex faq
  5456. @enumerate
  5457. @anchor{FAQ RTCK}
  5458. @item @b{RTCK, also known as: Adaptive Clocking - What is it?}
  5459. @cindex RTCK
  5460. @cindex adaptive clocking
  5461. @*
  5462. In digital circuit design it is often refered to as ``clock
  5463. synchronisation'' the JTAG interface uses one clock (TCK or TCLK)
  5464. operating at some speed, your target is operating at another. The two
  5465. clocks are not synchronised, they are ``asynchronous''
  5466. In order for the two to work together they must be synchronised. Otherwise
  5467. the two systems will get out of sync with each other and nothing will
  5468. work. There are 2 basic options:
  5469. @enumerate
  5470. @item
  5471. Use a special circuit.
  5472. @item
  5473. One clock must be some multiple slower than the other.
  5474. @end enumerate
  5475. @b{Does this really matter?} For some chips and some situations, this
  5476. is a non-issue (i.e.: A 500MHz ARM926) but for others - for example some
  5477. Atmel SAM7 and SAM9 chips start operation from reset at 32kHz -
  5478. program/enable the oscillators and eventually the main clock. It is in
  5479. those critical times you must slow the JTAG clock to sometimes 1 to
  5480. 4kHz.
  5481. Imagine debugging a 500MHz ARM926 hand held battery powered device
  5482. that ``deep sleeps'' at 32kHz between every keystroke. It can be
  5483. painful.
  5484. @b{Solution #1 - A special circuit}
  5485. In order to make use of this, your JTAG dongle must support the RTCK
  5486. feature. Not all dongles support this - keep reading!
  5487. The RTCK signal often found in some ARM chips is used to help with
  5488. this problem. ARM has a good description of the problem described at
  5489. this link: @url{} [checked
  5490. 28/nov/2008]. Link title: ``How does the JTAG synchronisation logic
  5491. work? / how does adaptive clocking work?''.
  5492. The nice thing about adaptive clocking is that ``battery powered hand
  5493. held device example'' - the adaptiveness works perfectly all the
  5494. time. One can set a break point or halt the system in the deep power
  5495. down code, slow step out until the system speeds up.
  5496. Note that adaptive clocking may also need to work at the board level,
  5497. when a board-level scan chain has multiple chips.
  5498. Parallel clock voting schemes are good way to implement this,
  5499. both within and between chips, and can easily be implemented
  5500. with a CPLD.
  5501. It's not difficult to have logic fan a module's input TCK signal out
  5502. to each TAP in the scan chain, and then wait until each TAP's RTCK comes
  5503. back with the right polarity before changing the output RTCK signal.
  5504. Texas Instruments makes some clock voting logic available
  5505. for free (with no support) in VHDL form; see
  5506. @url{}
  5507. @b{Solution #2 - Always works - but may be slower}
  5508. Often this is a perfectly acceptable solution.
  5509. In most simple terms: Often the JTAG clock must be 1/10 to 1/12 of
  5510. the target clock speed. But what that ``magic division'' is varies
  5511. depending on the chips on your board.
  5512. @b{ARM rule of thumb} Most ARM based systems require an 6:1 division;
  5513. ARM11 cores use an 8:1 division.
  5514. @b{Xilinx rule of thumb} is 1/12 the clock speed.
  5515. Note: Many FTDI2232C based JTAG dongles are limited to 6MHz.
  5516. You can still debug the 'low power' situations - you just need to
  5517. manually adjust the clock speed at every step. While painful and
  5518. tedious, it is not always practical.
  5519. It is however easy to ``code your way around it'' - i.e.: Cheat a little,
  5520. have a special debug mode in your application that does a ``high power
  5521. sleep''. If you are careful - 98% of your problems can be debugged
  5522. this way.
  5523. Note that on ARM you may need to avoid using the @emph{wait for interrupt}
  5524. operation in your idle loops even if you don't otherwise change the CPU
  5525. clock rate.
  5526. That operation gates the CPU clock, and thus the JTAG clock; which
  5527. prevents JTAG access. One consequence is not being able to @command{halt}
  5528. cores which are executing that @emph{wait for interrupt} operation.
  5529. To set the JTAG frequency use the command:
  5530. @example
  5531. # Example: 1.234MHz
  5532. jtag_khz 1234
  5533. @end example
  5534. @item @b{Win32 Pathnames} Why don't backslashes work in Windows paths?
  5535. OpenOCD uses Tcl and a backslash is an escape char. Use @{ and @}
  5536. around Windows filenames.
  5537. @example
  5538. > echo \a
  5539. > echo @{\a@}
  5540. \a
  5541. > echo "\a"
  5542. >
  5543. @end example
  5544. @item @b{Missing: cygwin1.dll} OpenOCD complains about a missing cygwin1.dll.
  5545. Make sure you have Cygwin installed, or at least a version of OpenOCD that
  5546. claims to come with all the necessary DLLs. When using Cygwin, try launching
  5547. OpenOCD from the Cygwin shell.
  5548. @item @b{Breakpoint Issue} I'm trying to set a breakpoint using GDB (or a frontend like Insight or
  5549. Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213
  5550. arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".
  5551. GDB issues software breakpoints when a normal breakpoint is requested, or to implement
  5552. source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720T or ARM920T,
  5553. software breakpoints consume one of the two available hardware breakpoints.
  5554. @item @b{LPC2000 Flash} When erasing or writing LPC2000 on-chip flash, the operation fails at random.
  5555. Make sure the core frequency specified in the @option{flash lpc2000} line matches the
  5556. clock at the time you're programming the flash. If you've specified the crystal's
  5557. frequency, make sure the PLL is disabled. If you've specified the full core speed
  5558. (e.g. 60MHz), make sure the PLL is enabled.
  5559. @item @b{Amontec Chameleon} When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
  5560. I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed
  5561. out while waiting for end of scan, rtck was disabled".
  5562. Make sure your PC's parallel port operates in EPP mode. You might have to try several
  5563. settings in your PC BIOS (ECP, EPP, and different versions of those).
  5564. @item @b{Data Aborts} When debugging with OpenOCD and GDB (plain GDB, Insight, or Eclipse),
  5565. I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():
  5566. memory read caused data abort".
  5567. The errors are non-fatal, and are the result of GDB trying to trace stack frames
  5568. beyond the last valid frame. It might be possible to prevent this by setting up
  5569. a proper "initial" stack frame, if you happen to know what exactly has to
  5570. be done, feel free to add this here.
  5571. @b{Simple:} In your startup code - push 8 registers of zeros onto the
  5572. stack before calling main(). What GDB is doing is ``climbing'' the run
  5573. time stack by reading various values on the stack using the standard
  5574. call frame for the target. GDB keeps going - until one of 2 things
  5575. happen @b{#1} an invalid frame is found, or @b{#2} some huge number of
  5576. stackframes have been processed. By pushing zeros on the stack, GDB
  5577. gracefully stops.
  5578. @b{Debugging Interrupt Service Routines} - In your ISR before you call
  5579. your C code, do the same - artifically push some zeros onto the stack,
  5580. remember to pop them off when the ISR is done.
  5581. @b{Also note:} If you have a multi-threaded operating system, they
  5582. often do not @b{in the intrest of saving memory} waste these few
  5583. bytes. Painful...
  5584. @item @b{JTAG Reset Config} I get the following message in the OpenOCD console (or log file):
  5585. "Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".
  5586. This warning doesn't indicate any serious problem, as long as you don't want to
  5587. debug your core right out of reset. Your .cfg file specified @option{jtag_reset
  5588. trst_and_srst srst_pulls_trst} to tell OpenOCD that either your board,
  5589. your debugger or your target uC (e.g. LPC2000) can't assert the two reset signals
  5590. independently. With this setup, it's not possible to halt the core right out of
  5591. reset, everything else should work fine.
  5592. @item @b{USB Power} When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto
  5593. toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be
  5594. unstable. When single-stepping over large blocks of code, GDB and OpenOCD
  5595. quit with an error message. Is there a stability issue with OpenOCD?
  5596. No, this is not a stability issue concerning OpenOCD. Most users have solved
  5597. this issue by simply using a self-powered USB hub, which they connect their
  5598. Amontec JTAGkey to. Apparently, some computers do not provide a USB power
  5599. supply stable enough for the Amontec JTAGkey to be operated.
  5600. @b{Laptops running on battery have this problem too...}
  5601. @item @b{USB Power} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the
  5602. following error messages: "Error: ft2232.c:201 ft2232_read(): FT_Read returned:
  5603. 4" and "Error: ft2232.c:365 ft2232_send_and_recv(): couldn't read from FT2232".
  5604. What does that mean and what might be the reason for this?
  5605. First of all, the reason might be the USB power supply. Try using a self-powered
  5606. hub instead of a direct connection to your computer. Secondly, the error code 4
  5607. corresponds to an FT_IO_ERROR, which means that the driver for the FTDI USB
  5608. chip ran into some sort of error - this points us to a USB problem.
  5609. @item @b{GDB Disconnects} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following
  5610. error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054".
  5611. What does that mean and what might be the reason for this?
  5612. Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB)
  5613. has closed the connection to OpenOCD. This might be a GDB issue.
  5614. @item @b{LPC2000 Flash} In the configuration file in the section where flash device configurations
  5615. are described, there is a parameter for specifying the clock frequency
  5616. for LPC2000 internal flash devices (e.g. @option{flash bank lpc2000
  5617. 0x0 0x40000 0 0 0 lpc2000_v1 14746 calc_checksum}), which must be
  5618. specified in kilohertz. However, I do have a quartz crystal of a
  5619. frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz,
  5620. i.e. 14,745.600 kHz). Is it possible to specify real numbers for the
  5621. clock frequency?
  5622. No. The clock frequency specified here must be given as an integral number.
  5623. However, this clock frequency is used by the In-Application-Programming (IAP)
  5624. routines of the LPC2000 family only, which seems to be very tolerant concerning
  5625. the given clock frequency, so a slight difference between the specified clock
  5626. frequency and the actual clock frequency will not cause any trouble.
  5627. @item @b{Command Order} Do I have to keep a specific order for the commands in the configuration file?
  5628. Well, yes and no. Commands can be given in arbitrary order, yet the
  5629. devices listed for the JTAG scan chain must be given in the right
  5630. order (jtag newdevice), with the device closest to the TDO-Pin being
  5631. listed first. In general, whenever objects of the same type exist
  5632. which require an index number, then these objects must be given in the
  5633. right order (jtag newtap, targets and flash banks - a target
  5634. references a jtag newtap and a flash bank references a target).
  5635. You can use the ``scan_chain'' command to verify and display the tap order.
  5636. Also, some commands can't execute until after @command{init} has been
  5637. processed. Such commands include @command{nand probe} and everything
  5638. else that needs to write to controller registers, perhaps for setting
  5639. up DRAM and loading it with code.
  5640. @anchor{FAQ TAP Order}
  5641. @item @b{JTAG TAP Order} Do I have to declare the TAPS in some
  5642. particular order?
  5643. Yes; whenever you have more than one, you must declare them in
  5644. the same order used by the hardware.
  5645. Many newer devices have multiple JTAG TAPs. For example: ST
  5646. Microsystems STM32 chips have two TAPs, a ``boundary scan TAP'' and
  5647. ``Cortex-M3'' TAP. Example: The STM32 reference manual, Document ID:
  5648. RM0008, Section 26.5, Figure 259, page 651/681, the ``TDI'' pin is
  5649. connected to the boundary scan TAP, which then connects to the
  5650. Cortex-M3 TAP, which then connects to the TDO pin.
  5651. Thus, the proper order for the STM32 chip is: (1) The Cortex-M3, then
  5652. (2) The boundary scan TAP. If your board includes an additional JTAG
  5653. chip in the scan chain (for example a Xilinx CPLD or FPGA) you could
  5654. place it before or after the STM32 chip in the chain. For example:
  5655. @itemize @bullet
  5656. @item OpenOCD_TDI(output) -> STM32 TDI Pin (BS Input)
  5657. @item STM32 BS TDO (output) -> STM32 Cortex-M3 TDI (input)
  5658. @item STM32 Cortex-M3 TDO (output) -> SM32 TDO Pin
  5659. @item STM32 TDO Pin (output) -> Xilinx TDI Pin (input)
  5660. @item Xilinx TDO Pin -> OpenOCD TDO (input)
  5661. @end itemize
  5662. The ``jtag device'' commands would thus be in the order shown below. Note:
  5663. @itemize @bullet
  5664. @item jtag newtap Xilinx tap -irlen ...
  5665. @item jtag newtap stm32 cpu -irlen ...
  5666. @item jtag newtap stm32 bs -irlen ...
  5667. @item # Create the debug target and say where it is
  5668. @item target create stm32.cpu -chain-position stm32.cpu ...
  5669. @end itemize
  5670. @item @b{SYSCOMP} Sometimes my debugging session terminates with an error. When I look into the
  5671. log file, I can see these error messages: Error: arm7_9_common.c:561
  5672. arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP
  5673. TODO.
  5674. @end enumerate
  5675. @node Tcl Crash Course
  5676. @chapter Tcl Crash Course
  5677. @cindex Tcl
  5678. Not everyone knows Tcl - this is not intended to be a replacement for
  5679. learning Tcl, the intent of this chapter is to give you some idea of
  5680. how the Tcl scripts work.
  5681. This chapter is written with two audiences in mind. (1) OpenOCD users
  5682. who need to understand a bit more of how JIM-Tcl works so they can do
  5683. something useful, and (2) those that want to add a new command to
  5684. OpenOCD.
  5685. @section Tcl Rule #1
  5686. There is a famous joke, it goes like this:
  5687. @enumerate
  5688. @item Rule #1: The wife is always correct
  5689. @item Rule #2: If you think otherwise, See Rule #1
  5690. @end enumerate
  5691. The Tcl equal is this:
  5692. @enumerate
  5693. @item Rule #1: Everything is a string
  5694. @item Rule #2: If you think otherwise, See Rule #1
  5695. @end enumerate
  5696. As in the famous joke, the consequences of Rule #1 are profound. Once
  5697. you understand Rule #1, you will understand Tcl.
  5698. @section Tcl Rule #1b
  5699. There is a second pair of rules.
  5700. @enumerate
  5701. @item Rule #1: Control flow does not exist. Only commands
  5702. @* For example: the classic FOR loop or IF statement is not a control
  5703. flow item, they are commands, there is no such thing as control flow
  5704. in Tcl.
  5705. @item Rule #2: If you think otherwise, See Rule #1
  5706. @* Actually what happens is this: There are commands that by
  5707. convention, act like control flow key words in other languages. One of
  5708. those commands is the word ``for'', another command is ``if''.
  5709. @end enumerate
  5710. @section Per Rule #1 - All Results are strings
  5711. Every Tcl command results in a string. The word ``result'' is used
  5712. deliberatly. No result is just an empty string. Remember: @i{Rule #1 -
  5713. Everything is a string}
  5714. @section Tcl Quoting Operators
  5715. In life of a Tcl script, there are two important periods of time, the
  5716. difference is subtle.
  5717. @enumerate
  5718. @item Parse Time
  5719. @item Evaluation Time
  5720. @end enumerate
  5721. The two key items here are how ``quoted things'' work in Tcl. Tcl has
  5722. three primary quoting constructs, the [square-brackets] the
  5723. @{curly-braces@} and ``double-quotes''
  5724. By now you should know $VARIABLES always start with a $DOLLAR
  5725. sign. BTW: To set a variable, you actually use the command ``set'', as
  5726. in ``set VARNAME VALUE'' much like the ancient BASIC langauge ``let x
  5727. = 1'' statement, but without the equal sign.
  5728. @itemize @bullet
  5729. @item @b{[square-brackets]}
  5730. @* @b{[square-brackets]} are command substitutions. It operates much
  5731. like Unix Shell `back-ticks`. The result of a [square-bracket]
  5732. operation is exactly 1 string. @i{Remember Rule #1 - Everything is a
  5733. string}. These two statements are roughly identical:
  5734. @example
  5735. # bash example
  5736. X=`date`
  5737. echo "The Date is: $X"
  5738. # Tcl example
  5739. set X [date]
  5740. puts "The Date is: $X"
  5741. @end example
  5742. @item @b{``double-quoted-things''}
  5743. @* @b{``double-quoted-things''} are just simply quoted
  5744. text. $VARIABLES and [square-brackets] are expanded in place - the
  5745. result however is exactly 1 string. @i{Remember Rule #1 - Everything
  5746. is a string}
  5747. @example
  5748. set x "Dinner"
  5749. puts "It is now \"[date]\", $x is in 1 hour"
  5750. @end example
  5751. @item @b{@{Curly-Braces@}}
  5752. @*@b{@{Curly-Braces@}} are magic: $VARIABLES and [square-brackets] are
  5753. parsed, but are NOT expanded or executed. @{Curly-Braces@} are like
  5754. 'single-quote' operators in BASH shell scripts, with the added
  5755. feature: @{curly-braces@} can be nested, single quotes can not. @{@{@{this is
  5756. nested 3 times@}@}@} NOTE: [date] is a bad example;
  5757. at this writing, Jim/OpenOCD does not have a date command.
  5758. @end itemize
  5759. @section Consequences of Rule 1/2/3/4
  5760. The consequences of Rule 1 are profound.
  5761. @subsection Tokenisation & Execution.
  5762. Of course, whitespace, blank lines and #comment lines are handled in
  5763. the normal way.
  5764. As a script is parsed, each (multi) line in the script file is
  5765. tokenised and according to the quoting rules. After tokenisation, that
  5766. line is immedatly executed.
  5767. Multi line statements end with one or more ``still-open''
  5768. @{curly-braces@} which - eventually - closes a few lines later.
  5769. @subsection Command Execution
  5770. Remember earlier: There are no ``control flow''
  5771. statements in Tcl. Instead there are COMMANDS that simply act like
  5772. control flow operators.
  5773. Commands are executed like this:
  5774. @enumerate
  5775. @item Parse the next line into (argc) and (argv[]).
  5776. @item Look up (argv[0]) in a table and call its function.
  5777. @item Repeat until End Of File.
  5778. @end enumerate
  5779. It sort of works like this:
  5780. @example
  5781. for(;;)@{
  5782. ReadAndParse( &argc, &argv );
  5783. cmdPtr = LookupCommand( argv[0] );
  5784. (*cmdPtr->Execute)( argc, argv );
  5785. @}
  5786. @end example
  5787. When the command ``proc'' is parsed (which creates a procedure
  5788. function) it gets 3 parameters on the command line. @b{1} the name of
  5789. the proc (function), @b{2} the list of parameters, and @b{3} the body
  5790. of the function. Not the choice of words: LIST and BODY. The PROC
  5791. command stores these items in a table somewhere so it can be found by
  5792. ``LookupCommand()''
  5793. @subsection The FOR command
  5794. The most interesting command to look at is the FOR command. In Tcl,
  5795. the FOR command is normally implemented in C. Remember, FOR is a
  5796. command just like any other command.
  5797. When the ascii text containing the FOR command is parsed, the parser
  5798. produces 5 parameter strings, @i{(If in doubt: Refer to Rule #1)} they
  5799. are:
  5800. @enumerate 0
  5801. @item The ascii text 'for'
  5802. @item The start text
  5803. @item The test expression
  5804. @item The next text
  5805. @item The body text
  5806. @end enumerate
  5807. Sort of reminds you of ``main( int argc, char **argv )'' does it not?
  5808. Remember @i{Rule #1 - Everything is a string.} The key point is this:
  5809. Often many of those parameters are in @{curly-braces@} - thus the
  5810. variables inside are not expanded or replaced until later.
  5811. Remember that every Tcl command looks like the classic ``main( argc,
  5812. argv )'' function in C. In JimTCL - they actually look like this:
  5813. @example
  5814. int
  5815. MyCommand( Jim_Interp *interp,
  5816. int *argc,
  5817. Jim_Obj * const *argvs );
  5818. @end example
  5819. Real Tcl is nearly identical. Although the newer versions have
  5820. introduced a byte-code parser and intepreter, but at the core, it
  5821. still operates in the same basic way.
  5822. @subsection FOR command implementation
  5823. To understand Tcl it is perhaps most helpful to see the FOR
  5824. command. Remember, it is a COMMAND not a control flow structure.
  5825. In Tcl there are two underlying C helper functions.
  5826. Remember Rule #1 - You are a string.
  5827. The @b{first} helper parses and executes commands found in an ascii
  5828. string. Commands can be seperated by semicolons, or newlines. While
  5829. parsing, variables are expanded via the quoting rules.
  5830. The @b{second} helper evaluates an ascii string as a numerical
  5831. expression and returns a value.
  5832. Here is an example of how the @b{FOR} command could be
  5833. implemented. The pseudo code below does not show error handling.
  5834. @example
  5835. void Execute_AsciiString( void *interp, const char *string );
  5836. int Evaluate_AsciiExpression( void *interp, const char *string );
  5837. int
  5838. MyForCommand( void *interp,
  5839. int argc,
  5840. char **argv )
  5841. @{
  5842. if( argc != 5 )@{
  5843. SetResult( interp, "WRONG number of parameters");
  5844. return ERROR;
  5845. @}
  5846. // argv[0] = the ascii string just like C
  5847. // Execute the start statement.
  5848. Execute_AsciiString( interp, argv[1] );
  5849. // Top of loop test
  5850. for(;;)@{
  5851. i = Evaluate_AsciiExpression(interp, argv[2]);
  5852. if( i == 0 )
  5853. break;
  5854. // Execute the body
  5855. Execute_AsciiString( interp, argv[3] );
  5856. // Execute the LOOP part
  5857. Execute_AsciiString( interp, argv[4] );
  5858. @}
  5859. // Return no error
  5860. SetResult( interp, "" );
  5861. return SUCCESS;
  5862. @}
  5863. @end example
  5864. Every other command IF, WHILE, FORMAT, PUTS, EXPR, everything works
  5865. in the same basic way.
  5866. @section OpenOCD Tcl Usage
  5867. @subsection source and find commands
  5868. @b{Where:} In many configuration files
  5869. @* Example: @b{ source [find FILENAME] }
  5870. @*Remember the parsing rules
  5871. @enumerate
  5872. @item The FIND command is in square brackets.
  5873. @* The FIND command is executed with the parameter FILENAME. It should
  5874. find the full path to the named file. The RESULT is a string, which is
  5875. substituted on the orginal command line.
  5876. @item The command source is executed with the resulting filename.
  5877. @* SOURCE reads a file and executes as a script.
  5878. @end enumerate
  5879. @subsection format command
  5880. @b{Where:} Generally occurs in numerous places.
  5881. @* Tcl has no command like @b{printf()}, instead it has @b{format}, which is really more like
  5882. @b{sprintf()}.
  5883. @b{Example}
  5884. @example
  5885. set x 6
  5886. set y 7
  5887. puts [format "The answer: %d" [expr $x * $y]]
  5888. @end example
  5889. @enumerate
  5890. @item The SET command creates 2 variables, X and Y.
  5891. @item The double [nested] EXPR command performs math
  5892. @* The EXPR command produces numerical result as a string.
  5893. @* Refer to Rule #1
  5894. @item The format command is executed, producing a single string
  5895. @* Refer to Rule #1.
  5896. @item The PUTS command outputs the text.
  5897. @end enumerate
  5898. @subsection Body or Inlined Text
  5899. @b{Where:} Various TARGET scripts.
  5900. @example
  5901. #1 Good
  5902. proc someproc @{@} @{
  5903. ... multiple lines of stuff ...
  5904. @}
  5905. $_TARGETNAME configure -event FOO someproc
  5906. #2 Good - no variables
  5907. $_TARGETNAME confgure -event foo "this ; that;"
  5908. #3 Good Curly Braces
  5909. $_TARGETNAME configure -event FOO @{
  5910. puts "Time: [date]"
  5911. @}
  5913. $_TARGETNAME configure -event foo "puts \"Time: [date]\""
  5914. @end example
  5915. @enumerate
  5916. @item The $_TARGETNAME is an OpenOCD variable convention.
  5917. @*@b{$_TARGETNAME} represents the last target created, the value changes
  5918. each time a new target is created. Remember the parsing rules. When
  5919. the ascii text is parsed, the @b{$_TARGETNAME} becomes a simple string,
  5920. the name of the target which happens to be a TARGET (object)
  5921. command.
  5922. @item The 2nd parameter to the @option{-event} parameter is a TCBODY
  5923. @*There are 4 examples:
  5924. @enumerate
  5925. @item The TCLBODY is a simple string that happens to be a proc name
  5926. @item The TCLBODY is several simple commands seperated by semicolons
  5927. @item The TCLBODY is a multi-line @{curly-brace@} quoted string
  5928. @item The TCLBODY is a string with variables that get expanded.
  5929. @end enumerate
  5930. In the end, when the target event FOO occurs the TCLBODY is
  5931. evaluated. Method @b{#1} and @b{#2} are functionally identical. For
  5932. Method @b{#3} and @b{#4} it is more interesting. What is the TCLBODY?
  5933. Remember the parsing rules. In case #3, @{curly-braces@} mean the
  5934. $VARS and [square-brackets] are expanded later, when the EVENT occurs,
  5935. and the text is evaluated. In case #4, they are replaced before the
  5936. ``Target Object Command'' is executed. This occurs at the same time
  5937. $_TARGETNAME is replaced. In case #4 the date will never
  5938. change. @{BTW: [date] is a bad example; at this writing,
  5939. Jim/OpenOCD does not have a date command@}
  5940. @end enumerate
  5941. @subsection Global Variables
  5942. @b{Where:} You might discover this when writing your own procs @* In
  5943. simple terms: Inside a PROC, if you need to access a global variable
  5944. you must say so. See also ``upvar''. Example:
  5945. @example
  5946. proc myproc @{ @} @{
  5947. set y 0 #Local variable Y
  5948. global x #Global variable X
  5949. puts [format "X=%d, Y=%d" $x $y]
  5950. @}
  5951. @end example
  5952. @section Other Tcl Hacks
  5953. @b{Dynamic variable creation}
  5954. @example
  5955. # Dynamically create a bunch of variables.
  5956. for @{ set x 0 @} @{ $x < 32 @} @{ set x [expr $x + 1]@} @{
  5957. # Create var name
  5958. set vn [format "BIT%d" $x]
  5959. # Make it a global
  5960. global $vn
  5961. # Set it.
  5962. set $vn [expr (1 << $x)]
  5963. @}
  5964. @end example
  5965. @b{Dynamic proc/command creation}
  5966. @example
  5967. # One "X" function - 5 uart functions.
  5968. foreach who @{A B C D E@}
  5969. proc [format "show_uart%c" $who] @{ @} "show_UARTx $who"
  5970. @}
  5971. @end example
  5972. @include fdl.texi
  5973. @node OpenOCD Concept Index
  5974. @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
  5975. @comment case issue with ``Index.html'' and ``index.html''
  5976. @comment Occurs when creating ``--html --no-split'' output
  5977. @comment This fix is based on:
  5978. @unnumbered OpenOCD Concept Index
  5979. @printindex cp
  5980. @node Command and Driver Index
  5981. @unnumbered Command and Driver Index
  5982. @printindex fn
  5983. @bye