You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
 
 
 
 
 
 

1043 lines
28 KiB

  1. /***************************************************************************
  2. * Copyright (C) 2008 by Spencer Oliver *
  3. * spen@spen-soft.co.uk *
  4. * *
  5. * Copyright (C) 2008 by David T.L. Wong *
  6. * *
  7. * Copyright (C) 2009 by David N. Claffey <dnclaffey@gmail.com> *
  8. * *
  9. * This program is free software; you can redistribute it and/or modify *
  10. * it under the terms of the GNU General Public License as published by *
  11. * the Free Software Foundation; either version 2 of the License, or *
  12. * (at your option) any later version. *
  13. * *
  14. * This program is distributed in the hope that it will be useful, *
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  17. * GNU General Public License for more details. *
  18. * *
  19. * You should have received a copy of the GNU General Public License *
  20. * along with this program; if not, write to the *
  21. * Free Software Foundation, Inc., *
  22. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
  23. ***************************************************************************/
  24. #ifdef HAVE_CONFIG_H
  25. #include "config.h"
  26. #endif
  27. #include "breakpoints.h"
  28. #include "mips32.h"
  29. #include "mips_m4k.h"
  30. #include "mips32_dmaacc.h"
  31. #include "target_type.h"
  32. #include "register.h"
  33. int mips_m4k_examine_debug_reason(struct target *target)
  34. {
  35. uint32_t break_status;
  36. int retval;
  37. if ((target->debug_reason != DBG_REASON_DBGRQ)
  38. && (target->debug_reason != DBG_REASON_SINGLESTEP))
  39. {
  40. /* get info about inst breakpoint support */
  41. if ((retval = target_read_u32(target, EJTAG_IBS, &break_status)) != ERROR_OK)
  42. return retval;
  43. if (break_status & 0x1f)
  44. {
  45. /* we have halted on a breakpoint */
  46. if ((retval = target_write_u32(target, EJTAG_IBS, 0)) != ERROR_OK)
  47. return retval;
  48. target->debug_reason = DBG_REASON_BREAKPOINT;
  49. }
  50. /* get info about data breakpoint support */
  51. if ((retval = target_read_u32(target, EJTAG_DBS, &break_status)) != ERROR_OK)
  52. return retval;
  53. if (break_status & 0x1f)
  54. {
  55. /* we have halted on a breakpoint */
  56. if ((retval = target_write_u32(target, EJTAG_DBS, 0)) != ERROR_OK)
  57. return retval;
  58. target->debug_reason = DBG_REASON_WATCHPOINT;
  59. }
  60. }
  61. return ERROR_OK;
  62. }
  63. int mips_m4k_debug_entry(struct target *target)
  64. {
  65. struct mips32_common *mips32 = target_to_mips32(target);
  66. struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
  67. uint32_t debug_reg;
  68. /* read debug register */
  69. mips_ejtag_read_debug(ejtag_info, &debug_reg);
  70. /* make sure break unit configured */
  71. mips32_configure_break_unit(target);
  72. /* attempt to find halt reason */
  73. mips_m4k_examine_debug_reason(target);
  74. /* clear single step if active */
  75. if (debug_reg & EJTAG_DEBUG_DSS)
  76. {
  77. /* stopped due to single step - clear step bit */
  78. mips_ejtag_config_step(ejtag_info, 0);
  79. }
  80. mips32_save_context(target);
  81. /* default to mips32 isa, it will be changed below if required */
  82. mips32->isa_mode = MIPS32_ISA_MIPS32;
  83. if (ejtag_info->impcode & EJTAG_IMP_MIPS16) {
  84. mips32->isa_mode = buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 1);
  85. }
  86. LOG_DEBUG("entered debug state at PC 0x%" PRIx32 ", target->state: %s",
  87. buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32),
  88. target_state_name(target));
  89. return ERROR_OK;
  90. }
  91. int mips_m4k_poll(struct target *target)
  92. {
  93. int retval;
  94. struct mips32_common *mips32 = target_to_mips32(target);
  95. struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
  96. uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl;
  97. /* read ejtag control reg */
  98. jtag_set_end_state(TAP_IDLE);
  99. mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
  100. mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
  101. /* clear this bit before handling polling
  102. * as after reset registers will read zero */
  103. if (ejtag_ctrl & EJTAG_CTRL_ROCC)
  104. {
  105. /* we have detected a reset, clear flag
  106. * otherwise ejtag will not work */
  107. jtag_set_end_state(TAP_IDLE);
  108. ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_ROCC;
  109. mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
  110. mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
  111. LOG_DEBUG("Reset Detected");
  112. }
  113. /* check for processor halted */
  114. if (ejtag_ctrl & EJTAG_CTRL_BRKST)
  115. {
  116. if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
  117. {
  118. jtag_set_end_state(TAP_IDLE);
  119. mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT);
  120. target->state = TARGET_HALTED;
  121. if ((retval = mips_m4k_debug_entry(target)) != ERROR_OK)
  122. return retval;
  123. target_call_event_callbacks(target, TARGET_EVENT_HALTED);
  124. }
  125. else if (target->state == TARGET_DEBUG_RUNNING)
  126. {
  127. target->state = TARGET_HALTED;
  128. if ((retval = mips_m4k_debug_entry(target)) != ERROR_OK)
  129. return retval;
  130. target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
  131. }
  132. }
  133. else
  134. {
  135. target->state = TARGET_RUNNING;
  136. }
  137. // LOG_DEBUG("ctrl = 0x%08X", ejtag_ctrl);
  138. return ERROR_OK;
  139. }
  140. int mips_m4k_halt(struct target *target)
  141. {
  142. struct mips32_common *mips32 = target_to_mips32(target);
  143. struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
  144. LOG_DEBUG("target->state: %s",
  145. target_state_name(target));
  146. if (target->state == TARGET_HALTED)
  147. {
  148. LOG_DEBUG("target was already halted");
  149. return ERROR_OK;
  150. }
  151. if (target->state == TARGET_UNKNOWN)
  152. {
  153. LOG_WARNING("target was in unknown state when halt was requested");
  154. }
  155. if (target->state == TARGET_RESET)
  156. {
  157. if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst())
  158. {
  159. LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
  160. return ERROR_TARGET_FAILURE;
  161. }
  162. else
  163. {
  164. /* we came here in a reset_halt or reset_init sequence
  165. * debug entry was already prepared in mips32_prepare_reset_halt()
  166. */
  167. target->debug_reason = DBG_REASON_DBGRQ;
  168. return ERROR_OK;
  169. }
  170. }
  171. /* break processor */
  172. mips_ejtag_enter_debug(ejtag_info);
  173. target->debug_reason = DBG_REASON_DBGRQ;
  174. return ERROR_OK;
  175. }
  176. int mips_m4k_assert_reset(struct target *target)
  177. {
  178. struct mips_m4k_common *mips_m4k = target_to_m4k(target);
  179. struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;
  180. int assert_srst = 1;
  181. LOG_DEBUG("target->state: %s",
  182. target_state_name(target));
  183. enum reset_types jtag_reset_config = jtag_get_reset_config();
  184. if (!(jtag_reset_config & RESET_HAS_SRST))
  185. assert_srst = 0;
  186. if (target->reset_halt)
  187. {
  188. /* use hardware to catch reset */
  189. jtag_set_end_state(TAP_IDLE);
  190. mips_ejtag_set_instr(ejtag_info, EJTAG_INST_EJTAGBOOT);
  191. }
  192. else
  193. {
  194. jtag_set_end_state(TAP_IDLE);
  195. mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT);
  196. }
  197. if (assert_srst)
  198. {
  199. /* here we should issue a srst only, but we may have to assert trst as well */
  200. if (jtag_reset_config & RESET_SRST_PULLS_TRST)
  201. {
  202. jtag_add_reset(1, 1);
  203. }
  204. else
  205. {
  206. jtag_add_reset(0, 1);
  207. }
  208. }
  209. else
  210. {
  211. if (mips_m4k->is_pic32mx)
  212. {
  213. uint32_t mchip_cmd;
  214. LOG_DEBUG("Using MTAP reset to reset processor...");
  215. /* use microchip specific MTAP reset */
  216. mips_ejtag_set_instr(ejtag_info, MTAP_SW_MTAP);
  217. mips_ejtag_set_instr(ejtag_info, MTAP_COMMAND);
  218. mchip_cmd = MCHP_ASERT_RST;
  219. mips_ejtag_drscan_8(ejtag_info, &mchip_cmd);
  220. mchip_cmd = MCHP_DE_ASSERT_RST;
  221. mips_ejtag_drscan_8(ejtag_info, &mchip_cmd);
  222. mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP);
  223. }
  224. else
  225. {
  226. /* use ejtag reset - not supported by all cores */
  227. uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_PRRST | EJTAG_CTRL_PERRST;
  228. LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor...");
  229. mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
  230. mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
  231. }
  232. }
  233. target->state = TARGET_RESET;
  234. jtag_add_sleep(50000);
  235. register_cache_invalidate(mips_m4k->mips32.core_cache);
  236. if (target->reset_halt)
  237. {
  238. int retval;
  239. if ((retval = target_halt(target)) != ERROR_OK)
  240. return retval;
  241. }
  242. return ERROR_OK;
  243. }
  244. int mips_m4k_deassert_reset(struct target *target)
  245. {
  246. LOG_DEBUG("target->state: %s",
  247. target_state_name(target));
  248. /* deassert reset lines */
  249. jtag_add_reset(0, 0);
  250. return ERROR_OK;
  251. }
  252. int mips_m4k_soft_reset_halt(struct target *target)
  253. {
  254. /* TODO */
  255. return ERROR_OK;
  256. }
  257. int mips_m4k_single_step_core(struct target *target)
  258. {
  259. struct mips32_common *mips32 = target_to_mips32(target);
  260. struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
  261. /* configure single step mode */
  262. mips_ejtag_config_step(ejtag_info, 1);
  263. /* disable interrupts while stepping */
  264. mips32_enable_interrupts(target, 0);
  265. /* exit debug mode */
  266. mips_ejtag_exit_debug(ejtag_info);
  267. mips_m4k_debug_entry(target);
  268. return ERROR_OK;
  269. }
  270. int mips_m4k_resume(struct target *target, int current, uint32_t address, int handle_breakpoints, int debug_execution)
  271. {
  272. struct mips32_common *mips32 = target_to_mips32(target);
  273. struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
  274. struct breakpoint *breakpoint = NULL;
  275. uint32_t resume_pc;
  276. if (target->state != TARGET_HALTED)
  277. {
  278. LOG_WARNING("target not halted");
  279. return ERROR_TARGET_NOT_HALTED;
  280. }
  281. if (!debug_execution)
  282. {
  283. target_free_all_working_areas(target);
  284. mips_m4k_enable_breakpoints(target);
  285. mips_m4k_enable_watchpoints(target);
  286. }
  287. /* current = 1: continue on current pc, otherwise continue at <address> */
  288. if (!current)
  289. {
  290. buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);
  291. mips32->core_cache->reg_list[MIPS32_PC].dirty = 1;
  292. mips32->core_cache->reg_list[MIPS32_PC].valid = 1;
  293. }
  294. if (ejtag_info->impcode & EJTAG_IMP_MIPS16) {
  295. buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 1, mips32->isa_mode);
  296. }
  297. resume_pc = buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32);
  298. mips32_restore_context(target);
  299. /* the front-end may request us not to handle breakpoints */
  300. if (handle_breakpoints)
  301. {
  302. /* Single step past breakpoint at current address */
  303. if ((breakpoint = breakpoint_find(target, resume_pc)))
  304. {
  305. LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 "", breakpoint->address);
  306. mips_m4k_unset_breakpoint(target, breakpoint);
  307. mips_m4k_single_step_core(target);
  308. mips_m4k_set_breakpoint(target, breakpoint);
  309. }
  310. }
  311. /* enable interrupts if we are running */
  312. mips32_enable_interrupts(target, !debug_execution);
  313. /* exit debug mode */
  314. mips_ejtag_exit_debug(ejtag_info);
  315. target->debug_reason = DBG_REASON_NOTHALTED;
  316. /* registers are now invalid */
  317. register_cache_invalidate(mips32->core_cache);
  318. if (!debug_execution)
  319. {
  320. target->state = TARGET_RUNNING;
  321. target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
  322. LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
  323. }
  324. else
  325. {
  326. target->state = TARGET_DEBUG_RUNNING;
  327. target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
  328. LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
  329. }
  330. return ERROR_OK;
  331. }
  332. int mips_m4k_step(struct target *target, int current, uint32_t address, int handle_breakpoints)
  333. {
  334. /* get pointers to arch-specific information */
  335. struct mips32_common *mips32 = target_to_mips32(target);
  336. struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
  337. struct breakpoint *breakpoint = NULL;
  338. if (target->state != TARGET_HALTED)
  339. {
  340. LOG_WARNING("target not halted");
  341. return ERROR_TARGET_NOT_HALTED;
  342. }
  343. /* current = 1: continue on current pc, otherwise continue at <address> */
  344. if (!current)
  345. buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);
  346. /* the front-end may request us not to handle breakpoints */
  347. if (handle_breakpoints) {
  348. breakpoint = breakpoint_find(target,
  349. buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32));
  350. if (breakpoint)
  351. mips_m4k_unset_breakpoint(target, breakpoint);
  352. }
  353. /* restore context */
  354. mips32_restore_context(target);
  355. /* configure single step mode */
  356. mips_ejtag_config_step(ejtag_info, 1);
  357. target->debug_reason = DBG_REASON_SINGLESTEP;
  358. target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
  359. /* disable interrupts while stepping */
  360. mips32_enable_interrupts(target, 0);
  361. /* exit debug mode */
  362. mips_ejtag_exit_debug(ejtag_info);
  363. /* registers are now invalid */
  364. register_cache_invalidate(mips32->core_cache);
  365. if (breakpoint)
  366. mips_m4k_set_breakpoint(target, breakpoint);
  367. LOG_DEBUG("target stepped ");
  368. mips_m4k_debug_entry(target);
  369. target_call_event_callbacks(target, TARGET_EVENT_HALTED);
  370. return ERROR_OK;
  371. }
  372. void mips_m4k_enable_breakpoints(struct target *target)
  373. {
  374. struct breakpoint *breakpoint = target->breakpoints;
  375. /* set any pending breakpoints */
  376. while (breakpoint)
  377. {
  378. if (breakpoint->set == 0)
  379. mips_m4k_set_breakpoint(target, breakpoint);
  380. breakpoint = breakpoint->next;
  381. }
  382. }
  383. int mips_m4k_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
  384. {
  385. struct mips32_common *mips32 = target_to_mips32(target);
  386. struct mips32_comparator * comparator_list = mips32->inst_break_list;
  387. int retval;
  388. if (breakpoint->set)
  389. {
  390. LOG_WARNING("breakpoint already set");
  391. return ERROR_OK;
  392. }
  393. if (breakpoint->type == BKPT_HARD)
  394. {
  395. int bp_num = 0;
  396. while (comparator_list[bp_num].used && (bp_num < mips32->num_inst_bpoints))
  397. bp_num++;
  398. if (bp_num >= mips32->num_inst_bpoints)
  399. {
  400. LOG_ERROR("Can not find free FP Comparator(bpid: %d)",
  401. breakpoint->unique_id );
  402. return ERROR_FAIL;
  403. }
  404. breakpoint->set = bp_num + 1;
  405. comparator_list[bp_num].used = 1;
  406. comparator_list[bp_num].bp_value = breakpoint->address;
  407. target_write_u32(target, comparator_list[bp_num].reg_address, comparator_list[bp_num].bp_value);
  408. target_write_u32(target, comparator_list[bp_num].reg_address + 0x08, 0x00000000);
  409. target_write_u32(target, comparator_list[bp_num].reg_address + 0x18, 1);
  410. LOG_DEBUG("bpid: %d, bp_num %i bp_value 0x%" PRIx32 "",
  411. breakpoint->unique_id,
  412. bp_num, comparator_list[bp_num].bp_value);
  413. }
  414. else if (breakpoint->type == BKPT_SOFT)
  415. {
  416. LOG_DEBUG("bpid: %d", breakpoint->unique_id );
  417. if (breakpoint->length == 4)
  418. {
  419. uint32_t verify = 0xffffffff;
  420. if ((retval = target_read_memory(target, breakpoint->address, breakpoint->length, 1,
  421. breakpoint->orig_instr)) != ERROR_OK)
  422. {
  423. return retval;
  424. }
  425. if ((retval = target_write_u32(target, breakpoint->address, MIPS32_SDBBP)) != ERROR_OK)
  426. {
  427. return retval;
  428. }
  429. if ((retval = target_read_u32(target, breakpoint->address, &verify)) != ERROR_OK)
  430. {
  431. return retval;
  432. }
  433. if (verify != MIPS32_SDBBP)
  434. {
  435. LOG_ERROR("Unable to set 32bit breakpoint at address %08" PRIx32 " - check that memory is read/writable", breakpoint->address);
  436. return ERROR_OK;
  437. }
  438. }
  439. else
  440. {
  441. uint16_t verify = 0xffff;
  442. if ((retval = target_read_memory(target, breakpoint->address, breakpoint->length, 1,
  443. breakpoint->orig_instr)) != ERROR_OK)
  444. {
  445. return retval;
  446. }
  447. if ((retval = target_write_u16(target, breakpoint->address, MIPS16_SDBBP)) != ERROR_OK)
  448. {
  449. return retval;
  450. }
  451. if ((retval = target_read_u16(target, breakpoint->address, &verify)) != ERROR_OK)
  452. {
  453. return retval;
  454. }
  455. if (verify != MIPS16_SDBBP)
  456. {
  457. LOG_ERROR("Unable to set 16bit breakpoint at address %08" PRIx32 " - check that memory is read/writable", breakpoint->address);
  458. return ERROR_OK;
  459. }
  460. }
  461. breakpoint->set = 20; /* Any nice value but 0 */
  462. }
  463. return ERROR_OK;
  464. }
  465. int mips_m4k_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
  466. {
  467. /* get pointers to arch-specific information */
  468. struct mips32_common *mips32 = target_to_mips32(target);
  469. struct mips32_comparator *comparator_list = mips32->inst_break_list;
  470. int retval;
  471. if (!breakpoint->set)
  472. {
  473. LOG_WARNING("breakpoint not set");
  474. return ERROR_OK;
  475. }
  476. if (breakpoint->type == BKPT_HARD)
  477. {
  478. int bp_num = breakpoint->set - 1;
  479. if ((bp_num < 0) || (bp_num >= mips32->num_inst_bpoints))
  480. {
  481. LOG_DEBUG("Invalid FP Comparator number in breakpoint (bpid: %d)",
  482. breakpoint->unique_id);
  483. return ERROR_OK;
  484. }
  485. LOG_DEBUG("bpid: %d - releasing hw: %d",
  486. breakpoint->unique_id,
  487. bp_num );
  488. comparator_list[bp_num].used = 0;
  489. comparator_list[bp_num].bp_value = 0;
  490. target_write_u32(target, comparator_list[bp_num].reg_address + 0x18, 0);
  491. }
  492. else
  493. {
  494. /* restore original instruction (kept in target endianness) */
  495. LOG_DEBUG("bpid: %d", breakpoint->unique_id);
  496. if (breakpoint->length == 4)
  497. {
  498. uint32_t current_instr;
  499. /* check that user program has not modified breakpoint instruction */
  500. if ((retval = target_read_memory(target, breakpoint->address, 4, 1,
  501. (uint8_t*)&current_instr)) != ERROR_OK)
  502. {
  503. return retval;
  504. }
  505. if (current_instr == MIPS32_SDBBP)
  506. {
  507. if ((retval = target_write_memory(target, breakpoint->address, 4, 1,
  508. breakpoint->orig_instr)) != ERROR_OK)
  509. {
  510. return retval;
  511. }
  512. }
  513. }
  514. else
  515. {
  516. uint16_t current_instr;
  517. /* check that user program has not modified breakpoint instruction */
  518. if ((retval = target_read_memory(target, breakpoint->address, 2, 1,
  519. (uint8_t*)&current_instr)) != ERROR_OK)
  520. {
  521. return retval;
  522. }
  523. if (current_instr == MIPS16_SDBBP)
  524. {
  525. if ((retval = target_write_memory(target, breakpoint->address, 2, 1,
  526. breakpoint->orig_instr)) != ERROR_OK)
  527. {
  528. return retval;
  529. }
  530. }
  531. }
  532. }
  533. breakpoint->set = 0;
  534. return ERROR_OK;
  535. }
  536. int mips_m4k_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
  537. {
  538. struct mips32_common *mips32 = target_to_mips32(target);
  539. if (breakpoint->type == BKPT_HARD)
  540. {
  541. if (mips32->num_inst_bpoints_avail < 1)
  542. {
  543. LOG_INFO("no hardware breakpoint available");
  544. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  545. }
  546. mips32->num_inst_bpoints_avail--;
  547. }
  548. mips_m4k_set_breakpoint(target, breakpoint);
  549. return ERROR_OK;
  550. }
  551. int mips_m4k_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
  552. {
  553. /* get pointers to arch-specific information */
  554. struct mips32_common *mips32 = target_to_mips32(target);
  555. if (target->state != TARGET_HALTED)
  556. {
  557. LOG_WARNING("target not halted");
  558. return ERROR_TARGET_NOT_HALTED;
  559. }
  560. if (breakpoint->set)
  561. {
  562. mips_m4k_unset_breakpoint(target, breakpoint);
  563. }
  564. if (breakpoint->type == BKPT_HARD)
  565. mips32->num_inst_bpoints_avail++;
  566. return ERROR_OK;
  567. }
  568. int mips_m4k_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
  569. {
  570. struct mips32_common *mips32 = target_to_mips32(target);
  571. struct mips32_comparator *comparator_list = mips32->data_break_list;
  572. int wp_num = 0;
  573. /*
  574. * watchpoint enabled, ignore all byte lanes in value register
  575. * and exclude both load and store accesses from watchpoint
  576. * condition evaluation
  577. */
  578. int enable = EJTAG_DBCn_NOSB | EJTAG_DBCn_NOLB | EJTAG_DBCn_BE |
  579. (0xff << EJTAG_DBCn_BLM_SHIFT);
  580. if (watchpoint->set)
  581. {
  582. LOG_WARNING("watchpoint already set");
  583. return ERROR_OK;
  584. }
  585. while(comparator_list[wp_num].used && (wp_num < mips32->num_data_bpoints))
  586. wp_num++;
  587. if (wp_num >= mips32->num_data_bpoints)
  588. {
  589. LOG_ERROR("Can not find free FP Comparator");
  590. return ERROR_FAIL;
  591. }
  592. if (watchpoint->length != 4)
  593. {
  594. LOG_ERROR("Only watchpoints of length 4 are supported");
  595. return ERROR_TARGET_UNALIGNED_ACCESS;
  596. }
  597. if (watchpoint->address % 4)
  598. {
  599. LOG_ERROR("Watchpoints address should be word aligned");
  600. return ERROR_TARGET_UNALIGNED_ACCESS;
  601. }
  602. switch (watchpoint->rw)
  603. {
  604. case WPT_READ:
  605. enable &= ~EJTAG_DBCn_NOLB;
  606. break;
  607. case WPT_WRITE:
  608. enable &= ~EJTAG_DBCn_NOSB;
  609. break;
  610. case WPT_ACCESS:
  611. enable &= ~(EJTAG_DBCn_NOLB | EJTAG_DBCn_NOSB);
  612. break;
  613. default:
  614. LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");
  615. }
  616. watchpoint->set = wp_num + 1;
  617. comparator_list[wp_num].used = 1;
  618. comparator_list[wp_num].bp_value = watchpoint->address;
  619. target_write_u32(target, comparator_list[wp_num].reg_address, comparator_list[wp_num].bp_value);
  620. target_write_u32(target, comparator_list[wp_num].reg_address + 0x08, 0x00000000);
  621. target_write_u32(target, comparator_list[wp_num].reg_address + 0x10, 0x00000000);
  622. target_write_u32(target, comparator_list[wp_num].reg_address + 0x18, enable);
  623. target_write_u32(target, comparator_list[wp_num].reg_address + 0x20, 0);
  624. LOG_DEBUG("wp_num %i bp_value 0x%" PRIx32 "", wp_num, comparator_list[wp_num].bp_value);
  625. return ERROR_OK;
  626. }
  627. int mips_m4k_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
  628. {
  629. /* get pointers to arch-specific information */
  630. struct mips32_common *mips32 = target_to_mips32(target);
  631. struct mips32_comparator *comparator_list = mips32->data_break_list;
  632. if (!watchpoint->set)
  633. {
  634. LOG_WARNING("watchpoint not set");
  635. return ERROR_OK;
  636. }
  637. int wp_num = watchpoint->set - 1;
  638. if ((wp_num < 0) || (wp_num >= mips32->num_data_bpoints))
  639. {
  640. LOG_DEBUG("Invalid FP Comparator number in watchpoint");
  641. return ERROR_OK;
  642. }
  643. comparator_list[wp_num].used = 0;
  644. comparator_list[wp_num].bp_value = 0;
  645. target_write_u32(target, comparator_list[wp_num].reg_address + 0x18, 0);
  646. watchpoint->set = 0;
  647. return ERROR_OK;
  648. }
  649. int mips_m4k_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
  650. {
  651. struct mips32_common *mips32 = target_to_mips32(target);
  652. if (mips32->num_data_bpoints_avail < 1)
  653. {
  654. LOG_INFO("no hardware watchpoints available");
  655. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  656. }
  657. mips32->num_data_bpoints_avail--;
  658. mips_m4k_set_watchpoint(target, watchpoint);
  659. return ERROR_OK;
  660. }
  661. int mips_m4k_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
  662. {
  663. /* get pointers to arch-specific information */
  664. struct mips32_common *mips32 = target_to_mips32(target);
  665. if (target->state != TARGET_HALTED)
  666. {
  667. LOG_WARNING("target not halted");
  668. return ERROR_TARGET_NOT_HALTED;
  669. }
  670. if (watchpoint->set)
  671. {
  672. mips_m4k_unset_watchpoint(target, watchpoint);
  673. }
  674. mips32->num_data_bpoints_avail++;
  675. return ERROR_OK;
  676. }
  677. void mips_m4k_enable_watchpoints(struct target *target)
  678. {
  679. struct watchpoint *watchpoint = target->watchpoints;
  680. /* set any pending watchpoints */
  681. while (watchpoint)
  682. {
  683. if (watchpoint->set == 0)
  684. mips_m4k_set_watchpoint(target, watchpoint);
  685. watchpoint = watchpoint->next;
  686. }
  687. }
  688. int mips_m4k_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
  689. {
  690. struct mips32_common *mips32 = target_to_mips32(target);
  691. struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
  692. LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", address, size, count);
  693. if (target->state != TARGET_HALTED)
  694. {
  695. LOG_WARNING("target not halted");
  696. return ERROR_TARGET_NOT_HALTED;
  697. }
  698. /* sanitize arguments */
  699. if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
  700. return ERROR_INVALID_ARGUMENTS;
  701. if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
  702. return ERROR_TARGET_UNALIGNED_ACCESS;
  703. /* if noDMA off, use DMAACC mode for memory read */
  704. int retval;
  705. if (ejtag_info->impcode & EJTAG_IMP_NODMA)
  706. retval = mips32_pracc_read_mem(ejtag_info, address, size, count, (void *)buffer);
  707. else
  708. retval = mips32_dmaacc_read_mem(ejtag_info, address, size, count, (void *)buffer);
  709. if (ERROR_OK != retval)
  710. return retval;
  711. return ERROR_OK;
  712. }
  713. int mips_m4k_write_memory(struct target *target, uint32_t address, uint32_t size,
  714. uint32_t count, uint8_t *buffer)
  715. {
  716. struct mips32_common *mips32 = target_to_mips32(target);
  717. struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
  718. LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",
  719. address, size, count);
  720. if (target->state != TARGET_HALTED)
  721. {
  722. LOG_WARNING("target not halted");
  723. return ERROR_TARGET_NOT_HALTED;
  724. }
  725. /* sanitize arguments */
  726. if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
  727. return ERROR_INVALID_ARGUMENTS;
  728. if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
  729. return ERROR_TARGET_UNALIGNED_ACCESS;
  730. /* if noDMA off, use DMAACC mode for memory write */
  731. if (ejtag_info->impcode & EJTAG_IMP_NODMA)
  732. return mips32_pracc_write_mem(ejtag_info, address, size, count, (void *)buffer);
  733. else
  734. return mips32_dmaacc_write_mem(ejtag_info, address, size, count, (void *)buffer);
  735. }
  736. int mips_m4k_init_target(struct command_context *cmd_ctx, struct target *target)
  737. {
  738. mips32_build_reg_cache(target);
  739. return ERROR_OK;
  740. }
  741. int mips_m4k_init_arch_info(struct target *target, struct mips_m4k_common *mips_m4k,
  742. struct jtag_tap *tap)
  743. {
  744. struct mips32_common *mips32 = &mips_m4k->mips32;
  745. mips_m4k->common_magic = MIPSM4K_COMMON_MAGIC;
  746. /* initialize mips4k specific info */
  747. mips32_init_arch_info(target, mips32, tap);
  748. mips32->arch_info = mips_m4k;
  749. return ERROR_OK;
  750. }
  751. int mips_m4k_target_create(struct target *target, Jim_Interp *interp)
  752. {
  753. struct mips_m4k_common *mips_m4k = calloc(1, sizeof(struct mips_m4k_common));
  754. mips_m4k_init_arch_info(target, mips_m4k, target->tap);
  755. return ERROR_OK;
  756. }
  757. int mips_m4k_examine(struct target *target)
  758. {
  759. int retval;
  760. struct mips_m4k_common *mips_m4k = target_to_m4k(target);
  761. struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;
  762. uint32_t idcode = 0;
  763. if (!target_was_examined(target))
  764. {
  765. mips_ejtag_get_idcode(ejtag_info, &idcode);
  766. ejtag_info->idcode = idcode;
  767. if (((idcode >> 1) & 0x7FF) == 0x29)
  768. {
  769. /* we are using a pic32mx so select ejtag port
  770. * as it is not selected by default */
  771. mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP);
  772. LOG_DEBUG("PIC32MX Detected - using EJTAG Interface");
  773. mips_m4k->is_pic32mx = true;
  774. }
  775. }
  776. /* init rest of ejtag interface */
  777. if ((retval = mips_ejtag_init(ejtag_info)) != ERROR_OK)
  778. return retval;
  779. if ((retval = mips32_examine(target)) != ERROR_OK)
  780. return retval;
  781. return ERROR_OK;
  782. }
  783. int mips_m4k_bulk_write_memory(struct target *target, uint32_t address,
  784. uint32_t count, uint8_t *buffer)
  785. {
  786. struct mips32_common *mips32 = target_to_mips32(target);
  787. struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
  788. struct working_area *source;
  789. int retval;
  790. int write = 1;
  791. LOG_DEBUG("address: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", address, count);
  792. if (target->state != TARGET_HALTED)
  793. {
  794. LOG_WARNING("target not halted");
  795. return ERROR_TARGET_NOT_HALTED;
  796. }
  797. /* check alignment */
  798. if (address & 0x3u)
  799. return ERROR_TARGET_UNALIGNED_ACCESS;
  800. /* Get memory for block write handler */
  801. retval = target_alloc_working_area(target, MIPS32_FASTDATA_HANDLER_SIZE, &source);
  802. if (retval != ERROR_OK)
  803. {
  804. LOG_WARNING("No working area available, falling back to non-bulk write");
  805. return mips_m4k_write_memory(target, address, 4, count, buffer);
  806. }
  807. /* TAP data register is loaded LSB first (little endian) */
  808. if (target->endianness == TARGET_BIG_ENDIAN)
  809. {
  810. uint32_t i, t32;
  811. for(i = 0; i < (count * 4); i += 4)
  812. {
  813. t32 = be_to_h_u32((uint8_t *) &buffer[i]);
  814. h_u32_to_le(&buffer[i], t32);
  815. }
  816. }
  817. retval = mips32_pracc_fastdata_xfer(ejtag_info, source, write, address,
  818. count, (uint32_t*) buffer);
  819. if (retval != ERROR_OK)
  820. {
  821. /* FASTDATA access failed, try normal memory write */
  822. LOG_DEBUG("Fastdata access Failed, falling back to non-bulk write");
  823. retval = mips_m4k_write_memory(target, address, 4, count, buffer);
  824. }
  825. if (source)
  826. target_free_working_area(target, source);
  827. return retval;
  828. }
  829. struct target_type mips_m4k_target =
  830. {
  831. .name = "mips_m4k",
  832. .poll = mips_m4k_poll,
  833. .arch_state = mips32_arch_state,
  834. .target_request_data = NULL,
  835. .halt = mips_m4k_halt,
  836. .resume = mips_m4k_resume,
  837. .step = mips_m4k_step,
  838. .assert_reset = mips_m4k_assert_reset,
  839. .deassert_reset = mips_m4k_deassert_reset,
  840. .soft_reset_halt = mips_m4k_soft_reset_halt,
  841. .get_gdb_reg_list = mips32_get_gdb_reg_list,
  842. .read_memory = mips_m4k_read_memory,
  843. .write_memory = mips_m4k_write_memory,
  844. .bulk_write_memory = mips_m4k_bulk_write_memory,
  845. .checksum_memory = mips32_checksum_memory,
  846. .blank_check_memory = mips32_blank_check_memory,
  847. .run_algorithm = mips32_run_algorithm,
  848. .add_breakpoint = mips_m4k_add_breakpoint,
  849. .remove_breakpoint = mips_m4k_remove_breakpoint,
  850. .add_watchpoint = mips_m4k_add_watchpoint,
  851. .remove_watchpoint = mips_m4k_remove_watchpoint,
  852. .target_create = mips_m4k_target_create,
  853. .init_target = mips_m4k_init_target,
  854. .examine = mips_m4k_examine,
  855. };