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  1. /***************************************************************************
  2. * Copyright (C) 2013 by Andes Technology *
  3. * Hsiangkai Wang <hkwang@andestech.com> *
  4. * *
  5. * This program is free software; you can redistribute it and/or modify *
  6. * it under the terms of the GNU General Public License as published by *
  7. * the Free Software Foundation; either version 2 of the License, or *
  8. * (at your option) any later version. *
  9. * *
  10. * This program is distributed in the hope that it will be useful, *
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  13. * GNU General Public License for more details. *
  14. * *
  15. * You should have received a copy of the GNU General Public License *
  16. * along with this program; if not, write to the *
  17. * Free Software Foundation, Inc., *
  18. * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
  19. ***************************************************************************/
  20. #ifndef _AICE_PORT_H_
  21. #define _AICE_PORT_H_
  22. #include <target/nds32_edm.h>
  23. #define AICE_MAX_NUM_CORE (0x10)
  24. #define ERROR_AICE_DISCONNECT (-200)
  25. #define ERROR_AICE_TIMEOUT (-201)
  26. enum aice_target_state_s {
  27. AICE_DISCONNECT = 0,
  28. AICE_TARGET_DETACH,
  29. AICE_TARGET_UNKNOWN,
  30. AICE_TARGET_RUNNING,
  31. AICE_TARGET_HALTED,
  32. AICE_TARGET_RESET,
  33. AICE_TARGET_DEBUG_RUNNING,
  34. };
  35. enum aice_srst_type_s {
  36. AICE_SRST = 0x1,
  37. AICE_RESET_HOLD = 0x8,
  38. };
  39. enum aice_target_endian {
  40. AICE_LITTLE_ENDIAN = 0,
  41. AICE_BIG_ENDIAN,
  42. };
  43. enum aice_api_s {
  44. AICE_OPEN = 0x0,
  45. AICE_CLOSE,
  46. AICE_RESET,
  47. AICE_IDCODE,
  48. AICE_SET_JTAG_CLOCK,
  49. AICE_ASSERT_SRST,
  50. AICE_RUN,
  51. AICE_HALT,
  52. AICE_STEP,
  53. AICE_READ_REG,
  54. AICE_WRITE_REG,
  55. AICE_READ_REG_64,
  56. AICE_WRITE_REG_64,
  57. AICE_READ_MEM_UNIT,
  58. AICE_WRITE_MEM_UNIT,
  59. AICE_READ_MEM_BULK,
  60. AICE_WRITE_MEM_BULK,
  61. AICE_READ_DEBUG_REG,
  62. AICE_WRITE_DEBUG_REG,
  63. AICE_STATE,
  64. AICE_MEMORY_ACCESS,
  65. AICE_MEMORY_MODE,
  66. AICE_READ_TLB,
  67. AICE_CACHE_CTL,
  68. AICE_SET_RETRY_TIMES,
  69. AICE_PROGRAM_EDM,
  70. AICE_SET_COMMAND_MODE,
  71. AICE_EXECUTE,
  72. AICE_SET_CUSTOM_SRST_SCRIPT,
  73. AICE_SET_CUSTOM_TRST_SCRIPT,
  74. AICE_SET_CUSTOM_RESTART_SCRIPT,
  75. AICE_SET_COUNT_TO_CHECK_DBGER,
  76. AICE_SET_DATA_ENDIAN,
  77. };
  78. enum aice_error_s {
  79. AICE_OK,
  80. AICE_ACK,
  81. AICE_ERROR,
  82. };
  83. enum aice_cache_ctl_type {
  84. AICE_CACHE_CTL_L1D_INVALALL = 0,
  85. AICE_CACHE_CTL_L1D_VA_INVAL,
  86. AICE_CACHE_CTL_L1D_WBALL,
  87. AICE_CACHE_CTL_L1D_VA_WB,
  88. AICE_CACHE_CTL_L1I_INVALALL,
  89. AICE_CACHE_CTL_L1I_VA_INVAL,
  90. };
  91. enum aice_command_mode {
  92. AICE_COMMAND_MODE_NORMAL,
  93. AICE_COMMAND_MODE_PACK,
  94. AICE_COMMAND_MODE_BATCH,
  95. };
  96. struct aice_port_param_s {
  97. /** */
  98. const char *device_desc;
  99. /** */
  100. const char *serial;
  101. /** */
  102. uint16_t vid;
  103. /** */
  104. uint16_t pid;
  105. /** */
  106. char *adapter_name;
  107. };
  108. struct aice_port_s {
  109. /** */
  110. uint32_t coreid;
  111. /** */
  112. const struct aice_port *port;
  113. };
  114. /** */
  115. extern struct aice_port_api_s aice_usb_layout_api;
  116. /** */
  117. struct aice_port_api_s {
  118. /** */
  119. int (*open)(struct aice_port_param_s *param);
  120. /** */
  121. int (*close)(void);
  122. /** */
  123. int (*reset)(void);
  124. /** */
  125. int (*idcode)(uint32_t *idcode, uint8_t *num_of_idcode);
  126. /** */
  127. int (*set_jtag_clock)(uint32_t a_clock);
  128. /** */
  129. int (*assert_srst)(uint32_t coreid, enum aice_srst_type_s srst);
  130. /** */
  131. int (*run)(uint32_t coreid);
  132. /** */
  133. int (*halt)(uint32_t coreid);
  134. /** */
  135. int (*step)(uint32_t coreid);
  136. /** */
  137. int (*read_reg)(uint32_t coreid, uint32_t num, uint32_t *val);
  138. /** */
  139. int (*write_reg)(uint32_t coreid, uint32_t num, uint32_t val);
  140. /** */
  141. int (*read_reg_64)(uint32_t coreid, uint32_t num, uint64_t *val);
  142. /** */
  143. int (*write_reg_64)(uint32_t coreid, uint32_t num, uint64_t val);
  144. /** */
  145. int (*read_mem_unit)(uint32_t coreid, uint32_t addr, uint32_t size,
  146. uint32_t count, uint8_t *buffer);
  147. /** */
  148. int (*write_mem_unit)(uint32_t coreid, uint32_t addr, uint32_t size,
  149. uint32_t count, const uint8_t *buffer);
  150. /** */
  151. int (*read_mem_bulk)(uint32_t coreid, uint32_t addr, uint32_t length,
  152. uint8_t *buffer);
  153. /** */
  154. int (*write_mem_bulk)(uint32_t coreid, uint32_t addr, uint32_t length,
  155. const uint8_t *buffer);
  156. /** */
  157. int (*read_debug_reg)(uint32_t coreid, uint32_t addr, uint32_t *val);
  158. /** */
  159. int (*write_debug_reg)(uint32_t coreid, uint32_t addr, const uint32_t val);
  160. /** */
  161. int (*state)(uint32_t coreid, enum aice_target_state_s *state);
  162. /** */
  163. int (*memory_access)(uint32_t coreid, enum nds_memory_access a_access);
  164. /** */
  165. int (*memory_mode)(uint32_t coreid, enum nds_memory_select mem_select);
  166. /** */
  167. int (*read_tlb)(uint32_t coreid, uint32_t virtual_address, uint32_t *physical_address);
  168. /** */
  169. int (*cache_ctl)(uint32_t coreid, uint32_t subtype, uint32_t address);
  170. /** */
  171. int (*set_retry_times)(uint32_t a_retry_times);
  172. /** */
  173. int (*program_edm)(uint32_t coreid, char *command_sequence);
  174. /** */
  175. int (*set_command_mode)(enum aice_command_mode command_mode);
  176. /** */
  177. int (*execute)(uint32_t coreid, uint32_t *instructions, uint32_t instruction_num);
  178. /** */
  179. int (*set_custom_srst_script)(const char *script);
  180. /** */
  181. int (*set_custom_trst_script)(const char *script);
  182. /** */
  183. int (*set_custom_restart_script)(const char *script);
  184. /** */
  185. int (*set_count_to_check_dbger)(uint32_t count_to_check);
  186. /** */
  187. int (*set_data_endian)(uint32_t coreid, enum aice_target_endian target_data_endian);
  188. /** */
  189. int (*profiling)(uint32_t coreid, uint32_t interval, uint32_t iteration,
  190. uint32_t reg_no, uint32_t *samples, uint32_t *num_samples);
  191. };
  192. #define AICE_PORT_UNKNOWN 0
  193. #define AICE_PORT_AICE_USB 1
  194. #define AICE_PORT_AICE_PIPE 2
  195. /** */
  196. struct aice_port {
  197. /** */
  198. const char *name;
  199. /** */
  200. int type;
  201. /** */
  202. struct aice_port_api_s *const api;
  203. };
  204. /** */
  205. const struct aice_port *aice_port_get_list(void);
  206. #endif