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7.1 KiB

  1. # The IMX35PDK eval board has a single IMX35 chip
  2. source [find target/imx35.cfg]
  3. $_TARGETNAME configure -event reset-init { imx35pdk_init }
  4. global TARGETNAME
  5. set TARGETNAME $_TARGETNAME
  6. # rewrite commands of the form below to arm11 mcr...
  7. # Data.Set c15:0x042f %long 0x40000015
  8. proc setc15 {regs value} {
  9. global TARGETNAME
  10. echo [format "set p15 0x%04x, 0x%08x" $regs $value]
  11. arm11 mcr $TARGETNAME 15 [expr ($regs>>12)&0x7] [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] [expr ($regs>>8)&0x7] $value
  12. }
  13. proc imx35pdk_init { } {
  14. # this reset script comes from the Freescale PDK
  15. #
  16. # http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=IMX35PDK
  17. echo "Target Setup: initialize DRAM controller and peripherals"
  18. # Data.Set c15:0x01 %long 0x00050078
  19. setc15 0x01 0x00050078
  20. echo "configuring CP15 for enabling the peripheral bus"
  21. # Data.Set c15:0x042f %long 0x40000015
  22. setc15 0x042f 0x40000015
  23. mww 0x43f00040 0x00000000
  24. mww 0x43f00044 0x00000000
  25. mww 0x43f00048 0x00000000
  26. mww 0x43f0004C 0x00000000
  27. mww 0x43f00050 0x00000000
  28. mww 0x43f00000 0x77777777
  29. mww 0x43f00004 0x77777777
  30. mww 0x53f00040 0x00000000
  31. mww 0x53f00044 0x00000000
  32. mww 0x53f00048 0x00000000
  33. mww 0x53f0004C 0x00000000
  34. mww 0x53f00050 0x00000000
  35. mww 0x53f00000 0x77777777
  36. mww 0x53f00004 0x77777777
  37. # clock setup
  38. mww 0x53F80004 0x00821000 # first need to set IPU_HND_BYP
  39. mww 0x53F80004 0x00821000 #arm clock is 399Mhz and ahb clock is 133Mhz.
  40. #=================================================
  41. # WEIM config
  42. #=================================================
  43. # CS0U
  44. mww 0xB8002000 0x0000CC03
  45. # CS0L
  46. mww 0xB8002004 0xA0330D01
  47. # CS0A
  48. mww 0xB8002008 0x00220800
  49. # CS5U
  50. mww 0xB8002050 0x0000dcf6
  51. # CS5L
  52. mww 0xB8002054 0x444a4541
  53. # CS5A
  54. mww 0xB8002058 0x44443302
  55. # IO SW PAD Control registers - setting of 0x0002 is high drive, mDDR
  56. mww 0x43FAC368 0x00000006
  57. mww 0x43FAC36C 0x00000006
  58. mww 0x43FAC370 0x00000006
  59. mww 0x43FAC374 0x00000006
  60. mww 0x43FAC378 0x00000006
  61. mww 0x43FAC37C 0x00000006
  62. mww 0x43FAC380 0x00000006
  63. mww 0x43FAC384 0x00000006
  64. mww 0x43FAC388 0x00000006
  65. mww 0x43FAC38C 0x00000006
  66. mww 0x43FAC390 0x00000006
  67. mww 0x43FAC394 0x00000006
  68. mww 0x43FAC398 0x00000006
  69. mww 0x43FAC39C 0x00000006
  70. mww 0x43FAC3A0 0x00000006
  71. mww 0x43FAC3A4 0x00000006
  72. mww 0x43FAC3A8 0x00000006
  73. mww 0x43FAC3AC 0x00000006
  74. mww 0x43FAC3B0 0x00000006
  75. mww 0x43FAC3B4 0x00000006
  76. mww 0x43FAC3B8 0x00000006
  77. mww 0x43FAC3BC 0x00000006
  78. mww 0x43FAC3C0 0x00000006
  79. mww 0x43FAC3C4 0x00000006
  80. mww 0x43FAC3C8 0x00000006
  81. mww 0x43FAC3CC 0x00000006
  82. mww 0x43FAC3D0 0x00000006
  83. mww 0x43FAC3D4 0x00000006
  84. mww 0x43FAC3D8 0x00000006
  85. # DDR data bus SD 0 through 31
  86. mww 0x43FAC3DC 0x00000082
  87. mww 0x43FAC3E0 0x00000082
  88. mww 0x43FAC3E4 0x00000082
  89. mww 0x43FAC3E8 0x00000082
  90. mww 0x43FAC3EC 0x00000082
  91. mww 0x43FAC3F0 0x00000082
  92. mww 0x43FAC3F4 0x00000082
  93. mww 0x43FAC3F8 0x00000082
  94. mww 0x43FAC3FC 0x00000082
  95. mww 0x43FAC400 0x00000082
  96. mww 0x43FAC404 0x00000082
  97. mww 0x43FAC408 0x00000082
  98. mww 0x43FAC40C 0x00000082
  99. mww 0x43FAC410 0x00000082
  100. mww 0x43FAC414 0x00000082
  101. mww 0x43FAC418 0x00000082
  102. mww 0x43FAC41c 0x00000082
  103. mww 0x43FAC420 0x00000082
  104. mww 0x43FAC424 0x00000082
  105. mww 0x43FAC428 0x00000082
  106. mww 0x43FAC42c 0x00000082
  107. mww 0x43FAC430 0x00000082
  108. mww 0x43FAC434 0x00000082
  109. mww 0x43FAC438 0x00000082
  110. mww 0x43FAC43c 0x00000082
  111. mww 0x43FAC440 0x00000082
  112. mww 0x43FAC444 0x00000082
  113. mww 0x43FAC448 0x00000082
  114. mww 0x43FAC44c 0x00000082
  115. mww 0x43FAC450 0x00000082
  116. mww 0x43FAC454 0x00000082
  117. mww 0x43FAC458 0x00000082
  118. # DQM setup
  119. mww 0x43FAC45c 0x00000082
  120. mww 0x43FAC460 0x00000082
  121. mww 0x43FAC464 0x00000082
  122. mww 0x43FAC468 0x00000082
  123. mww 0x43FAC46c 0x00000006
  124. mww 0x43FAC470 0x00000006
  125. mww 0x43FAC474 0x00000006
  126. mww 0x43FAC478 0x00000006
  127. mww 0x43FAC47c 0x00000006
  128. mww 0x43FAC480 0x00000006 # CSD0
  129. mww 0x43FAC484 0x00000006 # CSD1
  130. mww 0x43FAC488 0x00000006
  131. mww 0x43FAC48c 0x00000006
  132. mww 0x43FAC490 0x00000006
  133. mww 0x43FAC494 0x00000006
  134. mww 0x43FAC498 0x00000006
  135. mww 0x43FAC49c 0x00000006
  136. mww 0x43FAC4A0 0x00000006
  137. mww 0x43FAC4A4 0x00000006 # RAS
  138. mww 0x43FAC4A8 0x00000006 # CAS
  139. mww 0x43FAC4Ac 0x00000006 # SDWE
  140. mww 0x43FAC4B0 0x00000006 # SDCKE0
  141. mww 0x43FAC4B4 0x00000006 # SDCKE1
  142. mww 0x43FAC4B8 0x00000002 # SDCLK
  143. # SDQS0 through SDQS3
  144. mww 0x43FAC4Bc 0x00000082
  145. mww 0x43FAC4C0 0x00000082
  146. mww 0x43FAC4C4 0x00000082
  147. mww 0x43FAC4C8 0x00000082
  148. # *==================================================
  149. # Initialization script for 32 bit DDR2 on RINGO 3DS
  150. # *==================================================
  151. #--------------------------------------------
  152. # Init CCM
  153. #--------------------------------------------
  154. mww 0x53F80028 0x7D000028
  155. #--------------------------------------------
  156. # Init IOMUX for JTAG
  157. #--------------------------------------------
  158. mww 0x43FAC5EC 0x000000C3
  159. mww 0x43FAC5F0 0x000000C3
  160. mww 0x43FAC5F4 0x000000F3
  161. mww 0x43FAC5F8 0x000000F3
  162. mww 0x43FAC5FC 0x000000F3
  163. mww 0x43FAC600 0x000000F3
  164. mww 0x43FAC604 0x000000F3
  165. # ESD_MISC : enable DDR2
  166. mww 0xB8001010 0x00000304
  167. #--------------------------------------------
  168. # Init 32-bit DDR2 memeory on CSD0
  169. # COL=10-bit, ROW=13-bit, BA[1:0]=Addr[26:25]
  170. #--------------------------------------------
  171. # ESD_ESDCFG0 : set timing paramters
  172. mww 0xB8001004 0x007ffC2f
  173. # ESD_ESDCTL0 : select Prechare-All mode
  174. mww 0xB8001000 0x92220000
  175. # DDR2 : Prechare-All
  176. mww 0x80000400 0x12345678
  177. # ESD_ESDCTL0 : select Load-Mode-Register mode
  178. mww 0xB8001000 0xB2220000
  179. # DDR2 : Load reg EMR2
  180. mwb 0x84000000 0xda
  181. # DDR2 : Load reg EMR3
  182. mwb 0x86000000 0xda
  183. # DDR2 : Load reg EMR1 -- enable DLL
  184. mwb 0x82000400 0xda
  185. # DDR2 : Load reg MR -- reset DLL
  186. mwb 0x80000333 0xda
  187. # ESD_ESDCTL0 : select Prechare-All mode
  188. mww 0xB8001000 0x92220000
  189. # DDR2 : Prechare-All
  190. mwb 0x80000400 0x12345678
  191. # ESD_ESDCTL0 : select Manual-Refresh mode
  192. mww 0xB8001000 0xA2220000
  193. # DDR2 : Manual-Refresh 2 times
  194. mww 0x80000000 0x87654321
  195. mww 0x80000000 0x87654321
  196. # ESD_ESDCTL0 : select Load-Mode-Register mode
  197. mww 0xB8001000 0xB2220000
  198. # DDR2 : Load reg MR -- CL=3, BL=8, end DLL reset
  199. mwb 0x80000233 0xda
  200. # DDR2 : Load reg EMR1 -- OCD default
  201. mwb 0x82000780 0xda
  202. # DDR2 : Load reg EMR1 -- OCD exit
  203. mwb 0x82000400 0xda # ODT disabled
  204. # ESD_ESDCTL0 : select normal-operation mode
  205. # DSIZ=32-bit, BL=8, COL=10-bit, ROW=13-bit
  206. # disable PWT & PRCT
  207. # disable Auto-Refresh
  208. mww 0xB8001000 0x82220080
  209. ## ESD_ESDCTL0 : enable Auto-Refresh
  210. mww 0xB8001000 0x82228080
  211. ## ESD_ESDCTL1 : enable Auto-Refresh
  212. mww 0xB8001008 0x00002000
  213. #***********************************************
  214. # Adjust the ESDCDLY5 register
  215. #***********************************************
  216. # Vary DQS_ABS_OFFSET5 for writes
  217. mww 0xB8001020 0x00F48000 # this is the default value
  218. mww 0xB8001024 0x00F48000 # this is the default value
  219. mww 0xB8001028 0x00F48000 # this is the default value
  220. mww 0xB800102c 0x00F48000 # this is the default value
  221. #Then you can make force measure with the dedicated bit (Bit 7 at ESDMISC)
  222. mww 0xB8001010 0x00000384
  223. # wait a while
  224. sleep 1000
  225. # now clear the force measurement bit
  226. mww 0xB8001010 0x00000304
  227. # dummy write to DDR memory to set DQS low
  228. mww 0x80000000 0x00000000
  229. mww 0x30000100 0x0
  230. mww 0x30000104 0x31024
  231. }