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  1. <html>
  2. <head>
  3. <title>Test results for revision 1.62</title>
  4. </head>
  5. <body>
  6. <H1>LPC2148</H1>
  7. <H2>Connectivity</H2>
  8. <table border=1>
  9. <tr>
  10. <td>ID</td>
  11. <td>Target</td>
  12. <td>Interface</td>
  13. <td>Description</td>
  14. <td>Initial state</td>
  15. <td>Input</td>
  16. <td>Expected output</td>
  17. <td>Actual output</td>
  18. <td>Pass/Fail</td>
  19. </tr>
  20. <tr>
  21. <td><a name="CON001"/>CON001</td>
  22. <td>LPC2148</td>
  23. <td>ZY1000</td>
  24. <td>Telnet connection</td>
  25. <td>Power on, jtag target attached</td>
  26. <td>On console, type<br><code>telnet ip port</code></td>
  27. <td><code>Open On-Chip Debugger<br>></code></td>
  28. <td><code>Open On-Chip Debugger<br>></code></td>
  29. <td>PASS</td>
  30. </tr>
  31. <tr>
  32. <td><a name="CON002"/>CON002</td>
  33. <td>LPC2148</td>
  34. <td>ZY1000</td>
  35. <td>GDB server connection</td>
  36. <td>Power on, jtag target attached</td>
  37. <td>On GDB console, type<br><code>target remote ip:port</code></td>
  38. <td><code>Remote debugging using 10.0.0.73:3333</code></td>
  39. <td><code>
  40. (gdb) tar remo 10.0.0.73:3333<br>
  41. Remote debugging using 10.0.0.73:3333<br>
  42. 0x00000000 in ?? ()<br>
  43. </code></td>
  44. <td>PASS</td>
  45. </tr>
  46. </table>
  47. <H2>Reset</H2>
  48. <table border=1>
  49. <tr>
  50. <td>ID</td>
  51. <td>Target</td>
  52. <td>Interface</td>
  53. <td>Description</td>
  54. <td>Initial state</td>
  55. <td>Input</td>
  56. <td>Expected output</td>
  57. <td>Actual output</td>
  58. <td>Pass/Fail</td>
  59. </tr>
  60. <tr>
  61. <td><a name="RES001"/>RES001</td>
  62. <td>LPC2148</td>
  63. <td>ZY1000</td>
  64. <td>Reset halt on a blank target</td>
  65. <td>Erase all the content of the flash</td>
  66. <td>Connect via the telnet interface and type <br><code>reset halt</code></td>
  67. <td>Reset should return without error and the output should contain<br><code>target state: halted</code></td>
  68. <td>
  69. <code>
  70. > mdw 0 32<br>
  71. 0x00000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
  72. 0x00000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
  73. 0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
  74. 0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
  75. > reset halt<br>
  76. JTAG tap: lpc2148.cpu tap/device found: 0x4f1f0f0f (mfg: 0x787, part: 0xf1f0, ver: 0x4)<br>
  77. srst pulls trst - can not reset into halted mode. Issuing halt after reset.<br>
  78. target state: halted<br>
  79. target halted in Thumb state due to debug-request, current mode: Supervisor<br>
  80. cpsr: 0xa00000f3 pc: 0x7fffd2d6<br>
  81. >
  82. </code>
  83. </td>
  84. <td>PASS</td>
  85. </tr>
  86. <tr>
  87. <td><a name="RES002"/>RES002</td>
  88. <td>LPC2148</td>
  89. <td>ZY1000</td>
  90. <td>Reset init on a blank target</td>
  91. <td>Erase all the content of the flash</td>
  92. <td>Connect via the telnet interface and type <br><code>reset init</code></td>
  93. <td>Reset should return without error and the output should contain <br><code>executing reset script 'name_of_the_script'</code></td>
  94. <td>
  95. <code>
  96. > reset init<br>
  97. JTAG tap: lpc2148.cpu tap/device found: 0x4f1f0f0f (mfg: 0x787, part: 0xf1f0, ver: 0x4)<br>
  98. srst pulls trst - can not reset into halted mode. Issuing halt after reset.<br>
  99. target state: halted<br>
  100. target halted in Thumb state due to debug-request, current mode: Supervisor<br>
  101. cpsr: 0xa00000f3 pc: 0x7fffd2da<br>
  102. core state: ARM<br>
  103. >
  104. </code>
  105. </td>
  106. <td>PASS<br>
  107. NOTE! Even if there is no message, the reset script is being executed (proved by side effects)</td>
  108. </tr>
  109. <tr>
  110. <td><a name="RES003"/>RES003</td>
  111. <td>LPC2148</td>
  112. <td>ZY1000</td>
  113. <td>Reset after a power cycle of the target</td>
  114. <td>Reset the target then power cycle the target</td>
  115. <td>Connect via the telnet interface and type <br><code>reset halt</code> after the power was detected</td>
  116. <td>Reset should return without error and the output should contain<br><code>target state: halted</code></td>
  117. <td>
  118. <code>
  119. nsed nSRST asserted.<br>
  120. nsed power dropout.<br>
  121. nsed power restore.<br>
  122. SRST took 186ms to deassert<br>
  123. JTAG tap: lpc2148.cpu tap/device found: 0x4f1f0f0f (mfg: 0x787, part: 0xf1f0, ver: 0x4)<br>
  124. srst pulls trst - can not reset into halted mode. Issuing halt after reset.<br>
  125. target state: halted<br>
  126. target halted in Thumb state due to debug-request, current mode: Supervisor<br>
  127. cpsr: 0xa00000f3 pc: 0x7fffd2d6<br>
  128. core state: ARM<br>
  129. > reset halt<br>
  130. JTAG tap: lpc2148.cpu tap/device found: 0x4f1f0f0f (mfg: 0x787, part: 0xf1f0, ver: 0x4)<br>
  131. srst pulls trst - can not reset into halted mode. Issuing halt after reset.<br>
  132. target state: halted<br>
  133. target halted in Thumb state due to debug-request, current mode: Supervisor<br>
  134. cpsr: 0xa00000f3 pc: 0x7fffd2d6<br>
  135. >
  136. </code>
  137. </td>
  138. <td>PASS</td>
  139. </tr>
  140. <tr>
  141. <td><a name="RES004"/>RES004</td>
  142. <td>LPC2148</td>
  143. <td>ZY1000</td>
  144. <td>Reset halt on a blank target where reset halt is supported</td>
  145. <td>Erase all the content of the flash</td>
  146. <td>Connect via the telnet interface and type <br><code>reset halt</code></td>
  147. <td>Reset should return without error and the output should contain<br><code>target state: halted<br>pc = 0</code></td>
  148. <td>
  149. <code>
  150. > reset halt<br>
  151. JTAG tap: lpc2148.cpu tap/device found: 0x4f1f0f0f (mfg: 0x787, part: 0xf1f0, ver: 0x4)<br>
  152. srst pulls trst - can not reset into halted mode. Issuing halt after reset.<br>
  153. target state: halted<br>
  154. target halted in Thumb state due to debug-request, current mode: Supervisor<br>
  155. cpsr: 0xa00000f3 pc: 0x7fffd2d6<br>
  156. >
  157. </code>
  158. </td>
  159. <td>PASS</td>
  160. </tr>
  161. <tr>
  162. <td><a name="RES005"/>RES005</td>
  163. <td>LPC2148</td>
  164. <td>ZY1000</td>
  165. <td>Reset halt on a blank target using return clock</td>
  166. <td>Erase all the content of the flash, set the configuration script to use RCLK</td>
  167. <td>Connect via the telnet interface and type <br><code>reset halt</code></td>
  168. <td>Reset should return without error and the output should contain<br><code>target state: halted</code></td>
  169. <td>
  170. <code>
  171. > jtag_khz 0<br>
  172. RCLK - adaptive<br>
  173. > reset init<br>
  174. JTAG tap: lpc2148.cpu tap/device found: 0x4f1f0f0f (mfg: 0x787, part: 0xf1f0, ver: 0x4)<br>
  175. srst pulls trst - can not reset into halted mode. Issuing halt after reset.<br>
  176. target state: halted<br>
  177. target halted in Thumb state due to debug-request, current mode: Supervisor<br>
  178. cpsr: 0xa00000f3 pc: 0x7fffd2d6<br>
  179. core state: ARM<br>
  180. >
  181. </code>
  182. </td>
  183. <td>PASS</td>
  184. </tr>
  185. </table>
  186. <H2>JTAG Speed</H2>
  187. <table border=1>
  188. <tr>
  189. <td>ID</td>
  190. <td>Target</td>
  191. <td>ZY1000</td>
  192. <td>Description</td>
  193. <td>Initial state</td>
  194. <td>Input</td>
  195. <td>Expected output</td>
  196. <td>Actual output</td>
  197. <td>Pass/Fail</td>
  198. </tr>
  199. <tr>
  200. <td><a name="SPD001"/>SPD001</td>
  201. <td>LPC2148</td>
  202. <td>ZY1000</td>
  203. <td>16MHz on normal operation</td>
  204. <td>Reset init the target according to RES002 </td>
  205. <td>Change speed and exercise a memory access over the JTAG, for example <br><code>mdw 0x0 32</code></td>
  206. <td>The command should run without any errors. If any JTAG checking errors happen, the test failed</td>
  207. <td>
  208. <code>
  209. > jtag_khz 16000<br>
  210. jtag_speed 4 => JTAG clk=16.000000<br>
  211. 16000 kHz<br>
  212. > reset halt<br>
  213. JTAG scan chain interrogation failed: all zeroes<br>
  214. Check JTAG interface, timings, target power, etc.<br>
  215. error: -100<br>
  216. Command handler execution failed<br>
  217. in procedure 'reset' called at file "command.c", line 638<br>
  218. called at file "/home/laurentiu/workspace/zy1000/build/../openocd/src/helper/command.c", line 352<br>
  219. invalid mode value encountered 0<br>
  220. cpsr contains invalid mode value - communication failure<br>
  221. ThumbEE -- incomplete support<br>
  222. target state: halted<br>
  223. target halted in ThumbEE state due to debug-request, current mode: System<br>
  224. cpsr: 0x1fffffff pc: 0xfffffffa<br>
  225. invalid mode value encountered 0<br>
  226. cpsr contains invalid mode value - communication failure<br>
  227. target state: halted<br>
  228. target halted in Thumb state due to debug-request, current mode: System<br>
  229. cpsr: 0xc00003ff pc: 0xfffffff0<br>
  230. invalid mode value encountered 0<br>
  231. cpsr contains invalid mode value - communication failure<br>
  232. invalid mode value encountered 0<br>
  233. cpsr contains invalid mode value - communication failure<br>
  234. invalid mode value encountered 0<br>
  235. cpsr contains invalid mode value - communication failure<br>
  236. invalid mode value encountered 0<br>
  237. cpsr contains invalid mode value - communication failure<br>
  238. ThumbEE -- incomplete support<br>
  239. target state: halted<br>
  240. target halted in ThumbEE state due to debug-request, current mode: System<br>
  241. cpsr: 0xffffffff pc: 0xfffffffa<br>
  242. >
  243. </code>
  244. </td>
  245. <td><font color=red><b>FAIL</b></font></td>
  246. </tr>
  247. <tr>
  248. <td><a name="SPD002"/>SPD002</td>
  249. <td>LPC2148</td>
  250. <td>ZY1000</td>
  251. <td>8MHz on normal operation</td>
  252. <td>Reset init the target according to RES002 </td>
  253. <td>Change speed and exercise a memory access over the JTAG, for example <br><code>mdw 0x0 32</code></td>
  254. <td>The command should run without any errors. If any JTAG checking errors happen, the test failed</td>
  255. <td>
  256. <code>
  257. > jtag_khz 8000<br>
  258. jtag_speed 8 => JTAG clk=8.000000<br>
  259. 8000 kHz<br>
  260. > reset halt<br>
  261. JTAG scan chain interrogation failed: all zeroes<br>
  262. Check JTAG interface, timings, target power, etc.<br>
  263. error: -100<br>
  264. Command handler execution failed<br>
  265. in procedure 'reset' called at file "command.c", line 638<br>
  266. called at file "/home/laurentiu/workspace/zy1000/build/../openocd/src/helper/command.c", line 352<br>
  267. invalid mode value encountered 0<br>
  268. cpsr contains invalid mode value - communication failure<br>
  269. invalid mode value encountered 0<br>
  270. cpsr contains invalid mode value - communication failure<br>
  271. >
  272. </code>
  273. </td>
  274. <td><font color=red><b>FAIL</b></font></td>
  275. </tr>
  276. <tr>
  277. <td><a name="SPD003"/>SPD003</td>
  278. <td>LPC2148</td>
  279. <td>ZY1000</td>
  280. <td>4MHz on normal operation</td>
  281. <td>Reset init the target according to RES002 </td>
  282. <td>Change speed and exercise a memory access over the JTAG, for example <br><code>mdw 0x0 32</code></td>
  283. <td>The command should run without any errors. If any JTAG checking errors happen, the test failed</td>
  284. <td>
  285. <code>
  286. > jtag_khz 4000<br>
  287. jtag_speed 16 => JTAG clk=4.000000<br>
  288. 4000 kHz<br>
  289. > reset halt<br>
  290. JTAG tap: lpc2148.cpu tap/device found: 0xc79f0f87 (mfg: 0x7c3, part: 0x79f0, ver: 0xc)<br>
  291. JTAG tap: lpc2148.cpu UNEXPECTED: 0xc79f0f87 (mfg: 0x7c3, part: 0x79f0, ver: 0xc)<br>
  292. JTAG tap: lpc2148.cpu expected 1 of 1: 0x4f1f0f0f (mfg: 0x787, part: 0xf1f0, ver: 0x4)<br>
  293. Unexpected idcode after end of chain: 64 0x0000007f<br>
  294. Unexpected idcode after end of chain: 160 0x0000007f<br>
  295. Unexpected idcode after end of chain: 192 0x0000007f<br>
  296. Unexpected idcode after end of chain: 320 0x0000007f<br>
  297. Unexpected idcode after end of chain: 352 0x0000007f<br>
  298. Unexpected idcode after end of chain: 384 0x0000007f<br>
  299. Unexpected idcode after end of chain: 480 0x0000007f<br>
  300. Unexpected idcode after end of chain: 512 0x0000007f<br>
  301. Unexpected idcode after end of chain: 544 0x0000007f<br>
  302. double-check your JTAG setup (interface, speed, missing TAPs, ...)<br>
  303. error: -100<br>
  304. Command handler execution failed<br>
  305. in procedure 'reset' called at file "command.c", line 638<br>
  306. called at file "/home/laurentiu/workspace/zy1000/build/../openocd/src/helper/command.c", line 352<br>
  307. >
  308. </code>
  309. </td>
  310. <td><font color=red><b>FAIL</b></font></td>
  311. </tr>
  312. <tr>
  313. <td><a name="SPD004"/>SPD004</td>
  314. <td>LPC2148</td>
  315. <td>ZY1000</td>
  316. <td>2MHz on normal operation</td>
  317. <td>Reset init the target according to RES002 </td>
  318. <td>Change speed and exercise a memory access over the JTAG, for example <br><code>mdw 0x0 32</code></td>
  319. <td>The command should run without any errors. If any JTAG checking errors happen, the test failed</td>
  320. <td>
  321. <code>
  322. > jtag_khz 2000<br>
  323. jtag_speed 32 => JTAG clk=2.000000<br>
  324. 2000 kHz<br>
  325. > reset halt<br>
  326. JTAG tap: lpc2148.cpu tap/device found: 0x4f1f0f0f (mfg: 0x787, part: 0xf1f0, ver: 0x4)<br>
  327. srst pulls trst - can not reset into halted mode. Issuing halt after reset.<br>
  328. target state: halted<br>
  329. target halted in Thumb state due to debug-request, current mode: Supervisor<br>
  330. cpsr: 0xa00000f3 pc: 0x7fffd2da<br>
  331. > mdw 0 32<br>
  332. 0x00000000: e59f4034 e3a05002 e5845000 e3a05003 e5845004 e59f201c e3a03000 e1020093<br>
  333. 0x00000020: e2822028 e1021093 e3c03007 e5023028 e51ff004 7fffd1c4 e002c014 e01fc000<br>
  334. 0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
  335. 0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
  336. >
  337. </code>
  338. </td>
  339. <td>PASS</td>
  340. </tr>
  341. <tr>
  342. <td><a name="SPD005"/>SPD005</td>
  343. <td>LPC2148</td>
  344. <td>ZY1000</td>
  345. <td>RCLK on normal operation</td>
  346. <td>Reset init the target according to RES002 </td>
  347. <td>Change speed and exercise a memory access over the JTAG, for example <br><code>mdw 0x0 32</code></td>
  348. <td>The command should run without any errors. If any JTAG checking errors happen, the test failed</td>
  349. <td>
  350. <code>
  351. > jtag_khz 0<br>
  352. RCLK - adaptive<br>
  353. > mdw 0 32<br>
  354. 0x00000000: e59f4034 e3a05002 e5845000 e3a05003 e5845004 e59f201c e3a03000 e1020093<br>
  355. 0x00000020: e2822028 e1021093 e3c03007 e5023028 e51ff004 7fffd1c4 e002c014 e01fc000<br>
  356. 0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
  357. 0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
  358. >
  359. </code>
  360. </td>
  361. <td>PASS</td>
  362. </tr>
  363. </table>
  364. <H2>Debugging</H2>
  365. <table border=1>
  366. <tr>
  367. <td>ID</td>
  368. <td>Target</td>
  369. <td>Interface</td>
  370. <td>Description</td>
  371. <td>Initial state</td>
  372. <td>Input</td>
  373. <td>Expected output</td>
  374. <td>Actual output</td>
  375. <td>Pass/Fail</td>
  376. </tr>
  377. <tr>
  378. <td><a name="DBG001"/>DBG001</td>
  379. <td>LPC2148</td>
  380. <td>ZY1000</td>
  381. <td>Load is working</td>
  382. <td>Reset init is working, RAM is accesible, GDB server is started</td>
  383. <td>On the console of the OS: <br>
  384. <code>arm-elf-gdb test_ram.elf</code><br>
  385. <code>(gdb) target remote ip:port</code><br>
  386. <code>(gdb) load</load>
  387. </td>
  388. <td>Load should return without error, typical output looks like:<br>
  389. <code>
  390. Loading section .text, size 0x14c lma 0x0<br>
  391. Start address 0x40, load size 332<br>
  392. Transfer rate: 180 bytes/sec, 332 bytes/write.<br>
  393. </code>
  394. </td>
  395. <td><code>
  396. (gdb) load<br>
  397. Loading section .text, size 0x16c lma 0x40000000<br>
  398. Start address 0x40000040, load size 364<br>
  399. Transfer rate: 32 KB/sec, 364 bytes/write.<br>
  400. (gdb)
  401. </code></td>
  402. <td>PASS</td>
  403. </tr>
  404. <tr>
  405. <td><a name="DBG002"/>DBG002</td>
  406. <td>LPC2148</td>
  407. <td>ZY1000</td>
  408. <td>Software breakpoint</td>
  409. <td>Load the test_ram.elf application, use instructions from GDB001</td>
  410. <td>In the GDB console:<br>
  411. <code>
  412. (gdb) monitor gdb_breakpoint_override soft<br>
  413. software breakpoints enabled<br>
  414. (gdb) break main<br>
  415. Breakpoint 1 at 0xec: file src/main.c, line 71.<br>
  416. (gdb) continue<br>
  417. Continuing.
  418. </code>
  419. </td>
  420. <td>The software breakpoint should be reached, a typical output looks like:<br>
  421. <code>
  422. target state: halted<br>
  423. target halted in ARM state due to breakpoint, current mode: Supervisor<br>
  424. cpsr: 0x000000d3 pc: 0x000000ec<br>
  425. <br>
  426. Breakpoint 1, main () at src/main.c:71<br>
  427. 71 DWORD a = 1;
  428. </code>
  429. </td>
  430. <td>
  431. <code>
  432. (gdb) monitor gdb_breakpoint_override soft<br>
  433. force soft breakpoints<br>
  434. Current language: auto<br>
  435. The current source language is "auto; currently asm".<br>
  436. (gdb) break main<br>
  437. Breakpoint 1 at 0x4000010c: file src/main.c, line 71.<br>
  438. (gdb) c<br>
  439. Continuing.<br>
  440. <br>
  441. Breakpoint 1, main () at src/main.c:71<br>
  442. 71 DWORD a = 1;<br>
  443. Current language: auto<br>
  444. The current source language is "auto; currently c".<br>
  445. (gdb)
  446. </code>
  447. </td>
  448. <td>PASS</td>
  449. </tr>
  450. <tr>
  451. <td><a name="DBG003"/>DBG003</td>
  452. <td>LPC2148</td>
  453. <td>ZY1000</td>
  454. <td>Single step in a RAM application</td>
  455. <td>Load the test_ram.elf application, use instructions from GDB001, break in main using the instructions from GDB002</td>
  456. <td>In GDB, type <br><code>(gdb) step</code></td>
  457. <td>The next instruction should be reached, typical output:<br>
  458. <code>
  459. (gdb) step<br>
  460. target state: halted<br>
  461. target halted in ARM state due to single step, current mode: Abort<br>
  462. cpsr: 0x20000097 pc: 0x000000f0<br>
  463. target state: halted<br>
  464. target halted in ARM state due to single step, current mode: Abort<br>
  465. cpsr: 0x20000097 pc: 0x000000f4<br>
  466. 72 DWORD b = 2;
  467. </code>
  468. </td>
  469. <td>
  470. <code>
  471. (gdb) step<br>
  472. 72 DWORD b = 2;<br>
  473. (gdb)
  474. </code>
  475. </td>
  476. <td>PASS</td>
  477. </tr>
  478. <tr>
  479. <td><a name="DBG004"/>DBG004</td>
  480. <td>LPC2148</td>
  481. <td>ZY1000</td>
  482. <td>Software break points are working after a reset</td>
  483. <td>Load the test_ram.elf application, use instructions from GDB001, break in main using the instructions from GDB002</td>
  484. <td>In GDB, type <br><code>
  485. (gdb) monitor reset init<br>
  486. (gdb) load<br>
  487. (gdb) continue<br>
  488. </code></td>
  489. <td>The breakpoint should be reached, typical output:<br>
  490. <code>
  491. target state: halted<br>
  492. target halted in ARM state due to breakpoint, current mode: Supervisor<br>
  493. cpsr: 0x000000d3 pc: 0x000000ec<br>
  494. <br>
  495. Breakpoint 1, main () at src/main.c:71<br>
  496. 71 DWORD a = 1;
  497. </code>
  498. </td>
  499. <td><code>
  500. (gdb) moni reset init<br>
  501. JTAG tap: lpc2148.cpu tap/device found: 0x4f1f0f0f (mfg: 0x787, part: 0xf1f0, ver: 0x4)<br>
  502. srst pulls trst - can not reset into halted mode. Issuing halt after reset.<br>
  503. target state: halted<br>
  504. target halted in Thumb state due to debug-request, current mode: Supervisor<br>
  505. cpsr: 0xa00000f3 pc: 0x7fffd2d6<br>
  506. core state: ARM<br>
  507. (gdb) load<br>
  508. Loading section .text, size 0x16c lma 0x40000000<br>
  509. Start address 0x40000040, load size 364<br>
  510. Transfer rate: 27 KB/sec, 364 bytes/write.<br>
  511. (gdb) c<br>
  512. Continuing.<br>
  513. <br>
  514. Breakpoint 1, main () at src/main.c:71<br>
  515. 71 DWORD a = 1;<br>
  516. (gdb)
  517. </code></td>
  518. <td>PASS</td>
  519. </tr>
  520. <tr>
  521. <td><a name="DBG005"/>DBG005</td>
  522. <td>LPC2148</td>
  523. <td>ZY1000</td>
  524. <td>Hardware breakpoint</td>
  525. <td>Flash the test_rom.elf application. Make this test after FLA004 has passed</td>
  526. <td>Be sure that <code>gdb_memory_map</code> and <code>gdb_flash_program</code> are enabled. In GDB, type <br>
  527. <code>
  528. (gdb) monitor reset init<br>
  529. (gdb) load<br>
  530. Loading section .text, size 0x194 lma 0x100000<br>
  531. Start address 0x100040, load size 404<br>
  532. Transfer rate: 179 bytes/sec, 404 bytes/write.<br>
  533. (gdb) monitor gdb_breakpoint_override hard<br>
  534. force hard breakpoints<br>
  535. (gdb) break main<br>
  536. Breakpoint 1 at 0x100134: file src/main.c, line 69.<br>
  537. (gdb) continue<br>
  538. </code>
  539. </td>
  540. <td>The breakpoint should be reached, typical output:<br>
  541. <code>
  542. Continuing.<br>
  543. <br>
  544. Breakpoint 1, main () at src/main.c:69<br>
  545. 69 DWORD a = 1;<br>
  546. </code>
  547. </td>
  548. <td>
  549. <code>
  550. (gdb) monitor gdb_breakpoint_override hard<br>
  551. force hard breakpoints<br>
  552. (gdb) break main<br>
  553. Breakpoint 1 at 0x10c: file src/main.c, line 71.<br>
  554. (gdb) continue<br>
  555. Continuing.<br>
  556. Note: automatically using hardware breakpoints for read-only addresses.<br>
  557. <br>
  558. Breakpoint 1, main () at src/main.c:71<br>
  559. 71 DWORD a = 1;<br>
  560. Current language: auto<br>
  561. The current source language is "auto; currently c".<br>
  562. (gdb)
  563. </code>
  564. </td>
  565. <td>PASS <font color=red>NOTE: This test is failing from time to time, not able to describe a cause</font></td>
  566. </tr>
  567. <tr>
  568. <td><a name="DBG006"/>DBG006</td>
  569. <td>LPC2148</td>
  570. <td>ZY1000</td>
  571. <td>Hardware breakpoint is set after a reset</td>
  572. <td>Follow the instructions to flash and insert a hardware breakpoint from DBG005</td>
  573. <td>In GDB, type <br>
  574. <code>
  575. (gdb) monitor reset<br>
  576. (gdb) monitor reg pc 0x100000<br>
  577. pc (/32): 0x00100000<br>
  578. (gdb) continue
  579. </code><br>
  580. where the value inserted in PC is the start address of the application
  581. </td>
  582. <td>The breakpoint should be reached, typical output:<br>
  583. <code>
  584. Continuing.<br>
  585. <br>
  586. Breakpoint 1, main () at src/main.c:69<br>
  587. 69 DWORD a = 1;<br>
  588. </code>
  589. </td>
  590. <td>
  591. <code>
  592. (gdb) monitor reset init<br>
  593. JTAG tap: lpc2148.cpu tap/device found: 0x4f1f0f0f (mfg: 0x787, part: 0xf1f0, ver: 0x4)<br>
  594. srst pulls trst - can not reset into halted mode. Issuing halt after reset.<br>
  595. target state: halted<br>
  596. target halted in ARM state due to debug-request, current mode: Supervisor<br>
  597. cpsr: 0x60000013 pc: 0x00000160<br>
  598. core state: ARM<br>
  599. (gdb) monitor reg pc 0x40<br>
  600. pc (/32): 0x00000040<br>
  601. (gdb) continue<br>
  602. Continuing.<br>
  603. <br>
  604. Breakpoint 1, main () at src/main.c:71<br>
  605. 71 DWORD a = 1;<br>
  606. (gdb)
  607. </code>
  608. </td>
  609. <td>PASS</td>
  610. </tr>
  611. <tr>
  612. <td><a name="DBG007"/>DBG007</td>
  613. <td>LPC2148</td>
  614. <td>ZY1000</td>
  615. <td>Single step in ROM</td>
  616. <td>Flash the test_rom.elf application and set a breakpoint in main, use DBG005. Make this test after FLA004 has passed</td>
  617. <td>Be sure that <code>gdb_memory_map</code> and <code>gdb_flash_program</code> are enabled. In GDB, type <br>
  618. <code>
  619. (gdb) monitor reset<br>
  620. (gdb) load<br>
  621. Loading section .text, size 0x194 lma 0x100000<br>
  622. Start address 0x100040, load size 404<br>
  623. Transfer rate: 179 bytes/sec, 404 bytes/write.<br>
  624. (gdb) monitor gdb_breakpoint_override hard<br>
  625. force hard breakpoints<br>
  626. (gdb) break main<br>
  627. Breakpoint 1 at 0x100134: file src/main.c, line 69.<br>
  628. (gdb) continue<br>
  629. Continuing.<br>
  630. <br>
  631. Breakpoint 1, main () at src/main.c:69<br>
  632. 69 DWORD a = 1;<br>
  633. (gdb) step
  634. </code>
  635. </td>
  636. <td>The breakpoint should be reached, typical output:<br>
  637. <code>
  638. target state: halted<br>
  639. target halted in ARM state due to single step, current mode: Supervisor<br>
  640. cpsr: 0x60000013 pc: 0x0010013c<br>
  641. 70 DWORD b = 2;<br>
  642. </code>
  643. </td>
  644. <td><code>
  645. (gdb) load<br>
  646. Loading section .text, size 0x16c lma 0x0<br>
  647. Start address 0x40, load size 364<br>
  648. Transfer rate: 637 bytes/sec, 364 bytes/write.<br>
  649. (gdb) monitor gdb_breakpoint_override hard<br>
  650. force hard breakpoints<br>
  651. Current language: auto<br>
  652. The current source language is "auto; currently asm".<br>
  653. (gdb) break main<br>
  654. Breakpoint 1 at 0x10c: file src/main.c, line 71.<br>
  655. (gdb) continue<br>
  656. Continuing.<br>
  657. Note: automatically using hardware breakpoints for read-only addresses.<br>
  658. <br>
  659. Breakpoint 1, main () at src/main.c:71<br>
  660. 71 DWORD a = 1;<br>
  661. Current language: auto<br>
  662. The current source language is "auto; currently c".<br>
  663. (gdb) step<br>
  664. 72 DWORD b = 2;<br>
  665. (gdb)
  666. </code></td>
  667. <td>PASS</td>
  668. </tr>
  669. </table>
  670. <H2>RAM access</H2>
  671. Note: these tests are not designed to test/debug the target, but to test functionalities!
  672. <table border=1>
  673. <tr>
  674. <td>ID</td>
  675. <td>Target</td>
  676. <td>Interface</td>
  677. <td>Description</td>
  678. <td>Initial state</td>
  679. <td>Input</td>
  680. <td>Expected output</td>
  681. <td>Actual output</td>
  682. <td>Pass/Fail</td>
  683. </tr>
  684. <tr>
  685. <td><a name="RAM001"/>RAM001</td>
  686. <td>LPC2148</td>
  687. <td>ZY1000</td>
  688. <td>32 bit Write/read RAM</td>
  689. <td>Reset init is working</td>
  690. <td>On the telnet interface<br>
  691. <code> > mww ram_address 0xdeadbeef 16<br>
  692. > mdw ram_address 32
  693. </code>
  694. </td>
  695. <td>The commands should execute without error. A clear failure is a memory access exception. The result of running the commands should be a list of 16 locations 32bit long containing 0xdeadbeef.<br>
  696. <code>
  697. > mww 0x0 0xdeadbeef 16<br>
  698. > mdw 0x0 32<br>
  699. 0x00000000: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
  700. 0x00000020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
  701. 0x00000040: e1a00000 e59fa51c e59f051c e04aa000 00080017 00009388 00009388 00009388<br>
  702. 0x00000060: 00009388 0002c2c0 0002c2c0 000094f8 000094f4 00009388 00009388 00009388<br>
  703. </code>
  704. </td>
  705. <td><code>
  706. > mww 0x40000000 0xdeadbeef 16<br>
  707. > mdw 0x40000000 32<br>
  708. 0x40000000: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
  709. 0x40000020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
  710. 0x40000040: e1a00000 e1a00000 e1a00000 e1a00000 e1a00000 e1a00000 e1a00000 e1a00000<br>
  711. 0x40000060: e321f0db e59fd07c e321f0d7 e59fd078 e321f0d1 e59fd074 e321f0d2 e59fd070<br>
  712. >
  713. </code></td>
  714. <td>PASS</td>
  715. </tr>
  716. <tr>
  717. <td><a name="RAM002"/>RAM002</td>
  718. <td>LPC2148</td>
  719. <td>ZY1000</td>
  720. <td>16 bit Write/read RAM</td>
  721. <td>Reset init is working</td>
  722. <td>On the telnet interface<br>
  723. <code> > mwh ram_address 0xbeef 16<br>
  724. > mdh ram_address 32
  725. </code>
  726. </td>
  727. <td>The commands should execute without error. A clear failure is a memory access exception. The result of running the commands should be a list of 16 locations 16bit long containing 0xbeef.<br>
  728. <code>
  729. > mwh 0x0 0xbeef 16<br>
  730. > mdh 0x0 32<br>
  731. 0x00000000: beef beef beef beef beef beef beef beef beef beef beef beef beef beef beef beef<br>
  732. 0x00000020: 00e0 0000 021c 0000 0240 0000 026c 0000 0288 0000 0000 0000 0388 0000 0350 0000<br>
  733. >
  734. </code>
  735. </td>
  736. <td><code>
  737. > mwh 0x40000000 0xbeef 16<br>
  738. > mdh 0x40000000 32<br>
  739. 0x40000000: beef beef beef beef beef beef beef beef beef beef beef beef beef beef beef beef<br>
  740. 0x40000020: beef dead beef dead beef dead beef dead beef dead beef dead beef dead beef dead<br>
  741. >
  742. </code></td>
  743. <td>PASS</td>
  744. </tr>
  745. <tr>
  746. <td><a name="RAM003"/>RAM003</td>
  747. <td>LPC2148</td>
  748. <td>ZY1000</td>
  749. <td>8 bit Write/read RAM</td>
  750. <td>Reset init is working</td>
  751. <td>On the telnet interface<br>
  752. <code> > mwb ram_address 0xab 16<br>
  753. > mdb ram_address 32
  754. </code>
  755. </td>
  756. <td>The commands should execute without error. A clear failure is a memory access exception. The result of running the commands should be a list of 16 locations 8bit long containing 0xab.<br>
  757. <code>
  758. > mwb ram_address 0xab 16<br>
  759. > mdb ram_address 32<br>
  760. 0x00000000: ab ab ab ab ab ab ab ab ab ab ab ab ab ab ab ab 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>
  761. >
  762. </code>
  763. </td>
  764. <td><code>
  765. > mwb 0x40000000 0xab 16
  766. > mdb 0x40000000 32
  767. 0x40000000: ab ab ab ab ab ab ab ab ab ab ab ab ab ab ab ab ef be ef be ef be ef be ef be ef be ef be ef be
  768. >
  769. </code></td>
  770. <td>PASS</td>
  771. </tr>
  772. </table>
  773. <H2>Flash access</H2>
  774. <table border=1>
  775. <tr>
  776. <td>ID</td>
  777. <td>Target</td>
  778. <td>Interface</td>
  779. <td>Description</td>
  780. <td>Initial state</td>
  781. <td>Input</td>
  782. <td>Expected output</td>
  783. <td>Actual output</td>
  784. <td>Pass/Fail</td>
  785. </tr>
  786. <tr>
  787. <td><a name="FLA001"/>FLA001</td>
  788. <td>LPC2148</td>
  789. <td>ZY1000</td>
  790. <td>Flash probe</td>
  791. <td>Reset init is working</td>
  792. <td>On the telnet interface:<br>
  793. <code> > flash probe 0</code>
  794. </td>
  795. <td>The command should execute without error. The output should state the name of the flash and the starting address. An example of output:<br>
  796. <code>flash 'ecosflash' found at 0x01000000</code>
  797. </td>
  798. <td>
  799. <code>
  800. > flash probe 0<br>
  801. flash 'lpc2000' found at 0x00000000
  802. </code>
  803. </td>
  804. <td>PASS</td>
  805. </tr>
  806. <tr>
  807. <td><a name="FLA002"/>FLA002</td>
  808. <td>LPC2148</td>
  809. <td>ZY1000</td>
  810. <td>flash fillw</td>
  811. <td>Reset init is working, flash is probed</td>
  812. <td>On the telnet interface<br>
  813. <code> > flash fillw 0x1000000 0xdeadbeef 16
  814. </code>
  815. </td>
  816. <td>The commands should execute without error. The output looks like:<br>
  817. <code>
  818. wrote 64 bytes to 0x01000000 in 11.610000s (0.091516 kb/s)
  819. </code><br>
  820. To verify the contents of the flash:<br>
  821. <code>
  822. > mdw 0x1000000 32<br>
  823. 0x01000000: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
  824. 0x01000020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
  825. 0x01000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
  826. 0x01000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
  827. </code>
  828. </td>
  829. <td><code>
  830. > flash fillw 0x0 0xdeadbeef 16<br>
  831. Verification will fail since checksum in image (0xdeadbeef) to be written to flash is different from calculated vector checksum (0xe93fc777).<br>
  832. To remove this warning modify build tools on developer PC to inject correct LPC vector checksum.<br>
  833. wrote 64 bytes to 0x00000000 in 0.040000s (1.563 kb/s)<br>
  834. > mdw 0 32<br>
  835. 0x00000000: deadbeef deadbeef deadbeef deadbeef deadbeef e93fc777 deadbeef deadbeef<br>
  836. 0x00000020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
  837. 0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
  838. 0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
  839. >
  840. </code></td>
  841. <td><font color=red>FAIL</font></td>
  842. </tr>
  843. <tr>
  844. <td><a name="FLA003"/>FLA003</td>
  845. <td>LPC2148</td>
  846. <td>ZY1000</td>
  847. <td>Flash erase</td>
  848. <td>Reset init is working, flash is probed</td>
  849. <td>On the telnet interface<br>
  850. <code> > flash erase_address 0x1000000 0x2000
  851. </code>
  852. </td>
  853. <td>The commands should execute without error.<br>
  854. <code>
  855. erased address 0x01000000 length 8192 in 4.970000s
  856. </code>
  857. To check that the flash has been erased, read at different addresses. The result should always be 0xff.
  858. <code>
  859. > mdw 0x1000000 32<br>
  860. 0x01000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
  861. 0x01000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
  862. 0x01000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
  863. 0x01000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
  864. </code>
  865. </td>
  866. <td><code>
  867. > flash erase_address 0 0x2000<br>
  868. erased address 0x00000000 (length 8192) in 0.510000s (15.686 kb/s)<br>
  869. > mdw 0 32<br>
  870. 0x00000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
  871. 0x00000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
  872. 0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
  873. 0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
  874. >
  875. </code></td>
  876. <td>PASS</td>
  877. </tr>
  878. <tr>
  879. <td><a name="FLA004"/>FLA004</td>
  880. <td>LPC2148</td>
  881. <td>ZY1000</td>
  882. <td>Loading to flash from GDB</td>
  883. <td>Reset init is working, flash is probed, connectivity to GDB server is working</td>
  884. <td>Start GDB using a ROM elf image, eg: arm-elf-gdb test_rom.elf. <br>
  885. <code>
  886. (gdb) target remote ip:port<br>
  887. (gdb) monitor reset<br>
  888. (gdb) load<br>
  889. Loading section .text, size 0x194 lma 0x100000<br>
  890. Start address 0x100040, load size 404<br>
  891. Transfer rate: 179 bytes/sec, 404 bytes/write.
  892. (gdb) monitor verify_image path_to_elf_file
  893. </code>
  894. </td>
  895. <td>The output should look like:<br>
  896. <code>
  897. verified 404 bytes in 5.060000s
  898. </code><br>
  899. The failure message is something like:<br>
  900. <code>Verify operation failed address 0x00200000. Was 0x00 instead of 0x18</code>
  901. </td>
  902. <td>
  903. <code>
  904. (gdb) moni verify_image /tftp/10.0.0.194/test_rom.elf<br>
  905. checksum mismatch - attempting binary compare<br>
  906. Verify operation failed address 0x00000014. Was 0x58 instead of 0x60<br>
  907. <br>
  908. Command handler execution failed<br>
  909. in procedure 'verify_image' called at file "command.c", line 647<br>
  910. called at file "command.c", line 361<br>
  911. (gdb)
  912. </code>
  913. </td>
  914. <td><font color=red>FAIL</font></td>
  915. </tr>
  916. </table>
  917. </body>
  918. </html>