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  1. <html>
  2. <head>
  3. <title>Test results for revision 1.62</title>
  4. </head>
  5. <body>
  6. <H1>SAM7</H1>
  7. <H2>Connectivity</H2>
  8. <table border=1>
  9. <tr>
  10. <td>ID</td>
  11. <td>Target</td>
  12. <td>Interface</td>
  13. <td>Description</td>
  14. <td>Initial state</td>
  15. <td>Input</td>
  16. <td>Expected output</td>
  17. <td>Actual output</td>
  18. <td>Pass/Fail</td>
  19. </tr>
  20. <tr>
  21. <td><a name="CON001"/>CON001</td>
  22. <td>SAM7S64</td>
  23. <td>ZY1000</td>
  24. <td>Telnet connection</td>
  25. <td>Power on, jtag target attached</td>
  26. <td>On console, type<br><code>telnet ip port</code></td>
  27. <td><code>Open On-Chip Debugger<br>></code></td>
  28. <td><code>Open On-Chip Debugger<br>></code></td>
  29. <td>PASS</td>
  30. </tr>
  31. <tr>
  32. <td><a name="CON002"/>CON002</td>
  33. <td>SAM7S64</td>
  34. <td>ZY1000</td>
  35. <td>GDB server connection</td>
  36. <td>Power on, jtag target attached</td>
  37. <td>On GDB console, type<br><code>target remote ip:port</code></td>
  38. <td><code>Remote debugging using 10.0.0.73:3333</code></td>
  39. <td><code>
  40. (gdb) tar remo 10.0.0.73:3333<br>
  41. Remote debugging using 10.0.0.73:3333<br>
  42. 0x00100174 in ?? ()<br>
  43. </code></td>
  44. <td>PASS</td>
  45. </tr>
  46. </table>
  47. <H2>Reset</H2>
  48. <table border=1>
  49. <tr>
  50. <td>ID</td>
  51. <td>Target</td>
  52. <td>Interface</td>
  53. <td>Description</td>
  54. <td>Initial state</td>
  55. <td>Input</td>
  56. <td>Expected output</td>
  57. <td>Actual output</td>
  58. <td>Pass/Fail</td>
  59. </tr>
  60. <tr>
  61. <td><a name="RES001"/>RES001</td>
  62. <td>SAM7S64</td>
  63. <td>ZY1000</td>
  64. <td>Reset halt on a blank target</td>
  65. <td>Erase all the content of the flash</td>
  66. <td>Connect via the telnet interface and type <br><code>reset halt</code></td>
  67. <td>Reset should return without error and the output should contain<br><code>target state: halted</code></td>
  68. <td>
  69. <code>
  70. > mdw 0 32<br>
  71. 0x00000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
  72. 0x00000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
  73. 0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
  74. 0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
  75. > reset halt<br>
  76. SRST took 2ms to deassert<br>
  77. JTAG device found: 0x3f0f0f0f (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)<br>
  78. srst pulls trst - can not reset into halted mode. Issuing halt after reset.<br>
  79. target state: halted<br>
  80. target halted in ARM state due to debug request, current mode: Supervisor<br>
  81. cpsr: 0x600000d3 pc: 0x000003c4<br>
  82. >
  83. </code>
  84. </td>
  85. <td>PASS</td>
  86. </tr>
  87. <tr>
  88. <td><a name="RES002"/>RES002</td>
  89. <td>SAM7S64</td>
  90. <td>ZY1000</td>
  91. <td>Reset init on a blank target</td>
  92. <td>Erase all the content of the flash</td>
  93. <td>Connect via the telnet interface and type <br><code>reset init</code></td>
  94. <td>Reset should return without error and the output should contain <br><code>executing reset script 'name_of_the_script'</code></td>
  95. <td>
  96. <code>
  97. > reset init<br>
  98. SRST took 2ms to deassert<br>
  99. JTAG device found: 0x3f0f0f0f (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)<br>
  100. srst pulls trst - can not reset into halted mode. Issuing halt after reset.<br>
  101. target state: halted<br>
  102. target halted in ARM state due to debug request, current mode: Supervisor<br>
  103. cpsr: 0x600000d3 pc: 0x000003c0<br>
  104. >
  105. </code>
  106. </td>
  107. <td>PASS<br>
  108. NOTE! Even if there is no message, the reset script is being executed (proved by side effects)</td>
  109. </tr>
  110. <tr>
  111. <td><a name="RES003"/>RES003</td>
  112. <td>SAM7S64</td>
  113. <td>ZY1000</td>
  114. <td>Reset after a power cycle of the target</td>
  115. <td>Reset the target then power cycle the target</td>
  116. <td>Connect via the telnet interface and type <br><code>reset halt</code> after the power was detected</td>
  117. <td>Reset should return without error and the output should contain<br><code>target state: halted</code></td>
  118. <td>
  119. <code>
  120. Sensed nSRST asserted<br>
  121. Sensed power dropout.<br>
  122. target state: halted<br>
  123. target halted in ARM state due to debug request, current mode: Supervisor<br>
  124. cpsr: 0xf00000d3 pc: 0xd5dff7e6<br>
  125. Sensed power restore.<br>
  126. Sensed nSRST deasserted<br>
  127. > reset halt<br>
  128. JTAG device found: 0x3f0f0f0f (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)<br>
  129. srst pulls trst - can not reset into halted mode. Issuing halt after reset.<br>
  130. target state: halted<br>
  131. target halted in ARM state due to debug request, current mode: Supervisor<br>
  132. cpsr: 0xf00000d3 pc: 0x0000072c<br>
  133. >
  134. </code>
  135. </td>
  136. <td>PASS</td>
  137. </tr>
  138. <tr>
  139. <td><a name="RES004"/>RES004</td>
  140. <td>SAM7S64</td>
  141. <td>ZY1000</td>
  142. <td>Reset halt on a blank target where reset halt is supported</td>
  143. <td>Erase all the content of the flash</td>
  144. <td>Connect via the telnet interface and type <br><code>reset halt</code></td>
  145. <td>Reset should return without error and the output should contain<br><code>target state: halted<br>pc = 0</code></td>
  146. <td>
  147. <code>
  148. > reset halt<br>
  149. SRST took 2ms to deassert<br>
  150. JTAG device found: 0x3f0f0f0f (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)<br>
  151. srst pulls trst - can not reset into halted mode. Issuing halt after reset.<br>
  152. target state: halted<br>
  153. target halted in ARM state due to debug request, current mode: Supervisor<br>
  154. cpsr: 0x300000d3 pc: 0x000003c0
  155. </code>
  156. </td>
  157. <td>PASS</td>
  158. </tr>
  159. <tr>
  160. <td><a name="RES005"/>RES005</td>
  161. <td>SAM7S64</td>
  162. <td>ZY1000</td>
  163. <td>Reset halt on a blank target using return clock</td>
  164. <td>Erase all the content of the flash, set the configuration script to use RCLK</td>
  165. <td>Connect via the telnet interface and type <br><code>reset halt</code></td>
  166. <td>Reset should return without error and the output should contain<br><code>target state: halted</code></td>
  167. <td>
  168. <code>
  169. > jtag_khz 0<br>
  170. jtag_khz: 0<br>
  171. > reset init<br>
  172. SRST took 2ms to deassert<br>
  173. JTAG device found: 0x3f0f0f0f (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)<br>
  174. srst pulls trst - can not reset into halted mode. Issuing halt after reset.<br>
  175. target state: halted<br>
  176. target halted in ARM state due to debug request, current mode: Supervisor<br>
  177. cpsr: 0x300000d3 pc: 0x000003c0<br>
  178. executing event/sam7s256_reset.script<br>
  179. >
  180. </code>
  181. </td>
  182. <td>PASS</td>
  183. </tr>
  184. </table>
  185. <H2>JTAG Speed</H2>
  186. <table border=1>
  187. <tr>
  188. <td>ID</td>
  189. <td>Target</td>
  190. <td>ZY1000</td>
  191. <td>Description</td>
  192. <td>Initial state</td>
  193. <td>Input</td>
  194. <td>Expected output</td>
  195. <td>Actual output</td>
  196. <td>Pass/Fail</td>
  197. </tr>
  198. <tr>
  199. <td><a name="SPD001"/>SPD001</td>
  200. <td>SAM7S64</td>
  201. <td>ZY1000</td>
  202. <td>16MHz on normal operation</td>
  203. <td>Reset init the target according to RES002 </td>
  204. <td>Change speed and exercise a memory access over the JTAG, for example <br><code>mdw 0x0 32</code></td>
  205. <td>The command should run without any errors. If any JTAG checking errors happen, the test failed</td>
  206. <td>
  207. <code>
  208. > jtag_khz 16000<br>
  209. jtag_speed 4 => JTAG clk=16.000000<br>
  210. jtag_khz: 16000<br>
  211. > mdw 0 32<br>
  212. 0x00000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
  213. 0x00000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
  214. 0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
  215. 0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
  216. >
  217. </code>
  218. </td>
  219. <td>PASS</td>
  220. </tr>
  221. <tr>
  222. <td><a name="SPD002"/>SPD002</td>
  223. <td>SAM7S64</td>
  224. <td>ZY1000</td>
  225. <td>8MHz on normal operation</td>
  226. <td>Reset init the target according to RES002 </td>
  227. <td>Change speed and exercise a memory access over the JTAG, for example <br><code>mdw 0x0 32</code></td>
  228. <td>The command should run without any errors. If any JTAG checking errors happen, the test failed</td>
  229. <td>
  230. <code>
  231. > jtag_khz 8000<br>
  232. jtag_speed 8 => JTAG clk=8.000000<br>
  233. jtag_khz: 8000<br>
  234. > mdw 0 32<br>
  235. 0x00000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
  236. 0x00000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
  237. 0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
  238. 0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
  239. </code>
  240. </td>
  241. <td>PASS</td>
  242. </tr>
  243. <tr>
  244. <td><a name="SPD003"/>SPD003</td>
  245. <td>SAM7S64</td>
  246. <td>ZY1000</td>
  247. <td>4MHz on normal operation</td>
  248. <td>Reset init the target according to RES002 </td>
  249. <td>Change speed and exercise a memory access over the JTAG, for example <br><code>mdw 0x0 32</code></td>
  250. <td>The command should run without any errors. If any JTAG checking errors happen, the test failed</td>
  251. <td>
  252. <code>
  253. > jtag_khz 4000<br>
  254. jtag_speed 16 => JTAG clk=4.000000<br>
  255. jtag_khz: 4000<br>
  256. > mdw 0 32<br>
  257. 0x00000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
  258. 0x00000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
  259. 0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
  260. 0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
  261. >
  262. </code>
  263. </td>
  264. <td>PASS</td>
  265. </tr>
  266. <tr>
  267. <td><a name="SPD004"/>SPD004</td>
  268. <td>SAM7S64</td>
  269. <td>ZY1000</td>
  270. <td>2MHz on normal operation</td>
  271. <td>Reset init the target according to RES002 </td>
  272. <td>Change speed and exercise a memory access over the JTAG, for example <br><code>mdw 0x0 32</code></td>
  273. <td>The command should run without any errors. If any JTAG checking errors happen, the test failed</td>
  274. <td>
  275. <code>
  276. > jtag_khz 2000<br>
  277. jtag_speed 32 => JTAG clk=2.000000<br>
  278. jtag_khz: 2000<br>
  279. > mdw 0 32<br>
  280. 0x00000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
  281. 0x00000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
  282. 0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
  283. 0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
  284. >
  285. </code>
  286. </td>
  287. <td>PASS</td>
  288. </tr>
  289. <tr>
  290. <td><a name="SPD005"/>SPD005</td>
  291. <td>SAM7S64</td>
  292. <td>ZY1000</td>
  293. <td>RCLK on normal operation</td>
  294. <td>Reset init the target according to RES002 </td>
  295. <td>Change speed and exercise a memory access over the JTAG, for example <br><code>mdw 0x0 32</code></td>
  296. <td>The command should run without any errors. If any JTAG checking errors happen, the test failed</td>
  297. <td>
  298. <code>
  299. > jtag_khz 0<br>
  300. jtag_khz: 0<br>
  301. > mdw 0 32<br>
  302. 0x00000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
  303. 0x00000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
  304. 0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
  305. 0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
  306. >
  307. </code>
  308. </td>
  309. <td>PASS</td>
  310. </tr>
  311. </table>
  312. <H2>Debugging</H2>
  313. <table border=1>
  314. <tr>
  315. <td>ID</td>
  316. <td>Target</td>
  317. <td>Interface</td>
  318. <td>Description</td>
  319. <td>Initial state</td>
  320. <td>Input</td>
  321. <td>Expected output</td>
  322. <td>Actual output</td>
  323. <td>Pass/Fail</td>
  324. </tr>
  325. <tr>
  326. <td><a name="DBG001"/>DBG001</td>
  327. <td>SAM7S64</td>
  328. <td>ZY1000</td>
  329. <td>Load is working</td>
  330. <td>Reset init is working, RAM is accesible, GDB server is started</td>
  331. <td>On the console of the OS: <br>
  332. <code>arm-elf-gdb test_ram.elf</code><br>
  333. <code>(gdb) target remote ip:port</code><br>
  334. <code>(gdb) load</load>
  335. </td>
  336. <td>Load should return without error, typical output looks like:<br>
  337. <code>
  338. Loading section .text, size 0x14c lma 0x0<br>
  339. Start address 0x40, load size 332<br>
  340. Transfer rate: 180 bytes/sec, 332 bytes/write.<br>
  341. </code>
  342. </td>
  343. <td><code>
  344. (gdb) load<br>
  345. Loading section .text, size 0x194 lma 0x200000<br>
  346. Start address 0x200040, load size 404<br>
  347. Transfer rate: 443 bytes/sec, 404 bytes/write.<br>
  348. (gdb)
  349. </code></td>
  350. <td>PASS</td>
  351. </tr>
  352. <tr>
  353. <td><a name="DBG002"/>DBG002</td>
  354. <td>SAM7S64</td>
  355. <td>ZY1000</td>
  356. <td>Software breakpoint</td>
  357. <td>Load the test_ram.elf application, use instructions from GDB001</td>
  358. <td>In the GDB console:<br>
  359. <code>
  360. (gdb) monitor arm7_9 dbgrq enable<br>
  361. software breakpoints enabled<br>
  362. (gdb) break main<br>
  363. Breakpoint 1 at 0xec: file src/main.c, line 71.<br>
  364. (gdb) continue<br>
  365. Continuing.
  366. </code>
  367. </td>
  368. <td>The software breakpoint should be reached, a typical output looks like:<br>
  369. <code>
  370. Breakpoint 1, main () at src/main.c:69<br>
  371. 69 DWORD a = 1;<br>
  372. </code>
  373. </td>
  374. <td>
  375. <code>
  376. (gdb) monitor arm7_9 dbgrq enable<br>
  377. use of EmbeddedICE dbgrq instead of breakpoint for target halt enabled<br>
  378. (gdb) break main<br>
  379. Breakpoint 1 at 0x200134: file src/main.c, line 69.<br>
  380. (gdb) c<br>
  381. Continuing.<br>
  382. <br>
  383. Breakpoint 1, main () at src/main.c:69<br>
  384. 69 DWORD a = 1;<br>
  385. Current language: auto<br>
  386. The current source language is "auto; currently c".<br>
  387. (gdb)
  388. </code>
  389. </td>
  390. <td>PASS</td>
  391. </tr>
  392. <tr>
  393. <td><a name="DBG003"/>DBG003</td>
  394. <td>SAM7S64</td>
  395. <td>ZY1000</td>
  396. <td>Single step in a RAM application</td>
  397. <td>Load the test_ram.elf application, use instructions from GDB001, break in main using the instructions from GDB002</td>
  398. <td>In GDB, type <br><code>(gdb) step</code></td>
  399. <td>The next instruction should be reached, typical output:<br>
  400. <code>
  401. (gdb) step<br>
  402. 70 DWORD b = 2;
  403. </code>
  404. </td>
  405. <td>
  406. <code>
  407. (gdb) step<br>
  408. 70 DWORD b = 2;
  409. (gdb)
  410. </code>
  411. </td>
  412. <td>PASS</td>
  413. </tr>
  414. <tr>
  415. <td><a name="DBG004"/>DBG004</td>
  416. <td>SAM7S64</td>
  417. <td>ZY1000</td>
  418. <td>Software break points are working after a reset</td>
  419. <td>Load the test_ram.elf application, use instructions from GDB001, break in main using the instructions from GDB002</td>
  420. <td>In GDB, type <br><code>
  421. (gdb) monitor reset init<br>
  422. (gdb) load<br>
  423. (gdb) continue<br>
  424. </code></td>
  425. <td>The breakpoint should be reached, typical output:<br>
  426. <code>
  427. Breakpoint 1, main () at src/main.c:69<br>
  428. 69 DWORD a = 1;
  429. </code>
  430. </td>
  431. <td><code>
  432. (gdb) monitor reset init<br>
  433. JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f (mfg: 0x787, part: 0xf0f0, ver: 0x3)<br>
  434. srst pulls trst - can not reset into halted mode. Issuing halt after reset.<br>
  435. target state: halted<br>
  436. target halted in ARM state due to debug-request, current mode: Supervisor<br>
  437. cpsr: 0x600000d3 pc: 0x0000031c<br>
  438. (gdb) load<br>
  439. Loading section .text, size 0x194 lma 0x200000<br>
  440. Start address 0x200040, load size 404<br>
  441. Transfer rate: 26 KB/sec, 404 bytes/write.<br>
  442. (gdb) continue<br>
  443. Continuing.<br>
  444. <br>
  445. Breakpoint 1, main () at src/main.c:69<br>
  446. 69 DWORD a = 1;<br>
  447. (gdb)
  448. </code></td>
  449. <td>PASS</td>
  450. </tr>
  451. <tr>
  452. <td><a name="DBG005"/>DBG005</td>
  453. <td>SAM7S64</td>
  454. <td>ZY1000</td>
  455. <td>Hardware breakpoint</td>
  456. <td>Flash the test_rom.elf application. Make this test after FLA004 has passed</td>
  457. <td>Be sure that <code>gdb_memory_map</code> and <code>gdb_flash_program</code> are enabled. In GDB, type <br>
  458. <code>
  459. (gdb) monitor reset init<br>
  460. (gdb) load<br>
  461. Loading section .text, size 0x194 lma 0x100000<br>
  462. Start address 0x100040, load size 404<br>
  463. Transfer rate: 179 bytes/sec, 404 bytes/write.<br>
  464. (gdb) monitor arm7_9 force_hw_bkpts enable<br>
  465. force hardware breakpoints enabled<br>
  466. (gdb) break main<br>
  467. Breakpoint 1 at 0x100134: file src/main.c, line 69.<br>
  468. (gdb) continue<br>
  469. </code>
  470. </td>
  471. <td>The breakpoint should be reached, typical output:<br>
  472. <code>
  473. Continuing.<br>
  474. <br>
  475. Breakpoint 1, main () at src/main.c:69<br>
  476. 69 DWORD a = 1;<br>
  477. </code>
  478. </td>
  479. <td>
  480. <code>
  481. (gdb) monitor arm7_9 force_hw_bkpts enable<br>
  482. force hardware breakpoints enabled<br>
  483. (gdb) break main<br>
  484. Breakpoint 1 at 0x100134: file src/main.c, line 69.<br>
  485. (gdb) continue<br>
  486. Continuing.<br>
  487. Note: automatically using hardware breakpoints for read-only addresses.<br>
  488. target state: halted<br>
  489. target halted in ARM state due to breakpoint, current mode: Supervisor<br>
  490. cpsr: 0x60000013 pc: 0x00100134<br>
  491. <br>
  492. Breakpoint 1, main () at src/main.c:69<br>
  493. 69 DWORD a = 1;<br>
  494. (gdb)
  495. </code>
  496. </td>
  497. <td>PASS</td>
  498. </tr>
  499. <tr>
  500. <td><a name="DBG006"/>DBG006</td>
  501. <td>SAM7S64</td>
  502. <td>ZY1000</td>
  503. <td>Hardware breakpoint is set after a reset</td>
  504. <td>Follow the instructions to flash and insert a hardware breakpoint from DBG005</td>
  505. <td>In GDB, type <br>
  506. <code>
  507. (gdb) monitor reset<br>
  508. (gdb) monitor reg pc 0x100000<br>
  509. pc (/32): 0x00100000<br>
  510. (gdb) continue
  511. </code><br>
  512. where the value inserted in PC is the start address of the application
  513. </td>
  514. <td>The breakpoint should be reached, typical output:<br>
  515. <code>
  516. Continuing.<br>
  517. <br>
  518. Breakpoint 1, main () at src/main.c:69<br>
  519. 69 DWORD a = 1;<br>
  520. </code>
  521. </td>
  522. <td>
  523. <code>
  524. (gdb) monitor reset init<br>
  525. SRST took 3ms to deassert<br>
  526. JTAG device found: 0x3f0f0f0f (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)<br>
  527. srst pulls trst - can not reset into halted mode. Issuing halt after reset.<br>
  528. target state: halted<br>
  529. target halted in ARM state due to debug request, current mode: Supervisor<br>
  530. cpsr: 0x60000013 pc: 0x00100168<br>
  531. executing event/sam7s256_reset.script<br>
  532. (gdb) monitor reg pc 0x100000<br>
  533. pc (/32): 0x00100000<br>
  534. (gdb) continue<br>
  535. Continuing.<br>
  536. target state: halted<br>
  537. target halted in ARM state due to single step, current mode: Supervisor<br>
  538. cpsr: 0x60000013 pc: 0x00100040<br>
  539. target state: halted<br>
  540. target halted in ARM state due to breakpoint, current mode: Supervisor<br>
  541. cpsr: 0x60000013 pc: 0x00100134<br>
  542. <br>
  543. Breakpoint 1, main () at src/main.c:69<br>
  544. 69 DWORD a = 1;<br>
  545. (gdb)
  546. </code>
  547. </td>
  548. <td>PASS</td>
  549. </tr>
  550. <tr>
  551. <td><a name="DBG007"/>DBG007</td>
  552. <td>SAM7S64</td>
  553. <td>ZY1000</td>
  554. <td>Single step in ROM</td>
  555. <td>Flash the test_rom.elf application and set a breakpoint in main, use DBG005. Make this test after FLA004 has passed</td>
  556. <td>Be sure that <code>gdb_memory_map</code> and <code>gdb_flash_program</code> are enabled. In GDB, type <br>
  557. <code>
  558. (gdb) monitor reset<br>
  559. (gdb) load<br>
  560. Loading section .text, size 0x194 lma 0x100000<br>
  561. Start address 0x100040, load size 404<br>
  562. Transfer rate: 179 bytes/sec, 404 bytes/write.<br>
  563. (gdb) monitor arm7_9 force_hw_bkpts enable<br>
  564. force hardware breakpoints enabled<br>
  565. (gdb) break main<br>
  566. Breakpoint 1 at 0x100134: file src/main.c, line 69.<br>
  567. (gdb) continue<br>
  568. Continuing.<br>
  569. <br>
  570. Breakpoint 1, main () at src/main.c:69<br>
  571. 69 DWORD a = 1;<br>
  572. (gdb) step
  573. </code>
  574. </td>
  575. <td>The breakpoint should be reached, typical output:<br>
  576. <code>
  577. target state: halted<br>
  578. target halted in ARM state due to single step, current mode: Supervisor<br>
  579. cpsr: 0x60000013 pc: 0x0010013c<br>
  580. 70 DWORD b = 2;<br>
  581. </code>
  582. </td>
  583. <td><code>
  584. Breakpoint 1, main () at src/main.c:69<br>
  585. 69 DWORD a = 1;<br>
  586. (gdb) step<br>
  587. target state: halted<br>
  588. target halted in ARM state due to single step, current mode: Supervisor<br>
  589. cpsr: 0x60000013 pc: 0x00100138<br>
  590. target state: halted<br>
  591. target halted in ARM state due to single step, current mode: Supervisor<br>
  592. cpsr: 0x60000013 pc: 0x0010013c<br>
  593. 70 DWORD b = 2;<br>
  594. (gdb)
  595. </code></td>
  596. <td>PASS</td>
  597. </tr>
  598. </table>
  599. <H2>RAM access</H2>
  600. Note: these tests are not designed to test/debug the target, but to test functionalities!
  601. <table border=1>
  602. <tr>
  603. <td>ID</td>
  604. <td>Target</td>
  605. <td>Interface</td>
  606. <td>Description</td>
  607. <td>Initial state</td>
  608. <td>Input</td>
  609. <td>Expected output</td>
  610. <td>Actual output</td>
  611. <td>Pass/Fail</td>
  612. </tr>
  613. <tr>
  614. <td><a name="RAM001"/>RAM001</td>
  615. <td>SAM7S64</td>
  616. <td>ZY1000</td>
  617. <td>32 bit Write/read RAM</td>
  618. <td>Reset init is working</td>
  619. <td>On the telnet interface<br>
  620. <code> > mww ram_address 0xdeadbeef 16<br>
  621. > mdw ram_address 32
  622. </code>
  623. </td>
  624. <td>The commands should execute without error. A clear failure is a memory access exception. The result of running the commands should be a list of 16 locations 32bit long containing 0xdeadbeef.<br>
  625. <code>
  626. > mww 0x0 0xdeadbeef 16<br>
  627. > mdw 0x0 32<br>
  628. 0x00000000: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
  629. 0x00000020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
  630. 0x00000040: e1a00000 e59fa51c e59f051c e04aa000 00080017 00009388 00009388 00009388<br>
  631. 0x00000060: 00009388 0002c2c0 0002c2c0 000094f8 000094f4 00009388 00009388 00009388<br>
  632. </code>
  633. </td>
  634. <td><code>
  635. > mww 0x00200000 0xdeadbeef 16<br>
  636. > mdw 0x00200000 32<br>
  637. 0x00200000: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
  638. 0x00200020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
  639. 0x00200040: e59f10b4 e3a00902 e5810004 e59f00ac e59f10ac e5810000 e3e010ff e59f00a4<br>
  640. 0x00200060: e5810060 e59f10a0 e3e00000 e5810130 e5810124 e321f0db e59fd090 e321f0d7
  641. </code></td>
  642. <td>PASS</td>
  643. </tr>
  644. <tr>
  645. <td><a name="RAM002"/>RAM002</td>
  646. <td>SAM7S64</td>
  647. <td>ZY1000</td>
  648. <td>16 bit Write/read RAM</td>
  649. <td>Reset init is working</td>
  650. <td>On the telnet interface<br>
  651. <code> > mwh ram_address 0xbeef 16<br>
  652. > mdh ram_address 32
  653. </code>
  654. </td>
  655. <td>The commands should execute without error. A clear failure is a memory access exception. The result of running the commands should be a list of 16 locations 16bit long containing 0xbeef.<br>
  656. <code>
  657. > mwh 0x0 0xbeef 16<br>
  658. > mdh 0x0 32<br>
  659. 0x00000000: beef beef beef beef beef beef beef beef beef beef beef beef beef beef beef beef<br>
  660. 0x00000020: 00e0 0000 021c 0000 0240 0000 026c 0000 0288 0000 0000 0000 0388 0000 0350 0000<br>
  661. >
  662. </code>
  663. </td>
  664. <td><code>
  665. > mwh 0x00200000 0xbeef 16<br>
  666. > mdh 0x00200000 32<br>
  667. 0x00200000: beef beef beef beef beef beef beef beef beef beef beef beef beef beef beef beef<br>
  668. 0x00200020: 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
  669. </code></td>
  670. <td>PASS</td>
  671. </tr>
  672. <tr>
  673. <td><a name="RAM003"/>RAM003</td>
  674. <td>SAM7S64</td>
  675. <td>ZY1000</td>
  676. <td>8 bit Write/read RAM</td>
  677. <td>Reset init is working</td>
  678. <td>On the telnet interface<br>
  679. <code> > mwb ram_address 0xab 16<br>
  680. > mdb ram_address 32
  681. </code>
  682. </td>
  683. <td>The commands should execute without error. A clear failure is a memory access exception. The result of running the commands should be a list of 16 locations 8bit long containing 0xab.<br>
  684. <code>
  685. > mwb ram_address 0xab 16<br>
  686. > mdb ram_address 32<br>
  687. 0x00000000: ab ab ab ab ab ab ab ab ab ab ab ab ab ab ab ab 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>
  688. >
  689. </code>
  690. </td>
  691. <td><code>
  692. > mwb 0x00200000 0xab 16<br>
  693. > mdb 0x00200000 32<br>
  694. 0x00200000: ab ab ab ab ab ab ab ab ab ab ab ab ab ab ab ab 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
  695. </code></td>
  696. <td>PASS</td>
  697. </tr>
  698. </table>
  699. <H2>Flash access</H2>
  700. <table border=1>
  701. <tr>
  702. <td>ID</td>
  703. <td>Target</td>
  704. <td>Interface</td>
  705. <td>Description</td>
  706. <td>Initial state</td>
  707. <td>Input</td>
  708. <td>Expected output</td>
  709. <td>Actual output</td>
  710. <td>Pass/Fail</td>
  711. </tr>
  712. <tr>
  713. <td><a name="FLA001"/>FLA001</td>
  714. <td>SAM7S64</td>
  715. <td>ZY1000</td>
  716. <td>Flash probe</td>
  717. <td>Reset init is working</td>
  718. <td>On the telnet interface:<br>
  719. <code> > flash probe 0</code>
  720. </td>
  721. <td>The command should execute without error. The output should state the name of the flash and the starting address. An example of output:<br>
  722. <code>flash 'ecosflash' found at 0x01000000</code>
  723. </td>
  724. <td>
  725. <code>
  726. > flash probe 0<br>
  727. flash 'at91sam7' found at 0x00100000
  728. </code>
  729. </td>
  730. <td>PASS</td>
  731. </tr>
  732. <tr>
  733. <td><a name="FLA002"/>FLA002</td>
  734. <td>SAM7S64</td>
  735. <td>ZY1000</td>
  736. <td>flash fillw</td>
  737. <td>Reset init is working, flash is probed</td>
  738. <td>On the telnet interface<br>
  739. <code> > flash fillw 0x100000 0xdeadbeef 16
  740. </code>
  741. </td>
  742. <td>The commands should execute without error. The output looks like:<br>
  743. <code>
  744. wrote 64 bytes to 0x0100000 in 11.610000s (0.091516 kb/s)
  745. </code><br>
  746. To verify the contents of the flash:<br>
  747. <code>
  748. > mdw 0x100000 32<br>
  749. 0x0100000: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
  750. 0x0100020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
  751. 0x0100040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
  752. 0x0100060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
  753. </code>
  754. </td>
  755. <td><code>
  756. > flash fillw 0x100000 0xdeadbeef 16<br>
  757. wrote 64 bytes to 0x00100000 in 0.040000s (26.562500 kb/s)<br>
  758. > mdw 0x100000 32<br>
  759. 0x00100000: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
  760. 0x00100020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
  761. 0x00100040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
  762. 0x00100060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
  763. >
  764. </code></td>
  765. <td>PASS</td>
  766. </tr>
  767. <tr>
  768. <td><a name="FLA003"/>FLA003</td>
  769. <td>SAM7S64</td>
  770. <td>ZY1000</td>
  771. <td>Flash erase</td>
  772. <td>Reset init is working, flash is probed</td>
  773. <td>On the telnet interface<br>
  774. <code> > flash erase_address 0x100000 0x2000
  775. </code>
  776. </td>
  777. <td>The commands should execute without error.<br>
  778. <code>
  779. erased address 0x0100000 length 8192 in 4.970000s
  780. </code>
  781. To check that the flash has been erased, read at different addresses. The result should always be 0xff.
  782. <code>
  783. > mdw 0x100000 32<br>
  784. 0x0100000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
  785. 0x0100020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
  786. 0x0100040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
  787. 0x0100060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
  788. </code>
  789. </td>
  790. <td><code>
  791. > flash erase_address 0x100000 0x2000<br>
  792. erased address 0x00100000 length 8192 in 0.020000s<br>
  793. > mdw 0x100000 32<br>
  794. 0x00100000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
  795. 0x00100020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
  796. 0x00100040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
  797. 0x00100060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
  798. >
  799. </code></td>
  800. <td>PASS</td>
  801. </tr>
  802. <tr>
  803. <td><a name="FLA004"/>FLA004</td>
  804. <td>SAM7S64</td>
  805. <td>ZY1000</td>
  806. <td>Loading to flash from GDB</td>
  807. <td>Reset init is working, flash is probed, connectivity to GDB server is working</td>
  808. <td>Start GDB using a ROM elf image, eg: arm-elf-gdb test_rom.elf. <br>
  809. <code>
  810. (gdb) target remote ip:port<br>
  811. (gdb) monitor reset halt<br>
  812. (gdb) load<br>
  813. Loading section .text, size 0x194 lma 0x100000<br>
  814. Start address 0x100040, load size 404<br>
  815. Transfer rate: 179 bytes/sec, 404 bytes/write.<br>
  816. (gdb) monitor verify_image path_to_elf_file
  817. </code>
  818. </td>
  819. <td>The output should look like:<br>
  820. <code>
  821. verified 404 bytes in 5.060000s
  822. </code><br>
  823. The failure message is something like:<br>
  824. <code>Verify operation failed address 0x00200000. Was 0x00 instead of 0x18</code>
  825. </td>
  826. <td>
  827. <code>
  828. (gdb) load<br>
  829. Loading section .text, size 0x194 lma 0x100000<br>
  830. Start address 0x100040, load size 404<br>
  831. Transfer rate: 4 KB/sec, 404 bytes/write.<br>
  832. (gdb) moni verify_image /tftp/10.0.0.9/c:/temp/testing/examples/SAM7S256Test/test_rom.elf<br>
  833. verified 404 bytes in 0.570000s
  834. </code>
  835. </td>
  836. <td>PASS</td>
  837. </tr>
  838. </table>
  839. </body>
  840. </html>