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  1. #
  2. # stm32l1 devices support both JTAG and SWD transports.
  3. #
  4. source [find target/swj-dp.tcl]
  5. if { [info exists CHIPNAME] } {
  6. set _CHIPNAME $CHIPNAME
  7. } else {
  8. set _CHIPNAME stm32l
  9. }
  10. if { [info exists ENDIAN] } {
  11. set _ENDIAN $ENDIAN
  12. } else {
  13. set _ENDIAN little
  14. }
  15. # Work-area is a space in RAM used for flash programming
  16. # By default use 10kB
  17. if { [info exists WORKAREASIZE] } {
  18. set _WORKAREASIZE $WORKAREASIZE
  19. } else {
  20. set _WORKAREASIZE 0x2800
  21. }
  22. # JTAG speed should be <= F_CPU/6.
  23. # F_CPU after reset is 2MHz, so use F_JTAG max = 333kHz
  24. adapter_khz 300
  25. adapter_nsrst_delay 100
  26. if {[using_jtag]} {
  27. jtag_ntrst_delay 100
  28. }
  29. #jtag scan chain
  30. if { [info exists CPUTAPID] } {
  31. set _CPUTAPID $CPUTAPID
  32. } else {
  33. if { [using_jtag] } {
  34. # See STM Document RM0038
  35. # Section 30.6.3 - corresponds to Cortex-M3 r2p0
  36. set _CPUTAPID 0x4ba00477
  37. } else {
  38. # SWD IDCODE (single drop, arm)
  39. set _CPUTAPID 0x2ba01477
  40. }
  41. }
  42. swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
  43. if { [info exists BSTAPID] } {
  44. # FIXME this never gets used to override defaults...
  45. set _BSTAPID $BSTAPID
  46. } else {
  47. # See STM Document RM0038 Section 30.6.1
  48. # (section 30.6.2 seems incorrect, at least in RM0038 DocID 15965 Rev 10)
  49. # Low and medium density
  50. set _BSTAPID1 0x06416041
  51. # Cat.3 device (medium+ density)
  52. set _BSTAPID2 0x06427041
  53. # Cat.4 device, STM32L15/6xxD or Cat.3 device, some STM32L15/6xxC-A models
  54. set _BSTAPID3 0x06436041
  55. # Cat.5 device (high density), STM32L15/6xxE
  56. set _BSTAPID4 0x06437041
  57. }
  58. if {[using_jtag]} {
  59. swj_newdap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 -expected-id $_BSTAPID2 -expected-id $_BSTAPID3 -expected-id $_BSTAPID4
  60. }
  61. set _TARGETNAME $_CHIPNAME.cpu
  62. target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
  63. $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
  64. # flash size will be probed
  65. set _FLASHNAME $_CHIPNAME.flash
  66. flash bank $_FLASHNAME stm32lx 0x08000000 0 0 0 $_TARGETNAME
  67. if {![using_hla]} {
  68. # if srst is not fitted use SYSRESETREQ to
  69. # perform a soft reset
  70. cortex_m reset_config sysresetreq
  71. }
  72. proc stm32l_enable_HSI {} {
  73. # Enable HSI as clock source
  74. echo "STM32L: Enabling HSI"
  75. # Set HSION in RCC_CR
  76. mww 0x40023800 0x00000101
  77. # Set HSI as SYSCLK
  78. mww 0x40023808 0x00000001
  79. # Increase JTAG speed
  80. adapter_khz 2000
  81. }
  82. $_TARGETNAME configure -event reset-init {
  83. stm32l_enable_HSI
  84. }
  85. $_TARGETNAME configure -event reset-start {
  86. adapter_khz 300
  87. }