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  1. #
  2. # Texas Instruments DaVinci family: TMS320DM355
  3. #
  4. if { [info exists CHIPNAME] } {
  5. set _CHIPNAME $CHIPNAME
  6. } else {
  7. set _CHIPNAME dm355
  8. }
  9. # TI boards default to EMU0/EMU1 *high* -- ARM and ETB are *disabled*
  10. # after JTAG reset until ICEpick is used to route them in.
  11. #set EMU01 "-disable"
  12. # With EMU0/EMU1 jumpered *low* ARM and ETB are *enabled* without
  13. # needing any ICEpick interaction.
  14. set EMU01 "-enable"
  15. source [find target/icepick.cfg]
  16. #
  17. # Also note: when running without RTCK before the PLLs are set up, you
  18. # may need to slow the JTAG clock down quite a lot (under 2 MHz).
  19. #
  20. # Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer
  21. if { [info exists ETB_TAPID ] } {
  22. set _ETB_TAPID $ETB_TAPID
  23. } else {
  24. set _ETB_TAPID 0x2b900f0f
  25. }
  26. jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETB_TAPID $EMU01
  27. jtag configure $_CHIPNAME.etb -event tap-enable \
  28. "icepick_c_tapenable $_CHIPNAME.jrc 1"
  29. # Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM.
  30. if { [info exists CPU_TAPID ] } {
  31. set _CPU_TAPID $CPU_TAPID
  32. } else {
  33. set _CPU_TAPID 0x07926001
  34. }
  35. jtag newtap $_CHIPNAME arm -irlen 4 -irmask 0xf -expected-id $_CPU_TAPID $EMU01
  36. jtag configure $_CHIPNAME.arm -event tap-enable \
  37. "icepick_c_tapenable $_CHIPNAME.jrc 0"
  38. # Primary TAP: ICEpick (JTAG route controller) and boundary scan
  39. if { [info exists JRC_TAPID ] } {
  40. set _JRC_TAPID $JRC_TAPID
  41. } else {
  42. set _JRC_TAPID 0x0b73b02f
  43. }
  44. jtag newtap $_CHIPNAME jrc -irlen 6 -irmask 0x3f -expected-id $_JRC_TAPID
  45. ################
  46. # various symbol definitions, to avoid hard-wiring addresses
  47. # and enable some sharing of DaVinci-family utility code
  48. global dm355
  49. set dm355 [ dict create ]
  50. # Physical addresses for controllers and memory
  51. # (Some of these are valid for many DaVinci family chips)
  52. dict set dm355 sram0 0x00010000
  53. dict set dm355 sram1 0x00014000
  54. dict set dm355 sysbase 0x01c40000
  55. dict set dm355 pllc1 0x01c40800
  56. dict set dm355 pllc2 0x01c40c00
  57. dict set dm355 psc 0x01c41000
  58. dict set dm355 gpio 0x01c67000
  59. dict set dm355 a_emif 0x01e10000
  60. dict set dm355 a_emif_cs0 0x02000000
  61. dict set dm355 a_emif_cs1 0x04000000
  62. dict set dm355 ddr_emif 0x20000000
  63. dict set dm355 ddr 0x80000000
  64. dict set dm355 uart0 0x01c20000
  65. dict set dm355 uart1 0x01c20400
  66. dict set dm355 uart2 0x01e06000
  67. source [find target/davinci.cfg]
  68. ################
  69. # GDB target: the ARM, using SRAM1 for scratch. SRAM0 (also 16K)
  70. # and the ETB memory (4K) are other options, while trace is unused.
  71. set _TARGETNAME $_CHIPNAME.arm
  72. target create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME
  73. # NOTE that work-area-virt presumes a Linux 2.6.30-rc2+ kernel,
  74. # and that the work area is used only with a kernel mmu context ...
  75. $_TARGETNAME configure \
  76. -work-area-virt [expr 0xfffe0000 + 0x4000] \
  77. -work-area-phys [dict get $dm355 sram1] \
  78. -work-area-size 0x4000 \
  79. -work-area-backup 0
  80. # be absolutely certain the JTAG clock will work with the worst-case
  81. # CLKIN = 24 MHz (best case: 36 MHz) even when no bootloader turns
  82. # on the PLL and starts using it. OK to speed up after clock setup.
  83. jtag_rclk 1500
  84. $_TARGETNAME configure -event "reset-start" { jtag_rclk 1500 }
  85. arm7_9 fast_memory_access enable
  86. arm7_9 dcc_downloads enable
  87. # trace setup
  88. etm config $_TARGETNAME 16 normal full etb
  89. etb config $_TARGETNAME $_CHIPNAME.etb