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  1. #
  2. # Texas Instruments DaVinci family: TMS320DM365
  3. #
  4. if { [info exists CHIPNAME] } {
  5. set _CHIPNAME $CHIPNAME
  6. } else {
  7. set _CHIPNAME dm365
  8. }
  9. #
  10. # For now, expect EMU0/EMU1 jumpered LOW (not TI's default) so ARM and ETB
  11. # are enabled without making ICEpick route ARM and ETB into the JTAG chain.
  12. #
  13. # Also note: when running without RTCK before the PLLs are set up, you
  14. # may need to slow the JTAG clock down quite a lot (under 2 MHz).
  15. #
  16. source [find target/icepick.cfg]
  17. set EMU01 "-enable"
  18. #set EMU01 "-disable"
  19. # Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer
  20. if { [info exists ETB_TAPID ] } {
  21. set _ETB_TAPID $ETB_TAPID
  22. } else {
  23. set _ETB_TAPID 0x2b900f0f
  24. }
  25. jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETB_TAPID $EMU01
  26. jtag configure $_CHIPNAME.etb -event tap-enable \
  27. "icepick_c_tapenable $_CHIPNAME.jrc 1"
  28. # Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM.
  29. if { [info exists CPU_TAPID ] } {
  30. set _CPU_TAPID $CPU_TAPID
  31. } else {
  32. set _CPU_TAPID 0x0792602f
  33. }
  34. jtag newtap $_CHIPNAME arm -irlen 4 -irmask 0xf -expected-id $_CPU_TAPID $EMU01
  35. jtag configure $_CHIPNAME.arm -event tap-enable \
  36. "icepick_c_tapenable $_CHIPNAME.jrc 0"
  37. # Primary TAP: ICEpick (JTAG route controller) and boundary scan
  38. if { [info exists JRC_TAPID ] } {
  39. set _JRC_TAPID $JRC_TAPID
  40. } else {
  41. set _JRC_TAPID 0x0b83e02f
  42. }
  43. jtag newtap $_CHIPNAME jrc -irlen 6 -irmask 0x3f -expected-id $_JRC_TAPID
  44. ################
  45. # various symbol definitions, to avoid hard-wiring addresses
  46. # and enable some sharing of DaVinci-family utility code
  47. global dm365
  48. set dm365 [ dict create ]
  49. # Physical addresses for controllers and memory
  50. # (Some of these are valid for many DaVinci family chips)
  51. dict set dm365 sram0 0x00010000
  52. dict set dm365 sram1 0x00014000
  53. dict set dm365 sysbase 0x01c40000
  54. dict set dm365 pllc1 0x01c40800
  55. dict set dm365 pllc2 0x01c40c00
  56. dict set dm365 psc 0x01c41000
  57. dict set dm365 gpio 0x01c67000
  58. dict set dm365 a_emif 0x01d10000
  59. dict set dm365 a_emif_cs0 0x02000000
  60. dict set dm365 a_emif_cs1 0x04000000
  61. dict set dm365 ddr_emif 0x20000000
  62. dict set dm365 ddr 0x80000000
  63. source [find target/davinci.cfg]
  64. ################
  65. # GDB target: the ARM, using SRAM1 for scratch. SRAM0 (also 16K)
  66. # and the ETB memory (4K) are other options, while trace is unused.
  67. set _TARGETNAME $_CHIPNAME.arm
  68. target create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME
  69. # NOTE that work-area-virt presumes a Linux 2.6.30-rc2+ kernel,
  70. # and that the work area is used only with a kernel mmu context ...
  71. $_TARGETNAME configure \
  72. -work-area-virt [expr 0xfffe0000 + 0x4000] \
  73. -work-area-phys [dict get $dm365 sram1] \
  74. -work-area-size 0x4000 \
  75. -work-area-backup 0
  76. # be absolutely certain the JTAG clock will work with the worst-case
  77. # CLKIN = 19.2 MHz (best case: 36 MHz) even when no bootloader turns
  78. # on the PLL and starts using it. OK to speed up after clock setup.
  79. jtag_rclk 1500
  80. $_TARGETNAME configure -event "reset-start" { jtag_rclk 1500 }
  81. arm7_9 fast_memory_access enable
  82. arm7_9 dcc_downloads enable
  83. # trace setup
  84. etm config $_TARGETNAME 16 normal full etb
  85. etb config $_TARGETNAME $_CHIPNAME.etb