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2959 lines
86 KiB

  1. /***************************************************************************
  2. * Copyright (C) 2005, 2007 by Dominic Rath *
  3. * Dominic.Rath@gmx.de *
  4. * Copyright (C) 2009 Michael Schwingen *
  5. * michael@schwingen.org *
  6. * Copyright (C) 2010 √ėyvind Harboe <oyvind.harboe@zylin.com> *
  7. * Copyright (C) 2010 by Antonio Borneo <borneo.antonio@gmail.com> *
  8. * *
  9. * This program is free software; you can redistribute it and/or modify *
  10. * it under the terms of the GNU General Public License as published by *
  11. * the Free Software Foundation; either version 2 of the License, or *
  12. * (at your option) any later version. *
  13. * *
  14. * This program is distributed in the hope that it will be useful, *
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  17. * GNU General Public License for more details. *
  18. * *
  19. * You should have received a copy of the GNU General Public License *
  20. * along with this program; if not, write to the *
  21. * Free Software Foundation, Inc., *
  22. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
  23. ***************************************************************************/
  24. #ifdef HAVE_CONFIG_H
  25. #include "config.h"
  26. #endif
  27. #include "imp.h"
  28. #include "cfi.h"
  29. #include "non_cfi.h"
  30. #include <target/arm.h>
  31. #include <helper/binarybuffer.h>
  32. #include <target/algorithm.h>
  33. #define CFI_MAX_BUS_WIDTH 4
  34. #define CFI_MAX_CHIP_WIDTH 4
  35. /* defines internal maximum size for code fragment in cfi_intel_write_block() */
  36. #define CFI_MAX_INTEL_CODESIZE 256
  37. static struct cfi_unlock_addresses cfi_unlock_addresses[] =
  38. {
  39. [CFI_UNLOCK_555_2AA] = { .unlock1 = 0x555, .unlock2 = 0x2aa },
  40. [CFI_UNLOCK_5555_2AAA] = { .unlock1 = 0x5555, .unlock2 = 0x2aaa },
  41. };
  42. /* CFI fixups foward declarations */
  43. static void cfi_fixup_0002_erase_regions(struct flash_bank *bank, void *param);
  44. static void cfi_fixup_0002_unlock_addresses(struct flash_bank *bank, void *param);
  45. static void cfi_fixup_reversed_erase_regions(struct flash_bank *bank, void *param);
  46. static void cfi_fixup_0002_write_buffer(struct flash_bank *bank, void *param);
  47. /* fixup after reading cmdset 0002 primary query table */
  48. static const struct cfi_fixup cfi_0002_fixups[] = {
  49. {CFI_MFR_SST, 0x00D4, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  50. {CFI_MFR_SST, 0x00D5, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  51. {CFI_MFR_SST, 0x00D6, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  52. {CFI_MFR_SST, 0x00D7, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  53. {CFI_MFR_SST, 0x2780, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  54. {CFI_MFR_SST, 0x236d, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
  55. {CFI_MFR_ATMEL, 0x00C8, cfi_fixup_reversed_erase_regions, NULL},
  56. {CFI_MFR_ST, 0x22C4, cfi_fixup_reversed_erase_regions, NULL}, /* M29W160ET */
  57. {CFI_MFR_FUJITSU, 0x22ea, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
  58. {CFI_MFR_FUJITSU, 0x226b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  59. {CFI_MFR_AMIC, 0xb31a, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
  60. {CFI_MFR_MX, 0x225b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
  61. {CFI_MFR_AMD, 0x225b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
  62. {CFI_MFR_ANY, CFI_ID_ANY, cfi_fixup_0002_erase_regions, NULL},
  63. {CFI_MFR_ST, 0x227E, cfi_fixup_0002_write_buffer, NULL}, /* M29W128G */
  64. {0, 0, NULL, NULL}
  65. };
  66. /* fixup after reading cmdset 0001 primary query table */
  67. static const struct cfi_fixup cfi_0001_fixups[] = {
  68. {0, 0, NULL, NULL}
  69. };
  70. static void cfi_fixup(struct flash_bank *bank, const struct cfi_fixup *fixups)
  71. {
  72. struct cfi_flash_bank *cfi_info = bank->driver_priv;
  73. const struct cfi_fixup *f;
  74. for (f = fixups; f->fixup; f++)
  75. {
  76. if (((f->mfr == CFI_MFR_ANY) || (f->mfr == cfi_info->manufacturer)) &&
  77. ((f->id == CFI_ID_ANY) || (f->id == cfi_info->device_id)))
  78. {
  79. f->fixup(bank, f->param);
  80. }
  81. }
  82. }
  83. /* inline uint32_t flash_address(struct flash_bank *bank, int sector, uint32_t offset) */
  84. static __inline__ uint32_t flash_address(struct flash_bank *bank, int sector, uint32_t offset)
  85. {
  86. struct cfi_flash_bank *cfi_info = bank->driver_priv;
  87. if (cfi_info->x16_as_x8) offset *= 2;
  88. /* while the sector list isn't built, only accesses to sector 0 work */
  89. if (sector == 0)
  90. return bank->base + offset * bank->bus_width;
  91. else
  92. {
  93. if (!bank->sectors)
  94. {
  95. LOG_ERROR("BUG: sector list not yet built");
  96. exit(-1);
  97. }
  98. return bank->base + bank->sectors[sector].offset + offset * bank->bus_width;
  99. }
  100. }
  101. static void cfi_command(struct flash_bank *bank, uint8_t cmd, uint8_t *cmd_buf)
  102. {
  103. int i;
  104. /* clear whole buffer, to ensure bits that exceed the bus_width
  105. * are set to zero
  106. */
  107. for (i = 0; i < CFI_MAX_BUS_WIDTH; i++)
  108. cmd_buf[i] = 0;
  109. if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
  110. {
  111. for (i = bank->bus_width; i > 0; i--)
  112. {
  113. *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
  114. }
  115. }
  116. else
  117. {
  118. for (i = 1; i <= bank->bus_width; i++)
  119. {
  120. *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
  121. }
  122. }
  123. }
  124. static int cfi_send_command(struct flash_bank *bank, uint8_t cmd, uint32_t address)
  125. {
  126. uint8_t command[CFI_MAX_BUS_WIDTH];
  127. cfi_command(bank, cmd, command);
  128. return target_write_memory(bank->target, address, bank->bus_width, 1, command);
  129. }
  130. /* read unsigned 8-bit value from the bank
  131. * flash banks are expected to be made of similar chips
  132. * the query result should be the same for all
  133. */
  134. static int cfi_query_u8(struct flash_bank *bank, int sector, uint32_t offset, uint8_t *val)
  135. {
  136. struct target *target = bank->target;
  137. uint8_t data[CFI_MAX_BUS_WIDTH];
  138. int retval;
  139. retval = target_read_memory(target, flash_address(bank, sector, offset),
  140. bank->bus_width, 1, data);
  141. if (retval != ERROR_OK)
  142. return retval;
  143. if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
  144. *val = data[0];
  145. else
  146. *val = data[bank->bus_width - 1];
  147. return ERROR_OK;
  148. }
  149. /* read unsigned 8-bit value from the bank
  150. * in case of a bank made of multiple chips,
  151. * the individual values are ORed
  152. */
  153. static int cfi_get_u8(struct flash_bank *bank, int sector, uint32_t offset, uint8_t *val)
  154. {
  155. struct target *target = bank->target;
  156. uint8_t data[CFI_MAX_BUS_WIDTH];
  157. int i;
  158. int retval;
  159. retval = target_read_memory(target, flash_address(bank, sector, offset),
  160. bank->bus_width, 1, data);
  161. if (retval != ERROR_OK)
  162. return retval;
  163. if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
  164. {
  165. for (i = 0; i < bank->bus_width / bank->chip_width; i++)
  166. data[0] |= data[i];
  167. *val = data[0];
  168. }
  169. else
  170. {
  171. uint8_t value = 0;
  172. for (i = 0; i < bank->bus_width / bank->chip_width; i++)
  173. value |= data[bank->bus_width - 1 - i];
  174. *val = value;
  175. }
  176. return ERROR_OK;
  177. }
  178. static int cfi_query_u16(struct flash_bank *bank, int sector, uint32_t offset, uint16_t *val)
  179. {
  180. struct target *target = bank->target;
  181. struct cfi_flash_bank *cfi_info = bank->driver_priv;
  182. uint8_t data[CFI_MAX_BUS_WIDTH * 2];
  183. int retval;
  184. if (cfi_info->x16_as_x8)
  185. {
  186. uint8_t i;
  187. for (i = 0;i < 2;i++)
  188. {
  189. retval = target_read_memory(target, flash_address(bank, sector, offset + i),
  190. bank->bus_width, 1, &data[i * bank->bus_width]);
  191. if (retval != ERROR_OK)
  192. return retval;
  193. }
  194. } else
  195. {
  196. retval = target_read_memory(target, flash_address(bank, sector, offset),
  197. bank->bus_width, 2, data);
  198. if (retval != ERROR_OK)
  199. return retval;
  200. }
  201. if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
  202. *val = data[0] | data[bank->bus_width] << 8;
  203. else
  204. *val = data[bank->bus_width - 1] | data[(2 * bank->bus_width) - 1] << 8;
  205. return ERROR_OK;
  206. }
  207. static int cfi_query_u32(struct flash_bank *bank, int sector, uint32_t offset, uint32_t *val)
  208. {
  209. struct target *target = bank->target;
  210. struct cfi_flash_bank *cfi_info = bank->driver_priv;
  211. uint8_t data[CFI_MAX_BUS_WIDTH * 4];
  212. int retval;
  213. if (cfi_info->x16_as_x8)
  214. {
  215. uint8_t i;
  216. for (i = 0;i < 4;i++)
  217. {
  218. retval = target_read_memory(target, flash_address(bank, sector, offset + i),
  219. bank->bus_width, 1, &data[i * bank->bus_width]);
  220. if (retval != ERROR_OK)
  221. return retval;
  222. }
  223. }
  224. else
  225. {
  226. retval = target_read_memory(target, flash_address(bank, sector, offset),
  227. bank->bus_width, 4, data);
  228. if (retval != ERROR_OK)
  229. return retval;
  230. }
  231. if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
  232. *val = data[0] | data[bank->bus_width] << 8 |
  233. data[bank->bus_width * 2] << 16 | data[bank->bus_width * 3] << 24;
  234. else
  235. *val = data[bank->bus_width - 1] | data[(2* bank->bus_width) - 1] << 8 |
  236. data[(3 * bank->bus_width) - 1] << 16 | data[(4 * bank->bus_width) - 1] << 24;
  237. return ERROR_OK;
  238. }
  239. static int cfi_reset(struct flash_bank *bank)
  240. {
  241. struct cfi_flash_bank *cfi_info = bank->driver_priv;
  242. int retval = ERROR_OK;
  243. if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
  244. {
  245. return retval;
  246. }
  247. if ((retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0))) != ERROR_OK)
  248. {
  249. return retval;
  250. }
  251. if (cfi_info->manufacturer == 0x20 &&
  252. (cfi_info->device_id == 0x227E || cfi_info->device_id == 0x7E))
  253. {
  254. /* Numonix M29W128G is cmd 0xFF intolerant - causes internal undefined state
  255. * so we send an extra 0xF0 reset to fix the bug */
  256. if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x00))) != ERROR_OK)
  257. {
  258. return retval;
  259. }
  260. }
  261. return retval;
  262. }
  263. static void cfi_intel_clear_status_register(struct flash_bank *bank)
  264. {
  265. struct target *target = bank->target;
  266. if (target->state != TARGET_HALTED)
  267. {
  268. LOG_ERROR("BUG: attempted to clear status register while target wasn't halted");
  269. exit(-1);
  270. }
  271. cfi_send_command(bank, 0x50, flash_address(bank, 0, 0x0));
  272. }
  273. static int cfi_intel_wait_status_busy(struct flash_bank *bank, int timeout, uint8_t *val)
  274. {
  275. uint8_t status;
  276. int retval = ERROR_OK;
  277. for (;;)
  278. {
  279. if (timeout-- < 0)
  280. {
  281. LOG_ERROR("timeout while waiting for WSM to become ready");
  282. return ERROR_FAIL;
  283. }
  284. retval = cfi_get_u8(bank, 0, 0x0, &status);
  285. if (retval != ERROR_OK)
  286. return retval;
  287. if (status & 0x80)
  288. break;
  289. alive_sleep(1);
  290. }
  291. /* mask out bit 0 (reserved) */
  292. status = status & 0xfe;
  293. LOG_DEBUG("status: 0x%x", status);
  294. if (status != 0x80)
  295. {
  296. LOG_ERROR("status register: 0x%x", status);
  297. if (status & 0x2)
  298. LOG_ERROR("Block Lock-Bit Detected, Operation Abort");
  299. if (status & 0x4)
  300. LOG_ERROR("Program suspended");
  301. if (status & 0x8)
  302. LOG_ERROR("Low Programming Voltage Detected, Operation Aborted");
  303. if (status & 0x10)
  304. LOG_ERROR("Program Error / Error in Setting Lock-Bit");
  305. if (status & 0x20)
  306. LOG_ERROR("Error in Block Erasure or Clear Lock-Bits");
  307. if (status & 0x40)
  308. LOG_ERROR("Block Erase Suspended");
  309. cfi_intel_clear_status_register(bank);
  310. retval = ERROR_FAIL;
  311. }
  312. *val = status;
  313. return retval;
  314. }
  315. static int cfi_spansion_wait_status_busy(struct flash_bank *bank, int timeout)
  316. {
  317. uint8_t status, oldstatus;
  318. struct cfi_flash_bank *cfi_info = bank->driver_priv;
  319. int retval;
  320. retval = cfi_get_u8(bank, 0, 0x0, &oldstatus);
  321. if (retval != ERROR_OK)
  322. return retval;
  323. do {
  324. retval = cfi_get_u8(bank, 0, 0x0, &status);
  325. if (retval != ERROR_OK)
  326. return retval;
  327. if ((status ^ oldstatus) & 0x40) {
  328. if (status & cfi_info->status_poll_mask & 0x20) {
  329. retval = cfi_get_u8(bank, 0, 0x0, &oldstatus);
  330. if (retval != ERROR_OK)
  331. return retval;
  332. retval = cfi_get_u8(bank, 0, 0x0, &status);
  333. if (retval != ERROR_OK)
  334. return retval;
  335. if ((status ^ oldstatus) & 0x40) {
  336. LOG_ERROR("dq5 timeout, status: 0x%x", status);
  337. return(ERROR_FLASH_OPERATION_FAILED);
  338. } else {
  339. LOG_DEBUG("status: 0x%x", status);
  340. return(ERROR_OK);
  341. }
  342. }
  343. } else { /* no toggle: finished, OK */
  344. LOG_DEBUG("status: 0x%x", status);
  345. return(ERROR_OK);
  346. }
  347. oldstatus = status;
  348. alive_sleep(1);
  349. } while (timeout-- > 0);
  350. LOG_ERROR("timeout, status: 0x%x", status);
  351. return(ERROR_FLASH_BUSY);
  352. }
  353. static int cfi_read_intel_pri_ext(struct flash_bank *bank)
  354. {
  355. int retval;
  356. struct cfi_flash_bank *cfi_info = bank->driver_priv;
  357. struct cfi_intel_pri_ext *pri_ext;
  358. if (cfi_info->pri_ext)
  359. free(cfi_info->pri_ext);
  360. pri_ext = malloc(sizeof(struct cfi_intel_pri_ext));
  361. if (pri_ext == NULL)
  362. {
  363. LOG_ERROR("Out of memory");
  364. return ERROR_FAIL;
  365. }
  366. cfi_info->pri_ext = pri_ext;
  367. retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0, &pri_ext->pri[0]);
  368. if (retval != ERROR_OK)
  369. return retval;
  370. retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1, &pri_ext->pri[1]);
  371. if (retval != ERROR_OK)
  372. return retval;
  373. retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2, &pri_ext->pri[2]);
  374. if (retval != ERROR_OK)
  375. return retval;
  376. if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
  377. {
  378. if ((retval = cfi_reset(bank)) != ERROR_OK)
  379. {
  380. return retval;
  381. }
  382. LOG_ERROR("Could not read bank flash bank information");
  383. return ERROR_FLASH_BANK_INVALID;
  384. }
  385. retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3, &pri_ext->major_version);
  386. if (retval != ERROR_OK)
  387. return retval;
  388. retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4, &pri_ext->minor_version);
  389. if (retval != ERROR_OK)
  390. return retval;
  391. LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1],
  392. pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
  393. retval = cfi_query_u32(bank, 0, cfi_info->pri_addr + 5, &pri_ext->feature_support);
  394. if (retval != ERROR_OK)
  395. return retval;
  396. retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9, &pri_ext->suspend_cmd_support);
  397. if (retval != ERROR_OK)
  398. return retval;
  399. retval = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xa, &pri_ext->blk_status_reg_mask);
  400. if (retval != ERROR_OK)
  401. return retval;
  402. LOG_DEBUG("feature_support: 0x%" PRIx32 ", suspend_cmd_support: "
  403. "0x%x, blk_status_reg_mask: 0x%x",
  404. pri_ext->feature_support,
  405. pri_ext->suspend_cmd_support,
  406. pri_ext->blk_status_reg_mask);
  407. retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xc, &pri_ext->vcc_optimal);
  408. if (retval != ERROR_OK)
  409. return retval;
  410. retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xd, &pri_ext->vpp_optimal);
  411. if (retval != ERROR_OK)
  412. return retval;
  413. LOG_DEBUG("Vcc opt: %x.%x, Vpp opt: %u.%x",
  414. (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
  415. (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
  416. retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xe, &pri_ext->num_protection_fields);
  417. if (retval != ERROR_OK)
  418. return retval;
  419. if (pri_ext->num_protection_fields != 1)
  420. {
  421. LOG_WARNING("expected one protection register field, but found %i",
  422. pri_ext->num_protection_fields);
  423. }
  424. retval = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xf, &pri_ext->prot_reg_addr);
  425. if (retval != ERROR_OK)
  426. return retval;
  427. retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x11, &pri_ext->fact_prot_reg_size);
  428. if (retval != ERROR_OK)
  429. return retval;
  430. retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x12, &pri_ext->user_prot_reg_size);
  431. if (retval != ERROR_OK)
  432. return retval;
  433. LOG_DEBUG("protection_fields: %i, prot_reg_addr: 0x%x, "
  434. "factory pre-programmed: %i, user programmable: %i",
  435. pri_ext->num_protection_fields, pri_ext->prot_reg_addr,
  436. 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
  437. return ERROR_OK;
  438. }
  439. static int cfi_read_spansion_pri_ext(struct flash_bank *bank)
  440. {
  441. int retval;
  442. struct cfi_flash_bank *cfi_info = bank->driver_priv;
  443. struct cfi_spansion_pri_ext *pri_ext;
  444. if (cfi_info->pri_ext)
  445. free(cfi_info->pri_ext);
  446. pri_ext = malloc(sizeof(struct cfi_spansion_pri_ext));
  447. if (pri_ext == NULL)
  448. {
  449. LOG_ERROR("Out of memory");
  450. return ERROR_FAIL;
  451. }
  452. cfi_info->pri_ext = pri_ext;
  453. retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0, &pri_ext->pri[0]);
  454. if (retval != ERROR_OK)
  455. return retval;
  456. retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1, &pri_ext->pri[1]);
  457. if (retval != ERROR_OK)
  458. return retval;
  459. retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2, &pri_ext->pri[2]);
  460. if (retval != ERROR_OK)
  461. return retval;
  462. if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
  463. {
  464. if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
  465. {
  466. return retval;
  467. }
  468. LOG_ERROR("Could not read spansion bank information");
  469. return ERROR_FLASH_BANK_INVALID;
  470. }
  471. retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3, &pri_ext->major_version);
  472. if (retval != ERROR_OK)
  473. return retval;
  474. retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4, &pri_ext->minor_version);
  475. if (retval != ERROR_OK)
  476. return retval;
  477. LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1],
  478. pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
  479. retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5, &pri_ext->SiliconRevision);
  480. if (retval != ERROR_OK)
  481. return retval;
  482. retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6, &pri_ext->EraseSuspend);
  483. if (retval != ERROR_OK)
  484. return retval;
  485. retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7, &pri_ext->BlkProt);
  486. if (retval != ERROR_OK)
  487. return retval;
  488. retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8, &pri_ext->TmpBlkUnprotect);
  489. if (retval != ERROR_OK)
  490. return retval;
  491. retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9, &pri_ext->BlkProtUnprot);
  492. if (retval != ERROR_OK)
  493. return retval;
  494. retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 10, &pri_ext->SimultaneousOps);
  495. if (retval != ERROR_OK)
  496. return retval;
  497. retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 11, &pri_ext->BurstMode);
  498. if (retval != ERROR_OK)
  499. return retval;
  500. retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 12, &pri_ext->PageMode);
  501. if (retval != ERROR_OK)
  502. return retval;
  503. retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 13, &pri_ext->VppMin);
  504. if (retval != ERROR_OK)
  505. return retval;
  506. retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 14, &pri_ext->VppMax);
  507. if (retval != ERROR_OK)
  508. return retval;
  509. retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 15, &pri_ext->TopBottom);
  510. if (retval != ERROR_OK)
  511. return retval;
  512. LOG_DEBUG("Silicon Revision: 0x%x, Erase Suspend: 0x%x, Block protect: 0x%x",
  513. pri_ext->SiliconRevision, pri_ext->EraseSuspend, pri_ext->BlkProt);
  514. LOG_DEBUG("Temporary Unprotect: 0x%x, Block Protect Scheme: 0x%x, "
  515. "Simultaneous Ops: 0x%x", pri_ext->TmpBlkUnprotect,
  516. pri_ext->BlkProtUnprot, pri_ext->SimultaneousOps);
  517. LOG_DEBUG("Burst Mode: 0x%x, Page Mode: 0x%x, ", pri_ext->BurstMode, pri_ext->PageMode);
  518. LOG_DEBUG("Vpp min: %u.%x, Vpp max: %u.%x",
  519. (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
  520. (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
  521. LOG_DEBUG("WP# protection 0x%x", pri_ext->TopBottom);
  522. /* default values for implementation specific workarounds */
  523. pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
  524. pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
  525. pri_ext->_reversed_geometry = 0;
  526. return ERROR_OK;
  527. }
  528. static int cfi_read_atmel_pri_ext(struct flash_bank *bank)
  529. {
  530. int retval;
  531. struct cfi_atmel_pri_ext atmel_pri_ext;
  532. struct cfi_flash_bank *cfi_info = bank->driver_priv;
  533. struct cfi_spansion_pri_ext *pri_ext;
  534. if (cfi_info->pri_ext)
  535. free(cfi_info->pri_ext);
  536. pri_ext = malloc(sizeof(struct cfi_spansion_pri_ext));
  537. if (pri_ext == NULL)
  538. {
  539. LOG_ERROR("Out of memory");
  540. return ERROR_FAIL;
  541. }
  542. /* ATMEL devices use the same CFI primary command set (0x2) as AMD/Spansion,
  543. * but a different primary extended query table.
  544. * We read the atmel table, and prepare a valid AMD/Spansion query table.
  545. */
  546. memset(pri_ext, 0, sizeof(struct cfi_spansion_pri_ext));
  547. cfi_info->pri_ext = pri_ext;
  548. retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0, &atmel_pri_ext.pri[0]);
  549. if (retval != ERROR_OK)
  550. return retval;
  551. retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1, &atmel_pri_ext.pri[1]);
  552. if (retval != ERROR_OK)
  553. return retval;
  554. retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2, &atmel_pri_ext.pri[2]);
  555. if (retval != ERROR_OK)
  556. return retval;
  557. if ((atmel_pri_ext.pri[0] != 'P') || (atmel_pri_ext.pri[1] != 'R')
  558. || (atmel_pri_ext.pri[2] != 'I'))
  559. {
  560. if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
  561. {
  562. return retval;
  563. }
  564. LOG_ERROR("Could not read atmel bank information");
  565. return ERROR_FLASH_BANK_INVALID;
  566. }
  567. pri_ext->pri[0] = atmel_pri_ext.pri[0];
  568. pri_ext->pri[1] = atmel_pri_ext.pri[1];
  569. pri_ext->pri[2] = atmel_pri_ext.pri[2];
  570. retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3, &atmel_pri_ext.major_version);
  571. if (retval != ERROR_OK)
  572. return retval;
  573. retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4, &atmel_pri_ext.minor_version);
  574. if (retval != ERROR_OK)
  575. return retval;
  576. LOG_DEBUG("pri: '%c%c%c', version: %c.%c", atmel_pri_ext.pri[0],
  577. atmel_pri_ext.pri[1], atmel_pri_ext.pri[2],
  578. atmel_pri_ext.major_version, atmel_pri_ext.minor_version);
  579. pri_ext->major_version = atmel_pri_ext.major_version;
  580. pri_ext->minor_version = atmel_pri_ext.minor_version;
  581. retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5, &atmel_pri_ext.features);
  582. if (retval != ERROR_OK)
  583. return retval;
  584. retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6, &atmel_pri_ext.bottom_boot);
  585. if (retval != ERROR_OK)
  586. return retval;
  587. retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7, &atmel_pri_ext.burst_mode);
  588. if (retval != ERROR_OK)
  589. return retval;
  590. retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8, &atmel_pri_ext.page_mode);
  591. if (retval != ERROR_OK)
  592. return retval;
  593. LOG_DEBUG("features: 0x%2.2x, bottom_boot: 0x%2.2x, burst_mode: 0x%2.2x, page_mode: 0x%2.2x",
  594. atmel_pri_ext.features, atmel_pri_ext.bottom_boot,
  595. atmel_pri_ext.burst_mode, atmel_pri_ext.page_mode);
  596. if (atmel_pri_ext.features & 0x02)
  597. pri_ext->EraseSuspend = 2;
  598. if (atmel_pri_ext.bottom_boot)
  599. pri_ext->TopBottom = 2;
  600. else
  601. pri_ext->TopBottom = 3;
  602. pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
  603. pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
  604. return ERROR_OK;
  605. }
  606. static int cfi_read_0002_pri_ext(struct flash_bank *bank)
  607. {
  608. struct cfi_flash_bank *cfi_info = bank->driver_priv;
  609. if (cfi_info->manufacturer == CFI_MFR_ATMEL)
  610. {
  611. return cfi_read_atmel_pri_ext(bank);
  612. }
  613. else
  614. {
  615. return cfi_read_spansion_pri_ext(bank);
  616. }
  617. }
  618. static int cfi_spansion_info(struct flash_bank *bank, char *buf, int buf_size)
  619. {
  620. int printed;
  621. struct cfi_flash_bank *cfi_info = bank->driver_priv;
  622. struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
  623. printed = snprintf(buf, buf_size, "\nSpansion primary algorithm extend information:\n");
  624. buf += printed;
  625. buf_size -= printed;
  626. printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0],
  627. pri_ext->pri[1], pri_ext->pri[2],
  628. pri_ext->major_version, pri_ext->minor_version);
  629. buf += printed;
  630. buf_size -= printed;
  631. printed = snprintf(buf, buf_size, "Silicon Rev.: 0x%x, Address Sensitive unlock: 0x%x\n",
  632. (pri_ext->SiliconRevision) >> 2,
  633. (pri_ext->SiliconRevision) & 0x03);
  634. buf += printed;
  635. buf_size -= printed;
  636. printed = snprintf(buf, buf_size, "Erase Suspend: 0x%x, Sector Protect: 0x%x\n",
  637. pri_ext->EraseSuspend,
  638. pri_ext->BlkProt);
  639. buf += printed;
  640. buf_size -= printed;
  641. printed = snprintf(buf, buf_size, "VppMin: %u.%x, VppMax: %u.%x\n",
  642. (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
  643. (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
  644. return ERROR_OK;
  645. }
  646. static int cfi_intel_info(struct flash_bank *bank, char *buf, int buf_size)
  647. {
  648. int printed;
  649. struct cfi_flash_bank *cfi_info = bank->driver_priv;
  650. struct cfi_intel_pri_ext *pri_ext = cfi_info->pri_ext;
  651. printed = snprintf(buf, buf_size, "\nintel primary algorithm extend information:\n");
  652. buf += printed;
  653. buf_size -= printed;
  654. printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0],
  655. pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
  656. buf += printed;
  657. buf_size -= printed;
  658. printed = snprintf(buf, buf_size, "feature_support: 0x%" PRIx32 ", "
  659. "suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x\n",
  660. pri_ext->feature_support, pri_ext->suspend_cmd_support, pri_ext->blk_status_reg_mask);
  661. buf += printed;
  662. buf_size -= printed;
  663. printed = snprintf(buf, buf_size, "Vcc opt: %x.%x, Vpp opt: %u.%x\n",
  664. (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
  665. (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
  666. buf += printed;
  667. buf_size -= printed;
  668. printed = snprintf(buf, buf_size, "protection_fields: %i, prot_reg_addr: 0x%x, "
  669. "factory pre-programmed: %i, user programmable: %i\n",
  670. pri_ext->num_protection_fields, pri_ext->prot_reg_addr,
  671. 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
  672. return ERROR_OK;
  673. }
  674. /* flash_bank cfi <base> <size> <chip_width> <bus_width> <target#> [options]
  675. */
  676. FLASH_BANK_COMMAND_HANDLER(cfi_flash_bank_command)
  677. {
  678. struct cfi_flash_bank *cfi_info;
  679. if (CMD_ARGC < 6)
  680. {
  681. LOG_WARNING("incomplete flash_bank cfi configuration");
  682. return ERROR_FLASH_BANK_INVALID;
  683. }
  684. /* both widths must:
  685. * - not exceed max value;
  686. * - not be null;
  687. * - be equal to a power of 2.
  688. * bus must be wide enought to hold one chip */
  689. if ((bank->chip_width > CFI_MAX_CHIP_WIDTH)
  690. || (bank->bus_width > CFI_MAX_BUS_WIDTH)
  691. || (bank->chip_width == 0)
  692. || (bank->bus_width == 0)
  693. || (bank->chip_width & (bank->chip_width - 1))
  694. || (bank->bus_width & (bank->bus_width - 1))
  695. || (bank->chip_width > bank->bus_width))
  696. {
  697. LOG_ERROR("chip and bus width have to specified in bytes");
  698. return ERROR_FLASH_BANK_INVALID;
  699. }
  700. cfi_info = malloc(sizeof(struct cfi_flash_bank));
  701. cfi_info->probed = 0;
  702. cfi_info->erase_region_info = NULL;
  703. cfi_info->pri_ext = NULL;
  704. bank->driver_priv = cfi_info;
  705. cfi_info->write_algorithm = NULL;
  706. cfi_info->x16_as_x8 = 0;
  707. cfi_info->jedec_probe = 0;
  708. cfi_info->not_cfi = 0;
  709. for (unsigned i = 6; i < CMD_ARGC; i++)
  710. {
  711. if (strcmp(CMD_ARGV[i], "x16_as_x8") == 0)
  712. {
  713. cfi_info->x16_as_x8 = 1;
  714. }
  715. else if (strcmp(CMD_ARGV[i], "jedec_probe") == 0)
  716. {
  717. cfi_info->jedec_probe = 1;
  718. }
  719. }
  720. cfi_info->write_algorithm = NULL;
  721. /* bank wasn't probed yet */
  722. cfi_info->qry[0] = 0xff;
  723. return ERROR_OK;
  724. }
  725. static int cfi_intel_erase(struct flash_bank *bank, int first, int last)
  726. {
  727. int retval;
  728. struct cfi_flash_bank *cfi_info = bank->driver_priv;
  729. int i;
  730. cfi_intel_clear_status_register(bank);
  731. for (i = first; i <= last; i++)
  732. {
  733. if ((retval = cfi_send_command(bank, 0x20, flash_address(bank, i, 0x0))) != ERROR_OK)
  734. {
  735. return retval;
  736. }
  737. if ((retval = cfi_send_command(bank, 0xd0, flash_address(bank, i, 0x0))) != ERROR_OK)
  738. {
  739. return retval;
  740. }
  741. uint8_t status;
  742. retval = cfi_intel_wait_status_busy(bank, cfi_info->block_erase_timeout, &status);
  743. if (retval != ERROR_OK)
  744. return retval;
  745. if (status == 0x80)
  746. bank->sectors[i].is_erased = 1;
  747. else
  748. {
  749. if ((retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0))) != ERROR_OK)
  750. {
  751. return retval;
  752. }
  753. LOG_ERROR("couldn't erase block %i of flash bank at base 0x%" PRIx32 , i, bank->base);
  754. return ERROR_FLASH_OPERATION_FAILED;
  755. }
  756. }
  757. return cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0));
  758. }
  759. static int cfi_spansion_erase(struct flash_bank *bank, int first, int last)
  760. {
  761. int retval;
  762. struct cfi_flash_bank *cfi_info = bank->driver_priv;
  763. struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
  764. int i;
  765. for (i = first; i <= last; i++)
  766. {
  767. if ((retval = cfi_send_command(bank, 0xaa,
  768. flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
  769. {
  770. return retval;
  771. }
  772. if ((retval = cfi_send_command(bank, 0x55,
  773. flash_address(bank, 0, pri_ext->_unlock2))) != ERROR_OK)
  774. {
  775. return retval;
  776. }
  777. if ((retval = cfi_send_command(bank, 0x80,
  778. flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
  779. {
  780. return retval;
  781. }
  782. if ((retval = cfi_send_command(bank, 0xaa,
  783. flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
  784. {
  785. return retval;
  786. }
  787. if ((retval = cfi_send_command(bank, 0x55,
  788. flash_address(bank, 0, pri_ext->_unlock2))) != ERROR_OK)
  789. {
  790. return retval;
  791. }
  792. if ((retval = cfi_send_command(bank, 0x30,
  793. flash_address(bank, i, 0x0))) != ERROR_OK)
  794. {
  795. return retval;
  796. }
  797. if (cfi_spansion_wait_status_busy(bank, cfi_info->block_erase_timeout) == ERROR_OK)
  798. {
  799. bank->sectors[i].is_erased = 1;
  800. }
  801. else
  802. {
  803. if ((retval = cfi_send_command(bank, 0xf0,
  804. flash_address(bank, 0, 0x0))) != ERROR_OK)
  805. {
  806. return retval;
  807. }
  808. LOG_ERROR("couldn't erase block %i of flash bank at base 0x%"
  809. PRIx32, i, bank->base);
  810. return ERROR_FLASH_OPERATION_FAILED;
  811. }
  812. }
  813. return cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0));
  814. }
  815. static int cfi_erase(struct flash_bank *bank, int first, int last)
  816. {
  817. struct cfi_flash_bank *cfi_info = bank->driver_priv;
  818. if (bank->target->state != TARGET_HALTED)
  819. {
  820. LOG_ERROR("Target not halted");
  821. return ERROR_TARGET_NOT_HALTED;
  822. }
  823. if ((first < 0) || (last < first) || (last >= bank->num_sectors))
  824. {
  825. return ERROR_FLASH_SECTOR_INVALID;
  826. }
  827. if (cfi_info->qry[0] != 'Q')
  828. return ERROR_FLASH_BANK_NOT_PROBED;
  829. switch (cfi_info->pri_id)
  830. {
  831. case 1:
  832. case 3:
  833. return cfi_intel_erase(bank, first, last);
  834. break;
  835. case 2:
  836. return cfi_spansion_erase(bank, first, last);
  837. break;
  838. default:
  839. LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
  840. break;
  841. }
  842. return ERROR_OK;
  843. }
  844. static int cfi_intel_protect(struct flash_bank *bank, int set, int first, int last)
  845. {
  846. int retval;
  847. struct cfi_flash_bank *cfi_info = bank->driver_priv;
  848. struct cfi_intel_pri_ext *pri_ext = cfi_info->pri_ext;
  849. int retry = 0;
  850. int i;
  851. /* if the device supports neither legacy lock/unlock (bit 3) nor
  852. * instant individual block locking (bit 5).
  853. */
  854. if (!(pri_ext->feature_support & 0x28))
  855. {
  856. LOG_ERROR("lock/unlock not supported on flash");
  857. return ERROR_FLASH_OPERATION_FAILED;
  858. }
  859. cfi_intel_clear_status_register(bank);
  860. for (i = first; i <= last; i++)
  861. {
  862. if ((retval = cfi_send_command(bank, 0x60, flash_address(bank, i, 0x0))) != ERROR_OK)
  863. {
  864. return retval;
  865. }
  866. if (set)
  867. {
  868. if ((retval = cfi_send_command(bank, 0x01, flash_address(bank, i, 0x0))) != ERROR_OK)
  869. {
  870. return retval;
  871. }
  872. bank->sectors[i].is_protected = 1;
  873. }
  874. else
  875. {
  876. if ((retval = cfi_send_command(bank, 0xd0, flash_address(bank, i, 0x0))) != ERROR_OK)
  877. {
  878. return retval;
  879. }
  880. bank->sectors[i].is_protected = 0;
  881. }
  882. /* instant individual block locking doesn't require reading of the status register */
  883. if (!(pri_ext->feature_support & 0x20))
  884. {
  885. /* Clear lock bits operation may take up to 1.4s */
  886. uint8_t status;
  887. retval = cfi_intel_wait_status_busy(bank, 1400, &status);
  888. if (retval != ERROR_OK)
  889. return retval;
  890. }
  891. else
  892. {
  893. uint8_t block_status;
  894. /* read block lock bit, to verify status */
  895. if ((retval = cfi_send_command(bank, 0x90, flash_address(bank, 0, 0x55))) != ERROR_OK)
  896. {
  897. return retval;
  898. }
  899. retval = cfi_get_u8(bank, i, 0x2, &block_status);
  900. if (retval != ERROR_OK)
  901. return retval;
  902. if ((block_status & 0x1) != set)
  903. {
  904. LOG_ERROR("couldn't change block lock status (set = %i, block_status = 0x%2.2x)",
  905. set, block_status);
  906. if ((retval = cfi_send_command(bank, 0x70,
  907. flash_address(bank, 0, 0x55))) != ERROR_OK)
  908. {
  909. return retval;
  910. }
  911. uint8_t status;
  912. retval = cfi_intel_wait_status_busy(bank, 10, &status);
  913. if (retval != ERROR_OK)
  914. return retval;
  915. if (retry > 10)
  916. return ERROR_FLASH_OPERATION_FAILED;
  917. else
  918. {
  919. i--;
  920. retry++;
  921. }
  922. }
  923. }
  924. }
  925. /* if the device doesn't support individual block lock bits set/clear,
  926. * all blocks have been unlocked in parallel, so we set those that should be protected
  927. */
  928. if ((!set) && (!(pri_ext->feature_support & 0x20)))
  929. {
  930. /* FIX!!! this code path is broken!!!
  931. *
  932. * The correct approach is:
  933. *
  934. * 1. read out current protection status
  935. *
  936. * 2. override read out protection status w/unprotected.
  937. *
  938. * 3. re-protect what should be protected.
  939. *
  940. */
  941. for (i = 0; i < bank->num_sectors; i++)
  942. {
  943. if (bank->sectors[i].is_protected == 1)
  944. {
  945. cfi_intel_clear_status_register(bank);
  946. if ((retval = cfi_send_command(bank, 0x60,
  947. flash_address(bank, i, 0x0))) != ERROR_OK)
  948. {
  949. return retval;
  950. }
  951. if ((retval = cfi_send_command(bank, 0x01,
  952. flash_address(bank, i, 0x0))) != ERROR_OK)
  953. {
  954. return retval;
  955. }
  956. uint8_t status;
  957. retval = cfi_intel_wait_status_busy(bank, 100, &status);
  958. if (retval != ERROR_OK)
  959. return retval;
  960. }
  961. }
  962. }
  963. return cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0));
  964. }
  965. static int cfi_protect(struct flash_bank *bank, int set, int first, int last)
  966. {
  967. struct cfi_flash_bank *cfi_info = bank->driver_priv;
  968. if (bank->target->state != TARGET_HALTED)
  969. {
  970. LOG_ERROR("Target not halted");
  971. return ERROR_TARGET_NOT_HALTED;
  972. }
  973. if ((first < 0) || (last < first) || (last >= bank->num_sectors))
  974. {
  975. LOG_ERROR("Invalid sector range");
  976. return ERROR_FLASH_SECTOR_INVALID;
  977. }
  978. if (cfi_info->qry[0] != 'Q')
  979. return ERROR_FLASH_BANK_NOT_PROBED;
  980. switch (cfi_info->pri_id)
  981. {
  982. case 1:
  983. case 3:
  984. return cfi_intel_protect(bank, set, first, last);
  985. break;
  986. default:
  987. LOG_ERROR("protect: cfi primary command set %i unsupported", cfi_info->pri_id);
  988. return ERROR_FAIL;
  989. }
  990. }
  991. /* Convert code image to target endian */
  992. /* FIXME create general block conversion fcts in target.c?) */
  993. static void cfi_fix_code_endian(struct target *target, uint8_t *dest,
  994. const uint32_t *src, uint32_t count)
  995. {
  996. uint32_t i;
  997. for (i = 0; i< count; i++)
  998. {
  999. target_buffer_set_u32(target, dest, *src);
  1000. dest += 4;
  1001. src++;
  1002. }
  1003. }
  1004. static uint32_t cfi_command_val(struct flash_bank *bank, uint8_t cmd)
  1005. {
  1006. struct target *target = bank->target;
  1007. uint8_t buf[CFI_MAX_BUS_WIDTH];
  1008. cfi_command(bank, cmd, buf);
  1009. switch (bank->bus_width)
  1010. {
  1011. case 1 :
  1012. return buf[0];
  1013. break;
  1014. case 2 :
  1015. return target_buffer_get_u16(target, buf);
  1016. break;
  1017. case 4 :
  1018. return target_buffer_get_u32(target, buf);
  1019. break;
  1020. default :
  1021. LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
  1022. return 0;
  1023. }
  1024. }
  1025. static int cfi_intel_write_block(struct flash_bank *bank, uint8_t *buffer,
  1026. uint32_t address, uint32_t count)
  1027. {
  1028. struct cfi_flash_bank *cfi_info = bank->driver_priv;
  1029. struct target *target = bank->target;
  1030. struct reg_param reg_params[7];
  1031. struct arm_algorithm armv4_5_info;
  1032. struct working_area *source;
  1033. uint32_t buffer_size = 32768;
  1034. uint32_t write_command_val, busy_pattern_val, error_pattern_val;
  1035. /* algorithm register usage:
  1036. * r0: source address (in RAM)
  1037. * r1: target address (in Flash)
  1038. * r2: count
  1039. * r3: flash write command
  1040. * r4: status byte (returned to host)
  1041. * r5: busy test pattern
  1042. * r6: error test pattern
  1043. */
  1044. /* see contib/loaders/flash/armv4_5_cfi_intel_32.s for src */
  1045. static const uint32_t word_32_code[] = {
  1046. 0xe4904004, /* loop: ldr r4, [r0], #4 */
  1047. 0xe5813000, /* str r3, [r1] */
  1048. 0xe5814000, /* str r4, [r1] */
  1049. 0xe5914000, /* busy: ldr r4, [r1] */
  1050. 0xe0047005, /* and r7, r4, r5 */
  1051. 0xe1570005, /* cmp r7, r5 */
  1052. 0x1afffffb, /* bne busy */
  1053. 0xe1140006, /* tst r4, r6 */
  1054. 0x1a000003, /* bne done */
  1055. 0xe2522001, /* subs r2, r2, #1 */
  1056. 0x0a000001, /* beq done */
  1057. 0xe2811004, /* add r1, r1 #4 */
  1058. 0xeafffff2, /* b loop */
  1059. 0xeafffffe /* done: b -2 */
  1060. };
  1061. /* see contib/loaders/flash/armv4_5_cfi_intel_16.s for src */
  1062. static const uint32_t word_16_code[] = {
  1063. 0xe0d040b2, /* loop: ldrh r4, [r0], #2 */
  1064. 0xe1c130b0, /* strh r3, [r1] */
  1065. 0xe1c140b0, /* strh r4, [r1] */
  1066. 0xe1d140b0, /* busy ldrh r4, [r1] */
  1067. 0xe0047005, /* and r7, r4, r5 */
  1068. 0xe1570005, /* cmp r7, r5 */
  1069. 0x1afffffb, /* bne busy */
  1070. 0xe1140006, /* tst r4, r6 */
  1071. 0x1a000003, /* bne done */
  1072. 0xe2522001, /* subs r2, r2, #1 */
  1073. 0x0a000001, /* beq done */
  1074. 0xe2811002, /* add r1, r1 #2 */
  1075. 0xeafffff2, /* b loop */
  1076. 0xeafffffe /* done: b -2 */
  1077. };
  1078. /* see contib/loaders/flash/armv4_5_cfi_intel_8.s for src */
  1079. static const uint32_t word_8_code[] = {
  1080. 0xe4d04001, /* loop: ldrb r4, [r0], #1 */
  1081. 0xe5c13000, /* strb r3, [r1] */
  1082. 0xe5c14000, /* strb r4, [r1] */
  1083. 0xe5d14000, /* busy ldrb r4, [r1] */
  1084. 0xe0047005, /* and r7, r4, r5 */
  1085. 0xe1570005, /* cmp r7, r5 */
  1086. 0x1afffffb, /* bne busy */
  1087. 0xe1140006, /* tst r4, r6 */
  1088. 0x1a000003, /* bne done */
  1089. 0xe2522001, /* subs r2, r2, #1 */
  1090. 0x0a000001, /* beq done */
  1091. 0xe2811001, /* add r1, r1 #1 */
  1092. 0xeafffff2, /* b loop */
  1093. 0xeafffffe /* done: b -2 */
  1094. };
  1095. uint8_t target_code[4*CFI_MAX_INTEL_CODESIZE];
  1096. const uint32_t *target_code_src;
  1097. uint32_t target_code_size;
  1098. int retval = ERROR_OK;
  1099. cfi_intel_clear_status_register(bank);
  1100. armv4_5_info.common_magic = ARM_COMMON_MAGIC;
  1101. armv4_5_info.core_mode = ARM_MODE_SVC;
  1102. armv4_5_info.core_state = ARM_STATE_ARM;
  1103. /* If we are setting up the write_algorith, we need target_code_src */
  1104. /* if not we only need target_code_size. */
  1105. /* However, we don't want to create multiple code paths, so we */
  1106. /* do the unecessary evaluation of target_code_src, which the */
  1107. /* compiler will probably nicely optimize away if not needed */
  1108. /* prepare algorithm code for target endian */
  1109. switch (bank->bus_width)
  1110. {
  1111. case 1 :
  1112. target_code_src = word_8_code;
  1113. target_code_size = sizeof(word_8_code);
  1114. break;
  1115. case 2 :
  1116. target_code_src = word_16_code;
  1117. target_code_size = sizeof(word_16_code);
  1118. break;
  1119. case 4 :
  1120. target_code_src = word_32_code;
  1121. target_code_size = sizeof(word_32_code);
  1122. break;
  1123. default:
  1124. LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
  1125. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  1126. }
  1127. /* flash write code */
  1128. if (!cfi_info->write_algorithm)
  1129. {
  1130. if (target_code_size > sizeof(target_code))
  1131. {
  1132. LOG_WARNING("Internal error - target code buffer to small. "
  1133. "Increase CFI_MAX_INTEL_CODESIZE and recompile.");
  1134. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  1135. }
  1136. cfi_fix_code_endian(target, target_code, target_code_src, target_code_size / 4);
  1137. /* Get memory for block write handler */
  1138. retval = target_alloc_working_area(target, target_code_size, &cfi_info->write_algorithm);
  1139. if (retval != ERROR_OK)
  1140. {
  1141. LOG_WARNING("No working area available, can't do block memory writes");
  1142. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  1143. };
  1144. /* write algorithm code to working area */
  1145. retval = target_write_buffer(target, cfi_info->write_algorithm->address,
  1146. target_code_size, target_code);
  1147. if (retval != ERROR_OK)
  1148. {
  1149. LOG_ERROR("Unable to write block write code to target");
  1150. goto cleanup;
  1151. }
  1152. }
  1153. /* Get a workspace buffer for the data to flash starting with 32k size.
  1154. Half size until buffer would be smaller 256 Bytem then fail back */
  1155. /* FIXME Why 256 bytes, why not 32 bytes (smallest flash write page */
  1156. while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK)
  1157. {
  1158. buffer_size /= 2;
  1159. if (buffer_size <= 256)
  1160. {
  1161. LOG_WARNING("no large enough working area available, can't do block memory writes");
  1162. retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  1163. goto cleanup;
  1164. }
  1165. };
  1166. /* setup algo registers */
  1167. init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
  1168. init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
  1169. init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
  1170. init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
  1171. init_reg_param(&reg_params[4], "r4", 32, PARAM_IN);
  1172. init_reg_param(&reg_params[5], "r5", 32, PARAM_OUT);
  1173. init_reg_param(&reg_params[6], "r6", 32, PARAM_OUT);
  1174. /* prepare command and status register patterns */
  1175. write_command_val = cfi_command_val(bank, 0x40);
  1176. busy_pattern_val = cfi_command_val(bank, 0x80);
  1177. error_pattern_val = cfi_command_val(bank, 0x7e);
  1178. LOG_DEBUG("Using target buffer at 0x%08" PRIx32 " and of size 0x%04" PRIx32,
  1179. source->address, buffer_size);
  1180. /* Programming main loop */
  1181. while (count > 0)
  1182. {
  1183. uint32_t thisrun_count = (count > buffer_size) ? buffer_size : count;
  1184. uint32_t wsm_error;
  1185. if ((retval = target_write_buffer(target, source->address,
  1186. thisrun_count, buffer)) != ERROR_OK)
  1187. {
  1188. goto cleanup;
  1189. }
  1190. buf_set_u32(reg_params[0].value, 0, 32, source->address);
  1191. buf_set_u32(reg_params[1].value, 0, 32, address);
  1192. buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
  1193. buf_set_u32(reg_params[3].value, 0, 32, write_command_val);
  1194. buf_set_u32(reg_params[5].value, 0, 32, busy_pattern_val);
  1195. buf_set_u32(reg_params[6].value, 0, 32, error_pattern_val);
  1196. LOG_DEBUG("Write 0x%04" PRIx32 " bytes to flash at 0x%08" PRIx32 , thisrun_count, address);
  1197. /* Execute algorithm, assume breakpoint for last instruction */
  1198. retval = target_run_algorithm(target, 0, NULL, 7, reg_params,
  1199. cfi_info->write_algorithm->address,
  1200. cfi_info->write_algorithm->address + target_code_size - sizeof(uint32_t),
  1201. 10000, /* 10s should be enough for max. 32k of data */
  1202. &armv4_5_info);
  1203. /* On failure try a fall back to direct word writes */
  1204. if (retval != ERROR_OK)
  1205. {
  1206. cfi_intel_clear_status_register(bank);
  1207. LOG_ERROR("Execution of flash algorythm failed. Can't fall back. Please report.");
  1208. retval = ERROR_FLASH_OPERATION_FAILED;
  1209. /* retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE; */
  1210. /* FIXME To allow fall back or recovery, we must save the actual status
  1211. * somewhere, so that a higher level code can start recovery. */
  1212. goto cleanup;
  1213. }
  1214. /* Check return value from algo code */
  1215. wsm_error = buf_get_u32(reg_params[4].value, 0, 32) & error_pattern_val;
  1216. if (wsm_error)
  1217. {
  1218. /* read status register (outputs debug inforation) */
  1219. uint8_t status;
  1220. cfi_intel_wait_status_busy(bank, 100, &status);
  1221. cfi_intel_clear_status_register(bank);
  1222. retval = ERROR_FLASH_OPERATION_FAILED;
  1223. goto cleanup;
  1224. }
  1225. buffer += thisrun_count;
  1226. address += thisrun_count;
  1227. count -= thisrun_count;
  1228. keep_alive();
  1229. }
  1230. /* free up resources */
  1231. cleanup:
  1232. if (source)
  1233. target_free_working_area(target, source);
  1234. if (cfi_info->write_algorithm)
  1235. {
  1236. target_free_working_area(target, cfi_info->write_algorithm);
  1237. cfi_info->write_algorithm = NULL;
  1238. }
  1239. destroy_reg_param(&reg_params[0]);
  1240. destroy_reg_param(&reg_params[1]);
  1241. destroy_reg_param(&reg_params[2]);
  1242. destroy_reg_param(&reg_params[3]);
  1243. destroy_reg_param(&reg_params[4]);
  1244. destroy_reg_param(&reg_params[5]);
  1245. destroy_reg_param(&reg_params[6]);
  1246. return retval;
  1247. }
  1248. static int cfi_spansion_write_block(struct flash_bank *bank, uint8_t *buffer,
  1249. uint32_t address, uint32_t count)
  1250. {
  1251. struct cfi_flash_bank *cfi_info = bank->driver_priv;
  1252. struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
  1253. struct target *target = bank->target;
  1254. struct reg_param reg_params[10];
  1255. struct arm_algorithm armv4_5_info;
  1256. struct working_area *source;
  1257. uint32_t buffer_size = 32768;
  1258. uint32_t status;
  1259. int retval = ERROR_OK;
  1260. /* input parameters - */
  1261. /* R0 = source address */
  1262. /* R1 = destination address */
  1263. /* R2 = number of writes */
  1264. /* R3 = flash write command */
  1265. /* R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
  1266. /* output parameters - */
  1267. /* R5 = 0x80 ok 0x00 bad */
  1268. /* temp registers - */
  1269. /* R6 = value read from flash to test status */
  1270. /* R7 = holding register */
  1271. /* unlock registers - */
  1272. /* R8 = unlock1_addr */
  1273. /* R9 = unlock1_cmd */
  1274. /* R10 = unlock2_addr */
  1275. /* R11 = unlock2_cmd */
  1276. /* see contib/loaders/flash/armv4_5_cfi_span_32.s for src */
  1277. static const uint32_t word_32_code[] = {
  1278. /* 00008100 <sp_32_code>: */
  1279. 0xe4905004, /* ldr r5, [r0], #4 */
  1280. 0xe5889000, /* str r9, [r8] */
  1281. 0xe58ab000, /* str r11, [r10] */
  1282. 0xe5883000, /* str r3, [r8] */
  1283. 0xe5815000, /* str r5, [r1] */
  1284. 0xe1a00000, /* nop */
  1285. /* */
  1286. /* 00008110 <sp_32_busy>: */
  1287. 0xe5916000, /* ldr r6, [r1] */
  1288. 0xe0257006, /* eor r7, r5, r6 */
  1289. 0xe0147007, /* ands r7, r4, r7 */
  1290. 0x0a000007, /* beq 8140 <sp_32_cont> ; b if DQ7 == Data7 */
  1291. 0xe0166124, /* ands r6, r6, r4, lsr #2 */
  1292. 0x0afffff9, /* beq 8110 <sp_32_busy> ; b if DQ5 low */
  1293. 0xe5916000, /* ldr r6, [r1] */
  1294. 0xe0257006, /* eor r7, r5, r6 */
  1295. 0xe0147007, /* ands r7, r4, r7 */
  1296. 0x0a000001, /* beq 8140 <sp_32_cont> ; b if DQ7 == Data7 */
  1297. 0xe3a05000, /* mov r5, #0 ; 0x0 - return 0x00, error */
  1298. 0x1a000004, /* bne 8154 <sp_32_done> */
  1299. /* */
  1300. /* 00008140 <sp_32_cont>: */
  1301. 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
  1302. 0x03a05080, /* moveq r5, #128 ; 0x80 */
  1303. 0x0a000001, /* beq 8154 <sp_32_done> */
  1304. 0xe2811004, /* add r1, r1, #4 ; 0x4 */
  1305. 0xeaffffe8, /* b 8100 <sp_32_code> */
  1306. /* */
  1307. /* 00008154 <sp_32_done>: */
  1308. 0xeafffffe /* b 8154 <sp_32_done> */
  1309. };
  1310. /* see contib/loaders/flash/armv4_5_cfi_span_16.s for src */
  1311. static const uint32_t word_16_code[] = {
  1312. /* 00008158 <sp_16_code>: */
  1313. 0xe0d050b2, /* ldrh r5, [r0], #2 */
  1314. 0xe1c890b0, /* strh r9, [r8] */
  1315. 0xe1cab0b0, /* strh r11, [r10] */
  1316. 0xe1c830b0, /* strh r3, [r8] */
  1317. 0xe1c150b0, /* strh r5, [r1] */
  1318. 0xe1a00000, /* nop (mov r0,r0) */
  1319. /* */
  1320. /* 00008168 <sp_16_busy>: */
  1321. 0xe1d160b0, /* ldrh r6, [r1] */
  1322. 0xe0257006, /* eor r7, r5, r6 */
  1323. 0xe0147007, /* ands r7, r4, r7 */
  1324. 0x0a000007, /* beq 8198 <sp_16_cont> */
  1325. 0xe0166124, /* ands r6, r6, r4, lsr #2 */
  1326. 0x0afffff9, /* beq 8168 <sp_16_busy> */
  1327. 0xe1d160b0, /* ldrh r6, [r1] */
  1328. 0xe0257006, /* eor r7, r5, r6 */
  1329. 0xe0147007, /* ands r7, r4, r7 */
  1330. 0x0a000001, /* beq 8198 <sp_16_cont> */
  1331. 0xe3a05000, /* mov r5, #0 ; 0x0 */
  1332. 0x1a000004, /* bne 81ac <sp_16_done> */
  1333. /* */
  1334. /* 00008198 <sp_16_cont>: */
  1335. 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
  1336. 0x03a05080, /* moveq r5, #128 ; 0x80 */
  1337. 0x0a000001, /* beq 81ac <sp_16_done> */
  1338. 0xe2811002, /* add r1, r1, #2 ; 0x2 */
  1339. 0xeaffffe8, /* b 8158 <sp_16_code> */
  1340. /* */
  1341. /* 000081ac <sp_16_done>: */
  1342. 0xeafffffe /* b 81ac <sp_16_done> */
  1343. };
  1344. /* see contib/loaders/flash/armv4_5_cfi_span_16_dq7.s for src */
  1345. static const uint32_t word_16_code_dq7only[] = {
  1346. /* <sp_16_code>: */
  1347. 0xe0d050b2, /* ldrh r5, [r0], #2 */
  1348. 0xe1c890b0, /* strh r9, [r8] */
  1349. 0xe1cab0b0, /* strh r11, [r10] */
  1350. 0xe1c830b0, /* strh r3, [r8] */
  1351. 0xe1c150b0, /* strh r5, [r1] */
  1352. 0xe1a00000, /* nop (mov r0,r0) */
  1353. /* */
  1354. /* <sp_16_busy>: */
  1355. 0xe1d160b0, /* ldrh r6, [r1] */
  1356. 0xe0257006, /* eor r7, r5, r6 */
  1357. 0xe2177080, /* ands r7, #0x80 */
  1358. 0x1afffffb, /* bne 8168 <sp_16_busy> */
  1359. /* */
  1360. 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
  1361. 0x03a05080, /* moveq r5, #128 ; 0x80 */
  1362. 0x0a000001, /* beq 81ac <sp_16_done> */
  1363. 0xe2811002, /* add r1, r1, #2 ; 0x2 */
  1364. 0xeafffff0, /* b 8158 <sp_16_code> */
  1365. /* */
  1366. /* 000081ac <sp_16_done>: */
  1367. 0xeafffffe /* b 81ac <sp_16_done> */
  1368. };
  1369. /* see contib/loaders/flash/armv4_5_cfi_span_8.s for src */
  1370. static const uint32_t word_8_code[] = {
  1371. /* 000081b0 <sp_16_code_end>: */
  1372. 0xe4d05001, /* ldrb r5, [r0], #1 */
  1373. 0xe5c89000, /* strb r9, [r8] */
  1374. 0xe5cab000, /* strb r11, [r10] */
  1375. 0xe5c83000, /* strb r3, [r8] */
  1376. 0xe5c15000, /* strb r5, [r1] */
  1377. 0xe1a00000, /* nop (mov r0,r0) */
  1378. /* */
  1379. /* 000081c0 <sp_8_busy>: */
  1380. 0xe5d16000, /* ldrb r6, [r1] */
  1381. 0xe0257006, /* eor r7, r5, r6 */
  1382. 0xe0147007, /* ands r7, r4, r7 */
  1383. 0x0a000007, /* beq 81f0 <sp_8_cont> */
  1384. 0xe0166124, /* ands r6, r6, r4, lsr #2 */
  1385. 0x0afffff9, /* beq 81c0 <sp_8_busy> */
  1386. 0xe5d16000, /* ldrb r6, [r1] */
  1387. 0xe0257006, /* eor r7, r5, r6 */
  1388. 0xe0147007, /* ands r7, r4, r7 */
  1389. 0x0a000001, /* beq 81f0 <sp_8_cont> */
  1390. 0xe3a05000, /* mov r5, #0 ; 0x0 */
  1391. 0x1a000004, /* bne 8204 <sp_8_done> */
  1392. /* */
  1393. /* 000081f0 <sp_8_cont>: */
  1394. 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
  1395. 0x03a05080, /* moveq r5, #128 ; 0x80 */
  1396. 0x0a000001, /* beq 8204 <sp_8_done> */
  1397. 0xe2811001, /* add r1, r1, #1 ; 0x1 */
  1398. 0xeaffffe8, /* b 81b0 <sp_16_code_end> */
  1399. /* */
  1400. /* 00008204 <sp_8_done>: */
  1401. 0xeafffffe /* b 8204 <sp_8_done> */
  1402. };
  1403. armv4_5_info.common_magic = ARM_COMMON_MAGIC;
  1404. armv4_5_info.core_mode = ARM_MODE_SVC;
  1405. armv4_5_info.core_state = ARM_STATE_ARM;
  1406. int target_code_size;
  1407. const uint32_t *target_code_src;
  1408. switch (bank->bus_width)
  1409. {
  1410. case 1 :
  1411. target_code_src = word_8_code;
  1412. target_code_size = sizeof(word_8_code);
  1413. break;
  1414. case 2 :
  1415. /* Check for DQ5 support */
  1416. if( cfi_info->status_poll_mask & (1 << 5) )
  1417. {
  1418. target_code_src = word_16_code;
  1419. target_code_size = sizeof(word_16_code);
  1420. }
  1421. else
  1422. {
  1423. /* No DQ5 support. Use DQ7 DATA# polling only. */
  1424. target_code_src = word_16_code_dq7only;
  1425. target_code_size = sizeof(word_16_code_dq7only);
  1426. }
  1427. break;
  1428. case 4 :
  1429. target_code_src = word_32_code;
  1430. target_code_size = sizeof(word_32_code);
  1431. break;
  1432. default:
  1433. LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
  1434. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  1435. }
  1436. /* flash write code */
  1437. if (!cfi_info->write_algorithm)
  1438. {
  1439. uint8_t *target_code;
  1440. /* convert bus-width dependent algorithm code to correct endiannes */
  1441. target_code = malloc(target_code_size);
  1442. if (target_code == NULL)
  1443. {
  1444. LOG_ERROR("Out of memory");
  1445. return ERROR_FAIL;
  1446. }
  1447. cfi_fix_code_endian(target, target_code, target_code_src, target_code_size / 4);
  1448. /* allocate working area */
  1449. retval = target_alloc_working_area(target, target_code_size,
  1450. &cfi_info->write_algorithm);
  1451. if (retval != ERROR_OK)
  1452. {
  1453. free(target_code);
  1454. return retval;
  1455. }
  1456. /* write algorithm code to working area */
  1457. if ((retval = target_write_buffer(target, cfi_info->write_algorithm->address,
  1458. target_code_size, target_code)) != ERROR_OK)
  1459. {
  1460. free(target_code);
  1461. return retval;
  1462. }
  1463. free(target_code);
  1464. }
  1465. /* the following code still assumes target code is fixed 24*4 bytes */
  1466. while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK)
  1467. {
  1468. buffer_size /= 2;
  1469. if (buffer_size <= 256)
  1470. {
  1471. /* if we already allocated the writing code, but failed to get a
  1472. * buffer, free the algorithm */
  1473. if (cfi_info->write_algorithm)
  1474. target_free_working_area(target, cfi_info->write_algorithm);
  1475. LOG_WARNING("not enough working area available, can't do block memory writes");
  1476. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  1477. }
  1478. };
  1479. init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
  1480. init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
  1481. init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
  1482. init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
  1483. init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT);
  1484. init_reg_param(&reg_params[5], "r5", 32, PARAM_IN);
  1485. init_reg_param(&reg_params[6], "r8", 32, PARAM_OUT);
  1486. init_reg_param(&reg_params[7], "r9", 32, PARAM_OUT);
  1487. init_reg_param(&reg_params[8], "r10", 32, PARAM_OUT);
  1488. init_reg_param(&reg_params[9], "r11", 32, PARAM_OUT);
  1489. while (count > 0)
  1490. {
  1491. uint32_t thisrun_count = (count > buffer_size) ? buffer_size : count;
  1492. retval = target_write_buffer(target, source->address, thisrun_count, buffer);
  1493. if (retval != ERROR_OK)
  1494. {
  1495. break;
  1496. }
  1497. buf_set_u32(reg_params[0].value, 0, 32, source->address);
  1498. buf_set_u32(reg_params[1].value, 0, 32, address);
  1499. buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
  1500. buf_set_u32(reg_params[3].value, 0, 32, cfi_command_val(bank, 0xA0));
  1501. buf_set_u32(reg_params[4].value, 0, 32, cfi_command_val(bank, 0x80));
  1502. buf_set_u32(reg_params[6].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock1));
  1503. buf_set_u32(reg_params[7].value, 0, 32, 0xaaaaaaaa);
  1504. buf_set_u32(reg_params[8].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock2));
  1505. buf_set_u32(reg_params[9].value, 0, 32, 0x55555555);
  1506. retval = target_run_algorithm(target, 0, NULL, 10, reg_params,
  1507. cfi_info->write_algorithm->address,
  1508. cfi_info->write_algorithm->address + ((target_code_size) - 4),
  1509. 10000, &armv4_5_info);
  1510. if (retval != ERROR_OK)
  1511. {
  1512. break;
  1513. }
  1514. status = buf_get_u32(reg_params[5].value, 0, 32);
  1515. if (status != 0x80)
  1516. {
  1517. LOG_ERROR("flash write block failed status: 0x%" PRIx32 , status);
  1518. retval = ERROR_FLASH_OPERATION_FAILED;
  1519. break;
  1520. }
  1521. buffer += thisrun_count;
  1522. address += thisrun_count;
  1523. count -= thisrun_count;
  1524. }
  1525. target_free_all_working_areas(target);
  1526. destroy_reg_param(&reg_params[0]);
  1527. destroy_reg_param(&reg_params[1]);
  1528. destroy_reg_param(&reg_params[2]);
  1529. destroy_reg_param(&reg_params[3]);
  1530. destroy_reg_param(&reg_params[4]);
  1531. destroy_reg_param(&reg_params[5]);
  1532. destroy_reg_param(&reg_params[6]);
  1533. destroy_reg_param(&reg_params[7]);
  1534. destroy_reg_param(&reg_params[8]);
  1535. destroy_reg_param(&reg_params[9]);
  1536. return retval;
  1537. }
  1538. static int cfi_intel_write_word(struct flash_bank *bank, uint8_t *word, uint32_t address)
  1539. {
  1540. int retval;
  1541. struct cfi_flash_bank *cfi_info = bank->driver_priv;
  1542. struct target *target = bank->target;
  1543. cfi_intel_clear_status_register(bank);
  1544. if ((retval = cfi_send_command(bank, 0x40, address)) != ERROR_OK)
  1545. {
  1546. return retval;
  1547. }
  1548. if ((retval = target_write_memory(target, address, bank->bus_width, 1, word)) != ERROR_OK)
  1549. {
  1550. return retval;
  1551. }
  1552. uint8_t status;
  1553. retval = cfi_intel_wait_status_busy(bank, cfi_info->word_write_timeout, &status);
  1554. if (retval != 0x80)
  1555. {
  1556. if ((retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0))) != ERROR_OK)
  1557. {
  1558. return retval;
  1559. }
  1560. LOG_ERROR("couldn't write word at base 0x%" PRIx32 ", address 0x%" PRIx32,
  1561. bank->base, address);
  1562. return ERROR_FLASH_OPERATION_FAILED;
  1563. }
  1564. return ERROR_OK;
  1565. }
  1566. static int cfi_intel_write_words(struct flash_bank *bank, uint8_t *word,
  1567. uint32_t wordcount, uint32_t address)
  1568. {
  1569. int retval;
  1570. struct cfi_flash_bank *cfi_info = bank->driver_priv;
  1571. struct target *target = bank->target;
  1572. /* Calculate buffer size and boundary mask */
  1573. /* buffersize is (buffer size per chip) * (number of chips) */
  1574. /* bufferwsize is buffersize in words */
  1575. uint32_t buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
  1576. uint32_t buffermask = buffersize-1;
  1577. uint32_t bufferwsize = buffersize / bank->bus_width;
  1578. /* Check for valid range */
  1579. if (address & buffermask)
  1580. {
  1581. LOG_ERROR("Write address at base 0x%" PRIx32 ", address 0x%" PRIx32
  1582. " not aligned to 2^%d boundary",
  1583. bank->base, address, cfi_info->max_buf_write_size);
  1584. return ERROR_FLASH_OPERATION_FAILED;
  1585. }
  1586. /* Check for valid size */
  1587. if (wordcount > bufferwsize)
  1588. {
  1589. LOG_ERROR("Number of data words %" PRId32 " exceeds available buffersize %" PRId32,
  1590. wordcount, buffersize);
  1591. return ERROR_FLASH_OPERATION_FAILED;
  1592. }
  1593. /* Write to flash buffer */
  1594. cfi_intel_clear_status_register(bank);
  1595. /* Initiate buffer operation _*/
  1596. if ((retval = cfi_send_command(bank, 0xe8, address)) != ERROR_OK)
  1597. {
  1598. return retval;
  1599. }
  1600. uint8_t status;
  1601. retval = cfi_intel_wait_status_busy(bank, cfi_info->buf_write_timeout, &status);
  1602. if (retval != ERROR_OK)
  1603. return retval;
  1604. if (status != 0x80)
  1605. {
  1606. if ((retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0))) != ERROR_OK)
  1607. {
  1608. return retval;
  1609. }
  1610. LOG_ERROR("couldn't start buffer write operation at base 0x%" PRIx32 ", address 0x%" PRIx32,
  1611. bank->base, address);
  1612. return ERROR_FLASH_OPERATION_FAILED;
  1613. }
  1614. /* Write buffer wordcount-1 and data words */
  1615. if ((retval = cfi_send_command(bank, bufferwsize-1, address)) != ERROR_OK)
  1616. {
  1617. return retval;
  1618. }
  1619. if ((retval = target_write_memory(target,
  1620. address, bank->bus_width, bufferwsize, word)) != ERROR_OK)
  1621. {
  1622. return retval;
  1623. }
  1624. /* Commit write operation */
  1625. if ((retval = cfi_send_command(bank, 0xd0, address)) != ERROR_OK)
  1626. {
  1627. return retval;
  1628. }
  1629. retval = cfi_intel_wait_status_busy(bank, cfi_info->buf_write_timeout, &status);
  1630. if (retval != ERROR_OK)
  1631. return retval;
  1632. if (status != 0x80)
  1633. {
  1634. if ((retval = cfi_send_command(bank, 0xff,
  1635. flash_address(bank, 0, 0x0))) != ERROR_OK)
  1636. {
  1637. return retval;
  1638. }
  1639. LOG_ERROR("Buffer write at base 0x%" PRIx32
  1640. ", address 0x%" PRIx32 " failed.", bank->base, address);
  1641. return ERROR_FLASH_OPERATION_FAILED;
  1642. }
  1643. return ERROR_OK;
  1644. }
  1645. static int cfi_spansion_write_word(struct flash_bank *bank, uint8_t *word, uint32_t address)
  1646. {
  1647. int retval;
  1648. struct cfi_flash_bank *cfi_info = bank->driver_priv;
  1649. struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
  1650. struct target *target = bank->target;
  1651. if ((retval = cfi_send_command(bank, 0xaa,
  1652. flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
  1653. {
  1654. return retval;
  1655. }
  1656. if ((retval = cfi_send_command(bank, 0x55,
  1657. flash_address(bank, 0, pri_ext->_unlock2))) != ERROR_OK)
  1658. {
  1659. return retval;
  1660. }
  1661. if ((retval = cfi_send_command(bank, 0xa0,
  1662. flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
  1663. {
  1664. return retval;
  1665. }
  1666. if ((retval = target_write_memory(target,
  1667. address, bank->bus_width, 1, word)) != ERROR_OK)
  1668. {
  1669. return retval;
  1670. }
  1671. if (cfi_spansion_wait_status_busy(bank, cfi_info->word_write_timeout) != ERROR_OK)
  1672. {
  1673. if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
  1674. {
  1675. return retval;
  1676. }
  1677. LOG_ERROR("couldn't write word at base 0x%" PRIx32
  1678. ", address 0x%" PRIx32 , bank->base, address);
  1679. return ERROR_FLASH_OPERATION_FAILED;
  1680. }
  1681. return ERROR_OK;
  1682. }
  1683. static int cfi_spansion_write_words(struct flash_bank *bank, uint8_t *word,
  1684. uint32_t wordcount, uint32_t address)
  1685. {
  1686. int retval;
  1687. struct cfi_flash_bank *cfi_info = bank->driver_priv;
  1688. struct target *target = bank->target;
  1689. struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
  1690. /* Calculate buffer size and boundary mask */
  1691. /* buffersize is (buffer size per chip) * (number of chips) */
  1692. /* bufferwsize is buffersize in words */
  1693. uint32_t buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
  1694. uint32_t buffermask = buffersize-1;
  1695. uint32_t bufferwsize = buffersize / bank->bus_width;
  1696. /* Check for valid range */
  1697. if (address & buffermask)
  1698. {
  1699. LOG_ERROR("Write address at base 0x%" PRIx32
  1700. ", address 0x%" PRIx32 " not aligned to 2^%d boundary",
  1701. bank->base, address, cfi_info->max_buf_write_size);
  1702. return ERROR_FLASH_OPERATION_FAILED;
  1703. }
  1704. /* Check for valid size */
  1705. if (wordcount > bufferwsize)
  1706. {
  1707. LOG_ERROR("Number of data words %" PRId32 " exceeds available buffersize %"
  1708. PRId32, wordcount, buffersize);
  1709. return ERROR_FLASH_OPERATION_FAILED;
  1710. }
  1711. /* Unlock */
  1712. if ((retval = cfi_send_command(bank, 0xaa,
  1713. flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
  1714. {
  1715. return retval;
  1716. }
  1717. if ((retval = cfi_send_command(bank, 0x55,
  1718. flash_address(bank, 0, pri_ext->_unlock2))) != ERROR_OK)
  1719. {
  1720. return retval;
  1721. }
  1722. /* Buffer load command */
  1723. if ((retval = cfi_send_command(bank, 0x25, address)) != ERROR_OK)
  1724. {
  1725. return retval;
  1726. }
  1727. /* Write buffer wordcount-1 and data words */
  1728. if ((retval = cfi_send_command(bank, bufferwsize-1, address)) != ERROR_OK)
  1729. {
  1730. return retval;
  1731. }
  1732. if ((retval = target_write_memory(target,
  1733. address, bank->bus_width, bufferwsize, word)) != ERROR_OK)
  1734. {
  1735. return retval;
  1736. }
  1737. /* Commit write operation */
  1738. if ((retval = cfi_send_command(bank, 0x29, address)) != ERROR_OK)
  1739. {
  1740. return retval;
  1741. }
  1742. if (cfi_spansion_wait_status_busy(bank, cfi_info->buf_write_timeout) != ERROR_OK)
  1743. {
  1744. if ((retval = cfi_send_command(bank, 0xf0,
  1745. flash_address(bank, 0, 0x0))) != ERROR_OK)
  1746. {
  1747. return retval;
  1748. }
  1749. LOG_ERROR("couldn't write block at base 0x%" PRIx32
  1750. ", address 0x%" PRIx32 ", size 0x%" PRIx32, bank->base, address, bufferwsize);
  1751. return ERROR_FLASH_OPERATION_FAILED;
  1752. }
  1753. return ERROR_OK;
  1754. }
  1755. static int cfi_write_word(struct flash_bank *bank, uint8_t *word, uint32_t address)
  1756. {
  1757. struct cfi_flash_bank *cfi_info = bank->driver_priv;
  1758. switch (cfi_info->pri_id)
  1759. {
  1760. case 1:
  1761. case 3:
  1762. return cfi_intel_write_word(bank, word, address);
  1763. break;
  1764. case 2:
  1765. return cfi_spansion_write_word(bank, word, address);
  1766. break;
  1767. default:
  1768. LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
  1769. break;
  1770. }
  1771. return ERROR_FLASH_OPERATION_FAILED;
  1772. }
  1773. static int cfi_write_words(struct flash_bank *bank, uint8_t *word,
  1774. uint32_t wordcount, uint32_t address)
  1775. {
  1776. struct cfi_flash_bank *cfi_info = bank->driver_priv;
  1777. if (cfi_info->buf_write_timeout_typ == 0)
  1778. {
  1779. /* buffer writes are not supported */
  1780. LOG_DEBUG("Buffer Writes Not Supported");
  1781. return ERROR_FLASH_OPER_UNSUPPORTED;
  1782. }
  1783. switch (cfi_info->pri_id)
  1784. {
  1785. case 1:
  1786. case 3:
  1787. return cfi_intel_write_words(bank, word, wordcount, address);
  1788. break;
  1789. case 2:
  1790. return cfi_spansion_write_words(bank, word, wordcount, address);
  1791. break;
  1792. default:
  1793. LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
  1794. break;
  1795. }
  1796. return ERROR_FLASH_OPERATION_FAILED;
  1797. }
  1798. static int cfi_read(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
  1799. {
  1800. struct cfi_flash_bank *cfi_info = bank->driver_priv;
  1801. struct target *target = bank->target;
  1802. uint32_t address = bank->base + offset;
  1803. uint32_t read_p;
  1804. int align; /* number of unaligned bytes */
  1805. uint8_t current_word[CFI_MAX_BUS_WIDTH];
  1806. int i;
  1807. int retval;
  1808. LOG_DEBUG("reading buffer of %i byte at 0x%8.8x",
  1809. (int)count, (unsigned)offset);
  1810. if (bank->target->state != TARGET_HALTED)
  1811. {
  1812. LOG_ERROR("Target not halted");
  1813. return ERROR_TARGET_NOT_HALTED;
  1814. }
  1815. if (offset + count > bank->size)
  1816. return ERROR_FLASH_DST_OUT_OF_BANK;
  1817. if (cfi_info->qry[0] != 'Q')
  1818. return ERROR_FLASH_BANK_NOT_PROBED;
  1819. /* start at the first byte of the first word (bus_width size) */
  1820. read_p = address & ~(bank->bus_width - 1);
  1821. if ((align = address - read_p) != 0)
  1822. {
  1823. LOG_INFO("Fixup %d unaligned read head bytes", align);
  1824. /* read a complete word from flash */
  1825. if ((retval = target_read_memory(target, read_p,
  1826. bank->bus_width, 1, current_word)) != ERROR_OK)
  1827. return retval;
  1828. /* take only bytes we need */
  1829. for (i = align; (i < bank->bus_width) && (count > 0); i++, count--)
  1830. *buffer++ = current_word[i];
  1831. read_p += bank->bus_width;
  1832. }
  1833. align = count / bank->bus_width;
  1834. if (align)
  1835. {
  1836. if ((retval = target_read_memory(target, read_p,
  1837. bank->bus_width, align, buffer)) != ERROR_OK)
  1838. return retval;
  1839. read_p += align * bank->bus_width;
  1840. buffer += align * bank->bus_width;
  1841. count -= align * bank->bus_width;
  1842. }
  1843. if (count)
  1844. {
  1845. LOG_INFO("Fixup %d unaligned read tail bytes", count);
  1846. /* read a complete word from flash */
  1847. if ((retval = target_read_memory(target, read_p,
  1848. bank->bus_width, 1, current_word)) != ERROR_OK)
  1849. return retval;
  1850. /* take only bytes we need */
  1851. for (i = 0; (i < bank->bus_width) && (count > 0); i++, count--)
  1852. *buffer++ = current_word[i];
  1853. }
  1854. return ERROR_OK;
  1855. }
  1856. static int cfi_write(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
  1857. {
  1858. struct cfi_flash_bank *cfi_info = bank->driver_priv;
  1859. struct target *target = bank->target;
  1860. uint32_t address = bank->base + offset; /* address of first byte to be programmed */
  1861. uint32_t write_p;
  1862. int align; /* number of unaligned bytes */
  1863. int blk_count; /* number of bus_width bytes for block copy */
  1864. uint8_t current_word[CFI_MAX_BUS_WIDTH * 4]; /* word (bus_width size) currently being programmed */
  1865. int i;
  1866. int retval;
  1867. if (bank->target->state != TARGET_HALTED)
  1868. {
  1869. LOG_ERROR("Target not halted");
  1870. return ERROR_TARGET_NOT_HALTED;
  1871. }
  1872. if (offset + count > bank->size)
  1873. return ERROR_FLASH_DST_OUT_OF_BANK;
  1874. if (cfi_info->qry[0] != 'Q')
  1875. return ERROR_FLASH_BANK_NOT_PROBED;
  1876. /* start at the first byte of the first word (bus_width size) */
  1877. write_p = address & ~(bank->bus_width - 1);
  1878. if ((align = address - write_p) != 0)
  1879. {
  1880. LOG_INFO("Fixup %d unaligned head bytes", align);
  1881. /* read a complete word from flash */
  1882. if ((retval = target_read_memory(target, write_p,
  1883. bank->bus_width, 1, current_word)) != ERROR_OK)
  1884. return retval;
  1885. /* replace only bytes that must be written */
  1886. for (i = align; (i < bank->bus_width) && (count > 0); i++, count--)
  1887. current_word[i] = *buffer++;
  1888. retval = cfi_write_word(bank, current_word, write_p);
  1889. if (retval != ERROR_OK)
  1890. return retval;
  1891. write_p += bank->bus_width;
  1892. }
  1893. /* handle blocks of bus_size aligned bytes */
  1894. blk_count = count & ~(bank->bus_width - 1); /* round down, leave tail bytes */
  1895. switch (cfi_info->pri_id)
  1896. {
  1897. /* try block writes (fails without working area) */
  1898. case 1:
  1899. case 3:
  1900. retval = cfi_intel_write_block(bank, buffer, write_p, blk_count);
  1901. break;
  1902. case 2:
  1903. retval = cfi_spansion_write_block(bank, buffer, write_p, blk_count);
  1904. break;
  1905. default:
  1906. LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
  1907. retval = ERROR_FLASH_OPERATION_FAILED;
  1908. break;
  1909. }
  1910. if (retval == ERROR_OK)
  1911. {
  1912. /* Increment pointers and decrease count on succesful block write */
  1913. buffer += blk_count;
  1914. write_p += blk_count;
  1915. count -= blk_count;
  1916. }
  1917. else
  1918. {
  1919. if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
  1920. {
  1921. /* Calculate buffer size and boundary mask */
  1922. /* buffersize is (buffer size per chip) * (number of chips) */
  1923. /* bufferwsize is buffersize in words */
  1924. uint32_t buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
  1925. uint32_t buffermask = buffersize-1;
  1926. uint32_t bufferwsize = buffersize / bank->bus_width;
  1927. /* fall back to memory writes */
  1928. while (count >= (uint32_t)bank->bus_width)
  1929. {
  1930. int fallback;
  1931. if ((write_p & 0xff) == 0)
  1932. {
  1933. LOG_INFO("Programming at 0x%08" PRIx32 ", count 0x%08"
  1934. PRIx32 " bytes remaining", write_p, count);
  1935. }
  1936. fallback = 1;
  1937. if ((bufferwsize > 0) && (count >= buffersize) && !(write_p & buffermask))
  1938. {
  1939. retval = cfi_write_words(bank, buffer, bufferwsize, write_p);
  1940. if (retval == ERROR_OK)
  1941. {
  1942. buffer += buffersize;
  1943. write_p += buffersize;
  1944. count -= buffersize;
  1945. fallback = 0;
  1946. }
  1947. else if (retval != ERROR_FLASH_OPER_UNSUPPORTED)
  1948. return retval;
  1949. }
  1950. /* try the slow way? */
  1951. if (fallback)
  1952. {
  1953. for (i = 0; i < bank->bus_width; i++)
  1954. current_word[i] = *buffer++;
  1955. retval = cfi_write_word(bank, current_word, write_p);
  1956. if (retval != ERROR_OK)
  1957. return retval;
  1958. write_p += bank->bus_width;
  1959. count -= bank->bus_width;
  1960. }
  1961. }
  1962. }
  1963. else
  1964. return retval;
  1965. }
  1966. /* return to read array mode, so we can read from flash again for padding */
  1967. if ((retval = cfi_reset(bank)) != ERROR_OK)
  1968. {
  1969. return retval;
  1970. }
  1971. /* handle unaligned tail bytes */
  1972. if (count > 0)
  1973. {
  1974. LOG_INFO("Fixup %" PRId32 " unaligned tail bytes", count);
  1975. /* read a complete word from flash */
  1976. if ((retval = target_read_memory(target, write_p,
  1977. bank->bus_width, 1, current_word)) != ERROR_OK)
  1978. return retval;
  1979. /* replace only bytes that must be written */
  1980. for (i = 0; (i < bank->bus_width) && (count > 0); i++, count--)
  1981. current_word[i] = *buffer++;
  1982. retval = cfi_write_word(bank, current_word, write_p);
  1983. if (retval != ERROR_OK)
  1984. return retval;
  1985. }
  1986. /* return to read array mode */
  1987. return cfi_reset(bank);
  1988. }
  1989. static void cfi_fixup_reversed_erase_regions(struct flash_bank *bank, void *param)
  1990. {
  1991. (void) param;
  1992. struct cfi_flash_bank *cfi_info = bank->driver_priv;
  1993. struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
  1994. pri_ext->_reversed_geometry = 1;
  1995. }
  1996. static void cfi_fixup_0002_erase_regions(struct flash_bank *bank, void *param)
  1997. {
  1998. int i;
  1999. struct cfi_flash_bank *cfi_info = bank->driver_priv;
  2000. struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
  2001. (void) param;
  2002. if ((pri_ext->_reversed_geometry) || (pri_ext->TopBottom == 3))
  2003. {
  2004. LOG_DEBUG("swapping reversed erase region information on cmdset 0002 device");
  2005. for (i = 0; i < cfi_info->num_erase_regions / 2; i++)
  2006. {
  2007. int j = (cfi_info->num_erase_regions - 1) - i;
  2008. uint32_t swap;
  2009. swap = cfi_info->erase_region_info[i];
  2010. cfi_info->erase_region_info[i] = cfi_info->erase_region_info[j];
  2011. cfi_info->erase_region_info[j] = swap;
  2012. }
  2013. }
  2014. }
  2015. static void cfi_fixup_0002_unlock_addresses(struct flash_bank *bank, void *param)
  2016. {
  2017. struct cfi_flash_bank *cfi_info = bank->driver_priv;
  2018. struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
  2019. struct cfi_unlock_addresses *unlock_addresses = param;
  2020. pri_ext->_unlock1 = unlock_addresses->unlock1;
  2021. pri_ext->_unlock2 = unlock_addresses->unlock2;
  2022. }
  2023. static int cfi_query_string(struct flash_bank *bank, int address)
  2024. {
  2025. struct cfi_flash_bank *cfi_info = bank->driver_priv;
  2026. int retval;
  2027. if ((retval = cfi_send_command(bank, 0x98, flash_address(bank, 0, address))) != ERROR_OK)
  2028. {
  2029. return retval;
  2030. }
  2031. retval = cfi_query_u8(bank, 0, 0x10, &cfi_info->qry[0]);
  2032. if (retval != ERROR_OK)
  2033. return retval;
  2034. retval = cfi_query_u8(bank, 0, 0x11, &cfi_info->qry[1]);
  2035. if (retval != ERROR_OK)
  2036. return retval;
  2037. retval = cfi_query_u8(bank, 0, 0x12, &cfi_info->qry[2]);
  2038. if (retval != ERROR_OK)
  2039. return retval;
  2040. LOG_DEBUG("CFI qry returned: 0x%2.2x 0x%2.2x 0x%2.2x",
  2041. cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2]);
  2042. if ((cfi_info->qry[0] != 'Q') || (cfi_info->qry[1] != 'R') || (cfi_info->qry[2] != 'Y'))
  2043. {
  2044. if ((retval = cfi_reset(bank)) != ERROR_OK)
  2045. {
  2046. return retval;
  2047. }
  2048. LOG_ERROR("Could not probe bank: no QRY");
  2049. return ERROR_FLASH_BANK_INVALID;
  2050. }
  2051. return ERROR_OK;
  2052. }
  2053. static int cfi_probe(struct flash_bank *bank)
  2054. {
  2055. struct cfi_flash_bank *cfi_info = bank->driver_priv;
  2056. struct target *target = bank->target;
  2057. int num_sectors = 0;
  2058. int i;
  2059. int sector = 0;
  2060. uint32_t unlock1 = 0x555;
  2061. uint32_t unlock2 = 0x2aa;
  2062. int retval;
  2063. uint8_t value_buf0[CFI_MAX_BUS_WIDTH], value_buf1[CFI_MAX_BUS_WIDTH];
  2064. if (bank->target->state != TARGET_HALTED)
  2065. {
  2066. LOG_ERROR("Target not halted");
  2067. return ERROR_TARGET_NOT_HALTED;
  2068. }
  2069. cfi_info->probed = 0;
  2070. if (bank->sectors)
  2071. {
  2072. free(bank->sectors);
  2073. bank->sectors = NULL;
  2074. }
  2075. if(cfi_info->erase_region_info)
  2076. {
  2077. free(cfi_info->erase_region_info);
  2078. cfi_info->erase_region_info = NULL;
  2079. }
  2080. /* JEDEC standard JESD21C uses 0x5555 and 0x2aaa as unlock addresses,
  2081. * while CFI compatible AMD/Spansion flashes use 0x555 and 0x2aa
  2082. */
  2083. if (cfi_info->jedec_probe)
  2084. {
  2085. unlock1 = 0x5555;
  2086. unlock2 = 0x2aaa;
  2087. }
  2088. /* switch to read identifier codes mode ("AUTOSELECT") */
  2089. if ((retval = cfi_send_command(bank, 0xaa, flash_address(bank, 0, unlock1))) != ERROR_OK)
  2090. {
  2091. return retval;
  2092. }
  2093. if ((retval = cfi_send_command(bank, 0x55, flash_address(bank, 0, unlock2))) != ERROR_OK)
  2094. {
  2095. return retval;
  2096. }
  2097. if ((retval = cfi_send_command(bank, 0x90, flash_address(bank, 0, unlock1))) != ERROR_OK)
  2098. {
  2099. return retval;
  2100. }
  2101. if ((retval = target_read_memory(target, flash_address(bank, 0, 0x00),
  2102. bank->bus_width, 1, value_buf0)) != ERROR_OK)
  2103. {
  2104. return retval;
  2105. }
  2106. if ((retval = target_read_memory(target, flash_address(bank, 0, 0x01),
  2107. bank->bus_width, 1, value_buf1)) != ERROR_OK)
  2108. {
  2109. return retval;
  2110. }
  2111. switch (bank->chip_width) {
  2112. case 1:
  2113. cfi_info->manufacturer = *value_buf0;
  2114. cfi_info->device_id = *value_buf1;
  2115. break;
  2116. case 2:
  2117. cfi_info->manufacturer = target_buffer_get_u16(target, value_buf0);
  2118. cfi_info->device_id = target_buffer_get_u16(target, value_buf1);
  2119. break;
  2120. case 4:
  2121. cfi_info->manufacturer = target_buffer_get_u32(target, value_buf0);
  2122. cfi_info->device_id = target_buffer_get_u32(target, value_buf1);
  2123. break;
  2124. default:
  2125. LOG_ERROR("Unsupported bank chipwidth %d, can't probe memory", bank->chip_width);
  2126. return ERROR_FLASH_OPERATION_FAILED;
  2127. }
  2128. LOG_INFO("Flash Manufacturer/Device: 0x%04x 0x%04x",
  2129. cfi_info->manufacturer, cfi_info->device_id);
  2130. /* switch back to read array mode */
  2131. if ((retval = cfi_reset(bank)) != ERROR_OK)
  2132. {
  2133. return retval;
  2134. }
  2135. /* check device/manufacturer ID for known non-CFI flashes. */
  2136. cfi_fixup_non_cfi(bank);
  2137. /* query only if this is a CFI compatible flash,
  2138. * otherwise the relevant info has already been filled in
  2139. */
  2140. if (cfi_info->not_cfi == 0)
  2141. {
  2142. /* enter CFI query mode
  2143. * according to JEDEC Standard No. 68.01,
  2144. * a single bus sequence with address = 0x55, data = 0x98 should put
  2145. * the device into CFI query mode.
  2146. *
  2147. * SST flashes clearly violate this, and we will consider them incompatbile for now
  2148. */
  2149. retval = cfi_query_string(bank, 0x55);
  2150. if (retval != ERROR_OK)
  2151. {
  2152. /*
  2153. * Spansion S29WS-N CFI query fix is to try 0x555 if 0x55 fails. Should
  2154. * be harmless enough:
  2155. *
  2156. * http://www.infradead.org/pipermail/linux-mtd/2005-September/013618.html
  2157. */
  2158. LOG_USER("Try workaround w/0x555 instead of 0x55 to get QRY.");
  2159. retval = cfi_query_string(bank, 0x555);
  2160. }
  2161. if (retval != ERROR_OK)
  2162. return retval;
  2163. retval = cfi_query_u16(bank, 0, 0x13, &cfi_info->pri_id);
  2164. if (retval != ERROR_OK)
  2165. return retval;
  2166. retval = cfi_query_u16(bank, 0, 0x15, &cfi_info->pri_addr);
  2167. if (retval != ERROR_OK)
  2168. return retval;
  2169. retval = cfi_query_u16(bank, 0, 0x17, &cfi_info->alt_id);
  2170. if (retval != ERROR_OK)
  2171. return retval;
  2172. retval = cfi_query_u16(bank, 0, 0x19, &cfi_info->alt_addr);
  2173. if (retval != ERROR_OK)
  2174. return retval;
  2175. LOG_DEBUG("qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: "
  2176. "0x%4.4x, alt_addr: 0x%4.4x", cfi_info->qry[0], cfi_info->qry[1],
  2177. cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr,
  2178. cfi_info->alt_id, cfi_info->alt_addr);
  2179. retval = cfi_query_u8(bank, 0, 0x1b, &cfi_info->vcc_min);
  2180. if (retval != ERROR_OK)
  2181. return retval;
  2182. retval = cfi_query_u8(bank, 0, 0x1c, &cfi_info->vcc_max);
  2183. if (retval != ERROR_OK)
  2184. return retval;
  2185. retval = cfi_query_u8(bank, 0, 0x1d, &cfi_info->vpp_min);
  2186. if (retval != ERROR_OK)
  2187. return retval;
  2188. retval = cfi_query_u8(bank, 0, 0x1e, &cfi_info->vpp_max);
  2189. if (retval != ERROR_OK)
  2190. return retval;
  2191. retval = cfi_query_u8(bank, 0, 0x1f, &cfi_info->word_write_timeout_typ);
  2192. if (retval != ERROR_OK)
  2193. return retval;
  2194. retval = cfi_query_u8(bank, 0, 0x20, &cfi_info->buf_write_timeout_typ);
  2195. if (retval != ERROR_OK)
  2196. return retval;
  2197. retval = cfi_query_u8(bank, 0, 0x21, &cfi_info->block_erase_timeout_typ);
  2198. if (retval != ERROR_OK)
  2199. return retval;
  2200. retval = cfi_query_u8(bank, 0, 0x22, &cfi_info->chip_erase_timeout_typ);
  2201. if (retval != ERROR_OK)
  2202. return retval;
  2203. retval = cfi_query_u8(bank, 0, 0x23, &cfi_info->word_write_timeout_max);
  2204. if (retval != ERROR_OK)
  2205. return retval;
  2206. retval = cfi_query_u8(bank, 0, 0x24, &cfi_info->buf_write_timeout_max);
  2207. if (retval != ERROR_OK)
  2208. return retval;
  2209. retval = cfi_query_u8(bank, 0, 0x25, &cfi_info->block_erase_timeout_max);
  2210. if (retval != ERROR_OK)
  2211. return retval;
  2212. retval = cfi_query_u8(bank, 0, 0x26, &cfi_info->chip_erase_timeout_max);
  2213. if (retval != ERROR_OK)
  2214. return retval;
  2215. LOG_DEBUG("Vcc min: %x.%x, Vcc max: %x.%x, Vpp min: %u.%x, Vpp max: %u.%x",
  2216. (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
  2217. (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
  2218. (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
  2219. (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
  2220. LOG_DEBUG("typ. word write timeout: %u us, typ. buf write timeout: %u us, "
  2221. "typ. block erase timeout: %u ms, typ. chip erase timeout: %u ms",
  2222. 1 << cfi_info->word_write_timeout_typ, 1 << cfi_info->buf_write_timeout_typ,
  2223. 1 << cfi_info->block_erase_timeout_typ, 1 << cfi_info->chip_erase_timeout_typ);
  2224. LOG_DEBUG("max. word write timeout: %u us, max. buf write timeout: %u us, "
  2225. "max. block erase timeout: %u ms, max. chip erase timeout: %u ms",
  2226. (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
  2227. (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
  2228. (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
  2229. (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
  2230. /* convert timeouts to real values in ms */
  2231. cfi_info->word_write_timeout = DIV_ROUND_UP((1 << cfi_info->word_write_timeout_typ) *
  2232. (1 << cfi_info->word_write_timeout_max), 1000);
  2233. cfi_info->buf_write_timeout = DIV_ROUND_UP((1 << cfi_info->buf_write_timeout_typ) *
  2234. (1 << cfi_info->buf_write_timeout_max), 1000);
  2235. cfi_info->block_erase_timeout = (1 << cfi_info->block_erase_timeout_typ) *
  2236. (1 << cfi_info->block_erase_timeout_max);
  2237. cfi_info->chip_erase_timeout = (1 << cfi_info->chip_erase_timeout_typ) *
  2238. (1 << cfi_info->chip_erase_timeout_max);
  2239. LOG_DEBUG("calculated word write timeout: %u ms, buf write timeout: %u ms, "
  2240. "block erase timeout: %u ms, chip erase timeout: %u ms",
  2241. cfi_info->word_write_timeout, cfi_info->buf_write_timeout,
  2242. cfi_info->block_erase_timeout, cfi_info->chip_erase_timeout);
  2243. uint8_t data;
  2244. retval = cfi_query_u8(bank, 0, 0x27, &data);
  2245. if (retval != ERROR_OK)
  2246. return retval;
  2247. cfi_info->dev_size = 1 << data;
  2248. retval = cfi_query_u16(bank, 0, 0x28, &cfi_info->interface_desc);
  2249. if (retval != ERROR_OK)
  2250. return retval;
  2251. retval = cfi_query_u16(bank, 0, 0x2a, &cfi_info->max_buf_write_size);
  2252. if (retval != ERROR_OK)
  2253. return retval;
  2254. retval = cfi_query_u8(bank, 0, 0x2c, &cfi_info->num_erase_regions);
  2255. if (retval != ERROR_OK)
  2256. return retval;
  2257. LOG_DEBUG("size: 0x%" PRIx32 ", interface desc: %i, max buffer write size: 0x%x",
  2258. cfi_info->dev_size, cfi_info->interface_desc, (1 << cfi_info->max_buf_write_size));
  2259. if (cfi_info->num_erase_regions)
  2260. {
  2261. cfi_info->erase_region_info = malloc(sizeof(*cfi_info->erase_region_info)
  2262. * cfi_info->num_erase_regions);
  2263. for (i = 0; i < cfi_info->num_erase_regions; i++)
  2264. {
  2265. retval = cfi_query_u32(bank, 0, 0x2d + (4 * i), &cfi_info->erase_region_info[i]);
  2266. if (retval != ERROR_OK)
  2267. return retval;
  2268. LOG_DEBUG("erase region[%i]: %" PRIu32 " blocks of size 0x%" PRIx32 "", i,
  2269. (cfi_info->erase_region_info[i] & 0xffff) + 1,
  2270. (cfi_info->erase_region_info[i] >> 16) * 256);
  2271. }
  2272. }
  2273. else
  2274. {
  2275. cfi_info->erase_region_info = NULL;
  2276. }
  2277. /* We need to read the primary algorithm extended query table before calculating
  2278. * the sector layout to be able to apply fixups
  2279. */
  2280. switch (cfi_info->pri_id)
  2281. {
  2282. /* Intel command set (standard and extended) */
  2283. case 0x0001:
  2284. case 0x0003:
  2285. cfi_read_intel_pri_ext(bank);
  2286. break;
  2287. /* AMD/Spansion, Atmel, ... command set */
  2288. case 0x0002:
  2289. cfi_info->status_poll_mask = CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7; /* default for all CFI flashs */
  2290. cfi_read_0002_pri_ext(bank);
  2291. break;
  2292. default:
  2293. LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
  2294. break;
  2295. }
  2296. /* return to read array mode
  2297. * we use both reset commands, as some Intel flashes fail to recognize the 0xF0 command
  2298. */
  2299. if ((retval = cfi_reset(bank)) != ERROR_OK)
  2300. {
  2301. return retval;
  2302. }
  2303. } /* end CFI case */
  2304. /* apply fixups depending on the primary command set */
  2305. switch (cfi_info->pri_id)
  2306. {
  2307. /* Intel command set (standard and extended) */
  2308. case 0x0001:
  2309. case 0x0003:
  2310. cfi_fixup(bank, cfi_0001_fixups);
  2311. break;
  2312. /* AMD/Spansion, Atmel, ... command set */
  2313. case 0x0002:
  2314. cfi_fixup(bank, cfi_0002_fixups);
  2315. break;
  2316. default:
  2317. LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
  2318. break;
  2319. }
  2320. if ((cfi_info->dev_size * bank->bus_width / bank->chip_width) != bank->size)
  2321. {
  2322. LOG_WARNING("configuration specifies 0x%" PRIx32 " size, but a 0x%" PRIx32
  2323. " size flash was found", bank->size, cfi_info->dev_size);
  2324. }
  2325. if (cfi_info->num_erase_regions == 0)
  2326. {
  2327. /* a device might have only one erase block, spanning the whole device */
  2328. bank->num_sectors = 1;
  2329. bank->sectors = malloc(sizeof(struct flash_sector));
  2330. bank->sectors[sector].offset = 0x0;
  2331. bank->sectors[sector].size = bank->size;
  2332. bank->sectors[sector].is_erased = -1;
  2333. bank->sectors[sector].is_protected = -1;
  2334. }
  2335. else
  2336. {
  2337. uint32_t offset = 0;
  2338. for (i = 0; i < cfi_info->num_erase_regions; i++)
  2339. {
  2340. num_sectors += (cfi_info->erase_region_info[i] & 0xffff) + 1;
  2341. }
  2342. bank->num_sectors = num_sectors;
  2343. bank->sectors = malloc(sizeof(struct flash_sector) * num_sectors);
  2344. for (i = 0; i < cfi_info->num_erase_regions; i++)
  2345. {
  2346. uint32_t j;
  2347. for (j = 0; j < (cfi_info->erase_region_info[i] & 0xffff) + 1; j++)
  2348. {
  2349. bank->sectors[sector].offset = offset;
  2350. bank->sectors[sector].size = ((cfi_info->erase_region_info[i] >> 16) * 256)
  2351. * bank->bus_width / bank->chip_width;
  2352. offset += bank->sectors[sector].size;
  2353. bank->sectors[sector].is_erased = -1;
  2354. bank->sectors[sector].is_protected = -1;
  2355. sector++;
  2356. }
  2357. }
  2358. if (offset != (cfi_info->dev_size * bank->bus_width / bank->chip_width))
  2359. {
  2360. LOG_WARNING("CFI size is 0x%" PRIx32 ", but total sector size is 0x%" PRIx32 "", \
  2361. (cfi_info->dev_size * bank->bus_width / bank->chip_width), offset);
  2362. }
  2363. }
  2364. cfi_info->probed = 1;
  2365. return ERROR_OK;
  2366. }
  2367. static int cfi_auto_probe(struct flash_bank *bank)
  2368. {
  2369. struct cfi_flash_bank *cfi_info = bank->driver_priv;
  2370. if (cfi_info->probed)
  2371. return ERROR_OK;
  2372. return cfi_probe(bank);
  2373. }
  2374. static int cfi_intel_protect_check(struct flash_bank *bank)
  2375. {
  2376. int retval;
  2377. struct cfi_flash_bank *cfi_info = bank->driver_priv;
  2378. struct cfi_intel_pri_ext *pri_ext = cfi_info->pri_ext;
  2379. int i;
  2380. /* check if block lock bits are supported on this device */
  2381. if (!(pri_ext->blk_status_reg_mask & 0x1))
  2382. return ERROR_FLASH_OPERATION_FAILED;
  2383. if ((retval = cfi_send_command(bank, 0x90, flash_address(bank, 0, 0x55))) != ERROR_OK)
  2384. {
  2385. return retval;
  2386. }
  2387. for (i = 0; i < bank->num_sectors; i++)
  2388. {
  2389. uint8_t block_status;
  2390. retval = cfi_get_u8(bank, i, 0x2, &block_status);
  2391. if (retval != ERROR_OK)
  2392. return retval;
  2393. if (block_status & 1)
  2394. bank->sectors[i].is_protected = 1;
  2395. else
  2396. bank->sectors[i].is_protected = 0;
  2397. }
  2398. return cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0));
  2399. }
  2400. static int cfi_spansion_protect_check(struct flash_bank *bank)
  2401. {
  2402. int retval;
  2403. struct cfi_flash_bank *cfi_info = bank->driver_priv;
  2404. struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
  2405. int i;
  2406. if ((retval = cfi_send_command(bank, 0xaa,
  2407. flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
  2408. {
  2409. return retval;
  2410. }
  2411. if ((retval = cfi_send_command(bank, 0x55,
  2412. flash_address(bank, 0, pri_ext->_unlock2))) != ERROR_OK)
  2413. {
  2414. return retval;
  2415. }
  2416. if ((retval = cfi_send_command(bank, 0x90,
  2417. flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
  2418. {
  2419. return retval;
  2420. }
  2421. for (i = 0; i < bank->num_sectors; i++)
  2422. {
  2423. uint8_t block_status;
  2424. retval = cfi_get_u8(bank, i, 0x2, &block_status);
  2425. if (retval != ERROR_OK)
  2426. return retval;
  2427. if (block_status & 1)
  2428. bank->sectors[i].is_protected = 1;
  2429. else
  2430. bank->sectors[i].is_protected = 0;
  2431. }
  2432. return cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0));
  2433. }
  2434. static int cfi_protect_check(struct flash_bank *bank)
  2435. {
  2436. struct cfi_flash_bank *cfi_info = bank->driver_priv;
  2437. if (bank->target->state != TARGET_HALTED)
  2438. {
  2439. LOG_ERROR("Target not halted");
  2440. return ERROR_TARGET_NOT_HALTED;
  2441. }
  2442. if (cfi_info->qry[0] != 'Q')
  2443. return ERROR_FLASH_BANK_NOT_PROBED;
  2444. switch (cfi_info->pri_id)
  2445. {
  2446. case 1:
  2447. case 3:
  2448. return cfi_intel_protect_check(bank);
  2449. break;
  2450. case 2:
  2451. return cfi_spansion_protect_check(bank);
  2452. break;
  2453. default:
  2454. LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
  2455. break;
  2456. }
  2457. return ERROR_OK;
  2458. }
  2459. static int get_cfi_info(struct flash_bank *bank, char *buf, int buf_size)
  2460. {
  2461. int printed;
  2462. struct cfi_flash_bank *cfi_info = bank->driver_priv;
  2463. if (cfi_info->qry[0] == 0xff)
  2464. {
  2465. printed = snprintf(buf, buf_size, "\ncfi flash bank not probed yet\n");
  2466. return ERROR_OK;
  2467. }
  2468. if (cfi_info->not_cfi == 0)
  2469. printed = snprintf(buf, buf_size, "\ncfi information:\n");
  2470. else
  2471. printed = snprintf(buf, buf_size, "\nnon-cfi flash:\n");
  2472. buf += printed;
  2473. buf_size -= printed;
  2474. printed = snprintf(buf, buf_size, "\nmfr: 0x%4.4x, id:0x%4.4x\n",
  2475. cfi_info->manufacturer, cfi_info->device_id);
  2476. buf += printed;
  2477. buf_size -= printed;
  2478. if (cfi_info->not_cfi == 0)
  2479. {
  2480. printed = snprintf(buf, buf_size, "qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: "
  2481. "0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x\n",
  2482. cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2],
  2483. cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
  2484. buf += printed;
  2485. buf_size -= printed;
  2486. printed = snprintf(buf, buf_size, "Vcc min: %x.%x, Vcc max: %x.%x, "
  2487. "Vpp min: %u.%x, Vpp max: %u.%x\n",
  2488. (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
  2489. (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
  2490. (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
  2491. (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
  2492. buf += printed;
  2493. buf_size -= printed;
  2494. printed = snprintf(buf, buf_size, "typ. word write timeout: %u us, "
  2495. "typ. buf write timeout: %u us, "
  2496. "typ. block erase timeout: %u ms, "
  2497. "typ. chip erase timeout: %u ms\n",
  2498. 1 << cfi_info->word_write_timeout_typ,
  2499. 1 << cfi_info->buf_write_timeout_typ,
  2500. 1 << cfi_info->block_erase_timeout_typ,
  2501. 1 << cfi_info->chip_erase_timeout_typ);
  2502. buf += printed;
  2503. buf_size -= printed;
  2504. printed = snprintf(buf, buf_size, "max. word write timeout: %u us, "
  2505. "max. buf write timeout: %u us, max. "
  2506. "block erase timeout: %u ms, max. chip erase timeout: %u ms\n",
  2507. (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
  2508. (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
  2509. (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
  2510. (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
  2511. buf += printed;
  2512. buf_size -= printed;
  2513. printed = snprintf(buf, buf_size, "size: 0x%" PRIx32 ", interface desc: %i, "
  2514. "max buffer write size: 0x%x\n",
  2515. cfi_info->dev_size,
  2516. cfi_info->interface_desc,
  2517. 1 << cfi_info->max_buf_write_size);
  2518. buf += printed;
  2519. buf_size -= printed;
  2520. switch (cfi_info->pri_id)
  2521. {
  2522. case 1:
  2523. case 3:
  2524. cfi_intel_info(bank, buf, buf_size);
  2525. break;
  2526. case 2:
  2527. cfi_spansion_info(bank, buf, buf_size);
  2528. break;
  2529. default:
  2530. LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
  2531. break;
  2532. }
  2533. }
  2534. return ERROR_OK;
  2535. }
  2536. static void cfi_fixup_0002_write_buffer(struct flash_bank *bank, void *param)
  2537. {
  2538. struct cfi_flash_bank *cfi_info = bank->driver_priv;
  2539. /* disable write buffer for M29W128G */
  2540. cfi_info->buf_write_timeout_typ = 0;
  2541. }
  2542. struct flash_driver cfi_flash = {
  2543. .name = "cfi",
  2544. .flash_bank_command = cfi_flash_bank_command,
  2545. .erase = cfi_erase,
  2546. .protect = cfi_protect,
  2547. .write = cfi_write,
  2548. .read = cfi_read,
  2549. .probe = cfi_probe,
  2550. .auto_probe = cfi_auto_probe,
  2551. /* FIXME: access flash at bus_width size */
  2552. .erase_check = default_flash_blank_check,
  2553. .protect_check = cfi_protect_check,
  2554. .info = get_cfi_info,
  2555. };