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  1. \input texinfo @c -*-texinfo-*-
  2. @c %**start of header
  3. @setfilename
  4. @settitle OpenOCD User's Guide
  5. @dircategory Development
  6. @direntry
  7. * OpenOCD: (openocd). OpenOCD User's Guide
  8. @end direntry
  9. @paragraphindent 0
  10. @c %**end of header
  11. @include version.texi
  12. @copying
  13. This User's Guide documents
  14. release @value{VERSION},
  15. dated @value{UPDATED},
  16. of the Open On-Chip Debugger (OpenOCD).
  17. @itemize @bullet
  18. @item Copyright @copyright{} 2008 The OpenOCD Project
  19. @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{}
  20. @item Copyright @copyright{} 2008-2010 Oyvind Harboe @email{}
  21. @item Copyright @copyright{} 2008 Duane Ellis @email{}
  22. @item Copyright @copyright{} 2009-2010 David Brownell
  23. @end itemize
  24. @quotation
  25. Permission is granted to copy, distribute and/or modify this document
  26. under the terms of the GNU Free Documentation License, Version 1.2 or
  27. any later version published by the Free Software Foundation; with no
  28. Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
  29. Texts. A copy of the license is included in the section entitled ``GNU
  30. Free Documentation License''.
  31. @end quotation
  32. @end copying
  33. @titlepage
  34. @titlefont{@emph{Open On-Chip Debugger:}}
  35. @sp 1
  36. @title OpenOCD User's Guide
  37. @subtitle for release @value{VERSION}
  38. @subtitle @value{UPDATED}
  39. @page
  40. @vskip 0pt plus 1filll
  41. @insertcopying
  42. @end titlepage
  43. @summarycontents
  44. @contents
  45. @ifnottex
  46. @node Top
  47. @top OpenOCD User's Guide
  48. @insertcopying
  49. @end ifnottex
  50. @menu
  51. * About:: About OpenOCD
  52. * Developers:: OpenOCD Developer Resources
  53. * Debug Adapter Hardware:: Debug Adapter Hardware
  54. * About Jim-Tcl:: About Jim-Tcl
  55. * Running:: Running OpenOCD
  56. * OpenOCD Project Setup:: OpenOCD Project Setup
  57. * Config File Guidelines:: Config File Guidelines
  58. * Daemon Configuration:: Daemon Configuration
  59. * Debug Adapter Configuration:: Debug Adapter Configuration
  60. * Reset Configuration:: Reset Configuration
  61. * TAP Declaration:: TAP Declaration
  62. * CPU Configuration:: CPU Configuration
  63. * Flash Commands:: Flash Commands
  64. * Flash Programming:: Flash Programming
  65. * NAND Flash Commands:: NAND Flash Commands
  66. * PLD/FPGA Commands:: PLD/FPGA Commands
  67. * General Commands:: General Commands
  68. * Architecture and Core Commands:: Architecture and Core Commands
  69. * JTAG Commands:: JTAG Commands
  70. * Boundary Scan Commands:: Boundary Scan Commands
  71. * Utility Commands:: Utility Commands
  72. * TFTP:: TFTP
  73. * GDB and OpenOCD:: Using GDB and OpenOCD
  74. * Tcl Scripting API:: Tcl Scripting API
  75. * FAQ:: Frequently Asked Questions
  76. * Tcl Crash Course:: Tcl Crash Course
  77. * License:: GNU Free Documentation License
  78. @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
  79. @comment case issue with ``Index.html'' and ``index.html''
  80. @comment Occurs when creating ``--html --no-split'' output
  81. @comment This fix is based on:
  82. * OpenOCD Concept Index:: Concept Index
  83. * Command and Driver Index:: Command and Driver Index
  84. @end menu
  85. @node About
  86. @unnumbered About
  87. @cindex about
  88. OpenOCD was created by Dominic Rath as part of a 2005 diploma thesis written
  89. at the University of Applied Sciences Augsburg (@uref{}).
  90. Since that time, the project has grown into an active open-source project,
  91. supported by a diverse community of software and hardware developers from
  92. around the world.
  93. @section What is OpenOCD?
  94. @cindex TAP
  95. @cindex JTAG
  96. The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
  97. in-system programming and boundary-scan testing for embedded target
  98. devices.
  99. It does so with the assistance of a @dfn{debug adapter}, which is
  100. a small hardware module which helps provide the right kind of
  101. electrical signaling to the target being debugged. These are
  102. required since the debug host (on which OpenOCD runs) won't
  103. usually have native support for such signaling, or the connector
  104. needed to hook up to the target.
  105. Such debug adapters support one or more @dfn{transport} protocols,
  106. each of which involves different electrical signaling (and uses
  107. different messaging protocols on top of that signaling). There
  108. are many types of debug adapter, and little uniformity in what
  109. they are called. (There are also product naming differences.)
  110. These adapters are sometimes packaged as discrete dongles, which
  111. may generically be called @dfn{hardware interface dongles}.
  112. Some development boards also integrate them directly, which may
  113. let the development board connect directly to the debug
  114. host over USB (and sometimes also to power it over USB).
  115. For example, a @dfn{JTAG Adapter} supports JTAG
  116. signaling, and is used to communicate
  117. with JTAG (IEEE 1149.1) compliant TAPs on your target board.
  118. A @dfn{TAP} is a ``Test Access Port'', a module which processes
  119. special instructions and data. TAPs are daisy-chained within and
  120. between chips and boards. JTAG supports debugging and boundary
  121. scan operations.
  122. There are also @dfn{SWD Adapters} that support Serial Wire Debug (SWD)
  123. signaling to communicate with some newer ARM cores, as well as debug
  124. adapters which support both JTAG and SWD transports. SWD supports only
  125. debugging, whereas JTAG also supports boundary scan operations.
  126. For some chips, there are also @dfn{Programming Adapters} supporting
  127. special transports used only to write code to flash memory, without
  128. support for on-chip debugging or boundary scan.
  129. (At this writing, OpenOCD does not support such non-debug adapters.)
  130. @b{Dongles:} OpenOCD currently supports many types of hardware dongles:
  131. USB-based, parallel port-based, and other standalone boxes that run
  132. OpenOCD internally. @xref{Debug Adapter Hardware}.
  133. @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
  134. ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x), Cortex-M3
  135. (Stellaris LM3, ST STM32 and Energy Micro EFM32) and Intel Quark (x10xx)
  136. based cores to be debugged via the GDB protocol.
  137. @b{Flash Programming:} Flash writing is supported for external
  138. CFI-compatible NOR flashes (Intel and AMD/Spansion command set) and several
  139. internal flashes (LPC1700, LPC1800, LPC2000, LPC4300, AT91SAM7, AT91SAM3U,
  140. STR7x, STR9x, LM3, STM32x and EFM32). Preliminary support for various NAND flash
  141. controllers (LPC3180, Orion, S3C24xx, more) is included.
  142. @section OpenOCD Web Site
  143. The OpenOCD web site provides the latest public news from the community:
  144. @uref{}
  145. @section Latest User's Guide:
  146. The user's guide you are now reading may not be the latest one
  147. available. A version for more recent code may be available.
  148. Its HTML form is published regularly at:
  149. @uref{}
  150. PDF form is likewise published at:
  151. @uref{}
  152. @section OpenOCD User's Forum
  153. There is an OpenOCD forum (phpBB) hosted by SparkFun,
  154. which might be helpful to you. Note that if you want
  155. anything to come to the attention of developers, you
  156. should post it to the OpenOCD Developer Mailing List
  157. instead of this forum.
  158. @uref{}
  159. @section OpenOCD User's Mailing List
  160. The OpenOCD User Mailing List provides the primary means of
  161. communication between users:
  162. @uref{}
  163. @section OpenOCD IRC
  164. Support can also be found on irc:
  165. @uref{irc://}
  166. @node Developers
  167. @chapter OpenOCD Developer Resources
  168. @cindex developers
  169. If you are interested in improving the state of OpenOCD's debugging and
  170. testing support, new contributions will be welcome. Motivated developers
  171. can produce new target, flash or interface drivers, improve the
  172. documentation, as well as more conventional bug fixes and enhancements.
  173. The resources in this chapter are available for developers wishing to explore
  174. or expand the OpenOCD source code.
  175. @section OpenOCD Git Repository
  176. During the 0.3.x release cycle, OpenOCD switched from Subversion to
  177. a Git repository hosted at SourceForge. The repository URL is:
  178. @uref{git://}
  179. or via http
  180. @uref{}
  181. You may prefer to use a mirror and the HTTP protocol:
  182. @uref{}
  183. With standard Git tools, use @command{git clone} to initialize
  184. a local repository, and @command{git pull} to update it.
  185. There are also gitweb pages letting you browse the repository
  186. with a web browser, or download arbitrary snapshots without
  187. needing a Git client:
  188. @uref{}
  189. The @file{README} file contains the instructions for building the project
  190. from the repository or a snapshot.
  191. Developers that want to contribute patches to the OpenOCD system are
  192. @b{strongly} encouraged to work against mainline.
  193. Patches created against older versions may require additional
  194. work from their submitter in order to be updated for newer releases.
  195. @section Doxygen Developer Manual
  196. During the 0.2.x release cycle, the OpenOCD project began
  197. providing a Doxygen reference manual. This document contains more
  198. technical information about the software internals, development
  199. processes, and similar documentation:
  200. @uref{}
  201. This document is a work-in-progress, but contributions would be welcome
  202. to fill in the gaps. All of the source files are provided in-tree,
  203. listed in the Doxyfile configuration at the top of the source tree.
  204. @section Gerrit Review System
  205. All changes in the OpenOCD Git repository go through the web-based Gerrit
  206. Code Review System:
  207. @uref{}
  208. After a one-time registration and repository setup, anyone can push commits
  209. from their local Git repository directly into Gerrit.
  210. All users and developers are encouraged to review, test, discuss and vote
  211. for changes in Gerrit. The feedback provides the basis for a maintainer to
  212. eventually submit the change to the main Git repository.
  213. The @file{HACKING} file, also available as the Patch Guide in the Doxygen
  214. Developer Manual, contains basic information about how to connect a
  215. repository to Gerrit, prepare and push patches. Patch authors are expected to
  216. maintain their changes while they're in Gerrit, respond to feedback and if
  217. necessary rework and push improved versions of the change.
  218. @section OpenOCD Developer Mailing List
  219. The OpenOCD Developer Mailing List provides the primary means of
  220. communication between developers:
  221. @uref{}
  222. @section OpenOCD Bug Database
  223. During the 0.4.x release cycle the OpenOCD project team began
  224. using Trac for its bug database:
  225. @uref{}
  226. @node Debug Adapter Hardware
  227. @chapter Debug Adapter Hardware
  228. @cindex dongles
  229. @cindex FTDI
  230. @cindex wiggler
  231. @cindex zy1000
  232. @cindex printer port
  233. @cindex USB Adapter
  234. @cindex RTCK
  235. Defined: @b{dongle}: A small device that plugs into a computer and serves as
  236. an adapter .... [snip]
  237. In the OpenOCD case, this generally refers to @b{a small adapter} that
  238. attaches to your computer via USB or the parallel port. One
  239. exception is the Ultimate Solutions ZY1000, packaged as a small box you
  240. attach via an ethernet cable. The ZY1000 has the advantage that it does not
  241. require any drivers to be installed on the developer PC. It also has
  242. a built in web interface. It supports RTCK/RCLK or adaptive clocking
  243. and has a built-in relay to power cycle targets remotely.
  244. @section Choosing a Dongle
  245. There are several things you should keep in mind when choosing a dongle.
  246. @enumerate
  247. @item @b{Transport} Does it support the kind of communication that you need?
  248. OpenOCD focusses mostly on JTAG. Your version may also support
  249. other ways to communicate with target devices.
  250. @item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
  251. Does your dongle support it? You might need a level converter.
  252. @item @b{Pinout} What pinout does your target board use?
  253. Does your dongle support it? You may be able to use jumper
  254. wires, or an "octopus" connector, to convert pinouts.
  255. @item @b{Connection} Does your computer have the USB, parallel, or
  256. Ethernet port needed?
  257. @item @b{RTCK} Do you expect to use it with ARM chips and boards with
  258. RTCK support (also known as ``adaptive clocking'')?
  259. @end enumerate
  260. @section Stand-alone JTAG Probe
  261. The ZY1000 from Ultimate Solutions is technically not a dongle but a
  262. stand-alone JTAG probe that, unlike most dongles, doesn't require any drivers
  263. running on the developer's host computer.
  264. Once installed on a network using DHCP or a static IP assignment, users can
  265. access the ZY1000 probe locally or remotely from any host with access to the
  266. IP address assigned to the probe.
  267. The ZY1000 provides an intuitive web interface with direct access to the
  268. OpenOCD debugger.
  269. Users may also run a GDBSERVER directly on the ZY1000 to take full advantage
  270. of GCC & GDB to debug any distribution of embedded Linux or NetBSD running on
  271. the target.
  272. The ZY1000 supports RTCK & RCLK or adaptive clocking and has a built-in relay
  273. to power cycle the target remotely.
  274. For more information, visit:
  275. @b{ZY1000} See: @url{}
  276. @section USB FT2232 Based
  277. There are many USB JTAG dongles on the market, many of them based
  278. on a chip from ``Future Technology Devices International'' (FTDI)
  279. known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
  280. See: @url{} for more information.
  281. In summer 2009, USB high speed (480 Mbps) versions of these FTDI
  282. chips started to become available in JTAG adapters. Around 2012, a new
  283. variant appeared - FT232H - this is a single-channel version of FT2232H.
  284. (Adapters using those high speed FT2232H or FT232H chips may support adaptive
  285. clocking.)
  286. The FT2232 chips are flexible enough to support some other
  287. transport options, such as SWD or the SPI variants used to
  288. program some chips. They have two communications channels,
  289. and one can be used for a UART adapter at the same time the
  290. other one is used to provide a debug adapter.
  291. Also, some development boards integrate an FT2232 chip to serve as
  292. a built-in low-cost debug adapter and USB-to-serial solution.
  293. @itemize @bullet
  294. @item @b{usbjtag}
  295. @* Link @url{}
  296. @item @b{jtagkey}
  297. @* See: @url{}
  298. @item @b{jtagkey2}
  299. @* See: @url{}
  300. @item @b{oocdlink}
  301. @* See: @url{} By Joern Kaipf
  302. @item @b{signalyzer}
  303. @* See: @url{}
  304. @item @b{Stellaris Eval Boards}
  305. @* See: @url{} - The Stellaris eval boards
  306. bundle FT2232-based JTAG and SWD support, which can be used to debug
  307. the Stellaris chips. Using separate JTAG adapters is optional.
  308. These boards can also be used in a "pass through" mode as JTAG adapters
  309. to other target boards, disabling the Stellaris chip.
  310. @item @b{TI/Luminary ICDI}
  311. @* See: @url{} - TI/Luminary In-Circuit Debug
  312. Interface (ICDI) Boards are included in Stellaris LM3S9B9x
  313. Evaluation Kits. Like the non-detachable FT2232 support on the other
  314. Stellaris eval boards, they can be used to debug other target boards.
  315. @item @b{olimex-jtag}
  316. @* See: @url{}
  317. @item @b{Flyswatter/Flyswatter2}
  318. @* See: @url{}
  319. @item @b{turtelizer2}
  320. @* See:
  321. @uref{, Turtelizer 2}, or
  322. @url{}
  323. @item @b{comstick}
  324. @* Link: @url{}
  325. @item @b{stm32stick}
  326. @* Link @url{}
  327. @item @b{axm0432_jtag}
  328. @* Axiom AXM-0432 Link @url{} - NOTE: This JTAG does not appear
  329. to be available anymore as of April 2012.
  330. @item @b{cortino}
  331. @* Link @url{}
  332. @item @b{dlp-usb1232h}
  333. @* Link @url{}
  334. @item @b{digilent-hs1}
  335. @* Link @url{}
  336. @item @b{opendous}
  337. @* Link @url{} FT2232H-based
  338. (OpenHardware).
  339. @item @b{JTAG-lock-pick Tiny 2}
  340. @* Link @url{} FT232H-based
  341. @item @b{GW16042}
  342. @* Link: @url{}
  343. FT2232H-based
  344. @end itemize
  345. @section USB-JTAG / Altera USB-Blaster compatibles
  346. These devices also show up as FTDI devices, but are not
  347. protocol-compatible with the FT2232 devices. They are, however,
  348. protocol-compatible among themselves. USB-JTAG devices typically consist
  349. of a FT245 followed by a CPLD that understands a particular protocol,
  350. or emulates this protocol using some other hardware.
  351. They may appear under different USB VID/PID depending on the particular
  352. product. The driver can be configured to search for any VID/PID pair
  353. (see the section on driver commands).
  354. @itemize
  355. @item @b{USB-JTAG} Kolja Waschk's USB Blaster-compatible adapter
  356. @* Link: @url{}
  357. @item @b{Altera USB-Blaster}
  358. @* Link: @url{}
  359. @end itemize
  360. @section USB JLINK based
  361. There are several OEM versions of the Segger @b{JLINK} adapter. It is
  362. an example of a micro controller based JTAG adapter, it uses an
  363. AT91SAM764 internally.
  364. @itemize @bullet
  365. @item @b{ATMEL SAMICE} Only works with ATMEL chips!
  366. @* Link: @url{}
  367. @item @b{SEGGER JLINK}
  368. @* Link: @url{}
  369. @item @b{IAR J-Link}
  370. @* Link: @url{}
  371. @end itemize
  372. @section USB RLINK based
  373. Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer,
  374. permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for
  375. SWD and not JTAG, thus not supported.
  376. @itemize @bullet
  377. @item @b{Raisonance RLink}
  378. @* Link: @url{}
  379. @item @b{STM32 Primer}
  380. @* Link: @url{}
  381. @item @b{STM32 Primer2}
  382. @* Link: @url{}
  383. @end itemize
  384. @section USB ST-LINK based
  385. ST Micro has an adapter called @b{ST-LINK}.
  386. They only work with ST Micro chips, notably STM32 and STM8.
  387. @itemize @bullet
  388. @item @b{ST-LINK}
  389. @* This is available standalone and as part of some kits, eg. STM32VLDISCOVERY.
  390. @* Link: @url{}
  391. @item @b{ST-LINK/V2}
  392. @* This is available standalone and as part of some kits, eg. STM32F4DISCOVERY.
  393. @* Link: @url{}
  394. @end itemize
  395. For info the original ST-LINK enumerates using the mass storage usb class; however,
  396. its implementation is completely broken. The result is this causes issues under Linux.
  397. The simplest solution is to get Linux to ignore the ST-LINK using one of the following methods:
  398. @itemize @bullet
  399. @item modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i
  400. @item add "options usb-storage quirks=483:3744:i" to /etc/modprobe.conf
  401. @end itemize
  402. @section USB TI/Stellaris ICDI based
  403. Texas Instruments has an adapter called @b{ICDI}.
  404. It is not to be confused with the FTDI based adapters that were originally fitted to their
  405. evaluation boards. This is the adapter fitted to the Stellaris LaunchPad.
  406. @section USB CMSIS-DAP based
  407. ARM has released a interface standard called CMSIS-DAP that simplifies connecting
  408. debuggers to ARM Cortex based targets @url{}.
  409. @section USB Other
  410. @itemize @bullet
  411. @item @b{USBprog}
  412. @* Link: @url{} - which uses an Atmel MEGA32 and a UBN9604
  413. @item @b{USB - Presto}
  414. @* Link: @url{}
  415. @item @b{Versaloon-Link}
  416. @* Link: @url{}
  417. @item @b{ARM-JTAG-EW}
  418. @* Link: @url{}
  419. @item @b{Buspirate}
  420. @* Link: @url{}
  421. @item @b{opendous}
  422. @* Link: @url{} - which uses an AT90USB162
  423. @item @b{estick}
  424. @* Link: @url{}
  425. @item @b{Keil ULINK v1}
  426. @* Link: @url{}
  427. @end itemize
  428. @section IBM PC Parallel Printer Port Based
  429. The two well-known ``JTAG Parallel Ports'' cables are the Xilinx DLC5
  430. and the Macraigor Wiggler. There are many clones and variations of
  431. these on the market.
  432. Note that parallel ports are becoming much less common, so if you
  433. have the choice you should probably avoid these adapters in favor
  434. of USB-based ones.
  435. @itemize @bullet
  436. @item @b{Wiggler} - There are many clones of this.
  437. @* Link: @url{}
  438. @item @b{DLC5} - From XILINX - There are many clones of this
  439. @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
  440. produced, PDF schematics are easily found and it is easy to make.
  441. @item @b{Amontec - JTAG Accelerator}
  442. @* Link: @url{}
  443. @item @b{Wiggler2}
  444. @* Link: @url{}
  445. @item @b{Wiggler_ntrst_inverted}
  446. @* Yet another variation - See the source code, src/jtag/parport.c
  447. @item @b{old_amt_wiggler}
  448. @* Unknown - probably not on the market today
  449. @item @b{arm-jtag}
  450. @* Link: Most likely @url{} [another wiggler clone]
  451. @item @b{chameleon}
  452. @* Link: @url{}
  453. @item @b{Triton}
  454. @* Unknown.
  455. @item @b{Lattice}
  456. @* ispDownload from Lattice Semiconductor
  457. @url{}
  458. @item @b{flashlink}
  459. @* From ST Microsystems;
  460. @* Link: @url{}
  461. @end itemize
  462. @section Other...
  463. @itemize @bullet
  464. @item @b{ep93xx}
  465. @* An EP93xx based Linux machine using the GPIO pins directly.
  466. @item @b{at91rm9200}
  467. @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
  468. @item @b{bcm2835gpio}
  469. @* A BCM2835-based board (e.g. Raspberry Pi) using the GPIO pins of the expansion header.
  470. @item @b{jtag_vpi}
  471. @* A JTAG driver acting as a client for the JTAG VPI server interface.
  472. @* Link: @url{}
  473. @end itemize
  474. @node About Jim-Tcl
  475. @chapter About Jim-Tcl
  476. @cindex Jim-Tcl
  477. @cindex tcl
  478. OpenOCD uses a small ``Tcl Interpreter'' known as Jim-Tcl.
  479. This programming language provides a simple and extensible
  480. command interpreter.
  481. All commands presented in this Guide are extensions to Jim-Tcl.
  482. You can use them as simple commands, without needing to learn
  483. much of anything about Tcl.
  484. Alternatively, you can write Tcl programs with them.
  485. You can learn more about Jim at its website, @url{}.
  486. There is an active and responsive community, get on the mailing list
  487. if you have any questions. Jim-Tcl maintainers also lurk on the
  488. OpenOCD mailing list.
  489. @itemize @bullet
  490. @item @b{Jim vs. Tcl}
  491. @* Jim-Tcl is a stripped down version of the well known Tcl language,
  492. which can be found here: @url{}. Jim-Tcl has far
  493. fewer features. Jim-Tcl is several dozens of .C files and .H files and
  494. implements the basic Tcl command set. In contrast: Tcl 8.6 is a
  495. 4.2 MB .zip file containing 1540 files.
  496. @item @b{Missing Features}
  497. @* Our practice has been: Add/clone the real Tcl feature if/when
  498. needed. We welcome Jim-Tcl improvements, not bloat. Also there
  499. are a large number of optional Jim-Tcl features that are not
  500. enabled in OpenOCD.
  501. @item @b{Scripts}
  502. @* OpenOCD configuration scripts are Jim-Tcl Scripts. OpenOCD's
  503. command interpreter today is a mixture of (newer)
  504. Jim-Tcl commands, and the (older) original command interpreter.
  505. @item @b{Commands}
  506. @* At the OpenOCD telnet command line (or via the GDB monitor command) one
  507. can type a Tcl for() loop, set variables, etc.
  508. Some of the commands documented in this guide are implemented
  509. as Tcl scripts, from a @file{startup.tcl} file internal to the server.
  510. @item @b{Historical Note}
  511. @* Jim-Tcl was introduced to OpenOCD in spring 2008. Fall 2010,
  512. before OpenOCD 0.5 release, OpenOCD switched to using Jim-Tcl
  513. as a Git submodule, which greatly simplified upgrading Jim-Tcl
  514. to benefit from new features and bugfixes in Jim-Tcl.
  515. @item @b{Need a crash course in Tcl?}
  516. @*@xref{Tcl Crash Course}.
  517. @end itemize
  518. @node Running
  519. @chapter Running
  520. @cindex command line options
  521. @cindex logfile
  522. @cindex directory search
  523. Properly installing OpenOCD sets up your operating system to grant it access
  524. to the debug adapters. On Linux, this usually involves installing a file
  525. in @file{/etc/udev/rules.d,} so OpenOCD has permissions. An example rules file
  526. that works for many common adapters is shipped with OpenOCD in the
  527. @file{contrib} directory. MS-Windows needs
  528. complex and confusing driver configuration for every peripheral. Such issues
  529. are unique to each operating system, and are not detailed in this User's Guide.
  530. Then later you will invoke the OpenOCD server, with various options to
  531. tell it how each debug session should work.
  532. The @option{--help} option shows:
  533. @verbatim
  534. bash$ openocd --help
  535. --help | -h display this help
  536. --version | -v display OpenOCD version
  537. --file | -f use configuration file <name>
  538. --search | -s dir to search for config files and scripts
  539. --debug | -d set debug level <0-3>
  540. --log_output | -l redirect log output to file <name>
  541. --command | -c run <command>
  542. @end verbatim
  543. If you don't give any @option{-f} or @option{-c} options,
  544. OpenOCD tries to read the configuration file @file{openocd.cfg}.
  545. To specify one or more different
  546. configuration files, use @option{-f} options. For example:
  547. @example
  548. openocd -f config1.cfg -f config2.cfg -f config3.cfg
  549. @end example
  550. Configuration files and scripts are searched for in
  551. @enumerate
  552. @item the current directory,
  553. @item any search dir specified on the command line using the @option{-s} option,
  554. @item any search dir specified using the @command{add_script_search_dir} command,
  555. @item @file{$HOME/.openocd} (not on Windows),
  556. @item the site wide script library @file{$pkgdatadir/site} and
  557. @item the OpenOCD-supplied script library @file{$pkgdatadir/scripts}.
  558. @end enumerate
  559. The first found file with a matching file name will be used.
  560. @quotation Note
  561. Don't try to use configuration script names or paths which
  562. include the "#" character. That character begins Tcl comments.
  563. @end quotation
  564. @section Simple setup, no customization
  565. In the best case, you can use two scripts from one of the script
  566. libraries, hook up your JTAG adapter, and start the server ... and
  567. your JTAG setup will just work "out of the box". Always try to
  568. start by reusing those scripts, but assume you'll need more
  569. customization even if this works. @xref{OpenOCD Project Setup}.
  570. If you find a script for your JTAG adapter, and for your board or
  571. target, you may be able to hook up your JTAG adapter then start
  572. the server with some variation of one of the following:
  573. @example
  574. openocd -f interface/ADAPTER.cfg -f board/MYBOARD.cfg
  575. openocd -f interface/ftdi/ADAPTER.cfg -f board/MYBOARD.cfg
  576. @end example
  577. You might also need to configure which reset signals are present,
  578. using @option{-c 'reset_config trst_and_srst'} or something similar.
  579. If all goes well you'll see output something like
  580. @example
  581. Open On-Chip Debugger 0.4.0 (2010-01-14-15:06)
  582. For bug reports, read
  584. Info : JTAG tap: lm3s.cpu tap/device found: 0x3ba00477
  585. (mfg: 0x23b, part: 0xba00, ver: 0x3)
  586. @end example
  587. Seeing that "tap/device found" message, and no warnings, means
  588. the JTAG communication is working. That's a key milestone, but
  589. you'll probably need more project-specific setup.
  590. @section What OpenOCD does as it starts
  591. OpenOCD starts by processing the configuration commands provided
  592. on the command line or, if there were no @option{-c command} or
  593. @option{-f file.cfg} options given, in @file{openocd.cfg}.
  594. @xref{configurationstage,,Configuration Stage}.
  595. At the end of the configuration stage it verifies the JTAG scan
  596. chain defined using those commands; your configuration should
  597. ensure that this always succeeds.
  598. Normally, OpenOCD then starts running as a daemon.
  599. Alternatively, commands may be used to terminate the configuration
  600. stage early, perform work (such as updating some flash memory),
  601. and then shut down without acting as a daemon.
  602. Once OpenOCD starts running as a daemon, it waits for connections from
  603. clients (Telnet, GDB, Other) and processes the commands issued through
  604. those channels.
  605. If you are having problems, you can enable internal debug messages via
  606. the @option{-d} option.
  607. Also it is possible to interleave Jim-Tcl commands w/config scripts using the
  608. @option{-c} command line switch.
  609. To enable debug output (when reporting problems or working on OpenOCD
  610. itself), use the @option{-d} command line switch. This sets the
  611. @option{debug_level} to "3", outputting the most information,
  612. including debug messages. The default setting is "2", outputting only
  613. informational messages, warnings and errors. You can also change this
  614. setting from within a telnet or gdb session using @command{debug_level<n>}
  615. (@pxref{debuglevel,,debug_level}).
  616. You can redirect all output from the daemon to a file using the
  617. @option{-l <logfile>} switch.
  618. Note! OpenOCD will launch the GDB & telnet server even if it can not
  619. establish a connection with the target. In general, it is possible for
  620. the JTAG controller to be unresponsive until the target is set up
  621. correctly via e.g. GDB monitor commands in a GDB init script.
  622. @node OpenOCD Project Setup
  623. @chapter OpenOCD Project Setup
  624. To use OpenOCD with your development projects, you need to do more than
  625. just connect the JTAG adapter hardware (dongle) to your development board
  626. and start the OpenOCD server.
  627. You also need to configure your OpenOCD server so that it knows
  628. about your adapter and board, and helps your work.
  629. You may also want to connect OpenOCD to GDB, possibly
  630. using Eclipse or some other GUI.
  631. @section Hooking up the JTAG Adapter
  632. Today's most common case is a dongle with a JTAG cable on one side
  633. (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
  634. and a USB cable on the other.
  635. Instead of USB, some cables use Ethernet;
  636. older ones may use a PC parallel port, or even a serial port.
  637. @enumerate
  638. @item @emph{Start with power to your target board turned off},
  639. and nothing connected to your JTAG adapter.
  640. If you're particularly paranoid, unplug power to the board.
  641. It's important to have the ground signal properly set up,
  642. unless you are using a JTAG adapter which provides
  643. galvanic isolation between the target board and the
  644. debugging host.
  645. @item @emph{Be sure it's the right kind of JTAG connector.}
  646. If your dongle has a 20-pin ARM connector, you need some kind
  647. of adapter (or octopus, see below) to hook it up to
  648. boards using 14-pin or 10-pin connectors ... or to 20-pin
  649. connectors which don't use ARM's pinout.
  650. In the same vein, make sure the voltage levels are compatible.
  651. Not all JTAG adapters have the level shifters needed to work
  652. with 1.2 Volt boards.
  653. @item @emph{Be certain the cable is properly oriented} or you might
  654. damage your board. In most cases there are only two possible
  655. ways to connect the cable.
  656. Connect the JTAG cable from your adapter to the board.
  657. Be sure it's firmly connected.
  658. In the best case, the connector is keyed to physically
  659. prevent you from inserting it wrong.
  660. This is most often done using a slot on the board's male connector
  661. housing, which must match a key on the JTAG cable's female connector.
  662. If there's no housing, then you must look carefully and
  663. make sure pin 1 on the cable hooks up to pin 1 on the board.
  664. Ribbon cables are frequently all grey except for a wire on one
  665. edge, which is red. The red wire is pin 1.
  666. Sometimes dongles provide cables where one end is an ``octopus'' of
  667. color coded single-wire connectors, instead of a connector block.
  668. These are great when converting from one JTAG pinout to another,
  669. but are tedious to set up.
  670. Use these with connector pinout diagrams to help you match up the
  671. adapter signals to the right board pins.
  672. @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
  673. A USB, parallel, or serial port connector will go to the host which
  674. you are using to run OpenOCD.
  675. For Ethernet, consult the documentation and your network administrator.
  676. For USB-based JTAG adapters you have an easy sanity check at this point:
  677. does the host operating system see the JTAG adapter? If you're running
  678. Linux, try the @command{lsusb} command. If that host is an
  679. MS-Windows host, you'll need to install a driver before OpenOCD works.
  680. @item @emph{Connect the adapter's power supply, if needed.}
  681. This step is primarily for non-USB adapters,
  682. but sometimes USB adapters need extra power.
  683. @item @emph{Power up the target board.}
  684. Unless you just let the magic smoke escape,
  685. you're now ready to set up the OpenOCD server
  686. so you can use JTAG to work with that board.
  687. @end enumerate
  688. Talk with the OpenOCD server using
  689. telnet (@code{telnet localhost 4444} on many systems) or GDB.
  690. @xref{GDB and OpenOCD}.
  691. @section Project Directory
  692. There are many ways you can configure OpenOCD and start it up.
  693. A simple way to organize them all involves keeping a
  694. single directory for your work with a given board.
  695. When you start OpenOCD from that directory,
  696. it searches there first for configuration files, scripts,
  697. files accessed through semihosting,
  698. and for code you upload to the target board.
  699. It is also the natural place to write files,
  700. such as log files and data you download from the board.
  701. @section Configuration Basics
  702. There are two basic ways of configuring OpenOCD, and
  703. a variety of ways you can mix them.
  704. Think of the difference as just being how you start the server:
  705. @itemize
  706. @item Many @option{-f file} or @option{-c command} options on the command line
  707. @item No options, but a @dfn{user config file}
  708. in the current directory named @file{openocd.cfg}
  709. @end itemize
  710. Here is an example @file{openocd.cfg} file for a setup
  711. using a Signalyzer FT2232-based JTAG adapter to talk to
  712. a board with an Atmel AT91SAM7X256 microcontroller:
  713. @example
  714. source [find interface/signalyzer.cfg]
  715. # GDB can also flash my flash!
  716. gdb_memory_map enable
  717. gdb_flash_program enable
  718. source [find target/sam7x256.cfg]
  719. @end example
  720. Here is the command line equivalent of that configuration:
  721. @example
  722. openocd -f interface/signalyzer.cfg \
  723. -c "gdb_memory_map enable" \
  724. -c "gdb_flash_program enable" \
  725. -f target/sam7x256.cfg
  726. @end example
  727. You could wrap such long command lines in shell scripts,
  728. each supporting a different development task.
  729. One might re-flash the board with a specific firmware version.
  730. Another might set up a particular debugging or run-time environment.
  731. @quotation Important
  732. At this writing (October 2009) the command line method has
  733. problems with how it treats variables.
  734. For example, after @option{-c "set VAR value"}, or doing the
  735. same in a script, the variable @var{VAR} will have no value
  736. that can be tested in a later script.
  737. @end quotation
  738. Here we will focus on the simpler solution: one user config
  739. file, including basic configuration plus any TCL procedures
  740. to simplify your work.
  741. @section User Config Files
  742. @cindex config file, user
  743. @cindex user config file
  744. @cindex config file, overview
  745. A user configuration file ties together all the parts of a project
  746. in one place.
  747. One of the following will match your situation best:
  748. @itemize
  749. @item Ideally almost everything comes from configuration files
  750. provided by someone else.
  751. For example, OpenOCD distributes a @file{scripts} directory
  752. (probably in @file{/usr/share/openocd/scripts} on Linux).
  753. Board and tool vendors can provide these too, as can individual
  754. user sites; the @option{-s} command line option lets you say
  755. where to find these files. (@xref{Running}.)
  756. The AT91SAM7X256 example above works this way.
  757. Three main types of non-user configuration file each have their
  758. own subdirectory in the @file{scripts} directory:
  759. @enumerate
  760. @item @b{interface} -- one for each different debug adapter;
  761. @item @b{board} -- one for each different board
  762. @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
  763. @end enumerate
  764. Best case: include just two files, and they handle everything else.
  765. The first is an interface config file.
  766. The second is board-specific, and it sets up the JTAG TAPs and
  767. their GDB targets (by deferring to some @file{target.cfg} file),
  768. declares all flash memory, and leaves you nothing to do except
  769. meet your deadline:
  770. @example
  771. source [find interface/olimex-jtag-tiny.cfg]
  772. source [find board/csb337.cfg]
  773. @end example
  774. Boards with a single microcontroller often won't need more
  775. than the target config file, as in the AT91SAM7X256 example.
  776. That's because there is no external memory (flash, DDR RAM), and
  777. the board differences are encapsulated by application code.
  778. @item Maybe you don't know yet what your board looks like to JTAG.
  779. Once you know the @file{interface.cfg} file to use, you may
  780. need help from OpenOCD to discover what's on the board.
  781. Once you find the JTAG TAPs, you can just search for appropriate
  782. target and board
  783. configuration files ... or write your own, from the bottom up.
  784. @xref{autoprobing,,Autoprobing}.
  785. @item You can often reuse some standard config files but
  786. need to write a few new ones, probably a @file{board.cfg} file.
  787. You will be using commands described later in this User's Guide,
  788. and working with the guidelines in the next chapter.
  789. For example, there may be configuration files for your JTAG adapter
  790. and target chip, but you need a new board-specific config file
  791. giving access to your particular flash chips.
  792. Or you might need to write another target chip configuration file
  793. for a new chip built around the Cortex M3 core.
  794. @quotation Note
  795. When you write new configuration files, please submit
  796. them for inclusion in the next OpenOCD release.
  797. For example, a @file{board/newboard.cfg} file will help the
  798. next users of that board, and a @file{target/newcpu.cfg}
  799. will help support users of any board using that chip.
  800. @end quotation
  801. @item
  802. You may may need to write some C code.
  803. It may be as simple as supporting a new FT2232 or parport
  804. based adapter; a bit more involved, like a NAND or NOR flash
  805. controller driver; or a big piece of work like supporting
  806. a new chip architecture.
  807. @end itemize
  808. Reuse the existing config files when you can.
  809. Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
  810. You may find a board configuration that's a good example to follow.
  811. When you write config files, separate the reusable parts
  812. (things every user of that interface, chip, or board needs)
  813. from ones specific to your environment and debugging approach.
  814. @itemize
  815. @item
  816. For example, a @code{gdb-attach} event handler that invokes
  817. the @command{reset init} command will interfere with debugging
  818. early boot code, which performs some of the same actions
  819. that the @code{reset-init} event handler does.
  820. @item
  821. Likewise, the @command{arm9 vector_catch} command (or
  822. @cindex vector_catch
  823. its siblings @command{xscale vector_catch}
  824. and @command{cortex_m vector_catch}) can be a timesaver
  825. during some debug sessions, but don't make everyone use that either.
  826. Keep those kinds of debugging aids in your user config file,
  827. along with messaging and tracing setup.
  828. (@xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.)
  829. @item
  830. You might need to override some defaults.
  831. For example, you might need to move, shrink, or back up the target's
  832. work area if your application needs much SRAM.
  833. @item
  834. TCP/IP port configuration is another example of something which
  835. is environment-specific, and should only appear in
  836. a user config file. @xref{tcpipports,,TCP/IP Ports}.
  837. @end itemize
  838. @section Project-Specific Utilities
  839. A few project-specific utility
  840. routines may well speed up your work.
  841. Write them, and keep them in your project's user config file.
  842. For example, if you are making a boot loader work on a
  843. board, it's nice to be able to debug the ``after it's
  844. loaded to RAM'' parts separately from the finicky early
  845. code which sets up the DDR RAM controller and clocks.
  846. A script like this one, or a more GDB-aware sibling,
  847. may help:
  848. @example
  849. proc ramboot @{ @} @{
  850. # Reset, running the target's "reset-init" scripts
  851. # to initialize clocks and the DDR RAM controller.
  852. # Leave the CPU halted.
  853. reset init
  854. # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
  855. load_image u-boot.bin 0x20000000
  856. # Start running.
  857. resume 0x20000000
  858. @}
  859. @end example
  860. Then once that code is working you will need to make it
  861. boot from NOR flash; a different utility would help.
  862. Alternatively, some developers write to flash using GDB.
  863. (You might use a similar script if you're working with a flash
  864. based microcontroller application instead of a boot loader.)
  865. @example
  866. proc newboot @{ @} @{
  867. # Reset, leaving the CPU halted. The "reset-init" event
  868. # proc gives faster access to the CPU and to NOR flash;
  869. # "reset halt" would be slower.
  870. reset init
  871. # Write standard version of U-Boot into the first two
  872. # sectors of NOR flash ... the standard version should
  873. # do the same lowlevel init as "reset-init".
  874. flash protect 0 0 1 off
  875. flash erase_sector 0 0 1
  876. flash write_bank 0 u-boot.bin 0x0
  877. flash protect 0 0 1 on
  878. # Reboot from scratch using that new boot loader.
  879. reset run
  880. @}
  881. @end example
  882. You may need more complicated utility procedures when booting
  883. from NAND.
  884. That often involves an extra bootloader stage,
  885. running from on-chip SRAM to perform DDR RAM setup so it can load
  886. the main bootloader code (which won't fit into that SRAM).
  887. Other helper scripts might be used to write production system images,
  888. involving considerably more than just a three stage bootloader.
  889. @section Target Software Changes
  890. Sometimes you may want to make some small changes to the software
  891. you're developing, to help make JTAG debugging work better.
  892. For example, in C or assembly language code you might
  893. use @code{#ifdef JTAG_DEBUG} (or its converse) around code
  894. handling issues like:
  895. @itemize @bullet
  896. @item @b{Watchdog Timers}...
  897. Watchog timers are typically used to automatically reset systems if
  898. some application task doesn't periodically reset the timer. (The
  899. assumption is that the system has locked up if the task can't run.)
  900. When a JTAG debugger halts the system, that task won't be able to run
  901. and reset the timer ... potentially causing resets in the middle of
  902. your debug sessions.
  903. It's rarely a good idea to disable such watchdogs, since their usage
  904. needs to be debugged just like all other parts of your firmware.
  905. That might however be your only option.
  906. Look instead for chip-specific ways to stop the watchdog from counting
  907. while the system is in a debug halt state. It may be simplest to set
  908. that non-counting mode in your debugger startup scripts. You may however
  909. need a different approach when, for example, a motor could be physically
  910. damaged by firmware remaining inactive in a debug halt state. That might
  911. involve a type of firmware mode where that "non-counting" mode is disabled
  912. at the beginning then re-enabled at the end; a watchdog reset might fire
  913. and complicate the debug session, but hardware (or people) would be
  914. protected.@footnote{Note that many systems support a "monitor mode" debug
  915. that is a somewhat cleaner way to address such issues. You can think of
  916. it as only halting part of the system, maybe just one task,
  917. instead of the whole thing.
  918. At this writing, January 2010, OpenOCD based debugging does not support
  919. monitor mode debug, only "halt mode" debug.}
  920. @item @b{ARM Semihosting}...
  921. @cindex ARM semihosting
  922. When linked with a special runtime library provided with many
  923. toolchains@footnote{See chapter 8 "Semihosting" in
  924. @uref{,
  925. ARM DUI 0203I}, the "RealView Compilation Tools Developer Guide".
  926. The CodeSourcery EABI toolchain also includes a semihosting library.},
  927. your target code can use I/O facilities on the debug host. That library
  928. provides a small set of system calls which are handled by OpenOCD.
  929. It can let the debugger provide your system console and a file system,
  930. helping with early debugging or providing a more capable environment
  931. for sometimes-complex tasks like installing system firmware onto
  932. NAND or SPI flash.
  933. @item @b{ARM Wait-For-Interrupt}...
  934. Many ARM chips synchronize the JTAG clock using the core clock.
  935. Low power states which stop that core clock thus prevent JTAG access.
  936. Idle loops in tasking environments often enter those low power states
  937. via the @code{WFI} instruction (or its coprocessor equivalent, before ARMv7).
  938. You may want to @emph{disable that instruction} in source code,
  939. or otherwise prevent using that state,
  940. to ensure you can get JTAG access at any time.@footnote{As a more
  941. polite alternative, some processors have special debug-oriented
  942. registers which can be used to change various features including
  943. how the low power states are clocked while debugging.
  944. The STM32 DBGMCU_CR register is an example; at the cost of extra
  945. power consumption, JTAG can be used during low power states.}
  946. For example, the OpenOCD @command{halt} command may not
  947. work for an idle processor otherwise.
  948. @item @b{Delay after reset}...
  949. Not all chips have good support for debugger access
  950. right after reset; many LPC2xxx chips have issues here.
  951. Similarly, applications that reconfigure pins used for
  952. JTAG access as they start will also block debugger access.
  953. To work with boards like this, @emph{enable a short delay loop}
  954. the first thing after reset, before "real" startup activities.
  955. For example, one second's delay is usually more than enough
  956. time for a JTAG debugger to attach, so that
  957. early code execution can be debugged
  958. or firmware can be replaced.
  959. @item @b{Debug Communications Channel (DCC)}...
  960. Some processors include mechanisms to send messages over JTAG.
  961. Many ARM cores support these, as do some cores from other vendors.
  962. (OpenOCD may be able to use this DCC internally, speeding up some
  963. operations like writing to memory.)
  964. Your application may want to deliver various debugging messages
  965. over JTAG, by @emph{linking with a small library of code}
  966. provided with OpenOCD and using the utilities there to send
  967. various kinds of message.
  968. @xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.
  969. @end itemize
  970. @section Target Hardware Setup
  971. Chip vendors often provide software development boards which
  972. are highly configurable, so that they can support all options
  973. that product boards may require. @emph{Make sure that any
  974. jumpers or switches match the system configuration you are
  975. working with.}
  976. Common issues include:
  977. @itemize @bullet
  978. @item @b{JTAG setup} ...
  979. Boards may support more than one JTAG configuration.
  980. Examples include jumpers controlling pullups versus pulldowns
  981. on the nTRST and/or nSRST signals, and choice of connectors
  982. (e.g. which of two headers on the base board,
  983. or one from a daughtercard).
  984. For some Texas Instruments boards, you may need to jumper the
  985. EMU0 and EMU1 signals (which OpenOCD won't currently control).
  986. @item @b{Boot Modes} ...
  987. Complex chips often support multiple boot modes, controlled
  988. by external jumpers. Make sure this is set up correctly.
  989. For example many i.MX boards from NXP need to be jumpered
  990. to "ATX mode" to start booting using the on-chip ROM, when
  991. using second stage bootloader code stored in a NAND flash chip.
  992. Such explicit configuration is common, and not limited to
  993. booting from NAND. You might also need to set jumpers to
  994. start booting using code loaded from an MMC/SD card; external
  995. SPI flash; Ethernet, UART, or USB links; NOR flash; OneNAND
  996. flash; some external host; or various other sources.
  997. @item @b{Memory Addressing} ...
  998. Boards which support multiple boot modes may also have jumpers
  999. to configure memory addressing. One board, for example, jumpers
  1000. external chipselect 0 (used for booting) to address either
  1001. a large SRAM (which must be pre-loaded via JTAG), NOR flash,
  1002. or NAND flash. When it's jumpered to address NAND flash, that
  1003. board must also be told to start booting from on-chip ROM.
  1004. Your @file{board.cfg} file may also need to be told this jumper
  1005. configuration, so that it can know whether to declare NOR flash
  1006. using @command{flash bank} or instead declare NAND flash with
  1007. @command{nand device}; and likewise which probe to perform in
  1008. its @code{reset-init} handler.
  1009. A closely related issue is bus width. Jumpers might need to
  1010. distinguish between 8 bit or 16 bit bus access for the flash
  1011. used to start booting.
  1012. @item @b{Peripheral Access} ...
  1013. Development boards generally provide access to every peripheral
  1014. on the chip, sometimes in multiple modes (such as by providing
  1015. multiple audio codec chips).
  1016. This interacts with software
  1017. configuration of pin multiplexing, where for example a
  1018. given pin may be routed either to the MMC/SD controller
  1019. or the GPIO controller. It also often interacts with
  1020. configuration jumpers. One jumper may be used to route
  1021. signals to an MMC/SD card slot or an expansion bus (which
  1022. might in turn affect booting); others might control which
  1023. audio or video codecs are used.
  1024. @end itemize
  1025. Plus you should of course have @code{reset-init} event handlers
  1026. which set up the hardware to match that jumper configuration.
  1027. That includes in particular any oscillator or PLL used to clock
  1028. the CPU, and any memory controllers needed to access external
  1029. memory and peripherals. Without such handlers, you won't be
  1030. able to access those resources without working target firmware
  1031. which can do that setup ... this can be awkward when you're
  1032. trying to debug that target firmware. Even if there's a ROM
  1033. bootloader which handles a few issues, it rarely provides full
  1034. access to all board-specific capabilities.
  1035. @node Config File Guidelines
  1036. @chapter Config File Guidelines
  1037. This chapter is aimed at any user who needs to write a config file,
  1038. including developers and integrators of OpenOCD and any user who
  1039. needs to get a new board working smoothly.
  1040. It provides guidelines for creating those files.
  1041. You should find the following directories under @t{$(INSTALLDIR)/scripts},
  1042. with files including the ones listed here.
  1043. Use them as-is where you can; or as models for new files.
  1044. @itemize @bullet
  1045. @item @file{interface} ...
  1046. These are for debug adapters.
  1047. Files that configure JTAG adapters go here.
  1048. @example
  1049. $ ls interface -R
  1050. interface/:
  1051. altera-usb-blaster.cfg hilscher_nxhx50_re.cfg openocd-usb-hs.cfg
  1052. arm-jtag-ew.cfg hitex_str9-comstick.cfg openrd.cfg
  1053. at91rm9200.cfg icebear.cfg osbdm.cfg
  1054. axm0432.cfg jlink.cfg parport.cfg
  1055. busblaster.cfg jtagkey2.cfg parport_dlc5.cfg
  1056. buspirate.cfg jtagkey2p.cfg redbee-econotag.cfg
  1057. calao-usb-a9260-c01.cfg jtagkey.cfg redbee-usb.cfg
  1058. calao-usb-a9260-c02.cfg jtagkey-tiny.cfg rlink.cfg
  1059. calao-usb-a9260.cfg jtag-lock-pick_tiny_2.cfg sheevaplug.cfg
  1060. chameleon.cfg kt-link.cfg signalyzer.cfg
  1061. cortino.cfg lisa-l.cfg signalyzer-h2.cfg
  1062. digilent-hs1.cfg luminary.cfg signalyzer-h4.cfg
  1063. dlp-usb1232h.cfg luminary-icdi.cfg signalyzer-lite.cfg
  1064. dummy.cfg luminary-lm3s811.cfg stlink-v1.cfg
  1065. estick.cfg minimodule.cfg stlink-v2.cfg
  1066. flashlink.cfg neodb.cfg stm32-stick.cfg
  1067. flossjtag.cfg ngxtech.cfg sysfsgpio-raspberrypi.cfg
  1068. flossjtag-noeeprom.cfg olimex-arm-usb-ocd.cfg ti-icdi.cfg
  1069. flyswatter2.cfg olimex-arm-usb-ocd-h.cfg turtelizer2.cfg
  1070. flyswatter.cfg olimex-arm-usb-tiny-h.cfg ulink.cfg
  1071. ftdi olimex-jtag-tiny.cfg usb-jtag.cfg
  1072. hilscher_nxhx10_etm.cfg oocdlink.cfg usbprog.cfg
  1073. hilscher_nxhx500_etm.cfg opendous.cfg vpaclink.cfg
  1074. hilscher_nxhx500_re.cfg opendous_ftdi.cfg vsllink.cfg
  1075. hilscher_nxhx50_etm.cfg openocd-usb.cfg xds100v2.cfg
  1076. interface/ftdi:
  1077. axm0432.cfg hitex_str9-comstick.cfg olimex-jtag-tiny.cfg
  1078. calao-usb-a9260-c01.cfg icebear.cfg oocdlink.cfg
  1079. calao-usb-a9260-c02.cfg jtagkey2.cfg opendous_ftdi.cfg
  1080. cortino.cfg jtagkey2p.cfg openocd-usb.cfg
  1081. dlp-usb1232h.cfg jtagkey.cfg openocd-usb-hs.cfg
  1082. dp_busblaster.cfg jtag-lock-pick_tiny_2.cfg openrd.cfg
  1083. flossjtag.cfg kt-link.cfg redbee-econotag.cfg
  1084. flossjtag-noeeprom.cfg lisa-l.cfg redbee-usb.cfg
  1085. flyswatter2.cfg luminary.cfg sheevaplug.cfg
  1086. flyswatter.cfg luminary-icdi.cfg signalyzer.cfg
  1087. gw16042.cfg luminary-lm3s811.cfg signalyzer-lite.cfg
  1088. hilscher_nxhx10_etm.cfg minimodule.cfg stm32-stick.cfg
  1089. hilscher_nxhx500_etm.cfg neodb.cfg turtelizer2-revB.cfg
  1090. hilscher_nxhx500_re.cfg ngxtech.cfg turtelizer2-revC.cfg
  1091. hilscher_nxhx50_etm.cfg olimex-arm-usb-ocd.cfg vpaclink.cfg
  1092. hilscher_nxhx50_re.cfg olimex-arm-usb-ocd-h.cfg xds100v2.cfg
  1093. hitex_lpc1768stick.cfg olimex-arm-usb-tiny-h.cfg
  1094. $
  1095. @end example
  1096. @item @file{board} ...
  1097. think Circuit Board, PWA, PCB, they go by many names. Board files
  1098. contain initialization items that are specific to a board.
  1099. They reuse target configuration files, since the same
  1100. microprocessor chips are used on many boards,
  1101. but support for external parts varies widely. For
  1102. example, the SDRAM initialization sequence for the board, or the type
  1103. of external flash and what address it uses. Any initialization
  1104. sequence to enable that external flash or SDRAM should be found in the
  1105. board file. Boards may also contain multiple targets: two CPUs; or
  1106. a CPU and an FPGA.
  1107. @example
  1108. $ ls board
  1109. actux3.cfg lpc1850_spifi_generic.cfg
  1110. am3517evm.cfg lpc4350_spifi_generic.cfg
  1111. arm_evaluator7t.cfg lubbock.cfg
  1112. at91cap7a-stk-sdram.cfg mcb1700.cfg
  1113. at91eb40a.cfg microchip_explorer16.cfg
  1114. at91rm9200-dk.cfg mini2440.cfg
  1115. at91rm9200-ek.cfg mini6410.cfg
  1116. at91sam9261-ek.cfg netgear-dg834v3.cfg
  1117. at91sam9263-ek.cfg olimex_LPC2378STK.cfg
  1118. at91sam9g20-ek.cfg olimex_lpc_h2148.cfg
  1119. atmel_at91sam7s-ek.cfg olimex_sam7_ex256.cfg
  1120. atmel_at91sam9260-ek.cfg olimex_sam9_l9260.cfg
  1121. atmel_at91sam9rl-ek.cfg olimex_stm32_h103.cfg
  1122. atmel_sam3n_ek.cfg olimex_stm32_h107.cfg
  1123. atmel_sam3s_ek.cfg olimex_stm32_p107.cfg
  1124. atmel_sam3u_ek.cfg omap2420_h4.cfg
  1125. atmel_sam3x_ek.cfg open-bldc.cfg
  1126. atmel_sam4s_ek.cfg openrd.cfg
  1127. balloon3-cpu.cfg osk5912.cfg
  1128. colibri.cfg phone_se_j100i.cfg
  1129. crossbow_tech_imote2.cfg phytec_lpc3250.cfg
  1130. csb337.cfg pic-p32mx.cfg
  1131. csb732.cfg propox_mmnet1001.cfg
  1132. da850evm.cfg pxa255_sst.cfg
  1133. digi_connectcore_wi-9c.cfg redbee.cfg
  1134. diolan_lpc4350-db1.cfg rsc-w910.cfg
  1135. dm355evm.cfg sheevaplug.cfg
  1136. dm365evm.cfg smdk6410.cfg
  1137. dm6446evm.cfg spear300evb.cfg
  1138. efikamx.cfg spear300evb_mod.cfg
  1139. eir.cfg spear310evb20.cfg
  1140. ek-lm3s1968.cfg spear310evb20_mod.cfg
  1141. ek-lm3s3748.cfg spear320cpu.cfg
  1142. ek-lm3s6965.cfg spear320cpu_mod.cfg
  1143. ek-lm3s811.cfg steval_pcc010.cfg
  1144. ek-lm3s811-revb.cfg stm320518_eval_stlink.cfg
  1145. ek-lm3s8962.cfg stm32100b_eval.cfg
  1146. ek-lm3s9b9x.cfg stm3210b_eval.cfg
  1147. ek-lm3s9d92.cfg stm3210c_eval.cfg
  1148. ek-lm4f120xl.cfg stm3210e_eval.cfg
  1149. ek-lm4f232.cfg stm3220g_eval.cfg
  1150. embedded-artists_lpc2478-32.cfg stm3220g_eval_stlink.cfg
  1151. ethernut3.cfg stm3241g_eval.cfg
  1152. glyn_tonga2.cfg stm3241g_eval_stlink.cfg
  1153. hammer.cfg stm32f0discovery.cfg
  1154. hilscher_nxdb500sys.cfg stm32f3discovery.cfg
  1155. hilscher_nxeb500hmi.cfg stm32f4discovery.cfg
  1156. hilscher_nxhx10.cfg stm32ldiscovery.cfg
  1157. hilscher_nxhx500.cfg stm32vldiscovery.cfg
  1158. hilscher_nxhx50.cfg str910-eval.cfg
  1159. hilscher_nxsb100.cfg telo.cfg
  1160. hitex_lpc1768stick.cfg ti_am335xevm.cfg
  1161. hitex_lpc2929.cfg ti_beagleboard.cfg
  1162. hitex_stm32-performancestick.cfg ti_beagleboard_xm.cfg
  1163. hitex_str9-comstick.cfg ti_beaglebone.cfg
  1164. iar_lpc1768.cfg ti_blaze.cfg
  1165. iar_str912_sk.cfg ti_pandaboard.cfg
  1166. icnova_imx53_sodimm.cfg ti_pandaboard_es.cfg
  1167. icnova_sam9g45_sodimm.cfg topas910.cfg
  1168. imx27ads.cfg topasa900.cfg
  1169. imx27lnst.cfg twr-k60f120m.cfg
  1170. imx28evk.cfg twr-k60n512.cfg
  1171. imx31pdk.cfg tx25_stk5.cfg
  1172. imx35pdk.cfg tx27_stk5.cfg
  1173. imx53loco.cfg unknown_at91sam9260.cfg
  1174. keil_mcb1700.cfg uptech_2410.cfg
  1175. keil_mcb2140.cfg verdex.cfg
  1176. kwikstik.cfg voipac.cfg
  1177. linksys_nslu2.cfg voltcraft_dso-3062c.cfg
  1178. lisa-l.cfg x300t.cfg
  1179. logicpd_imx27.cfg zy1000.cfg
  1180. $
  1181. @end example
  1182. @item @file{target} ...
  1183. think chip. The ``target'' directory represents the JTAG TAPs
  1184. on a chip
  1185. which OpenOCD should control, not a board. Two common types of targets
  1186. are ARM chips and FPGA or CPLD chips.
  1187. When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
  1188. the target config file defines all of them.
  1189. @example
  1190. $ ls target
  1191. aduc702x.cfg lpc1763.cfg
  1192. am335x.cfg lpc1764.cfg
  1193. amdm37x.cfg lpc1765.cfg
  1194. ar71xx.cfg lpc1766.cfg
  1195. at32ap7000.cfg lpc1767.cfg
  1196. at91r40008.cfg lpc1768.cfg
  1197. at91rm9200.cfg lpc1769.cfg
  1198. at91sam3ax_4x.cfg lpc1788.cfg
  1199. at91sam3ax_8x.cfg lpc17xx.cfg
  1200. at91sam3ax_xx.cfg lpc1850.cfg
  1201. at91sam3nXX.cfg lpc2103.cfg
  1202. at91sam3sXX.cfg lpc2124.cfg
  1203. at91sam3u1c.cfg lpc2129.cfg
  1204. at91sam3u1e.cfg lpc2148.cfg
  1205. at91sam3u2c.cfg lpc2294.cfg
  1206. at91sam3u2e.cfg lpc2378.cfg
  1207. at91sam3u4c.cfg lpc2460.cfg
  1208. at91sam3u4e.cfg lpc2478.cfg
  1209. at91sam3uxx.cfg lpc2900.cfg
  1210. at91sam3XXX.cfg lpc2xxx.cfg
  1211. at91sam4sd32x.cfg lpc3131.cfg
  1212. at91sam4sXX.cfg lpc3250.cfg
  1213. at91sam4XXX.cfg lpc4350.cfg
  1214. at91sam7se512.cfg lpc4350.cfg.orig
  1215. at91sam7sx.cfg mc13224v.cfg
  1216. at91sam7x256.cfg nuc910.cfg
  1217. at91sam7x512.cfg omap2420.cfg
  1218. at91sam9260.cfg omap3530.cfg
  1219. at91sam9260_ext_RAM_ext_flash.cfg omap4430.cfg
  1220. at91sam9261.cfg omap4460.cfg
  1221. at91sam9263.cfg omap5912.cfg
  1222. at91sam9.cfg omapl138.cfg
  1223. at91sam9g10.cfg pic32mx.cfg
  1224. at91sam9g20.cfg pxa255.cfg
  1225. at91sam9g45.cfg pxa270.cfg
  1226. at91sam9rl.cfg pxa3xx.cfg
  1227. atmega128.cfg readme.txt
  1228. avr32.cfg samsung_s3c2410.cfg
  1229. c100.cfg samsung_s3c2440.cfg
  1230. c100config.tcl samsung_s3c2450.cfg
  1231. c100helper.tcl samsung_s3c4510.cfg
  1232. c100regs.tcl samsung_s3c6410.cfg
  1233. cs351x.cfg sharp_lh79532.cfg
  1234. davinci.cfg smp8634.cfg
  1235. dragonite.cfg spear3xx.cfg
  1236. dsp56321.cfg stellaris.cfg
  1237. dsp568013.cfg stellaris_icdi.cfg
  1238. dsp568037.cfg stm32f0x_stlink.cfg
  1239. efm32_stlink.cfg stm32f1x.cfg
  1240. epc9301.cfg stm32f1x_stlink.cfg
  1241. faux.cfg stm32f2x.cfg
  1242. feroceon.cfg stm32f2x_stlink.cfg
  1243. fm3.cfg stm32f3x.cfg
  1244. hilscher_netx10.cfg stm32f3x_stlink.cfg
  1245. hilscher_netx500.cfg stm32f4x.cfg
  1246. hilscher_netx50.cfg stm32f4x_stlink.cfg
  1247. icepick.cfg stm32l.cfg
  1248. imx21.cfg stm32lx_dual_bank.cfg
  1249. imx25.cfg stm32lx_stlink.cfg
  1250. imx27.cfg stm32_stlink.cfg
  1251. imx28.cfg stm32w108_stlink.cfg
  1252. imx31.cfg stm32xl.cfg
  1253. imx35.cfg str710.cfg
  1254. imx51.cfg str730.cfg
  1255. imx53.cfg str750.cfg
  1256. imx6.cfg str912.cfg
  1257. imx.cfg swj-dp.tcl
  1258. is5114.cfg test_reset_syntax_error.cfg
  1259. ixp42x.cfg test_syntax_error.cfg
  1260. k40.cfg ti-ar7.cfg
  1261. k60.cfg ti_calypso.cfg
  1262. lpc1751.cfg ti_dm355.cfg
  1263. lpc1752.cfg ti_dm365.cfg
  1264. lpc1754.cfg ti_dm6446.cfg
  1265. lpc1756.cfg tmpa900.cfg
  1266. lpc1758.cfg tmpa910.cfg
  1267. lpc1759.cfg u8500.cfg
  1268. @end example
  1269. @item @emph{more} ... browse for other library files which may be useful.
  1270. For example, there are various generic and CPU-specific utilities.
  1271. @end itemize
  1272. The @file{openocd.cfg} user config
  1273. file may override features in any of the above files by
  1274. setting variables before sourcing the target file, or by adding
  1275. commands specific to their situation.
  1276. @section Interface Config Files
  1277. The user config file
  1278. should be able to source one of these files with a command like this:
  1279. @example
  1280. source [find interface/FOOBAR.cfg]
  1281. @end example
  1282. A preconfigured interface file should exist for every debug adapter
  1283. in use today with OpenOCD.
  1284. That said, perhaps some of these config files
  1285. have only been used by the developer who created it.
  1286. A separate chapter gives information about how to set these up.
  1287. @xref{Debug Adapter Configuration}.
  1288. Read the OpenOCD source code (and Developer's Guide)
  1289. if you have a new kind of hardware interface
  1290. and need to provide a driver for it.
  1291. @section Board Config Files
  1292. @cindex config file, board
  1293. @cindex board config file
  1294. The user config file
  1295. should be able to source one of these files with a command like this:
  1296. @example
  1297. source [find board/FOOBAR.cfg]
  1298. @end example
  1299. The point of a board config file is to package everything
  1300. about a given board that user config files need to know.
  1301. In summary the board files should contain (if present)
  1302. @enumerate
  1303. @item One or more @command{source [find target/...cfg]} statements
  1304. @item NOR flash configuration (@pxref{norconfiguration,,NOR Configuration})
  1305. @item NAND flash configuration (@pxref{nandconfiguration,,NAND Configuration})
  1306. @item Target @code{reset} handlers for SDRAM and I/O configuration
  1307. @item JTAG adapter reset configuration (@pxref{Reset Configuration})
  1308. @item All things that are not ``inside a chip''
  1309. @end enumerate
  1310. Generic things inside target chips belong in target config files,
  1311. not board config files. So for example a @code{reset-init} event
  1312. handler should know board-specific oscillator and PLL parameters,
  1313. which it passes to target-specific utility code.
  1314. The most complex task of a board config file is creating such a
  1315. @code{reset-init} event handler.
  1316. Define those handlers last, after you verify the rest of the board
  1317. configuration works.
  1318. @subsection Communication Between Config files
  1319. In addition to target-specific utility code, another way that
  1320. board and target config files communicate is by following a
  1321. convention on how to use certain variables.
  1322. The full Tcl/Tk language supports ``namespaces'', but Jim-Tcl does not.
  1323. Thus the rule we follow in OpenOCD is this: Variables that begin with
  1324. a leading underscore are temporary in nature, and can be modified and
  1325. used at will within a target configuration file.
  1326. Complex board config files can do the things like this,
  1327. for a board with three chips:
  1328. @example
  1329. # Chip #1: PXA270 for network side, big endian
  1330. set CHIPNAME network
  1331. set ENDIAN big
  1332. source [find target/pxa270.cfg]
  1333. # on return: _TARGETNAME = network.cpu
  1334. # other commands can refer to the "network.cpu" target.
  1335. $_TARGETNAME configure .... events for this CPU..
  1336. # Chip #2: PXA270 for video side, little endian
  1337. set CHIPNAME video
  1338. set ENDIAN little
  1339. source [find target/pxa270.cfg]
  1340. # on return: _TARGETNAME = video.cpu
  1341. # other commands can refer to the "video.cpu" target.
  1342. $_TARGETNAME configure .... events for this CPU..
  1343. # Chip #3: Xilinx FPGA for glue logic
  1344. set CHIPNAME xilinx
  1345. unset ENDIAN
  1346. source [find target/spartan3.cfg]
  1347. @end example
  1348. That example is oversimplified because it doesn't show any flash memory,
  1349. or the @code{reset-init} event handlers to initialize external DRAM
  1350. or (assuming it needs it) load a configuration into the FPGA.
  1351. Such features are usually needed for low-level work with many boards,
  1352. where ``low level'' implies that the board initialization software may
  1353. not be working. (That's a common reason to need JTAG tools. Another
  1354. is to enable working with microcontroller-based systems, which often
  1355. have no debugging support except a JTAG connector.)
  1356. Target config files may also export utility functions to board and user
  1357. config files. Such functions should use name prefixes, to help avoid
  1358. naming collisions.
  1359. Board files could also accept input variables from user config files.
  1360. For example, there might be a @code{J4_JUMPER} setting used to identify
  1361. what kind of flash memory a development board is using, or how to set
  1362. up other clocks and peripherals.
  1363. @subsection Variable Naming Convention
  1364. @cindex variable names
  1365. Most boards have only one instance of a chip.
  1366. However, it should be easy to create a board with more than
  1367. one such chip (as shown above).
  1368. Accordingly, we encourage these conventions for naming
  1369. variables associated with different @file{target.cfg} files,
  1370. to promote consistency and
  1371. so that board files can override target defaults.
  1372. Inputs to target config files include:
  1373. @itemize @bullet
  1374. @item @code{CHIPNAME} ...
  1375. This gives a name to the overall chip, and is used as part of
  1376. tap identifier dotted names.
  1377. While the default is normally provided by the chip manufacturer,
  1378. board files may need to distinguish between instances of a chip.
  1379. @item @code{ENDIAN} ...
  1380. By default @option{little} - although chips may hard-wire @option{big}.
  1381. Chips that can't change endianness don't need to use this variable.
  1382. @item @code{CPUTAPID} ...
  1383. When OpenOCD examines the JTAG chain, it can be told verify the
  1384. chips against the JTAG IDCODE register.
  1385. The target file will hold one or more defaults, but sometimes the
  1386. chip in a board will use a different ID (perhaps a newer revision).
  1387. @end itemize
  1388. Outputs from target config files include:
  1389. @itemize @bullet
  1390. @item @code{_TARGETNAME} ...
  1391. By convention, this variable is created by the target configuration
  1392. script. The board configuration file may make use of this variable to
  1393. configure things like a ``reset init'' script, or other things
  1394. specific to that board and that target.
  1395. If the chip has 2 targets, the names are @code{_TARGETNAME0},
  1396. @code{_TARGETNAME1}, ... etc.
  1397. @end itemize
  1398. @subsection The reset-init Event Handler
  1399. @cindex event, reset-init
  1400. @cindex reset-init handler
  1401. Board config files run in the OpenOCD configuration stage;
  1402. they can't use TAPs or targets, since they haven't been
  1403. fully set up yet.
  1404. This means you can't write memory or access chip registers;
  1405. you can't even verify that a flash chip is present.
  1406. That's done later in event handlers, of which the target @code{reset-init}
  1407. handler is one of the most important.
  1408. Except on microcontrollers, the basic job of @code{reset-init} event
  1409. handlers is setting up flash and DRAM, as normally handled by boot loaders.
  1410. Microcontrollers rarely use boot loaders; they run right out of their
  1411. on-chip flash and SRAM memory. But they may want to use one of these
  1412. handlers too, if just for developer convenience.
  1413. @quotation Note
  1414. Because this is so very board-specific, and chip-specific, no examples
  1415. are included here.
  1416. Instead, look at the board config files distributed with OpenOCD.
  1417. If you have a boot loader, its source code will help; so will
  1418. configuration files for other JTAG tools
  1419. (@pxref{translatingconfigurationfiles,,Translating Configuration Files}).
  1420. @end quotation
  1421. Some of this code could probably be shared between different boards.
  1422. For example, setting up a DRAM controller often doesn't differ by
  1423. much except the bus width (16 bits or 32?) and memory timings, so a
  1424. reusable TCL procedure loaded by the @file{target.cfg} file might take
  1425. those as parameters.
  1426. Similarly with oscillator, PLL, and clock setup;
  1427. and disabling the watchdog.
  1428. Structure the code cleanly, and provide comments to help
  1429. the next developer doing such work.
  1430. (@emph{You might be that next person} trying to reuse init code!)
  1431. The last thing normally done in a @code{reset-init} handler is probing
  1432. whatever flash memory was configured. For most chips that needs to be
  1433. done while the associated target is halted, either because JTAG memory
  1434. access uses the CPU or to prevent conflicting CPU access.
  1435. @subsection JTAG Clock Rate
  1436. Before your @code{reset-init} handler has set up
  1437. the PLLs and clocking, you may need to run with
  1438. a low JTAG clock rate.
  1439. @xref{jtagspeed,,JTAG Speed}.
  1440. Then you'd increase that rate after your handler has
  1441. made it possible to use the faster JTAG clock.
  1442. When the initial low speed is board-specific, for example
  1443. because it depends on a board-specific oscillator speed, then
  1444. you should probably set it up in the board config file;
  1445. if it's target-specific, it belongs in the target config file.
  1446. For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
  1447. @uref{} gives details.}
  1448. is one sixth of the CPU clock; or one eighth for ARM11 cores.
  1449. Consult chip documentation to determine the peak JTAG clock rate,
  1450. which might be less than that.
  1451. @quotation Warning
  1452. On most ARMs, JTAG clock detection is coupled to the core clock, so
  1453. software using a @option{wait for interrupt} operation blocks JTAG access.
  1454. Adaptive clocking provides a partial workaround, but a more complete
  1455. solution just avoids using that instruction with JTAG debuggers.
  1456. @end quotation
  1457. If both the chip and the board support adaptive clocking,
  1458. use the @command{jtag_rclk}
  1459. command, in case your board is used with JTAG adapter which
  1460. also supports it. Otherwise use @command{adapter_khz}.
  1461. Set the slow rate at the beginning of the reset sequence,
  1462. and the faster rate as soon as the clocks are at full speed.
  1463. @anchor{theinitboardprocedure}
  1464. @subsection The init_board procedure
  1465. @cindex init_board procedure
  1466. The concept of @code{init_board} procedure is very similar to @code{init_targets}
  1467. (@xref{theinittargetsprocedure,,The init_targets procedure}.) - it's a replacement of ``linear''
  1468. configuration scripts. This procedure is meant to be executed when OpenOCD enters run stage
  1469. (@xref{enteringtherunstage,,Entering the Run Stage},) after @code{init_targets}. The idea to have
  1470. separate @code{init_targets} and @code{init_board} procedures is to allow the first one to configure
  1471. everything target specific (internal flash, internal RAM, etc.) and the second one to configure
  1472. everything board specific (reset signals, chip frequency, reset-init event handler, external memory, etc.).
  1473. Additionally ``linear'' board config file will most likely fail when target config file uses
  1474. @code{init_targets} scheme (``linear'' script is executed before @code{init} and @code{init_targets} - after),
  1475. so separating these two configuration stages is very convenient, as the easiest way to overcome this
  1476. problem is to convert board config file to use @code{init_board} procedure. Board config scripts don't
  1477. need to override @code{init_targets} defined in target config files when they only need to add some specifics.
  1478. Just as @code{init_targets}, the @code{init_board} procedure can be overridden by ``next level'' script (which sources
  1479. the original), allowing greater code reuse.
  1480. @example
  1481. ### board_file.cfg ###
  1482. # source target file that does most of the config in init_targets
  1483. source [find target/target.cfg]
  1484. proc enable_fast_clock @{@} @{
  1485. # enables fast on-board clock source
  1486. # configures the chip to use it
  1487. @}
  1488. # initialize only board specifics - reset, clock, adapter frequency
  1489. proc init_board @{@} @{
  1490. reset_config trst_and_srst trst_pulls_srst
  1491. $_TARGETNAME configure -event reset-init @{
  1492. adapter_khz 1
  1493. enable_fast_clock
  1494. adapter_khz 10000
  1495. @}
  1496. @}
  1497. @end example
  1498. @section Target Config Files
  1499. @cindex config file, target
  1500. @cindex target config file
  1501. Board config files communicate with target config files using
  1502. naming conventions as described above, and may source one or
  1503. more target config files like this:
  1504. @example
  1505. source [find target/FOOBAR.cfg]
  1506. @end example
  1507. The point of a target config file is to package everything
  1508. about a given chip that board config files need to know.
  1509. In summary the target files should contain
  1510. @enumerate
  1511. @item Set defaults
  1512. @item Add TAPs to the scan chain
  1513. @item Add CPU targets (includes GDB support)
  1514. @item CPU/Chip/CPU-Core specific features
  1515. @item On-Chip flash
  1516. @end enumerate
  1517. As a rule of thumb, a target file sets up only one chip.
  1518. For a microcontroller, that will often include a single TAP,
  1519. which is a CPU needing a GDB target, and its on-chip flash.
  1520. More complex chips may include multiple TAPs, and the target
  1521. config file may need to define them all before OpenOCD
  1522. can talk to the chip.
  1523. For example, some phone chips have JTAG scan chains that include
  1524. an ARM core for operating system use, a DSP,
  1525. another ARM core embedded in an image processing engine,
  1526. and other processing engines.
  1527. @subsection Default Value Boiler Plate Code
  1528. All target configuration files should start with code like this,
  1529. letting board config files express environment-specific
  1530. differences in how things should be set up.
  1531. @example
  1532. # Boards may override chip names, perhaps based on role,
  1533. # but the default should match what the vendor uses
  1534. if @{ [info exists CHIPNAME] @} @{
  1536. @} else @{
  1537. set _CHIPNAME sam7x256
  1538. @}
  1539. # ONLY use ENDIAN with targets that can change it.
  1540. if @{ [info exists ENDIAN] @} @{
  1541. set _ENDIAN $ENDIAN
  1542. @} else @{
  1543. set _ENDIAN little
  1544. @}
  1545. # TAP identifiers may change as chips mature, for example with
  1546. # new revision fields (the "3" here). Pick a good default; you
  1547. # can pass several such identifiers to the "jtag newtap" command.
  1548. if @{ [info exists CPUTAPID ] @} @{
  1550. @} else @{
  1551. set _CPUTAPID 0x3f0f0f0f
  1552. @}
  1553. @end example
  1554. @c but 0x3f0f0f0f is for an str73x part ...
  1555. @emph{Remember:} Board config files may include multiple target
  1556. config files, or the same target file multiple times
  1557. (changing at least @code{CHIPNAME}).
  1558. Likewise, the target configuration file should define
  1559. @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
  1560. use it later on when defining debug targets:
  1561. @example
  1562. set _TARGETNAME $_CHIPNAME.cpu
  1563. target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
  1564. @end example
  1565. @subsection Adding TAPs to the Scan Chain
  1566. After the ``defaults'' are set up,
  1567. add the TAPs on each chip to the JTAG scan chain.
  1568. @xref{TAP Declaration}, and the naming convention
  1569. for taps.
  1570. In the simplest case the chip has only one TAP,
  1571. probably for a CPU or FPGA.
  1572. The config file for the Atmel AT91SAM7X256
  1573. looks (in part) like this:
  1574. @example
  1575. jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
  1576. @end example
  1577. A board with two such at91sam7 chips would be able
  1578. to source such a config file twice, with different
  1579. values for @code{CHIPNAME}, so
  1580. it adds a different TAP each time.
  1581. If there are nonzero @option{-expected-id} values,
  1582. OpenOCD attempts to verify the actual tap id against those values.
  1583. It will issue error messages if there is mismatch, which
  1584. can help to pinpoint problems in OpenOCD configurations.
  1585. @example
  1586. JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
  1587. (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
  1588. ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
  1589. ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
  1590. ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
  1591. @end example
  1592. There are more complex examples too, with chips that have
  1593. multiple TAPs. Ones worth looking at include:
  1594. @itemize
  1595. @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
  1596. plus a JRC to enable them
  1597. @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
  1598. @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
  1599. is not currently used)
  1600. @end itemize
  1601. @subsection Add CPU targets
  1602. After adding a TAP for a CPU, you should set it up so that
  1603. GDB and other commands can use it.
  1604. @xref{CPU Configuration}.
  1605. For the at91sam7 example above, the command can look like this;
  1606. note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
  1607. to little endian, and this chip doesn't support changing that.
  1608. @example
  1609. set _TARGETNAME $_CHIPNAME.cpu
  1610. target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
  1611. @end example
  1612. Work areas are small RAM areas associated with CPU targets.
  1613. They are used by OpenOCD to speed up downloads,
  1614. and to download small snippets of code to program flash chips.
  1615. If the chip includes a form of ``on-chip-ram'' - and many do - define
  1616. a work area if you can.
  1617. Again using the at91sam7 as an example, this can look like:
  1618. @example
  1619. $_TARGETNAME configure -work-area-phys 0x00200000 \
  1620. -work-area-size 0x4000 -work-area-backup 0
  1621. @end example
  1622. @anchor{definecputargetsworkinginsmp}
  1623. @subsection Define CPU targets working in SMP
  1624. @cindex SMP
  1625. After setting targets, you can define a list of targets working in SMP.
  1626. @example
  1627. set _TARGETNAME_1 $_CHIPNAME.cpu1
  1628. set _TARGETNAME_2 $_CHIPNAME.cpu2
  1629. target create $_TARGETNAME_1 cortex_a -chain-position $_CHIPNAME.dap \
  1630. -coreid 0 -dbgbase $_DAP_DBG1
  1631. target create $_TARGETNAME_2 cortex_a -chain-position $_CHIPNAME.dap \
  1632. -coreid 1 -dbgbase $_DAP_DBG2
  1633. #define 2 targets working in smp.
  1634. target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1
  1635. @end example
  1636. In the above example on cortex_a, 2 cpus are working in SMP.
  1637. In SMP only one GDB instance is created and :
  1638. @itemize @bullet
  1639. @item a set of hardware breakpoint sets the same breakpoint on all targets in the list.
  1640. @item halt command triggers the halt of all targets in the list.
  1641. @item resume command triggers the write context and the restart of all targets in the list.
  1642. @item following a breakpoint: the target stopped by the breakpoint is displayed to the GDB session.
  1643. @item dedicated GDB serial protocol packets are implemented for switching/retrieving the target
  1644. displayed by the GDB session @pxref{usingopenocdsmpwithgdb,,Using OpenOCD SMP with GDB}.
  1645. @end itemize
  1646. The SMP behaviour can be disabled/enabled dynamically. On cortex_a following
  1647. command have been implemented.
  1648. @itemize @bullet
  1649. @item cortex_a smp_on : enable SMP mode, behaviour is as described above.
  1650. @item cortex_a smp_off : disable SMP mode, the current target is the one
  1651. displayed in the GDB session, only this target is now controlled by GDB
  1652. session. This behaviour is useful during system boot up.
  1653. @item cortex_a smp_gdb : display/fix the core id displayed in GDB session see
  1654. following example.
  1655. @end itemize
  1656. @example
  1657. >cortex_a smp_gdb
  1658. gdb coreid 0 -> -1
  1659. #0 : coreid 0 is displayed to GDB ,
  1660. #-> -1 : next resume triggers a real resume
  1661. > cortex_a smp_gdb 1
  1662. gdb coreid 0 -> 1
  1663. #0 :coreid 0 is displayed to GDB ,
  1664. #->1 : next resume displays coreid 1 to GDB
  1665. > resume
  1666. > cortex_a smp_gdb
  1667. gdb coreid 1 -> 1
  1668. #1 :coreid 1 is displayed to GDB ,
  1669. #->1 : next resume displays coreid 1 to GDB
  1670. > cortex_a smp_gdb -1
  1671. gdb coreid 1 -> -1
  1672. #1 :coreid 1 is displayed to GDB,
  1673. #->-1 : next resume triggers a real resume
  1674. @end example
  1675. @subsection Chip Reset Setup
  1676. As a rule, you should put the @command{reset_config} command
  1677. into the board file. Most things you think you know about a
  1678. chip can be tweaked by the board.
  1679. Some chips have specific ways the TRST and SRST signals are
  1680. managed. In the unusual case that these are @emph{chip specific}
  1681. and can never be changed by board wiring, they could go here.
  1682. For example, some chips can't support JTAG debugging without
  1683. both signals.
  1684. Provide a @code{reset-assert} event handler if you can.
  1685. Such a handler uses JTAG operations to reset the target,
  1686. letting this target config be used in systems which don't
  1687. provide the optional SRST signal, or on systems where you
  1688. don't want to reset all targets at once.
  1689. Such a handler might write to chip registers to force a reset,
  1690. use a JRC to do that (preferable -- the target may be wedged!),
  1691. or force a watchdog timer to trigger.
  1692. (For Cortex-M targets, this is not necessary. The target
  1693. driver knows how to use trigger an NVIC reset when SRST is
  1694. not available.)
  1695. Some chips need special attention during reset handling if
  1696. they're going to be used with JTAG.
  1697. An example might be needing to send some commands right
  1698. after the target's TAP has been reset, providing a
  1699. @code{reset-deassert-post} event handler that writes a chip
  1700. register to report that JTAG debugging is being done.
  1701. Another would be reconfiguring the watchdog so that it stops
  1702. counting while the core is halted in the debugger.
  1703. JTAG clocking constraints often change during reset, and in
  1704. some cases target config files (rather than board config files)
  1705. are the right places to handle some of those issues.
  1706. For example, immediately after reset most chips run using a
  1707. slower clock than they will use later.
  1708. That means that after reset (and potentially, as OpenOCD
  1709. first starts up) they must use a slower JTAG clock rate
  1710. than they will use later.
  1711. @xref{jtagspeed,,JTAG Speed}.
  1712. @quotation Important
  1713. When you are debugging code that runs right after chip
  1714. reset, getting these issues right is critical.
  1715. In particular, if you see intermittent failures when
  1716. OpenOCD verifies the scan chain after reset,
  1717. look at how you are setting up JTAG clocking.
  1718. @end quotation
  1719. @anchor{theinittargetsprocedure}
  1720. @subsection The init_targets procedure
  1721. @cindex init_targets procedure
  1722. Target config files can either be ``linear'' (script executed line-by-line when parsed in
  1723. configuration stage, @xref{configurationstage,,Configuration Stage},) or they can contain a special
  1724. procedure called @code{init_targets}, which will be executed when entering run stage
  1725. (after parsing all config files or after @code{init} command, @xref{enteringtherunstage,,Entering the Run Stage}.)
  1726. Such procedure can be overriden by ``next level'' script (which sources the original).
  1727. This concept faciliates code reuse when basic target config files provide generic configuration
  1728. procedures and @code{init_targets} procedure, which can then be sourced and enchanced or changed in
  1729. a ``more specific'' target config file. This is not possible with ``linear'' config scripts,
  1730. because sourcing them executes every initialization commands they provide.
  1731. @example
  1732. ### generic_file.cfg ###
  1733. proc setup_my_chip @{chip_name flash_size ram_size@} @{
  1734. # basic initialization procedure ...
  1735. @}
  1736. proc init_targets @{@} @{
  1737. # initializes generic chip with 4kB of flash and 1kB of RAM
  1738. setup_my_chip MY_GENERIC_CHIP 4096 1024
  1739. @}
  1740. ### specific_file.cfg ###
  1741. source [find target/generic_file.cfg]
  1742. proc init_targets @{@} @{
  1743. # initializes specific chip with 128kB of flash and 64kB of RAM
  1744. setup_my_chip MY_CHIP_WITH_128K_FLASH_64KB_RAM 131072 65536
  1745. @}
  1746. @end example
  1747. The easiest way to convert ``linear'' config files to @code{init_targets} version is to
  1748. enclose every line of ``code'' (i.e. not @code{source} commands, procedures, etc.) in this procedure.
  1749. For an example of this scheme see LPC2000 target config files.
  1750. The @code{init_boards} procedure is a similar concept concerning board config files
  1751. (@xref{theinitboardprocedure,,The init_board procedure}.)
  1752. @anchor{theinittargeteventsprocedure}
  1753. @subsection The init_target_events procedure
  1754. @cindex init_target_events procedure
  1755. A special procedure called @code{init_target_events} is run just after
  1756. @code{init_targets} (@xref{theinittargetsprocedure,,The init_targets
  1757. procedure}.) and before @code{init_board}
  1758. (@xref{theinitboardprocedure,,The init_board procedure}.) It is used
  1759. to set up default target events for the targets that do not have those
  1760. events already assigned.
  1761. @subsection ARM Core Specific Hacks
  1762. If the chip has a DCC, enable it. If the chip is an ARM9 with some
  1763. special high speed download features - enable it.
  1764. If present, the MMU, the MPU and the CACHE should be disabled.
  1765. Some ARM cores are equipped with trace support, which permits
  1766. examination of the instruction and data bus activity. Trace
  1767. activity is controlled through an ``Embedded Trace Module'' (ETM)
  1768. on one of the core's scan chains. The ETM emits voluminous data
  1769. through a ``trace port''. (@xref{armhardwaretracing,,ARM Hardware Tracing}.)
  1770. If you are using an external trace port,
  1771. configure it in your board config file.
  1772. If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
  1773. configure it in your target config file.
  1774. @example
  1775. etm config $_TARGETNAME 16 normal full etb
  1776. etb config $_TARGETNAME $_CHIPNAME.etb
  1777. @end example
  1778. @subsection Internal Flash Configuration
  1779. This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
  1780. @b{Never ever} in the ``target configuration file'' define any type of
  1781. flash that is external to the chip. (For example a BOOT flash on
  1782. Chip Select 0.) Such flash information goes in a board file - not
  1783. the TARGET (chip) file.
  1784. Examples:
  1785. @itemize @bullet
  1786. @item at91sam7x256 - has 256K flash YES enable it.
  1787. @item str912 - has flash internal YES enable it.
  1788. @item imx27 - uses boot flash on CS0 - it goes in the board file.
  1789. @item pxa270 - again - CS0 flash - it goes in the board file.
  1790. @end itemize
  1791. @anchor{translatingconfigurationfiles}
  1792. @section Translating Configuration Files
  1793. @cindex translation
  1794. If you have a configuration file for another hardware debugger
  1795. or toolset (Abatron, BDI2000, BDI3000, CCS,
  1796. Lauterbach, Segger, Macraigor, etc.), translating
  1797. it into OpenOCD syntax is often quite straightforward. The most tricky
  1798. part of creating a configuration script is oftentimes the reset init
  1799. sequence where e.g. PLLs, DRAM and the like is set up.
  1800. One trick that you can use when translating is to write small
  1801. Tcl procedures to translate the syntax into OpenOCD syntax. This
  1802. can avoid manual translation errors and make it easier to
  1803. convert other scripts later on.
  1804. Example of transforming quirky arguments to a simple search and
  1805. replace job:
  1806. @example
  1807. # Lauterbach syntax(?)
  1808. #
  1809. # Data.Set c15:0x042f %long 0x40000015
  1810. #
  1811. # OpenOCD syntax when using procedure below.
  1812. #
  1813. # setc15 0x01 0x00050078
  1814. proc setc15 @{regs value@} @{
  1815. global TARGETNAME
  1816. echo [format "set p15 0x%04x, 0x%08x" $regs $value]
  1817. arm mcr 15 [expr ($regs>>12)&0x7] \
  1818. [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] \
  1819. [expr ($regs>>8)&0x7] $value
  1820. @}
  1821. @end example
  1822. @node Daemon Configuration
  1823. @chapter Daemon Configuration
  1824. @cindex initialization
  1825. The commands here are commonly found in the openocd.cfg file and are
  1826. used to specify what TCP/IP ports are used, and how GDB should be
  1827. supported.
  1828. @anchor{configurationstage}
  1829. @section Configuration Stage
  1830. @cindex configuration stage
  1831. @cindex config command
  1832. When the OpenOCD server process starts up, it enters a
  1833. @emph{configuration stage} which is the only time that
  1834. certain commands, @emph{configuration commands}, may be issued.
  1835. Normally, configuration commands are only available
  1836. inside startup scripts.
  1837. In this manual, the definition of a configuration command is
  1838. presented as a @emph{Config Command}, not as a @emph{Command}
  1839. which may be issued interactively.
  1840. The runtime @command{help} command also highlights configuration
  1841. commands, and those which may be issued at any time.
  1842. Those configuration commands include declaration of TAPs,
  1843. flash banks,
  1844. the interface used for JTAG communication,
  1845. and other basic setup.
  1846. The server must leave the configuration stage before it
  1847. may access or activate TAPs.
  1848. After it leaves this stage, configuration commands may no
  1849. longer be issued.
  1850. @anchor{enteringtherunstage}
  1851. @section Entering the Run Stage
  1852. The first thing OpenOCD does after leaving the configuration
  1853. stage is to verify that it can talk to the scan chain
  1854. (list of TAPs) which has been configured.
  1855. It will warn if it doesn't find TAPs it expects to find,
  1856. or finds TAPs that aren't supposed to be there.
  1857. You should see no errors at this point.
  1858. If you see errors, resolve them by correcting the
  1859. commands you used to configure the server.
  1860. Common errors include using an initial JTAG speed that's too
  1861. fast, and not providing the right IDCODE values for the TAPs
  1862. on the scan chain.
  1863. Once OpenOCD has entered the run stage, a number of commands
  1864. become available.
  1865. A number of these relate to the debug targets you may have declared.
  1866. For example, the @command{mww} command will not be available until
  1867. a target has been successfuly instantiated.
  1868. If you want to use those commands, you may need to force
  1869. entry to the run stage.
  1870. @deffn {Config Command} init
  1871. This command terminates the configuration stage and
  1872. enters the run stage. This helps when you need to have
  1873. the startup scripts manage tasks such as resetting the target,
  1874. programming flash, etc. To reset the CPU upon startup, add "init" and
  1875. "reset" at the end of the config script or at the end of the OpenOCD
  1876. command line using the @option{-c} command line switch.
  1877. If this command does not appear in any startup/configuration file
  1878. OpenOCD executes the command for you after processing all
  1879. configuration files and/or command line options.
  1880. @b{NOTE:} This command normally occurs at or near the end of your
  1881. openocd.cfg file to force OpenOCD to ``initialize'' and make the
  1882. targets ready. For example: If your openocd.cfg file needs to
  1883. read/write memory on your target, @command{init} must occur before
  1884. the memory read/write commands. This includes @command{nand probe}.
  1885. @end deffn
  1886. @deffn {Overridable Procedure} jtag_init
  1887. This is invoked at server startup to verify that it can talk
  1888. to the scan chain (list of TAPs) which has been configured.
  1889. The default implementation first tries @command{jtag arp_init},
  1890. which uses only a lightweight JTAG reset before examining the
  1891. scan chain.
  1892. If that fails, it tries again, using a harder reset
  1893. from the overridable procedure @command{init_reset}.
  1894. Implementations must have verified the JTAG scan chain before
  1895. they return.
  1896. This is done by calling @command{jtag arp_init}
  1897. (or @command{jtag arp_init-reset}).
  1898. @end deffn
  1899. @anchor{tcpipports}
  1900. @section TCP/IP Ports
  1901. @cindex TCP port
  1902. @cindex server
  1903. @cindex port
  1904. @cindex security
  1905. The OpenOCD server accepts remote commands in several syntaxes.
  1906. Each syntax uses a different TCP/IP port, which you may specify
  1907. only during configuration (before those ports are opened).
  1908. For reasons including security, you may wish to prevent remote
  1909. access using one or more of these ports.
  1910. In such cases, just specify the relevant port number as zero.
  1911. If you disable all access through TCP/IP, you will need to
  1912. use the command line @option{-pipe} option.
  1913. @deffn {Command} gdb_port [number]
  1914. @cindex GDB server
  1915. Normally gdb listens to a TCP/IP port, but GDB can also
  1916. communicate via pipes(stdin/out or named pipes). The name
  1917. "gdb_port" stuck because it covers probably more than 90% of
  1918. the normal use cases.
  1919. No arguments reports GDB port. "pipe" means listen to stdin
  1920. output to stdout, an integer is base port number, "disable"
  1921. disables the gdb server.
  1922. When using "pipe", also use log_output to redirect the log
  1923. output to a file so as not to flood the stdin/out pipes.
  1924. The -p/--pipe option is deprecated and a warning is printed
  1925. as it is equivalent to passing in -c "gdb_port pipe; log_output openocd.log".
  1926. Any other string is interpreted as named pipe to listen to.
  1927. Output pipe is the same name as input pipe, but with 'o' appended,
  1928. e.g. /var/gdb, /var/gdbo.
  1929. The GDB port for the first target will be the base port, the
  1930. second target will listen on gdb_port + 1, and so on.
  1931. When not specified during the configuration stage,
  1932. the port @var{number} defaults to 3333.
  1933. @end deffn
  1934. @deffn {Command} tcl_port [number]
  1935. Specify or query the port used for a simplified RPC
  1936. connection that can be used by clients to issue TCL commands and get the
  1937. output from the Tcl engine.
  1938. Intended as a machine interface.
  1939. When not specified during the configuration stage,
  1940. the port @var{number} defaults to 6666.
  1941. @end deffn
  1942. @deffn {Command} telnet_port [number]
  1943. Specify or query the
  1944. port on which to listen for incoming telnet connections.
  1945. This port is intended for interaction with one human through TCL commands.
  1946. When not specified during the configuration stage,
  1947. the port @var{number} defaults to 4444.
  1948. When specified as zero, this port is not activated.
  1949. @end deffn
  1950. @anchor{gdbconfiguration}
  1951. @section GDB Configuration
  1952. @cindex GDB
  1953. @cindex GDB configuration
  1954. You can reconfigure some GDB behaviors if needed.
  1955. The ones listed here are static and global.
  1956. @xref{targetconfiguration,,Target Configuration}, about configuring individual targets.
  1957. @xref{targetevents,,Target Events}, about configuring target-specific event handling.
  1958. @anchor{gdbbreakpointoverride}
  1959. @deffn {Command} gdb_breakpoint_override [@option{hard}|@option{soft}|@option{disable}]
  1960. Force breakpoint type for gdb @command{break} commands.
  1961. This option supports GDB GUIs which don't
  1962. distinguish hard versus soft breakpoints, if the default OpenOCD and
  1963. GDB behaviour is not sufficient. GDB normally uses hardware
  1964. breakpoints if the memory map has been set up for flash regions.
  1965. @end deffn
  1966. @anchor{gdbflashprogram}
  1967. @deffn {Config Command} gdb_flash_program (@option{enable}|@option{disable})
  1968. Set to @option{enable} to cause OpenOCD to program the flash memory when a
  1969. vFlash packet is received.
  1970. The default behaviour is @option{enable}.
  1971. @end deffn
  1972. @deffn {Config Command} gdb_memory_map (@option{enable}|@option{disable})
  1973. Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
  1974. requested. GDB will then know when to set hardware breakpoints, and program flash
  1975. using the GDB load command. @command{gdb_flash_program enable} must also be enabled
  1976. for flash programming to work.
  1977. Default behaviour is @option{enable}.
  1978. @xref{gdbflashprogram,,gdb_flash_program}.
  1979. @end deffn
  1980. @deffn {Config Command} gdb_report_data_abort (@option{enable}|@option{disable})
  1981. Specifies whether data aborts cause an error to be reported
  1982. by GDB memory read packets.
  1983. The default behaviour is @option{disable};
  1984. use @option{enable} see these errors reported.
  1985. @end deffn
  1986. @deffn {Config Command} gdb_target_description (@option{enable}|@option{disable})
  1987. Set to @option{enable} to cause OpenOCD to send the target descriptions to gdb via qXfer:features:read packet.
  1988. The default behaviour is @option{disable}.
  1989. @end deffn
  1990. @deffn {Command} gdb_save_tdesc
  1991. Saves the target descripton file to the local file system.
  1992. The file name is @i{target_name}.xml.
  1993. @end deffn
  1994. @anchor{eventpolling}
  1995. @section Event Polling
  1996. Hardware debuggers are parts of asynchronous systems,
  1997. where significant events can happen at any time.
  1998. The OpenOCD server needs to detect some of these events,
  1999. so it can report them to through TCL command line
  2000. or to GDB.
  2001. Examples of such events include:
  2002. @itemize
  2003. @item One of the targets can stop running ... maybe it triggers
  2004. a code breakpoint or data watchpoint, or halts itself.
  2005. @item Messages may be sent over ``debug message'' channels ... many
  2006. targets support such messages sent over JTAG,
  2007. for receipt by the person debugging or tools.
  2008. @item Loss of power ... some adapters can detect these events.
  2009. @item Resets not issued through JTAG ... such reset sources
  2010. can include button presses or other system hardware, sometimes
  2011. including the target itself (perhaps through a watchdog).
  2012. @item Debug instrumentation sometimes supports event triggering
  2013. such as ``trace buffer full'' (so it can quickly be emptied)
  2014. or other signals (to correlate with code behavior).
  2015. @end itemize
  2016. None of those events are signaled through standard JTAG signals.
  2017. However, most conventions for JTAG connectors include voltage
  2018. level and system reset (SRST) signal detection.
  2019. Some connectors also include instrumentation signals, which
  2020. can imply events when those signals are inputs.
  2021. In general, OpenOCD needs to periodically check for those events,
  2022. either by looking at the status of signals on the JTAG connector
  2023. or by sending synchronous ``tell me your status'' JTAG requests
  2024. to the various active targets.
  2025. There is a command to manage and monitor that polling,
  2026. which is normally done in the background.
  2027. @deffn Command poll [@option{on}|@option{off}]
  2028. Poll the current target for its current state.
  2029. (Also, @pxref{targetcurstate,,target curstate}.)
  2030. If that target is in debug mode, architecture
  2031. specific information about the current state is printed.
  2032. An optional parameter
  2033. allows background polling to be enabled and disabled.
  2034. You could use this from the TCL command shell, or
  2035. from GDB using @command{monitor poll} command.
  2036. Leave background polling enabled while you're using GDB.
  2037. @example
  2038. > poll
  2039. background polling: on
  2040. target state: halted
  2041. target halted in ARM state due to debug-request, \
  2042. current mode: Supervisor
  2043. cpsr: 0x800000d3 pc: 0x11081bfc
  2044. MMU: disabled, D-Cache: disabled, I-Cache: enabled
  2045. >
  2046. @end example
  2047. @end deffn
  2048. @node Debug Adapter Configuration
  2049. @chapter Debug Adapter Configuration
  2050. @cindex config file, interface
  2051. @cindex interface config file
  2052. Correctly installing OpenOCD includes making your operating system give
  2053. OpenOCD access to debug adapters. Once that has been done, Tcl commands
  2054. are used to select which one is used, and to configure how it is used.
  2055. @quotation Note
  2056. Because OpenOCD started out with a focus purely on JTAG, you may find
  2057. places where it wrongly presumes JTAG is the only transport protocol
  2058. in use. Be aware that recent versions of OpenOCD are removing that
  2059. limitation. JTAG remains more functional than most other transports.
  2060. Other transports do not support boundary scan operations, or may be
  2061. specific to a given chip vendor. Some might be usable only for
  2062. programming flash memory, instead of also for debugging.
  2063. @end quotation
  2064. Debug Adapters/Interfaces/Dongles are normally configured
  2065. through commands in an interface configuration
  2066. file which is sourced by your @file{openocd.cfg} file, or
  2067. through a command line @option{-f interface/....cfg} option.
  2068. @example
  2069. source [find interface/olimex-jtag-tiny.cfg]
  2070. @end example
  2071. These commands tell
  2072. OpenOCD what type of JTAG adapter you have, and how to talk to it.
  2073. A few cases are so simple that you only need to say what driver to use:
  2074. @example
  2075. # jlink interface
  2076. interface jlink
  2077. @end example
  2078. Most adapters need a bit more configuration than that.
  2079. @section Interface Configuration
  2080. The interface command tells OpenOCD what type of debug adapter you are
  2081. using. Depending on the type of adapter, you may need to use one or
  2082. more additional commands to further identify or configure the adapter.
  2083. @deffn {Config Command} {interface} name
  2084. Use the interface driver @var{name} to connect to the
  2085. target.
  2086. @end deffn
  2087. @deffn Command {interface_list}
  2088. List the debug adapter drivers that have been built into
  2089. the running copy of OpenOCD.
  2090. @end deffn
  2091. @deffn Command {interface transports} transport_name+
  2092. Specifies the transports supported by this debug adapter.
  2093. The adapter driver builds-in similar knowledge; use this only
  2094. when external configuration (such as jumpering) changes what
  2095. the hardware can support.
  2096. @end deffn
  2097. @deffn Command {adapter_name}
  2098. Returns the name of the debug adapter driver being used.
  2099. @end deffn
  2100. @section Interface Drivers
  2101. Each of the interface drivers listed here must be explicitly
  2102. enabled when OpenOCD is configured, in order to be made
  2103. available at run time.
  2104. @deffn {Interface Driver} {amt_jtagaccel}
  2105. Amontec Chameleon in its JTAG Accelerator configuration,
  2106. connected to a PC's EPP mode parallel port.
  2107. This defines some driver-specific commands:
  2108. @deffn {Config Command} {parport_port} number
  2109. Specifies either the address of the I/O port (default: 0x378 for LPT1) or
  2110. the number of the @file{/dev/parport} device.
  2111. @end deffn
  2112. @deffn {Config Command} rtck [@option{enable}|@option{disable}]
  2113. Displays status of RTCK option.
  2114. Optionally sets that option first.
  2115. @end deffn
  2116. @end deffn
  2117. @deffn {Interface Driver} {arm-jtag-ew}
  2118. Olimex ARM-JTAG-EW USB adapter
  2119. This has one driver-specific command:
  2120. @deffn Command {armjtagew_info}
  2121. Logs some status
  2122. @end deffn
  2123. @end deffn
  2124. @deffn {Interface Driver} {at91rm9200}
  2125. Supports bitbanged JTAG from the local system,
  2126. presuming that system is an Atmel AT91rm9200
  2127. and a specific set of GPIOs is used.
  2128. @c command: at91rm9200_device NAME
  2129. @c chooses among list of bit configs ... only one option
  2130. @end deffn
  2131. @deffn {Interface Driver} {cmsis-dap}
  2132. ARM CMSIS-DAP compliant based adapter.
  2133. @deffn {Config Command} {cmsis_dap_vid_pid} [vid pid]+
  2134. The vendor ID and product ID of the CMSIS-DAP device. If not specified
  2135. the driver will attempt to auto detect the CMSIS-DAP device.
  2136. Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
  2137. @example
  2138. cmsis_dap_vid_pid 0xc251 0xf001 0x0d28 0x0204
  2139. @end example
  2140. @end deffn
  2141. @deffn {Command} {cmsis-dap info}
  2142. Display various device information, like hardware version, firmware version, current bus status.
  2143. @end deffn
  2144. @end deffn
  2145. @deffn {Interface Driver} {dummy}
  2146. A dummy software-only driver for debugging.
  2147. @end deffn
  2148. @deffn {Interface Driver} {ep93xx}
  2149. Cirrus Logic EP93xx based single-board computer bit-banging (in development)
  2150. @end deffn
  2151. @deffn {Interface Driver} {ft2232}
  2152. FTDI FT2232 (USB) based devices over one of the userspace libraries.
  2153. Note that this driver has several flaws and the @command{ftdi} driver is
  2154. recommended as its replacement.
  2155. These interfaces have several commands, used to configure the driver
  2156. before initializing the JTAG scan chain:
  2157. @deffn {Config Command} {ft2232_device_desc} description
  2158. Provides the USB device description (the @emph{iProduct string})
  2159. of the FTDI FT2232 device. If not
  2160. specified, the FTDI default value is used. This setting is only valid
  2161. if compiled with FTD2XX support.
  2162. @end deffn
  2163. @deffn {Config Command} {ft2232_serial} serial-number
  2164. Specifies the @var{serial-number} of the FTDI FT2232 device to use,
  2165. in case the vendor provides unique IDs and more than one FT2232 device
  2166. is connected to the host.
  2167. If not specified, serial numbers are not considered.
  2168. (Note that USB serial numbers can be arbitrary Unicode strings,
  2169. and are not restricted to containing only decimal digits.)
  2170. @end deffn
  2171. @deffn {Config Command} {ft2232_layout} name
  2172. Each vendor's FT2232 device can use different GPIO signals
  2173. to control output-enables, reset signals, and LEDs.
  2174. Currently valid layout @var{name} values include:
  2175. @itemize @minus
  2176. @item @b{axm0432_jtag} Axiom AXM-0432
  2177. @item @b{comstick} Hitex STR9 comstick
  2178. @item @b{cortino} Hitex Cortino JTAG interface
  2179. @item @b{evb_lm3s811} TI/Luminary Micro EVB_LM3S811 as a JTAG interface,
  2180. either for the local Cortex-M3 (SRST only)
  2181. or in a passthrough mode (neither SRST nor TRST)
  2182. This layout can not support the SWO trace mechanism, and should be
  2183. used only for older boards (before rev C).
  2184. @item @b{luminary_icdi} This layout should be used with most TI/Luminary
  2185. eval boards, including Rev C LM3S811 eval boards and the eponymous
  2186. ICDI boards, to debug either the local Cortex-M3 or in passthrough mode
  2187. to debug some other target. It can support the SWO trace mechanism.
  2188. @item @b{flyswatter} Tin Can Tools Flyswatter
  2189. @item @b{icebear} ICEbear JTAG adapter from Section 5
  2190. @item @b{jtagkey} Amontec JTAGkey and JTAGkey-Tiny (and compatibles)
  2191. @item @b{jtagkey2} Amontec JTAGkey2 (and compatibles)
  2192. @item @b{m5960} American Microsystems M5960
  2193. @item @b{olimex-jtag} Olimex ARM-USB-OCD and ARM-USB-Tiny
  2194. @item @b{oocdlink} OOCDLink
  2195. @c oocdlink ~= jtagkey_prototype_v1
  2196. @item @b{redbee-econotag} Integrated with a Redbee development board.
  2197. @item @b{redbee-usb} Integrated with a Redbee USB-stick development board.
  2198. @item @b{sheevaplug} Marvell Sheevaplug development kit
  2199. @item @b{signalyzer} Xverve Signalyzer
  2200. @item @b{stm32stick} Hitex STM32 Performance Stick
  2201. @item @b{turtelizer2} egnite Software turtelizer2
  2202. @item @b{usbjtag} "USBJTAG-1" layout described in the OpenOCD diploma thesis
  2203. @end itemize
  2204. @end deffn
  2205. @deffn {Config Command} {ft2232_vid_pid} [vid pid]+
  2206. The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
  2207. default values are used.
  2208. Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
  2209. @example
  2210. ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
  2211. @end example
  2212. @end deffn
  2213. @deffn {Config Command} {ft2232_latency} ms
  2214. On some systems using FT2232 based JTAG interfaces the FT_Read function call in
  2215. ft2232_read() fails to return the expected number of bytes. This can be caused by
  2216. USB communication delays and has proved hard to reproduce and debug. Setting the
  2217. FT2232 latency timer to a larger value increases delays for short USB packets but it
  2218. also reduces the risk of timeouts before receiving the expected number of bytes.
  2219. The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
  2220. @end deffn
  2221. @deffn {Config Command} {ft2232_channel} channel
  2222. Used to select the channel of the ft2232 chip to use (between 1 and 4).
  2223. The default value is 1.
  2224. @end deffn
  2225. For example, the interface config file for a
  2226. Turtelizer JTAG Adapter looks something like this:
  2227. @example
  2228. interface ft2232
  2229. ft2232_device_desc "Turtelizer JTAG/RS232 Adapter"
  2230. ft2232_layout turtelizer2
  2231. ft2232_vid_pid 0x0403 0xbdc8
  2232. @end example
  2233. @end deffn
  2234. @deffn {Interface Driver} {ftdi}
  2235. This driver is for adapters using the MPSSE (Multi-Protocol Synchronous Serial
  2236. Engine) mode built into many FTDI chips, such as the FT2232, FT4232 and FT232H.
  2237. It is a complete rewrite to address a large number of problems with the ft2232
  2238. interface driver.
  2239. The driver is using libusb-1.0 in asynchronous mode to talk to the FTDI device,
  2240. bypassing intermediate libraries like libftdi of D2XX. Performance-wise it is
  2241. consistently faster than the ft2232 driver, sometimes several times faster.
  2242. A major improvement of this driver is that support for new FTDI based adapters
  2243. can be added competely through configuration files, without the need to patch
  2244. and rebuild OpenOCD.
  2245. The driver uses a signal abstraction to enable Tcl configuration files to
  2246. define outputs for one or several FTDI GPIO. These outputs can then be
  2247. controlled using the @command{ftdi_set_signal} command. Special signal names
  2248. are reserved for nTRST, nSRST and LED (for blink) so that they, if defined,
  2249. will be used for their customary purpose.
  2250. Depending on the type of buffer attached to the FTDI GPIO, the outputs have to
  2251. be controlled differently. In order to support tristateable signals such as
  2252. nSRST, both a data GPIO and an output-enable GPIO can be specified for each
  2253. signal. The following output buffer configurations are supported:
  2254. @itemize @minus
  2255. @item Push-pull with one FTDI output as (non-)inverted data line
  2256. @item Open drain with one FTDI output as (non-)inverted output-enable
  2257. @item Tristate with one FTDI output as (non-)inverted data line and another
  2258. FTDI output as (non-)inverted output-enable
  2259. @item Unbuffered, using the FTDI GPIO as a tristate output directly by
  2260. switching data and direction as necessary
  2261. @end itemize
  2262. These interfaces have several commands, used to configure the driver
  2263. before initializing the JTAG scan chain:
  2264. @deffn {Config Command} {ftdi_vid_pid} [vid pid]+
  2265. The vendor ID and product ID of the adapter. If not specified, the FTDI
  2266. default values are used.
  2267. Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
  2268. @example
  2269. ftdi_vid_pid 0x0403 0xcff8 0x15ba 0x0003
  2270. @end example
  2271. @end deffn
  2272. @deffn {Config Command} {ftdi_device_desc} description
  2273. Provides the USB device description (the @emph{iProduct string})
  2274. of the adapter. If not specified, the device description is ignored
  2275. during device selection.
  2276. @end deffn
  2277. @deffn {Config Command} {ftdi_serial} serial-number
  2278. Specifies the @var{serial-number} of the adapter to use,
  2279. in case the vendor provides unique IDs and more than one adapter
  2280. is connected to the host.
  2281. If not specified, serial numbers are not considered.
  2282. (Note that USB serial numbers can be arbitrary Unicode strings,
  2283. and are not restricted to containing only decimal digits.)
  2284. @end deffn
  2285. @deffn {Config Command} {ftdi_channel} channel
  2286. Selects the channel of the FTDI device to use for MPSSE operations. Most
  2287. adapters use the default, channel 0, but there are exceptions.
  2288. @end deffn
  2289. @deffn {Config Command} {ftdi_layout_init} data direction
  2290. Specifies the initial values of the FTDI GPIO data and direction registers.
  2291. Each value is a 16-bit number corresponding to the concatenation of the high
  2292. and low FTDI GPIO registers. The values should be selected based on the
  2293. schematics of the adapter, such that all signals are set to safe levels with
  2294. minimal impact on the target system. Avoid floating inputs, conflicting outputs
  2295. and initially asserted reset signals.
  2296. @end deffn
  2297. @deffn {Config Command} {ftdi_layout_signal} name [@option{-data}|@option{-ndata} data_mask] [@option{-oe}|@option{-noe} oe_mask]
  2298. Creates a signal with the specified @var{name}, controlled by one or more FTDI
  2299. GPIO pins via a range of possible buffer connections. The masks are FTDI GPIO
  2300. register bitmasks to tell the driver the connection and type of the output
  2301. buffer driving the respective signal. @var{data_mask} is the bitmask for the
  2302. pin(s) connected to the data input of the output buffer. @option{-ndata} is
  2303. used with inverting data inputs and @option{-data} with non-inverting inputs.
  2304. The @option{-oe} (or @option{-noe}) option tells where the output-enable (or
  2305. not-output-enable) input to the output buffer is connected.
  2306. Both @var{data_mask} and @var{oe_mask} need not be specified. For example, a
  2307. simple open-collector transistor driver would be specified with @option{-oe}
  2308. only. In that case the signal can only be set to drive low or to Hi-Z and the
  2309. driver will complain if the signal is set to drive high. Which means that if
  2310. it's a reset signal, @command{reset_config} must be specified as
  2311. @option{srst_open_drain}, not @option{srst_push_pull}.
  2312. A special case is provided when @option{-data} and @option{-oe} is set to the
  2313. same bitmask. Then the FTDI pin is considered being connected straight to the
  2314. target without any buffer. The FTDI pin is then switched between output and
  2315. input as necessary to provide the full set of low, high and Hi-Z
  2316. characteristics. In all other cases, the pins specified in a signal definition
  2317. are always driven by the FTDI.
  2318. @end deffn
  2319. @deffn {Command} {ftdi_set_signal} name @option{0}|@option{1}|@option{z}
  2320. Set a previously defined signal to the specified level.
  2321. @itemize @minus
  2322. @item @option{0}, drive low
  2323. @item @option{1}, drive high
  2324. @item @option{z}, set to high-impedance
  2325. @end itemize
  2326. @end deffn
  2327. For example adapter definitions, see the configuration files shipped in the
  2328. @file{interface/ftdi} directory.
  2329. @end deffn
  2330. @deffn {Interface Driver} {remote_bitbang}
  2331. Drive JTAG from a remote process. This sets up a UNIX or TCP socket connection
  2332. with a remote process and sends ASCII encoded bitbang requests to that process
  2333. instead of directly driving JTAG.
  2334. The remote_bitbang driver is useful for debugging software running on
  2335. processors which are being simulated.
  2336. @deffn {Config Command} {remote_bitbang_port} number
  2337. Specifies the TCP port of the remote process to connect to or 0 to use UNIX
  2338. sockets instead of TCP.
  2339. @end deffn
  2340. @deffn {Config Command} {remote_bitbang_host} hostname
  2341. Specifies the hostname of the remote process to connect to using TCP, or the
  2342. name of the UNIX socket to use if remote_bitbang_port is 0.
  2343. @end deffn
  2344. For example, to connect remotely via TCP to the host foobar you might have
  2345. something like:
  2346. @example
  2347. interface remote_bitbang
  2348. remote_bitbang_port 3335
  2349. remote_bitbang_host foobar
  2350. @end example
  2351. To connect to another process running locally via UNIX sockets with socket
  2352. named mysocket:
  2353. @example
  2354. interface remote_bitbang
  2355. remote_bitbang_port 0
  2356. remote_bitbang_host mysocket
  2357. @end example
  2358. @end deffn
  2359. @deffn {Interface Driver} {usb_blaster}
  2360. USB JTAG/USB-Blaster compatibles over one of the userspace libraries
  2361. for FTDI chips. These interfaces have several commands, used to
  2362. configure the driver before initializing the JTAG scan chain:
  2363. @deffn {Config Command} {usb_blaster_device_desc} description
  2364. Provides the USB device description (the @emph{iProduct string})
  2365. of the FTDI FT245 device. If not
  2366. specified, the FTDI default value is used. This setting is only valid
  2367. if compiled with FTD2XX support.
  2368. @end deffn
  2369. @deffn {Config Command} {usb_blaster_vid_pid} vid pid
  2370. The vendor ID and product ID of the FTDI FT245 device. If not specified,
  2371. default values are used.
  2372. Currently, only one @var{vid}, @var{pid} pair may be given, e.g. for
  2373. Altera USB-Blaster (default):
  2374. @example
  2375. usb_blaster_vid_pid 0x09FB 0x6001
  2376. @end example
  2377. The following VID/PID is for Kolja Waschk's USB JTAG:
  2378. @example
  2379. usb_blaster_vid_pid 0x16C0 0x06AD
  2380. @end example
  2381. @end deffn
  2382. @deffn {Command} {usb_blaster} (@option{pin6}|@option{pin8}) (@option{0}|@option{1})
  2383. Sets the state of the unused GPIO pins on USB-Blasters (pins 6 and 8 on the
  2384. female JTAG header). These pins can be used as SRST and/or TRST provided the
  2385. appropriate connections are made on the target board.
  2386. For example, to use pin 6 as SRST (as with an AVR board):
  2387. @example
  2388. $_TARGETNAME configure -event reset-assert \
  2389. "usb_blaster pin6 1; wait 1; usb_blaster pin6 0"
  2390. @end example
  2391. @end deffn
  2392. @end deffn
  2393. @deffn {Interface Driver} {gw16012}
  2394. Gateworks GW16012 JTAG programmer.
  2395. This has one driver-specific command:
  2396. @deffn {Config Command} {parport_port} [port_number]
  2397. Display either the address of the I/O port
  2398. (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
  2399. If a parameter is provided, first switch to use that port.
  2400. This is a write-once setting.
  2401. @end deffn
  2402. @end deffn
  2403. @deffn {Interface Driver} {jlink}
  2404. Segger J-Link family of USB adapters. It currently supports only the JTAG transport.
  2405. @quotation Compatibility Note
  2406. Segger released many firmware versions for the many harware versions they
  2407. produced. OpenOCD was extensively tested and intended to run on all of them,
  2408. but some combinations were reported as incompatible. As a general
  2409. recommendation, it is advisable to use the latest firmware version
  2410. available for each hardware version. However the current V8 is a moving
  2411. target, and Segger firmware versions released after the OpenOCD was
  2412. released may not be compatible. In such cases it is recommended to
  2413. revert to the last known functional version. For 0.5.0, this is from
  2414. "Feb 8 2012 14:30:39", packed with 4.42c. For 0.6.0, the last known
  2415. version is from "May 3 2012 18:36:22", packed with 4.46f.
  2416. @end quotation
  2417. @deffn {Command} {jlink caps}
  2418. Display the device firmware capabilities.
  2419. @end deffn
  2420. @deffn {Command} {jlink info}
  2421. Display various device information, like hardware version, firmware version, current bus status.
  2422. @end deffn
  2423. @deffn {Command} {jlink hw_jtag} [@option{2}|@option{3}]
  2424. Set the JTAG protocol version to be used. Without argument, show the actual JTAG protocol version.
  2425. @end deffn
  2426. @deffn {Command} {jlink config}
  2427. Display the J-Link configuration.
  2428. @end deffn
  2429. @deffn {Command} {jlink config kickstart} [val]
  2430. Set the Kickstart power on JTAG-pin 19. Without argument, show the Kickstart configuration.
  2431. @end deffn
  2432. @deffn {Command} {jlink config mac_address} [@option{ff:ff:ff:ff:ff:ff}]
  2433. Set the MAC address of the J-Link Pro. Without argument, show the MAC address.
  2434. @end deffn
  2435. @deffn {Command} {jlink config ip} [@option{A.B.C.D}(@option{/E}|@option{F.G.H.I})]
  2436. Set the IP configuration of the J-Link Pro, where A.B.C.D is the IP address,
  2437. E the bit of the subnet mask and
  2438. F.G.H.I the subnet mask. Without arguments, show the IP configuration.
  2439. @end deffn
  2440. @deffn {Command} {jlink config usb_address} [@option{0x00} to @option{0x03} or @option{0xff}]
  2441. Set the USB address; this will also change the product id. Without argument, show the USB address.
  2442. @end deffn
  2443. @deffn {Command} {jlink config reset}
  2444. Reset the current configuration.
  2445. @end deffn
  2446. @deffn {Command} {jlink config save}
  2447. Save the current configuration to the internal persistent storage.
  2448. @end deffn
  2449. @deffn {Config} {jlink pid} val
  2450. Set the USB PID of the interface. As a configuration command, it can be used only before 'init'.
  2451. @end deffn
  2452. @end deffn
  2453. @deffn {Interface Driver} {parport}
  2454. Supports PC parallel port bit-banging cables:
  2455. Wigglers, PLD download cable, and more.
  2456. These interfaces have several commands, used to configure the driver
  2457. before initializing the JTAG scan chain:
  2458. @deffn {Config Command} {parport_cable} name
  2459. Set the layout of the parallel port cable used to connect to the target.
  2460. This is a write-once setting.
  2461. Currently valid cable @var{name} values include:
  2462. @itemize @minus
  2463. @item @b{altium} Altium Universal JTAG cable.
  2464. @item @b{arm-jtag} Same as original wiggler except SRST and
  2465. TRST connections reversed and TRST is also inverted.
  2466. @item @b{chameleon} The Amontec Chameleon's CPLD when operated
  2467. in configuration mode. This is only used to
  2468. program the Chameleon itself, not a connected target.
  2469. @item @b{dlc5} The Xilinx Parallel cable III.
  2470. @item @b{flashlink} The ST Parallel cable.
  2471. @item @b{lattice} Lattice ispDOWNLOAD Cable
  2472. @item @b{old_amt_wiggler} The Wiggler configuration that comes with
  2473. some versions of
  2474. Amontec's Chameleon Programmer. The new version available from
  2475. the website uses the original Wiggler layout ('@var{wiggler}')
  2476. @item @b{triton} The parallel port adapter found on the
  2477. ``Karo Triton 1 Development Board''.
  2478. This is also the layout used by the HollyGates design
  2479. (see @uref{}).
  2480. @item @b{wiggler} The original Wiggler layout, also supported by
  2481. several clones, such as the Olimex ARM-JTAG
  2482. @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
  2483. @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
  2484. @end itemize
  2485. @end deffn
  2486. @deffn {Config Command} {parport_port} [port_number]
  2487. Display either the address of the I/O port
  2488. (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
  2489. If a parameter is provided, first switch to use that port.
  2490. This is a write-once setting.
  2491. When using PPDEV to access the parallel port, use the number of the parallel port:
  2492. @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
  2493. you may encounter a problem.
  2494. @end deffn
  2495. @deffn Command {parport_toggling_time} [nanoseconds]
  2496. Displays how many nanoseconds the hardware needs to toggle TCK;
  2497. the parport driver uses this value to obey the
  2498. @command{adapter_khz} configuration.
  2499. When the optional @var{nanoseconds} parameter is given,
  2500. that setting is changed before displaying the current value.
  2501. The default setting should work reasonably well on commodity PC hardware.
  2502. However, you may want to calibrate for your specific hardware.
  2503. @quotation Tip
  2504. To measure the toggling time with a logic analyzer or a digital storage
  2505. oscilloscope, follow the procedure below:
  2506. @example
  2507. > parport_toggling_time 1000
  2508. > adapter_khz 500
  2509. @end example
  2510. This sets the maximum JTAG clock speed of the hardware, but
  2511. the actual speed probably deviates from the requested 500 kHz.
  2512. Now, measure the time between the two closest spaced TCK transitions.
  2513. You can use @command{runtest 1000} or something similar to generate a
  2514. large set of samples.
  2515. Update the setting to match your measurement:
  2516. @example
  2517. > parport_toggling_time <measured nanoseconds>
  2518. @end example
  2519. Now the clock speed will be a better match for @command{adapter_khz rate}
  2520. commands given in OpenOCD scripts and event handlers.
  2521. You can do something similar with many digital multimeters, but note
  2522. that you'll probably need to run the clock continuously for several
  2523. seconds before it decides what clock rate to show. Adjust the
  2524. toggling time up or down until the measured clock rate is a good
  2525. match for the adapter_khz rate you specified; be conservative.
  2526. @end quotation
  2527. @end deffn
  2528. @deffn {Config Command} {parport_write_on_exit} (@option{on}|@option{off})
  2529. This will configure the parallel driver to write a known
  2530. cable-specific value to the parallel interface on exiting OpenOCD.
  2531. @end deffn
  2532. For example, the interface configuration file for a
  2533. classic ``Wiggler'' cable on LPT2 might look something like this:
  2534. @example
  2535. interface parport
  2536. parport_port 0x278
  2537. parport_cable wiggler
  2538. @end example
  2539. @end deffn
  2540. @deffn {Interface Driver} {presto}
  2541. ASIX PRESTO USB JTAG programmer.
  2542. @deffn {Config Command} {presto_serial} serial_string
  2543. Configures the USB serial number of the Presto device to use.
  2544. @end deffn
  2545. @end deffn
  2546. @deffn {Interface Driver} {rlink}
  2547. Raisonance RLink USB adapter
  2548. @end deffn
  2549. @deffn {Interface Driver} {usbprog}
  2550. usbprog is a freely programmable USB adapter.
  2551. @end deffn
  2552. @deffn {Interface Driver} {vsllink}
  2553. vsllink is part of Versaloon which is a versatile USB programmer.
  2554. @quotation Note
  2555. This defines quite a few driver-specific commands,
  2556. which are not currently documented here.
  2557. @end quotation
  2558. @end deffn
  2559. @deffn {Interface Driver} {hla}
  2560. This is a driver that supports multiple High Level Adapters.
  2561. This type of adapter does not expose some of the lower level api's
  2562. that OpenOCD would normally use to access the target.
  2563. Currently supported adapters include the ST STLINK and TI ICDI.
  2564. @deffn {Config Command} {hla_device_desc} description
  2565. Currently Not Supported.
  2566. @end deffn
  2567. @deffn {Config Command} {hla_serial} serial
  2568. Currently Not Supported.
  2569. @end deffn
  2570. @deffn {Config Command} {hla_layout} (@option{stlink}|@option{icdi})
  2571. Specifies the adapter layout to use.
  2572. @end deffn
  2573. @deffn {Config Command} {hla_vid_pid} vid pid
  2574. The vendor ID and product ID of the device.
  2575. @end deffn
  2576. @deffn {Config Command} {trace} source_clock_hz [output_file_path]
  2577. Enable SWO tracing (if supported). The source clock rate for the
  2578. trace port must be specified, this is typically the CPU clock rate. If
  2579. the optional output file is specified then raw trace data is appended
  2580. to the file, and the file is created if it does not exist.
  2581. @end deffn
  2582. @end deffn
  2583. @deffn {Interface Driver} {opendous}
  2584. opendous-jtag is a freely programmable USB adapter.
  2585. @end deffn
  2586. @deffn {Interface Driver} {ulink}
  2587. This is the Keil ULINK v1 JTAG debugger.
  2588. @end deffn
  2589. @deffn {Interface Driver} {ZY1000}
  2590. This is the Zylin ZY1000 JTAG debugger.
  2591. @end deffn
  2592. @quotation Note
  2593. This defines some driver-specific commands,
  2594. which are not currently documented here.
  2595. @end quotation
  2596. @deffn Command power [@option{on}|@option{off}]
  2597. Turn power switch to target on/off.
  2598. No arguments: print status.
  2599. @end deffn
  2600. @deffn {Interface Driver} {bcm2835gpio}
  2601. This SoC is present in Raspberry Pi which is a cheap single-board computer
  2602. exposing some GPIOs on its expansion header.
  2603. The driver accesses memory-mapped GPIO peripheral registers directly
  2604. for maximum performance, but the only possible race condition is for
  2605. the pins' modes/muxing (which is highly unlikely), so it should be
  2606. able to coexist nicely with both sysfs bitbanging and various
  2607. peripherals' kernel drivers. The driver restores the previous
  2608. configuration on exit.
  2609. See @file{interface/raspberrypi-native.cfg} for a sample config and
  2610. pinout.
  2611. @end deffn
  2612. @section Transport Configuration
  2613. @cindex Transport
  2614. As noted earlier, depending on the version of OpenOCD you use,
  2615. and the debug adapter you are using,
  2616. several transports may be available to
  2617. communicate with debug targets (or perhaps to program flash memory).
  2618. @deffn Command {transport list}
  2619. displays the names of the transports supported by this
  2620. version of OpenOCD.
  2621. @end deffn
  2622. @deffn Command {transport select} transport_name
  2623. Select which of the supported transports to use in this OpenOCD session.
  2624. The transport must be supported by the debug adapter hardware and by the
  2625. version of OpenOCD you are using (including the adapter's driver).
  2626. No arguments: returns name of session's selected transport.
  2627. @end deffn
  2628. @subsection JTAG Transport
  2629. @cindex JTAG
  2630. JTAG is the original transport supported by OpenOCD, and most
  2631. of the OpenOCD commands support it.
  2632. JTAG transports expose a chain of one or more Test Access Points (TAPs),
  2633. each of which must be explicitly declared.
  2634. JTAG supports both debugging and boundary scan testing.
  2635. Flash programming support is built on top of debug support.
  2636. @subsection SWD Transport
  2637. @cindex SWD
  2638. @cindex Serial Wire Debug
  2639. SWD (Serial Wire Debug) is an ARM-specific transport which exposes one
  2640. Debug Access Point (DAP, which must be explicitly declared.
  2641. (SWD uses fewer signal wires than JTAG.)
  2642. SWD is debug-oriented, and does not support boundary scan testing.
  2643. Flash programming support is built on top of debug support.
  2644. (Some processors support both JTAG and SWD.)
  2645. @deffn Command {swd newdap} ...
  2646. Declares a single DAP which uses SWD transport.
  2647. Parameters are currently the same as "jtag newtap" but this is
  2648. expected to change.
  2649. @end deffn
  2650. @deffn Command {swd wcr trn prescale}
  2651. Updates TRN (turnaraound delay) and prescaling.fields of the
  2652. Wire Control Register (WCR).
  2653. No parameters: displays current settings.
  2654. @end deffn
  2655. @subsection CMSIS-DAP Transport
  2656. @cindex CMSIS-DAP
  2657. CMSIS-DAP is an ARM-specific transport that is used to connect to
  2658. compilant debuggers.
  2659. @subsection SPI Transport
  2660. @cindex SPI
  2661. @cindex Serial Peripheral Interface
  2662. The Serial Peripheral Interface (SPI) is a general purpose transport
  2663. which uses four wire signaling. Some processors use it as part of a
  2664. solution for flash programming.
  2665. @anchor{jtagspeed}
  2666. @section JTAG Speed
  2667. JTAG clock setup is part of system setup.
  2668. It @emph{does not belong with interface setup} since any interface
  2669. only knows a few of the constraints for the JTAG clock speed.
  2670. Sometimes the JTAG speed is
  2671. changed during the target initialization process: (1) slow at
  2672. reset, (2) program the CPU clocks, (3) run fast.
  2673. Both the "slow" and "fast" clock rates are functions of the
  2674. oscillators used, the chip, the board design, and sometimes
  2675. power management software that may be active.
  2676. The speed used during reset, and the scan chain verification which
  2677. follows reset, can be adjusted using a @code{reset-start}
  2678. target event handler.
  2679. It can then be reconfigured to a faster speed by a
  2680. @code{reset-init} target event handler after it reprograms those
  2681. CPU clocks, or manually (if something else, such as a boot loader,
  2682. sets up those clocks).
  2683. @xref{targetevents,,Target Events}.
  2684. When the initial low JTAG speed is a chip characteristic, perhaps
  2685. because of a required oscillator speed, provide such a handler
  2686. in the target config file.
  2687. When that speed is a function of a board-specific characteristic
  2688. such as which speed oscillator is used, it belongs in the board
  2689. config file instead.
  2690. In both cases it's safest to also set the initial JTAG clock rate
  2691. to that same slow speed, so that OpenOCD never starts up using a
  2692. clock speed that's faster than the scan chain can support.
  2693. @example
  2694. jtag_rclk 3000
  2695. $_TARGET.cpu configure -event reset-start @{ jtag_rclk 3000 @}
  2696. @end example
  2697. If your system supports adaptive clocking (RTCK), configuring
  2698. JTAG to use that is probably the most robust approach.
  2699. However, it introduces delays to synchronize clocks; so it
  2700. may not be the fastest solution.
  2701. @b{NOTE:} Script writers should consider using @command{jtag_rclk}
  2702. instead of @command{adapter_khz}, but only for (ARM) cores and boards
  2703. which support adaptive clocking.
  2704. @deffn {Command} adapter_khz max_speed_kHz
  2705. A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
  2706. JTAG interfaces usually support a limited number of
  2707. speeds. The speed actually used won't be faster
  2708. than the speed specified.
  2709. Chip data sheets generally include a top JTAG clock rate.
  2710. The actual rate is often a function of a CPU core clock,
  2711. and is normally less than that peak rate.
  2712. For example, most ARM cores accept at most one sixth of the CPU clock.
  2713. Speed 0 (khz) selects RTCK method.
  2714. @xref{faqrtck,,FAQ RTCK}.
  2715. If your system uses RTCK, you won't need to change the
  2716. JTAG clocking after setup.
  2717. Not all interfaces, boards, or targets support ``rtck''.
  2718. If the interface device can not
  2719. support it, an error is returned when you try to use RTCK.
  2720. @end deffn
  2721. @defun jtag_rclk fallback_speed_kHz
  2722. @cindex adaptive clocking
  2723. @cindex RTCK
  2724. This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
  2725. If that fails (maybe the interface, board, or target doesn't
  2726. support it), falls back to the specified frequency.
  2727. @example
  2728. # Fall back to 3mhz if RTCK is not supported
  2729. jtag_rclk 3000
  2730. @end example
  2731. @end defun
  2732. @node Reset Configuration
  2733. @chapter Reset Configuration
  2734. @cindex Reset Configuration
  2735. Every system configuration may require a different reset
  2736. configuration. This can also be quite confusing.
  2737. Resets also interact with @var{reset-init} event handlers,
  2738. which do things like setting up clocks and DRAM, and
  2739. JTAG clock rates. (@xref{jtagspeed,,JTAG Speed}.)
  2740. They can also interact with JTAG routers.
  2741. Please see the various board files for examples.
  2742. @quotation Note
  2743. To maintainers and integrators:
  2744. Reset configuration touches several things at once.
  2745. Normally the board configuration file
  2746. should define it and assume that the JTAG adapter supports
  2747. everything that's wired up to the board's JTAG connector.
  2748. However, the target configuration file could also make note
  2749. of something the silicon vendor has done inside the chip,
  2750. which will be true for most (or all) boards using that chip.
  2751. And when the JTAG adapter doesn't support everything, the
  2752. user configuration file will need to override parts of
  2753. the reset configuration provided by other files.
  2754. @end quotation
  2755. @section Types of Reset
  2756. There are many kinds of reset possible through JTAG, but
  2757. they may not all work with a given board and adapter.
  2758. That's part of why reset configuration can be error prone.
  2759. @itemize @bullet
  2760. @item
  2761. @emph{System Reset} ... the @emph{SRST} hardware signal
  2762. resets all chips connected to the JTAG adapter, such as processors,
  2763. power management chips, and I/O controllers. Normally resets triggered
  2764. with this signal behave exactly like pressing a RESET button.
  2765. @item
  2766. @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
  2767. just the TAP controllers connected to the JTAG adapter.
  2768. Such resets should not be visible to the rest of the system; resetting a
  2769. device's TAP controller just puts that controller into a known state.
  2770. @item
  2771. @emph{Emulation Reset} ... many devices can be reset through JTAG
  2772. commands. These resets are often distinguishable from system
  2773. resets, either explicitly (a "reset reason" register says so)
  2774. or implicitly (not all parts of the chip get reset).
  2775. @item
  2776. @emph{Other Resets} ... system-on-chip devices often support
  2777. several other types of reset.
  2778. You may need to arrange that a watchdog timer stops
  2779. while debugging, preventing a watchdog reset.
  2780. There may be individual module resets.
  2781. @end itemize
  2782. In the best case, OpenOCD can hold SRST, then reset
  2783. the TAPs via TRST and send commands through JTAG to halt the
  2784. CPU at the reset vector before the 1st instruction is executed.
  2785. Then when it finally releases the SRST signal, the system is
  2786. halted under debugger control before any code has executed.
  2787. This is the behavior required to support the @command{reset halt}
  2788. and @command{reset init} commands; after @command{reset init} a
  2789. board-specific script might do things like setting up DRAM.
  2790. (@xref{resetcommand,,Reset Command}.)
  2791. @anchor{srstandtrstissues}
  2792. @section SRST and TRST Issues
  2793. Because SRST and TRST are hardware signals, they can have a
  2794. variety of system-specific constraints. Some of the most
  2795. common issues are:
  2796. @itemize @bullet
  2797. @item @emph{Signal not available} ... Some boards don't wire
  2798. SRST or TRST to the JTAG connector. Some JTAG adapters don't
  2799. support such signals even if they are wired up.
  2800. Use the @command{reset_config} @var{signals} options to say
  2801. when either of those signals is not connected.
  2802. When SRST is not available, your code might not be able to rely
  2803. on controllers having been fully reset during code startup.
  2804. Missing TRST is not a problem, since JTAG-level resets can
  2805. be triggered using with TMS signaling.
  2806. @item @emph{Signals shorted} ... Sometimes a chip, board, or
  2807. adapter will connect SRST to TRST, instead of keeping them separate.
  2808. Use the @command{reset_config} @var{combination} options to say
  2809. when those signals aren't properly independent.
  2810. @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
  2811. delay circuit, reset supervisor, or on-chip features can extend
  2812. the effect of a JTAG adapter's reset for some time after the adapter
  2813. stops issuing the reset. For example, there may be chip or board
  2814. requirements that all reset pulses last for at least a
  2815. certain amount of time; and reset buttons commonly have
  2816. hardware debouncing.
  2817. Use the @command{adapter_nsrst_delay} and @command{jtag_ntrst_delay}
  2818. commands to say when extra delays are needed.
  2819. @item @emph{Drive type} ... Reset lines often have a pullup
  2820. resistor, letting the JTAG interface treat them as open-drain
  2821. signals. But that's not a requirement, so the adapter may need
  2822. to use push/pull output drivers.
  2823. Also, with weak pullups it may be advisable to drive
  2824. signals to both levels (push/pull) to minimize rise times.
  2825. Use the @command{reset_config} @var{trst_type} and
  2826. @var{srst_type} parameters to say how to drive reset signals.
  2827. @item @emph{Special initialization} ... Targets sometimes need
  2828. special JTAG initialization sequences to handle chip-specific
  2829. issues (not limited to errata).
  2830. For example, certain JTAG commands might need to be issued while
  2831. the system as a whole is in a reset state (SRST active)
  2832. but the JTAG scan chain is usable (TRST inactive).
  2833. Many systems treat combined assertion of SRST and TRST as a
  2834. trigger for a harder reset than SRST alone.
  2835. Such custom reset handling is discussed later in this chapter.
  2836. @end itemize
  2837. There can also be other issues.
  2838. Some devices don't fully conform to the JTAG specifications.
  2839. Trivial system-specific differences are common, such as
  2840. SRST and TRST using slightly different names.
  2841. There are also vendors who distribute key JTAG documentation for
  2842. their chips only to developers who have signed a Non-Disclosure
  2843. Agreement (NDA).
  2844. Sometimes there are chip-specific extensions like a requirement to use
  2845. the normally-optional TRST signal (precluding use of JTAG adapters which
  2846. don't pass TRST through), or needing extra steps to complete a TAP reset.
  2847. In short, SRST and especially TRST handling may be very finicky,
  2848. needing to cope with both architecture and board specific constraints.
  2849. @section Commands for Handling Resets
  2850. @deffn {Command} adapter_nsrst_assert_width milliseconds
  2851. Minimum amount of time (in milliseconds) OpenOCD should wait
  2852. after asserting nSRST (active-low system reset) before
  2853. allowing it to be deasserted.
  2854. @end deffn
  2855. @deffn {Command} adapter_nsrst_delay milliseconds
  2856. How long (in milliseconds) OpenOCD should wait after deasserting
  2857. nSRST (active-low system reset) before starting new JTAG operations.
  2858. When a board has a reset button connected to SRST line it will
  2859. probably have hardware debouncing, implying you should use this.
  2860. @end deffn
  2861. @deffn {Command} jtag_ntrst_assert_width milliseconds
  2862. Minimum amount of time (in milliseconds) OpenOCD should wait
  2863. after asserting nTRST (active-low JTAG TAP reset) before
  2864. allowing it to be deasserted.
  2865. @end deffn
  2866. @deffn {Command} jtag_ntrst_delay milliseconds
  2867. How long (in milliseconds) OpenOCD should wait after deasserting
  2868. nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
  2869. @end deffn
  2870. @deffn {Command} reset_config mode_flag ...
  2871. This command displays or modifies the reset configuration
  2872. of your combination of JTAG board and target in target
  2873. configuration scripts.
  2874. Information earlier in this section describes the kind of problems
  2875. the command is intended to address (@pxref{srstandtrstissues,,SRST and TRST Issues}).
  2876. As a rule this command belongs only in board config files,
  2877. describing issues like @emph{board doesn't connect TRST};
  2878. or in user config files, addressing limitations derived
  2879. from a particular combination of interface and board.
  2880. (An unlikely example would be using a TRST-only adapter
  2881. with a board that only wires up SRST.)
  2882. The @var{mode_flag} options can be specified in any order, but only one
  2883. of each type -- @var{signals}, @var{combination}, @var{gates},
  2884. @var{trst_type}, @var{srst_type} and @var{connect_type}
  2885. -- may be specified at a time.
  2886. If you don't provide a new value for a given type, its previous
  2887. value (perhaps the default) is unchanged.
  2888. For example, this means that you don't need to say anything at all about
  2889. TRST just to declare that if the JTAG adapter should want to drive SRST,
  2890. it must explicitly be driven high (@option{srst_push_pull}).
  2891. @itemize
  2892. @item
  2893. @var{signals} can specify which of the reset signals are connected.
  2894. For example, If the JTAG interface provides SRST, but the board doesn't
  2895. connect that signal properly, then OpenOCD can't use it.
  2896. Possible values are @option{none} (the default), @option{trst_only},
  2897. @option{srst_only} and @option{trst_and_srst}.
  2898. @quotation Tip
  2899. If your board provides SRST and/or TRST through the JTAG connector,
  2900. you must declare that so those signals can be used.
  2901. @end quotation
  2902. @item
  2903. The @var{combination} is an optional value specifying broken reset
  2904. signal implementations.
  2905. The default behaviour if no option given is @option{separate},
  2906. indicating everything behaves normally.
  2907. @option{srst_pulls_trst} states that the
  2908. test logic is reset together with the reset of the system (e.g. NXP
  2909. LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
  2910. the system is reset together with the test logic (only hypothetical, I
  2911. haven't seen hardware with such a bug, and can be worked around).
  2912. @option{combined} implies both @option{srst_pulls_trst} and
  2913. @option{trst_pulls_srst}.
  2914. @item
  2915. The @var{gates} tokens control flags that describe some cases where
  2916. JTAG may be unvailable during reset.
  2917. @option{srst_gates_jtag} (default)
  2918. indicates that asserting SRST gates the
  2919. JTAG clock. This means that no communication can happen on JTAG
  2920. while SRST is asserted.
  2921. Its converse is @option{srst_nogate}, indicating that JTAG commands
  2922. can safely be issued while SRST is active.
  2923. @item
  2924. The @var{connect_type} tokens control flags that describe some cases where
  2925. SRST is asserted while connecting to the target. @option{srst_nogate}
  2926. is required to use this option.
  2927. @option{connect_deassert_srst} (default)
  2928. indicates that SRST will not be asserted while connecting to the target.
  2929. Its converse is @option{connect_assert_srst}, indicating that SRST will
  2930. be asserted before any target connection.
  2931. Only some targets support this feature, STM32 and STR9 are examples.
  2932. This feature is useful if you are unable to connect to your target due
  2933. to incorrect options byte config or illegal program execution.
  2934. @end itemize
  2935. The optional @var{trst_type} and @var{srst_type} parameters allow the
  2936. driver mode of each reset line to be specified. These values only affect
  2937. JTAG interfaces with support for different driver modes, like the Amontec
  2938. JTAGkey and JTAG Accelerator. Also, they are necessarily ignored if the
  2939. relevant signal (TRST or SRST) is not connected.
  2940. @itemize
  2941. @item
  2942. Possible @var{trst_type} driver modes for the test reset signal (TRST)
  2943. are the default @option{trst_push_pull}, and @option{trst_open_drain}.
  2944. Most boards connect this signal to a pulldown, so the JTAG TAPs
  2945. never leave reset unless they are hooked up to a JTAG adapter.
  2946. @item
  2947. Possible @var{srst_type} driver modes for the system reset signal (SRST)
  2948. are the default @option{srst_open_drain}, and @option{srst_push_pull}.
  2949. Most boards connect this signal to a pullup, and allow the
  2950. signal to be pulled low by various events including system
  2951. powerup and pressing a reset button.
  2952. @end itemize
  2953. @end deffn
  2954. @section Custom Reset Handling
  2955. @cindex events
  2956. OpenOCD has several ways to help support the various reset
  2957. mechanisms provided by chip and board vendors.
  2958. The commands shown in the previous section give standard parameters.
  2959. There are also @emph{event handlers} associated with TAPs or Targets.
  2960. Those handlers are Tcl procedures you can provide, which are invoked
  2961. at particular points in the reset sequence.
  2962. @emph{When SRST is not an option} you must set
  2963. up a @code{reset-assert} event handler for your target.
  2964. For example, some JTAG adapters don't include the SRST signal;
  2965. and some boards have multiple targets, and you won't always
  2966. want to reset everything at once.
  2967. After configuring those mechanisms, you might still
  2968. find your board doesn't start up or reset correctly.
  2969. For example, maybe it needs a slightly different sequence
  2970. of SRST and/or TRST manipulations, because of quirks that
  2971. the @command{reset_config} mechanism doesn't address;
  2972. or asserting both might trigger a stronger reset, which
  2973. needs special attention.
  2974. Experiment with lower level operations, such as @command{jtag_reset}
  2975. and the @command{jtag arp_*} operations shown here,
  2976. to find a sequence of operations that works.
  2977. @xref{JTAG Commands}.
  2978. When you find a working sequence, it can be used to override
  2979. @command{jtag_init}, which fires during OpenOCD startup
  2980. (@pxref{configurationstage,,Configuration Stage});
  2981. or @command{init_reset}, which fires during reset processing.
  2982. You might also want to provide some project-specific reset
  2983. schemes. For example, on a multi-target board the standard
  2984. @command{reset} command would reset all targets, but you
  2985. may need the ability to reset only one target at time and
  2986. thus want to avoid using the board-wide SRST signal.
  2987. @deffn {Overridable Procedure} init_reset mode
  2988. This is invoked near the beginning of the @command{reset} command,
  2989. usually to provide as much of a cold (power-up) reset as practical.
  2990. By default it is also invoked from @command{jtag_init} if
  2991. the scan chain does not respond to pure JTAG operations.
  2992. The @var{mode} parameter is the parameter given to the
  2993. low level reset command (@option{halt},
  2994. @option{init}, or @option{run}), @option{setup},
  2995. or potentially some other value.
  2996. The default implementation just invokes @command{jtag arp_init-reset}.
  2997. Replacements will normally build on low level JTAG
  2998. operations such as @command{jtag_reset}.
  2999. Operations here must not address individual TAPs
  3000. (or their associated targets)
  3001. until the JTAG scan chain has first been verified to work.
  3002. Implementations must have verified the JTAG scan chain before
  3003. they return.
  3004. This is done by calling @command{jtag arp_init}
  3005. (or @command{jtag arp_init-reset}).
  3006. @end deffn
  3007. @deffn Command {jtag arp_init}
  3008. This validates the scan chain using just the four
  3009. standard JTAG signals (TMS, TCK, TDI, TDO).
  3010. It starts by issuing a JTAG-only reset.
  3011. Then it performs checks to verify that the scan chain configuration
  3012. matches the TAPs it can observe.
  3013. Those checks include checking IDCODE values for each active TAP,
  3014. and verifying the length of their instruction registers using
  3015. TAP @code{-ircapture} and @code{-irmask} values.
  3016. If these tests all pass, TAP @code{setup} events are
  3017. issued to all TAPs with handlers for that event.
  3018. @end deffn
  3019. @deffn Command {jtag arp_init-reset}
  3020. This uses TRST and SRST to try resetting
  3021. everything on the JTAG scan chain
  3022. (and anything else connected to SRST).
  3023. It then invokes the logic of @command{jtag arp_init}.
  3024. @end deffn
  3025. @node TAP Declaration
  3026. @chapter TAP Declaration
  3027. @cindex TAP declaration
  3028. @cindex TAP configuration
  3029. @emph{Test Access Ports} (TAPs) are the core of JTAG.
  3030. TAPs serve many roles, including:
  3031. @itemize @bullet
  3032. @item @b{Debug Target} A CPU TAP can be used as a GDB debug target.
  3033. @item @b{Flash Programming} Some chips program the flash directly via JTAG.
  3034. Others do it indirectly, making a CPU do it.
  3035. @item @b{Program Download} Using the same CPU support GDB uses,
  3036. you can initialize a DRAM controller, download code to DRAM, and then
  3037. start running that code.
  3038. @item @b{Boundary Scan} Most chips support boundary scan, which
  3039. helps test for board assembly problems like solder bridges
  3040. and missing connections.
  3041. @end itemize
  3042. OpenOCD must know about the active TAPs on your board(s).
  3043. Setting up the TAPs is the core task of your configuration files.
  3044. Once those TAPs are set up, you can pass their names to code
  3045. which sets up CPUs and exports them as GDB targets,
  3046. probes flash memory, performs low-level JTAG operations, and more.
  3047. @section Scan Chains
  3048. @cindex scan chain
  3049. TAPs are part of a hardware @dfn{scan chain},
  3050. which is a daisy chain of TAPs.
  3051. They also need to be added to
  3052. OpenOCD's software mirror of that hardware list,
  3053. giving each member a name and associating other data with it.
  3054. Simple scan chains, with a single TAP, are common in
  3055. systems with a single microcontroller or microprocessor.
  3056. More complex chips may have several TAPs internally.
  3057. Very complex scan chains might have a dozen or more TAPs:
  3058. several in one chip, more in the next, and connecting
  3059. to other boards with their own chips and TAPs.
  3060. You can display the list with the @command{scan_chain} command.
  3061. (Don't confuse this with the list displayed by the @command{targets}
  3062. command, presented in the next chapter.
  3063. That only displays TAPs for CPUs which are configured as
  3064. debugging targets.)
  3065. Here's what the scan chain might look like for a chip more than one TAP:
  3066. @verbatim
  3067. TapName Enabled IdCode Expected IrLen IrCap IrMask
  3068. -- ------------------ ------- ---------- ---------- ----- ----- ------
  3069. 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0x01 0x03
  3070. 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x01 0x0f
  3071. 2 omap5912.unknown Y 0x00000000 0x00000000 8 0x01 0x03
  3072. @end verbatim
  3073. OpenOCD can detect some of that information, but not all
  3074. of it. @xref{autoprobing,,Autoprobing}.
  3075. Unfortunately, those TAPs can't always be autoconfigured,
  3076. because not all devices provide good support for that.
  3077. JTAG doesn't require supporting IDCODE instructions, and
  3078. chips with JTAG routers may not link TAPs into the chain
  3079. until they are told to do so.
  3080. The configuration mechanism currently supported by OpenOCD
  3081. requires explicit configuration of all TAP devices using
  3082. @command{jtag newtap} commands, as detailed later in this chapter.
  3083. A command like this would declare one tap and name it @code{chip1.cpu}:
  3084. @example
  3085. jtag newtap chip1 cpu -irlen 4 -expected-id 0x3ba00477
  3086. @end example
  3087. Each target configuration file lists the TAPs provided
  3088. by a given chip.
  3089. Board configuration files combine all the targets on a board,
  3090. and so forth.
  3091. Note that @emph{the order in which TAPs are declared is very important.}
  3092. That declaration order must match the order in the JTAG scan chain,
  3093. both inside a single chip and between them.
  3094. @xref{faqtaporder,,FAQ TAP Order}.
  3095. For example, the ST Microsystems STR912 chip has
  3096. three separate TAPs@footnote{See the ST
  3097. document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
  3098. 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
  3099. @url{}}.
  3100. To configure those taps, @file{target/str912.cfg}
  3101. includes commands something like this:
  3102. @example
  3103. jtag newtap str912 flash ... params ...
  3104. jtag newtap str912 cpu ... params ...
  3105. jtag newtap str912 bs ... params ...
  3106. @end example
  3107. Actual config files typically use a variable such as @code{$_CHIPNAME}
  3108. instead of literals like @option{str912}, to support more than one chip
  3109. of each type. @xref{Config File Guidelines}.
  3110. @deffn Command {jtag names}
  3111. Returns the names of all current TAPs in the scan chain.
  3112. Use @command{jtag cget} or @command{jtag tapisenabled}
  3113. to examine attributes and state of each TAP.
  3114. @example
  3115. foreach t [jtag names] @{
  3116. puts [format "TAP: %s\n" $t]
  3117. @}
  3118. @end example
  3119. @end deffn
  3120. @deffn Command {scan_chain}
  3121. Displays the TAPs in the scan chain configuration,
  3122. and their status.
  3123. The set of TAPs listed by this command is fixed by
  3124. exiting the OpenOCD configuration stage,
  3125. but systems with a JTAG router can
  3126. enable or disable TAPs dynamically.
  3127. @end deffn
  3128. @c FIXME! "jtag cget" should be able to return all TAP
  3129. @c attributes, like "$target_name cget" does for targets.
  3130. @c Probably want "jtag eventlist", and a "tap-reset" event
  3131. @c (on entry to RESET state).
  3132. @section TAP Names
  3133. @cindex dotted name
  3134. When TAP objects are declared with @command{jtag newtap},
  3135. a @dfn{} is created for the TAP, combining the
  3136. name of a module (usually a chip) and a label for the TAP.
  3137. For example: @code{xilinx.tap}, @code{str912.flash},
  3138. @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
  3139. Many other commands use that to manipulate or
  3140. refer to the TAP. For example, CPU configuration uses the
  3141. name, as does declaration of NAND or NOR flash banks.
  3142. The components of a dotted name should follow ``C'' symbol
  3143. name rules: start with an alphabetic character, then numbers
  3144. and underscores are OK; while others (including dots!) are not.
  3145. @section TAP Declaration Commands
  3146. @c shouldn't this be(come) a {Config Command}?
  3147. @deffn Command {jtag newtap} chipname tapname configparams...
  3148. Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
  3149. and configured according to the various @var{configparams}.
  3150. The @var{chipname} is a symbolic name for the chip.
  3151. Conventionally target config files use @code{$_CHIPNAME},
  3152. defaulting to the model name given by the chip vendor but
  3153. overridable.
  3154. @cindex TAP naming convention
  3155. The @var{tapname} reflects the role of that TAP,
  3156. and should follow this convention:
  3157. @itemize @bullet
  3158. @item @code{bs} -- For boundary scan if this is a separate TAP;
  3159. @item @code{cpu} -- The main CPU of the chip, alternatively
  3160. @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
  3161. @code{arm1} and @code{arm2} on chips with two ARMs, and so forth;
  3162. @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
  3163. @item @code{flash} -- If the chip has a flash TAP, like the str912;
  3164. @item @code{jrc} -- For JTAG route controller (example: the ICEPick modules
  3165. on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
  3166. @item @code{tap} -- Should be used only for FPGA- or CPLD-like devices
  3167. with a single TAP;
  3168. @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
  3169. @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
  3170. For example, the Freescale i.MX31 has a SDMA (Smart DMA) with
  3171. a JTAG TAP; that TAP should be named @code{sdma}.
  3172. @end itemize
  3173. Every TAP requires at least the following @var{configparams}:
  3174. @itemize @bullet
  3175. @item @code{-irlen} @var{NUMBER}
  3176. @*The length in bits of the
  3177. instruction register, such as 4 or 5 bits.
  3178. @end itemize
  3179. A TAP may also provide optional @var{configparams}:
  3180. @itemize @bullet
  3181. @item @code{-disable} (or @code{-enable})
  3182. @*Use the @code{-disable} parameter to flag a TAP which is not
  3183. linked into the scan chain after a reset using either TRST
  3184. or the JTAG state machine's @sc{reset} state.
  3185. You may use @code{-enable} to highlight the default state
  3186. (the TAP is linked in).
  3187. @xref{enablinganddisablingtaps,,Enabling and Disabling TAPs}.
  3188. @item @code{-expected-id} @var{NUMBER}
  3189. @*A non-zero @var{number} represents a 32-bit IDCODE
  3190. which you expect to find when the scan chain is examined.
  3191. These codes are not required by all JTAG devices.
  3192. @emph{Repeat the option} as many times as required if more than one
  3193. ID code could appear (for example, multiple versions).
  3194. Specify @var{number} as zero to suppress warnings about IDCODE
  3195. values that were found but not included in the list.
  3196. Provide this value if at all possible, since it lets OpenOCD
  3197. tell when the scan chain it sees isn't right. These values
  3198. are provided in vendors' chip documentation, usually a technical
  3199. reference manual. Sometimes you may need to probe the JTAG
  3200. hardware to find these values.
  3201. @xref{autoprobing,,Autoprobing}.
  3202. @item @code{-ignore-version}
  3203. @*Specify this to ignore the JTAG version field in the @code{-expected-id}
  3204. option. When vendors put out multiple versions of a chip, or use the same
  3205. JTAG-level ID for several largely-compatible chips, it may be more practical
  3206. to ignore the version field than to update config files to handle all of
  3207. the various chip IDs. The version field is defined as bit 28-31 of the IDCODE.
  3208. @item @code{-ircapture} @var{NUMBER}
  3209. @*The bit pattern loaded by the TAP into the JTAG shift register
  3210. on entry to the @sc{ircapture} state, such as 0x01.
  3211. JTAG requires the two LSBs of this value to be 01.
  3212. By default, @code{-ircapture} and @code{-irmask} are set
  3213. up to verify that two-bit value. You may provide
  3214. additional bits if you know them, or indicate that
  3215. a TAP doesn't conform to the JTAG specification.
  3216. @item @code{-irmask} @var{NUMBER}
  3217. @*A mask used with @code{-ircapture}
  3218. to verify that instruction scans work correctly.
  3219. Such scans are not used by OpenOCD except to verify that
  3220. there seems to be no problems with JTAG scan chain operations.
  3221. @end itemize
  3222. @end deffn
  3223. @section Other TAP commands
  3224. @deffn Command {jtag cget} @option{-event} event_name
  3225. @deffnx Command {jtag configure} @option{-event} event_name handler
  3226. At this writing this TAP attribute
  3227. mechanism is used only for event handling.
  3228. (It is not a direct analogue of the @code{cget}/@code{configure}
  3229. mechanism for debugger targets.)
  3230. See the next section for information about the available events.
  3231. The @code{configure} subcommand assigns an event handler,
  3232. a TCL string which is evaluated when the event is triggered.
  3233. The @code{cget} subcommand returns that handler.
  3234. @end deffn
  3235. @section TAP Events
  3236. @cindex events
  3237. @cindex TAP events
  3238. OpenOCD includes two event mechanisms.
  3239. The one presented here applies to all JTAG TAPs.
  3240. The other applies to debugger targets,
  3241. which are associated with certain TAPs.
  3242. The TAP events currently defined are:
  3243. @itemize @bullet
  3244. @item @b{post-reset}
  3245. @* The TAP has just completed a JTAG reset.
  3246. The tap may still be in the JTAG @sc{reset} state.
  3247. Handlers for these events might perform initialization sequences
  3248. such as issuing TCK cycles, TMS sequences to ensure
  3249. exit from the ARM SWD mode, and more.
  3250. Because the scan chain has not yet been verified, handlers for these events
  3251. @emph{should not issue commands which scan the JTAG IR or DR registers}
  3252. of any particular target.
  3253. @b{NOTE:} As this is written (September 2009), nothing prevents such access.
  3254. @item @b{setup}
  3255. @* The scan chain has been reset and verified.
  3256. This handler may enable TAPs as needed.
  3257. @item @b{tap-disable}
  3258. @* The TAP needs to be disabled. This handler should
  3259. implement @command{jtag tapdisable}
  3260. by issuing the relevant JTAG commands.
  3261. @item @b{tap-enable}
  3262. @* The TAP needs to be enabled. This handler should
  3263. implement @command{jtag tapenable}
  3264. by issuing the relevant JTAG commands.
  3265. @end itemize
  3266. If you need some action after each JTAG reset which isn't actually
  3267. specific to any TAP (since you can't yet trust the scan chain's
  3268. contents to be accurate), you might:
  3269. @example
  3270. jtag configure CHIP.jrc -event post-reset @{
  3271. echo "JTAG Reset done"
  3272. ... non-scan jtag operations to be done after reset
  3273. @}
  3274. @end example
  3275. @anchor{enablinganddisablingtaps}
  3276. @section Enabling and Disabling TAPs
  3277. @cindex JTAG Route Controller
  3278. @cindex jrc
  3279. In some systems, a @dfn{JTAG Route Controller} (JRC)
  3280. is used to enable and/or disable specific JTAG TAPs.
  3281. Many ARM-based chips from Texas Instruments include
  3282. an ``ICEPick'' module, which is a JRC.
  3283. Such chips include DaVinci and OMAP3 processors.
  3284. A given TAP may not be visible until the JRC has been
  3285. told to link it into the scan chain; and if the JRC
  3286. has been told to unlink that TAP, it will no longer
  3287. be visible.
  3288. Such routers address problems that JTAG ``bypass mode''
  3289. ignores, such as:
  3290. @itemize
  3291. @item The scan chain can only go as fast as its slowest TAP.
  3292. @item Having many TAPs slows instruction scans, since all
  3293. TAPs receive new instructions.
  3294. @item TAPs in the scan chain must be powered up, which wastes
  3295. power and prevents debugging some power management mechanisms.
  3296. @end itemize
  3297. The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
  3298. as implied by the existence of JTAG routers.
  3299. However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
  3300. does include a kind of JTAG router functionality.
  3301. @c (a) currently the event handlers don't seem to be able to
  3302. @c fail in a way that could lead to no-change-of-state.
  3303. In OpenOCD, tap enabling/disabling is invoked by the Tcl commands
  3304. shown below, and is implemented using TAP event handlers.
  3305. So for example, when defining a TAP for a CPU connected to
  3306. a JTAG router, your @file{target.cfg} file
  3307. should define TAP event handlers using
  3308. code that looks something like this:
  3309. @example
  3310. jtag configure CHIP.cpu -event tap-enable @{
  3311. ... jtag operations using CHIP.jrc
  3312. @}
  3313. jtag configure CHIP.cpu -event tap-disable @{
  3314. ... jtag operations using CHIP.jrc
  3315. @}
  3316. @end example
  3317. Then you might want that CPU's TAP enabled almost all the time:
  3318. @example
  3319. jtag configure $CHIP.jrc -event setup "jtag tapenable $CHIP.cpu"
  3320. @end example
  3321. Note how that particular setup event handler declaration
  3322. uses quotes to evaluate @code{$CHIP} when the event is configured.
  3323. Using brackets @{ @} would cause it to be evaluated later,
  3324. at runtime, when it might have a different value.
  3325. @deffn Command {jtag tapdisable}
  3326. If necessary, disables the tap
  3327. by sending it a @option{tap-disable} event.
  3328. Returns the string "1" if the tap
  3329. specified by @var{} is enabled,
  3330. and "0" if it is disabled.
  3331. @end deffn
  3332. @deffn Command {jtag tapenable}
  3333. If necessary, enables the tap
  3334. by sending it a @option{tap-enable} event.
  3335. Returns the string "1" if the tap
  3336. specified by @var{} is enabled,
  3337. and "0" if it is disabled.
  3338. @end deffn
  3339. @deffn Command {jtag tapisenabled}
  3340. Returns the string "1" if the tap
  3341. specified by @var{} is enabled,
  3342. and "0" if it is disabled.
  3343. @quotation Note
  3344. Humans will find the @command{scan_chain} command more helpful
  3345. for querying the state of the JTAG taps.
  3346. @end quotation
  3347. @end deffn
  3348. @anchor{autoprobing}
  3349. @section Autoprobing
  3350. @cindex autoprobe
  3351. @cindex JTAG autoprobe
  3352. TAP configuration is the first thing that needs to be done
  3353. after interface and reset configuration. Sometimes it's
  3354. hard finding out what TAPs exist, or how they are identified.
  3355. Vendor documentation is not always easy to find and use.
  3356. To help you get past such problems, OpenOCD has a limited
  3357. @emph{autoprobing} ability to look at the scan chain, doing
  3358. a @dfn{blind interrogation} and then reporting the TAPs it finds.
  3359. To use this mechanism, start the OpenOCD server with only data
  3360. that configures your JTAG interface, and arranges to come up
  3361. with a slow clock (many devices don't support fast JTAG clocks
  3362. right when they come out of reset).
  3363. For example, your @file{openocd.cfg} file might have:
  3364. @example
  3365. source [find interface/olimex-arm-usb-tiny-h.cfg]
  3366. reset_config trst_and_srst
  3367. jtag_rclk 8
  3368. @end example
  3369. When you start the server without any TAPs configured, it will
  3370. attempt to autoconfigure the TAPs. There are two parts to this:
  3371. @enumerate
  3372. @item @emph{TAP discovery} ...
  3373. After a JTAG reset (sometimes a system reset may be needed too),
  3374. each TAP's data registers will hold the contents of either the
  3375. IDCODE or BYPASS register.
  3376. If JTAG communication is working, OpenOCD will see each TAP,
  3377. and report what @option{-expected-id} to use with it.
  3378. @item @emph{IR Length discovery} ...
  3379. Unfortunately JTAG does not provide a reliable way to find out
  3380. the value of the @option{-irlen} parameter to use with a TAP
  3381. that is discovered.
  3382. If OpenOCD can discover the length of a TAP's instruction
  3383. register, it will report it.
  3384. Otherwise you may need to consult vendor documentation, such
  3385. as chip data sheets or BSDL files.
  3386. @end enumerate
  3387. In many cases your board will have a simple scan chain with just
  3388. a single device. Here's what OpenOCD reported with one board
  3389. that's a bit more complex:
  3390. @example
  3391. clock speed 8 kHz
  3392. There are no enabled taps. AUTO PROBING MIGHT NOT WORK!!
  3393. AUTO auto0.tap - use "jtag newtap auto0 tap -expected-id 0x2b900f0f ..."
  3394. AUTO auto1.tap - use "jtag newtap auto1 tap -expected-id 0x07926001 ..."
  3395. AUTO auto2.tap - use "jtag newtap auto2 tap -expected-id 0x0b73b02f ..."
  3396. AUTO auto0.tap - use "... -irlen 4"
  3397. AUTO auto1.tap - use "... -irlen 4"
  3398. AUTO auto2.tap - use "... -irlen 6"
  3399. no gdb ports allocated as no target has been specified
  3400. @end example
  3401. Given that information, you should be able to either find some existing
  3402. config files to use, or create your own. If you create your own, you
  3403. would configure from the bottom up: first a @file{target.cfg} file
  3404. with these TAPs, any targets associated with them, and any on-chip
  3405. resources; then a @file{board.cfg} with off-chip resources, clocking,
  3406. and so forth.
  3407. @node CPU Configuration
  3408. @chapter CPU Configuration
  3409. @cindex GDB target
  3410. This chapter discusses how to set up GDB debug targets for CPUs.
  3411. You can also access these targets without GDB
  3412. (@pxref{Architecture and Core Commands},
  3413. and @ref{targetstatehandling,,Target State handling}) and
  3414. through various kinds of NAND and NOR flash commands.
  3415. If you have multiple CPUs you can have multiple such targets.
  3416. We'll start by looking at how to examine the targets you have,
  3417. then look at how to add one more target and how to configure it.
  3418. @section Target List
  3419. @cindex target, current
  3420. @cindex target, list
  3421. All targets that have been set up are part of a list,
  3422. where each member has a name.
  3423. That name should normally be the same as the TAP name.
  3424. You can display the list with the @command{targets}
  3425. (plural!) command.
  3426. This display often has only one CPU; here's what it might
  3427. look like with more than one:
  3428. @verbatim
  3429. TargetName Type Endian TapName State
  3430. -- ------------------ ---------- ------ ------------------ ------------
  3431. 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
  3432. 1 MyTarget cortex_m little tap-disabled
  3433. @end verbatim
  3434. One member of that list is the @dfn{current target}, which
  3435. is implicitly referenced by many commands.
  3436. It's the one marked with a @code{*} near the target name.
  3437. In particular, memory addresses often refer to the address
  3438. space seen by that current target.
  3439. Commands like @command{mdw} (memory display words)
  3440. and @command{flash erase_address} (erase NOR flash blocks)
  3441. are examples; and there are many more.
  3442. Several commands let you examine the list of targets:
  3443. @deffn Command {target count}
  3444. @emph{Note: target numbers are deprecated; don't use them.
  3445. They will be removed shortly after August 2010, including this command.
  3446. Iterate target using @command{target names}, not by counting.}
  3447. Returns the number of targets, @math{N}.
  3448. The highest numbered target is @math{N - 1}.
  3449. @example
  3450. set c [target count]
  3451. for @{ set x 0 @} @{ $x < $c @} @{ incr x @} @{
  3452. # Assuming you have created this function
  3453. print_target_details $x
  3454. @}
  3455. @end example
  3456. @end deffn
  3457. @deffn Command {target current}
  3458. Returns the name of the current target.
  3459. @end deffn
  3460. @deffn Command {target names}
  3461. Lists the names of all current targets in the list.
  3462. @example
  3463. foreach t [target names] @{
  3464. puts [format "Target: %s\n" $t]
  3465. @}
  3466. @end example
  3467. @end deffn
  3468. @deffn Command {target number} number
  3469. @emph{Note: target numbers are deprecated; don't use them.
  3470. They will be removed shortly after August 2010, including this command.}
  3471. The list of targets is numbered starting at zero.
  3472. This command returns the name of the target at index @var{number}.
  3473. @example
  3474. set thename [target number $x]
  3475. puts [format "Target %d is: %s\n" $x $thename]
  3476. @end example
  3477. @end deffn
  3478. @c yep, "target list" would have been better.
  3479. @c plus maybe "target setdefault".
  3480. @deffn Command targets [name]
  3481. @emph{Note: the name of this command is plural. Other target
  3482. command names are singular.}
  3483. With no parameter, this command displays a table of all known
  3484. targets in a user friendly form.
  3485. With a parameter, this command sets the current target to
  3486. the given target with the given @var{name}; this is
  3487. only relevant on boards which have more than one target.
  3488. @end deffn
  3489. @section Target CPU Types and Variants
  3490. @cindex target type
  3491. @cindex CPU type
  3492. @cindex CPU variant
  3493. Each target has a @dfn{CPU type}, as shown in the output of
  3494. the @command{targets} command. You need to specify that type
  3495. when calling @command{target create}.
  3496. The CPU type indicates more than just the instruction set.
  3497. It also indicates how that instruction set is implemented,
  3498. what kind of debug support it integrates,
  3499. whether it has an MMU (and if so, what kind),
  3500. what core-specific commands may be available
  3501. (@pxref{Architecture and Core Commands}),
  3502. and more.
  3503. For some CPU types, OpenOCD also defines @dfn{variants} which
  3504. indicate differences that affect their handling.
  3505. For example, a particular implementation bug might need to be
  3506. worked around in some chip versions.
  3507. It's easy to see what target types are supported,
  3508. since there's a command to list them.
  3509. However, there is currently no way to list what target variants
  3510. are supported (other than by reading the OpenOCD source code).
  3511. @anchor{targettypes}
  3512. @deffn Command {target types}
  3513. Lists all supported target types.
  3514. At this writing, the supported CPU types and variants are:
  3515. @itemize @bullet
  3516. @item @code{arm11} -- this is a generation of ARMv6 cores
  3517. @item @code{arm720t} -- this is an ARMv4 core with an MMU
  3518. @item @code{arm7tdmi} -- this is an ARMv4 core
  3519. @item @code{arm920t} -- this is an ARMv4 core with an MMU
  3520. @item @code{arm926ejs} -- this is an ARMv5 core with an MMU
  3521. @item @code{arm966e} -- this is an ARMv5 core
  3522. @item @code{arm9tdmi} -- this is an ARMv4 core
  3523. @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
  3524. (Support for this is preliminary and incomplete.)
  3525. @item @code{cortex_a} -- this is an ARMv7 core with an MMU
  3526. @item @code{cortex_m} -- this is an ARMv7 core, supporting only the
  3527. compact Thumb2 instruction set.
  3528. @item @code{dragonite} -- resembles arm966e
  3529. @item @code{dsp563xx} -- implements Freescale's 24-bit DSP.
  3530. (Support for this is still incomplete.)
  3531. @item @code{fa526} -- resembles arm920 (w/o Thumb)
  3532. @item @code{feroceon} -- resembles arm926
  3533. @item @code{mips_m4k} -- a MIPS core. This supports one variant:
  3534. @item @code{xscale} -- this is actually an architecture,
  3535. not a CPU type. It is based on the ARMv5 architecture.
  3536. There are several variants defined:
  3537. @itemize @minus
  3538. @item @code{ixp42x}, @code{ixp45x}, @code{ixp46x},
  3539. @code{pxa27x} ... instruction register length is 7 bits
  3540. @item @code{pxa250}, @code{pxa255},
  3541. @code{pxa26x} ... instruction register length is 5 bits
  3542. @item @code{pxa3xx} ... instruction register length is 11 bits
  3543. @end itemize
  3544. @item @code{openrisc} -- this is an OpenRISC 1000 core.
  3545. The current implementation supports three JTAG TAP cores:
  3546. @itemize @minus
  3547. @item @code{OpenCores TAP} (See: @emph{,jtag})
  3548. @item @code{Altera Virtual JTAG TAP} (See: @emph{})
  3549. @item @code{Xilinx BSCAN_* virtual JTAG interface} (See: @emph{})
  3550. @end itemize
  3551. And two debug interfaces cores:
  3552. @itemize @minus
  3553. @item @code{Advanced debug interface} (See: @emph{,adv_debug_sys})
  3554. @item @code{SoC Debug Interface} (See: @emph{,dbg_interface})
  3555. @end itemize
  3556. @end itemize
  3557. @end deffn
  3558. To avoid being confused by the variety of ARM based cores, remember
  3559. this key point: @emph{ARM is a technology licencing company}.
  3560. (See: @url{}.)
  3561. The CPU name used by OpenOCD will reflect the CPU design that was
  3562. licenced, not a vendor brand which incorporates that design.
  3563. Name prefixes like arm7, arm9, arm11, and cortex
  3564. reflect design generations;
  3565. while names like ARMv4, ARMv5, ARMv6, and ARMv7
  3566. reflect an architecture version implemented by a CPU design.
  3567. @anchor{targetconfiguration}
  3568. @section Target Configuration
  3569. Before creating a ``target'', you must have added its TAP to the scan chain.
  3570. When you've added that TAP, you will have a @code{}
  3571. which is used to set up the CPU support.
  3572. The chip-specific configuration file will normally configure its CPU(s)
  3573. right after it adds all of the chip's TAPs to the scan chain.
  3574. Although you can set up a target in one step, it's often clearer if you
  3575. use shorter commands and do it in two steps: create it, then configure
  3576. optional parts.
  3577. All operations on the target after it's created will use a new
  3578. command, created as part of target creation.
  3579. The two main things to configure after target creation are
  3580. a work area, which usually has target-specific defaults even
  3581. if the board setup code overrides them later;
  3582. and event handlers (@pxref{targetevents,,Target Events}), which tend
  3583. to be much more board-specific.
  3584. The key steps you use might look something like this
  3585. @example
  3586. target create MyTarget cortex_m -chain-position mychip.cpu
  3587. $MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
  3588. $MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
  3589. $MyTarget configure -event reset-init @{ myboard_reinit @}
  3590. @end example
  3591. You should specify a working area if you can; typically it uses some
  3592. on-chip SRAM.
  3593. Such a working area can speed up many things, including bulk
  3594. writes to target memory;
  3595. flash operations like checking to see if memory needs to be erased;
  3596. GDB memory checksumming;
  3597. and more.
  3598. @quotation Warning
  3599. On more complex chips, the work area can become
  3600. inaccessible when application code
  3601. (such as an operating system)
  3602. enables or disables the MMU.
  3603. For example, the particular MMU context used to acess the virtual
  3604. address will probably matter ... and that context might not have
  3605. easy access to other addresses needed.
  3606. At this writing, OpenOCD doesn't have much MMU intelligence.
  3607. @end quotation
  3608. It's often very useful to define a @code{reset-init} event handler.
  3609. For systems that are normally used with a boot loader,
  3610. common tasks include updating clocks and initializing memory
  3611. controllers.
  3612. That may be needed to let you write the boot loader into flash,
  3613. in order to ``de-brick'' your board; or to load programs into
  3614. external DDR memory without having run the boot loader.
  3615. @deffn Command {target create} target_name type configparams...
  3616. This command creates a GDB debug target that refers to a specific JTAG tap.
  3617. It enters that target into a list, and creates a new
  3618. command (@command{@var{target_name}}) which is used for various
  3619. purposes including additional configuration.
  3620. @itemize @bullet
  3621. @item @var{target_name} ... is the name of the debug target.
  3622. By convention this should be the same as the @emph{}
  3623. of the TAP associated with this target, which must be specified here
  3624. using the @code{-chain-position @var{}} configparam.
  3625. This name is also used to create the target object command,
  3626. referred to here as @command{$target_name},
  3627. and in other places the target needs to be identified.
  3628. @item @var{type} ... specifies the target type. @xref{targettypes,,target types}.
  3629. @item @var{configparams} ... all parameters accepted by
  3630. @command{$target_name configure} are permitted.
  3631. If the target is big-endian, set it here with @code{-endian big}.
  3632. If the variant matters, set it here with @code{-variant}.
  3633. You @emph{must} set the @code{-chain-position @var{}} here.
  3634. @end itemize
  3635. @end deffn
  3636. @deffn Command {$target_name configure} configparams...
  3637. The options accepted by this command may also be
  3638. specified as parameters to @command{target create}.
  3639. Their values can later be queried one at a time by
  3640. using the @command{$target_name cget} command.
  3641. @emph{Warning:} changing some of these after setup is dangerous.
  3642. For example, moving a target from one TAP to another;
  3643. and changing its endianness or variant.
  3644. @itemize @bullet
  3645. @item @code{-chain-position} @var{} -- names the TAP
  3646. used to access this target.
  3647. @item @code{-endian} (@option{big}|@option{little}) -- specifies
  3648. whether the CPU uses big or little endian conventions
  3649. @item @code{-event} @var{event_name} @var{event_body} --
  3650. @xref{targetevents,,Target Events}.
  3651. Note that this updates a list of named event handlers.
  3652. Calling this twice with two different event names assigns
  3653. two different handlers, but calling it twice with the
  3654. same event name assigns only one handler.
  3655. @item @code{-variant} @var{name} -- specifies a variant of the target,
  3656. which OpenOCD needs to know about.
  3657. @item @code{-work-area-backup} (@option{0}|@option{1}) -- says
  3658. whether the work area gets backed up; by default,
  3659. @emph{it is not backed up.}
  3660. When possible, use a working_area that doesn't need to be backed up,
  3661. since performing a backup slows down operations.
  3662. For example, the beginning of an SRAM block is likely to
  3663. be used by most build systems, but the end is often unused.
  3664. @item @code{-work-area-size} @var{size} -- specify work are size,
  3665. in bytes. The same size applies regardless of whether its physical
  3666. or virtual address is being used.
  3667. @item @code{-work-area-phys} @var{address} -- set the work area
  3668. base @var{address} to be used when no MMU is active.
  3669. @item @code{-work-area-virt} @var{address} -- set the work area
  3670. base @var{address} to be used when an MMU is active.
  3671. @emph{Do not specify a value for this except on targets with an MMU.}
  3672. The value should normally correspond to a static mapping for the
  3673. @code{-work-area-phys} address, set up by the current operating system.
  3674. @anchor{rtostype}
  3675. @item @code{-rtos} @var{rtos_type} -- enable rtos support for target,
  3676. @var{rtos_type} can be one of @option{auto}|@option{eCos}|@option{ThreadX}|
  3677. @option{FreeRTOS}|@option{linux}|@option{ChibiOS}|@option{embKernel}
  3678. @xref{gdbrtossupport,,RTOS Support}.
  3679. @end itemize
  3680. @end deffn
  3681. @section Other $target_name Commands
  3682. @cindex object command
  3683. The Tcl/Tk language has the concept of object commands,
  3684. and OpenOCD adopts that same model for targets.
  3685. A good Tk example is a on screen button.
  3686. Once a button is created a button
  3687. has a name (a path in Tk terms) and that name is useable as a first
  3688. class command. For example in Tk, one can create a button and later
  3689. configure it like this:
  3690. @example
  3691. # Create
  3692. button .foobar -background red -command @{ foo @}
  3693. # Modify
  3694. .foobar configure -foreground blue
  3695. # Query
  3696. set x [.foobar cget -background]
  3697. # Report
  3698. puts [format "The button is %s" $x]
  3699. @end example
  3700. In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
  3701. button, and its object commands are invoked the same way.
  3702. @example
  3703. str912.cpu mww 0x1234 0x42
  3704. omap3530.cpu mww 0x5555 123
  3705. @end example
  3706. The commands supported by OpenOCD target objects are:
  3707. @deffn Command {$target_name arp_examine}
  3708. @deffnx Command {$target_name arp_halt}
  3709. @deffnx Command {$target_name arp_poll}
  3710. @deffnx Command {$target_name arp_reset}
  3711. @deffnx Command {$target_name arp_waitstate}
  3712. Internal OpenOCD scripts (most notably @file{startup.tcl})
  3713. use these to deal with specific reset cases.
  3714. They are not otherwise documented here.
  3715. @end deffn
  3716. @deffn Command {$target_name array2mem} arrayname width address count
  3717. @deffnx Command {$target_name mem2array} arrayname width address count
  3718. These provide an efficient script-oriented interface to memory.
  3719. The @code{array2mem} primitive writes bytes, halfwords, or words;
  3720. while @code{mem2array} reads them.
  3721. In both cases, the TCL side uses an array, and
  3722. the target side uses raw memory.
  3723. The efficiency comes from enabling the use of
  3724. bulk JTAG data transfer operations.
  3725. The script orientation comes from working with data
  3726. values that are packaged for use by TCL scripts;
  3727. @command{mdw} type primitives only print data they retrieve,
  3728. and neither store nor return those values.
  3729. @itemize
  3730. @item @var{arrayname} ... is the name of an array variable
  3731. @item @var{width} ... is 8/16/32 - indicating the memory access size
  3732. @item @var{address} ... is the target memory address
  3733. @item @var{count} ... is the number of elements to process
  3734. @end itemize
  3735. @end deffn
  3736. @deffn Command {$target_name cget} queryparm
  3737. Each configuration parameter accepted by
  3738. @command{$target_name configure}
  3739. can be individually queried, to return its current value.
  3740. The @var{queryparm} is a parameter name
  3741. accepted by that command, such as @code{-work-area-phys}.
  3742. There are a few special cases:
  3743. @itemize @bullet
  3744. @item @code{-event} @var{event_name} -- returns the handler for the
  3745. event named @var{event_name}.
  3746. This is a special case because setting a handler requires
  3747. two parameters.
  3748. @item @code{-type} -- returns the target type.
  3749. This is a special case because this is set using
  3750. @command{target create} and can't be changed
  3751. using @command{$target_name configure}.
  3752. @end itemize
  3753. For example, if you wanted to summarize information about
  3754. all the targets you might use something like this:
  3755. @example
  3756. foreach name [target names] @{
  3757. set y [$name cget -endian]
  3758. set z [$name cget -type]
  3759. puts [format "Chip %d is %s, Endian: %s, type: %s" \
  3760. $x $name $y $z]
  3761. @}
  3762. @end example
  3763. @end deffn
  3764. @anchor{targetcurstate}
  3765. @deffn Command {$target_name curstate}
  3766. Displays the current target state:
  3767. @code{debug-running},
  3768. @code{halted},
  3769. @code{reset},
  3770. @code{running}, or @code{unknown}.
  3771. (Also, @pxref{eventpolling,,Event Polling}.)
  3772. @end deffn
  3773. @deffn Command {$target_name eventlist}
  3774. Displays a table listing all event handlers
  3775. currently associated with this target.
  3776. @xref{targetevents,,Target Events}.
  3777. @end deffn
  3778. @deffn Command {$target_name invoke-event} event_name
  3779. Invokes the handler for the event named @var{event_name}.
  3780. (This is primarily intended for use by OpenOCD framework
  3781. code, for example by the reset code in @file{startup.tcl}.)
  3782. @end deffn
  3783. @deffn Command {$target_name mdw} addr [count]
  3784. @deffnx Command {$target_name mdh} addr [count]
  3785. @deffnx Command {$target_name mdb} addr [count]
  3786. Display contents of address @var{addr}, as
  3787. 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
  3788. or 8-bit bytes (@command{mdb}).
  3789. If @var{count} is specified, displays that many units.
  3790. (If you want to manipulate the data instead of displaying it,
  3791. see the @code{mem2array} primitives.)
  3792. @end deffn
  3793. @deffn Command {$target_name mww} addr word
  3794. @deffnx Command {$target_name mwh} addr halfword
  3795. @deffnx Command {$target_name mwb} addr byte
  3796. Writes the specified @var{word} (32 bits),
  3797. @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
  3798. at the specified address @var{addr}.
  3799. @end deffn
  3800. @anchor{targetevents}
  3801. @section Target Events
  3802. @cindex target events
  3803. @cindex events
  3804. At various times, certain things can happen, or you want them to happen.
  3805. For example:
  3806. @itemize @bullet
  3807. @item What should happen when GDB connects? Should your target reset?
  3808. @item When GDB tries to flash the target, do you need to enable the flash via a special command?
  3809. @item Is using SRST appropriate (and possible) on your system?
  3810. Or instead of that, do you need to issue JTAG commands to trigger reset?
  3811. SRST usually resets everything on the scan chain, which can be inappropriate.
  3812. @item During reset, do you need to write to certain memory locations
  3813. to set up system clocks or
  3814. to reconfigure the SDRAM?
  3815. How about configuring the watchdog timer, or other peripherals,
  3816. to stop running while you hold the core stopped for debugging?
  3817. @end itemize
  3818. All of the above items can be addressed by target event handlers.
  3819. These are set up by @command{$target_name configure -event} or
  3820. @command{target create ... -event}.
  3821. The programmer's model matches the @code{-command} option used in Tcl/Tk
  3822. buttons and events. The two examples below act the same, but one creates
  3823. and invokes a small procedure while the other inlines it.
  3824. @example
  3825. proc my_attach_proc @{ @} @{
  3826. echo "Reset..."
  3827. reset halt
  3828. @}
  3829. mychip.cpu configure -event gdb-attach my_attach_proc
  3830. mychip.cpu configure -event gdb-attach @{
  3831. echo "Reset..."
  3832. # To make flash probe and gdb load to flash work we need a reset init.
  3833. reset init
  3834. @}
  3835. @end example
  3836. The following target events are defined:
  3837. @itemize @bullet
  3838. @item @b{debug-halted}
  3839. @* The target has halted for debug reasons (i.e.: breakpoint)
  3840. @item @b{debug-resumed}
  3841. @* The target has resumed (i.e.: gdb said run)
  3842. @item @b{early-halted}
  3843. @* Occurs early in the halt process
  3844. @item @b{examine-start}
  3845. @* Before target examine is called.
  3846. @item @b{examine-end}
  3847. @* After target examine is called with no errors.
  3848. @item @b{gdb-attach}
  3849. @* When GDB connects. This is before any communication with the target, so this
  3850. can be used to set up the target so it is possible to probe flash. Probing flash
  3851. is necessary during gdb connect if gdb load is to write the image to flash. Another
  3852. use of the flash memory map is for GDB to automatically hardware/software breakpoints
  3853. depending on whether the breakpoint is in RAM or read only memory.
  3854. @item @b{gdb-detach}
  3855. @* When GDB disconnects
  3856. @item @b{gdb-end}
  3857. @* When the target has halted and GDB is not doing anything (see early halt)
  3858. @item @b{gdb-flash-erase-start}
  3859. @* Before the GDB flash process tries to erase the flash (default is
  3860. @code{reset init})
  3861. @item @b{gdb-flash-erase-end}
  3862. @* After the GDB flash process has finished erasing the flash
  3863. @item @b{gdb-flash-write-start}
  3864. @* Before GDB writes to the flash
  3865. @item @b{gdb-flash-write-end}
  3866. @* After GDB writes to the flash (default is @code{reset halt})
  3867. @item @b{gdb-start}
  3868. @* Before the target steps, gdb is trying to start/resume the target
  3869. @item @b{halted}
  3870. @* The target has halted
  3871. @item @b{reset-assert-pre}
  3872. @* Issued as part of @command{reset} processing
  3873. after @command{reset_init} was triggered
  3874. but before either SRST alone is re-asserted on the scan chain,
  3875. or @code{reset-assert} is triggered.
  3876. @item @b{reset-assert}
  3877. @* Issued as part of @command{reset} processing
  3878. after @command{reset-assert-pre} was triggered.
  3879. When such a handler is present, cores which support this event will use
  3880. it instead of asserting SRST.
  3881. This support is essential for debugging with JTAG interfaces which
  3882. don't include an SRST line (JTAG doesn't require SRST), and for
  3883. selective reset on scan chains that have multiple targets.
  3884. @item @b{reset-assert-post}
  3885. @* Issued as part of @command{reset} processing
  3886. after @code{reset-assert} has been triggered.
  3887. or the target asserted SRST on the entire scan chain.
  3888. @item @b{reset-deassert-pre}
  3889. @* Issued as part of @command{reset} processing
  3890. after @code{reset-assert-post} has been triggered.
  3891. @item @b{reset-deassert-post}
  3892. @* Issued as part of @command{reset} processing
  3893. after @code{reset-deassert-pre} has been triggered
  3894. and (if the target is using it) after SRST has been
  3895. released on the scan chain.
  3896. @item @b{reset-end}
  3897. @* Issued as the final step in @command{reset} processing.
  3898. @ignore
  3899. @item @b{reset-halt-post}
  3900. @* Currently not used
  3901. @item @b{reset-halt-pre}
  3902. @* Currently not used
  3903. @end ignore
  3904. @item @b{reset-init}
  3905. @* Used by @b{reset init} command for board-specific initialization.
  3906. This event fires after @emph{reset-deassert-post}.
  3907. This is where you would configure PLLs and clocking, set up DRAM so
  3908. you can download programs that don't fit in on-chip SRAM, set up pin
  3909. multiplexing, and so on.
  3910. (You may be able to switch to a fast JTAG clock rate here, after
  3911. the target clocks are fully set up.)
  3912. @item @b{reset-start}
  3913. @* Issued as part of @command{reset} processing
  3914. before @command{reset_init} is called.
  3915. This is the most robust place to use @command{jtag_rclk}
  3916. or @command{adapter_khz} to switch to a low JTAG clock rate,
  3917. when reset disables PLLs needed to use a fast clock.
  3918. @ignore
  3919. @item @b{reset-wait-pos}
  3920. @* Currently not used
  3921. @item @b{reset-wait-pre}
  3922. @* Currently not used
  3923. @end ignore
  3924. @item @b{resume-start}
  3925. @* Before any target is resumed
  3926. @item @b{resume-end}
  3927. @* After all targets have resumed
  3928. @item @b{resumed}
  3929. @* Target has resumed
  3930. @end itemize
  3931. @node Flash Commands
  3932. @chapter Flash Commands
  3933. OpenOCD has different commands for NOR and NAND flash;
  3934. the ``flash'' command works with NOR flash, while
  3935. the ``nand'' command works with NAND flash.
  3936. This partially reflects different hardware technologies:
  3937. NOR flash usually supports direct CPU instruction and data bus access,
  3938. while data from a NAND flash must be copied to memory before it can be
  3939. used. (SPI flash must also be copied to memory before use.)
  3940. However, the documentation also uses ``flash'' as a generic term;
  3941. for example, ``Put flash configuration in board-specific files''.
  3942. Flash Steps:
  3943. @enumerate
  3944. @item Configure via the command @command{flash bank}
  3945. @* Do this in a board-specific configuration file,
  3946. passing parameters as needed by the driver.
  3947. @item Operate on the flash via @command{flash subcommand}
  3948. @* Often commands to manipulate the flash are typed by a human, or run
  3949. via a script in some automated way. Common tasks include writing a
  3950. boot loader, operating system, or other data.
  3951. @item GDB Flashing
  3952. @* Flashing via GDB requires the flash be configured via ``flash
  3953. bank'', and the GDB flash features be enabled.
  3954. @xref{gdbconfiguration,,GDB Configuration}.
  3955. @end enumerate
  3956. Many CPUs have the ablity to ``boot'' from the first flash bank.
  3957. This means that misprogramming that bank can ``brick'' a system,
  3958. so that it can't boot.
  3959. JTAG tools, like OpenOCD, are often then used to ``de-brick'' the
  3960. board by (re)installing working boot firmware.
  3961. @anchor{norconfiguration}
  3962. @section Flash Configuration Commands
  3963. @cindex flash configuration
  3964. @deffn {Config Command} {flash bank} name driver base size chip_width bus_width target [driver_options]
  3965. Configures a flash bank which provides persistent storage
  3966. for addresses from @math{base} to @math{base + size - 1}.
  3967. These banks will often be visible to GDB through the target's memory map.
  3968. In some cases, configuring a flash bank will activate extra commands;
  3969. see the driver-specific documentation.
  3970. @itemize @bullet
  3971. @item @var{name} ... may be used to reference the flash bank
  3972. in other flash commands. A number is also available.
  3973. @item @var{driver} ... identifies the controller driver
  3974. associated with the flash bank being declared.
  3975. This is usually @code{cfi} for external flash, or else
  3976. the name of a microcontroller with embedded flash memory.
  3977. @xref{flashdriverlist,,Flash Driver List}.
  3978. @item @var{base} ... Base address of the flash chip.
  3979. @item @var{size} ... Size of the chip, in bytes.
  3980. For some drivers, this value is detected from the hardware.
  3981. @item @var{chip_width} ... Width of the flash chip, in bytes;
  3982. ignored for most microcontroller drivers.
  3983. @item @var{bus_width} ... Width of the data bus used to access the
  3984. chip, in bytes; ignored for most microcontroller drivers.
  3985. @item @var{target} ... Names the target used to issue
  3986. commands to the flash controller.
  3987. @comment Actually, it's currently a controller-specific parameter...
  3988. @item @var{driver_options} ... drivers may support, or require,
  3989. additional parameters. See the driver-specific documentation
  3990. for more information.
  3991. @end itemize
  3992. @quotation Note
  3993. This command is not available after OpenOCD initialization has completed.
  3994. Use it in board specific configuration files, not interactively.
  3995. @end quotation
  3996. @end deffn
  3997. @comment the REAL name for this command is "ocd_flash_banks"
  3998. @comment less confusing would be: "flash list" (like "nand list")
  3999. @deffn Command {flash banks}
  4000. Prints a one-line summary of each device that was
  4001. declared using @command{flash bank}, numbered from zero.
  4002. Note that this is the @emph{plural} form;
  4003. the @emph{singular} form is a very different command.
  4004. @end deffn
  4005. @deffn Command {flash list}
  4006. Retrieves a list of associative arrays for each device that was
  4007. declared using @command{flash bank}, numbered from zero.
  4008. This returned list can be manipulated easily from within scripts.
  4009. @end deffn
  4010. @deffn Command {flash probe} num
  4011. Identify the flash, or validate the parameters of the configured flash. Operation
  4012. depends on the flash type.
  4013. The @var{num} parameter is a value shown by @command{flash banks}.
  4014. Most flash commands will implicitly @emph{autoprobe} the bank;
  4015. flash drivers can distinguish between probing and autoprobing,
  4016. but most don't bother.
  4017. @end deffn
  4018. @section Erasing, Reading, Writing to Flash
  4019. @cindex flash erasing
  4020. @cindex flash reading
  4021. @cindex flash writing
  4022. @cindex flash programming
  4023. @anchor{flashprogrammingcommands}
  4024. One feature distinguishing NOR flash from NAND or serial flash technologies
  4025. is that for read access, it acts exactly like any other addressible memory.
  4026. This means you can use normal memory read commands like @command{mdw} or
  4027. @command{dump_image} with it, with no special @command{flash} subcommands.
  4028. @xref{memoryaccess,,Memory access}, and @ref{imageaccess,,Image access}.
  4029. Write access works differently. Flash memory normally needs to be erased
  4030. before it's written. Erasing a sector turns all of its bits to ones, and
  4031. writing can turn ones into zeroes. This is why there are special commands
  4032. for interactive erasing and writing, and why GDB needs to know which parts
  4033. of the address space hold NOR flash memory.
  4034. @quotation Note
  4035. Most of these erase and write commands leverage the fact that NOR flash
  4036. chips consume target address space. They implicitly refer to the current
  4037. JTAG target, and map from an address in that target's address space
  4038. back to a flash bank.
  4039. @comment In May 2009, those mappings may fail if any bank associated
  4040. @comment with that target doesn't succesfuly autoprobe ... bug worth fixing?
  4041. A few commands use abstract addressing based on bank and sector numbers,
  4042. and don't depend on searching the current target and its address space.
  4043. Avoid confusing the two command models.
  4044. @end quotation
  4045. Some flash chips implement software protection against accidental writes,
  4046. since such buggy writes could in some cases ``brick'' a system.
  4047. For such systems, erasing and writing may require sector protection to be
  4048. disabled first.
  4049. Examples include CFI flash such as ``Intel Advanced Bootblock flash'',
  4050. and AT91SAM7 on-chip flash.
  4051. @xref{flashprotect,,flash protect}.
  4052. @deffn Command {flash erase_sector} num first last
  4053. Erase sectors in bank @var{num}, starting at sector @var{first}
  4054. up to and including @var{last}.
  4055. Sector numbering starts at 0.
  4056. Providing a @var{last} sector of @option{last}
  4057. specifies "to the end of the flash bank".
  4058. The @var{num} parameter is a value shown by @command{flash banks}.
  4059. @end deffn
  4060. @deffn Command {flash erase_address} [@option{pad}] [@option{unlock}] address length
  4061. Erase sectors starting at @var{address} for @var{length} bytes.
  4062. Unless @option{pad} is specified, @math{address} must begin a
  4063. flash sector, and @math{address + length - 1} must end a sector.
  4064. Specifying @option{pad} erases extra data at the beginning and/or
  4065. end of the specified region, as needed to erase only full sectors.
  4066. The flash bank to use is inferred from the @var{address}, and
  4067. the specified length must stay within that bank.
  4068. As a special case, when @var{length} is zero and @var{address} is
  4069. the start of the bank, the whole flash is erased.
  4070. If @option{unlock} is specified, then the flash is unprotected
  4071. before erase starts.
  4072. @end deffn
  4073. @deffn Command {flash fillw} address word length
  4074. @deffnx Command {flash fillh} address halfword length
  4075. @deffnx Command {flash fillb} address byte length
  4076. Fills flash memory with the specified @var{word} (32 bits),
  4077. @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
  4078. starting at @var{address} and continuing
  4079. for @var{length} units (word/halfword/byte).
  4080. No erasure is done before writing; when needed, that must be done
  4081. before issuing this command.
  4082. Writes are done in blocks of up to 1024 bytes, and each write is
  4083. verified by reading back the data and comparing it to what was written.
  4084. The flash bank to use is inferred from the @var{address} of
  4085. each block, and the specified length must stay within that bank.
  4086. @end deffn
  4087. @comment no current checks for errors if fill blocks touch multiple banks!
  4088. @deffn Command {flash write_bank} num filename offset
  4089. Write the binary @file{filename} to flash bank @var{num},
  4090. starting at @var{offset} bytes from the beginning of the bank.
  4091. The @var{num} parameter is a value shown by @command{flash banks}.
  4092. @end deffn
  4093. @deffn Command {flash write_image} [erase] [unlock] filename [offset] [type]
  4094. Write the image @file{filename} to the current target's flash bank(s).
  4095. A relocation @var{offset} may be specified, in which case it is added
  4096. to the base address for each section in the image.
  4097. The file [@var{type}] can be specified
  4098. explicitly as @option{bin} (binary), @option{ihex} (Intel hex),
  4099. @option{elf} (ELF file), @option{s19} (Motorola s19).
  4100. @option{mem}, or @option{builder}.
  4101. The relevant flash sectors will be erased prior to programming
  4102. if the @option{erase} parameter is given. If @option{unlock} is
  4103. provided, then the flash banks are unlocked before erase and
  4104. program. The flash bank to use is inferred from the address of
  4105. each image section.
  4106. @quotation Warning
  4107. Be careful using the @option{erase} flag when the flash is holding
  4108. data you want to preserve.
  4109. Portions of the flash outside those described in the image's
  4110. sections might be erased with no notice.
  4111. @itemize
  4112. @item
  4113. When a section of the image being written does not fill out all the
  4114. sectors it uses, the unwritten parts of those sectors are necessarily
  4115. also erased, because sectors can't be partially erased.
  4116. @item
  4117. Data stored in sector "holes" between image sections are also affected.
  4118. For example, "@command{flash write_image erase ...}" of an image with
  4119. one byte at the beginning of a flash bank and one byte at the end
  4120. erases the entire bank -- not just the two sectors being written.
  4121. @end itemize
  4122. Also, when flash protection is important, you must re-apply it after
  4123. it has been removed by the @option{unlock} flag.
  4124. @end quotation
  4125. @end deffn
  4126. @section Other Flash commands
  4127. @cindex flash protection
  4128. @deffn Command {flash erase_check} num
  4129. Check erase state of sectors in flash bank @var{num},
  4130. and display that status.
  4131. The @var{num} parameter is a value shown by @command{flash banks}.
  4132. @end deffn
  4133. @deffn Command {flash info} num
  4134. Print info about flash bank @var{num}
  4135. The @var{num} parameter is a value shown by @command{flash banks}.
  4136. This command will first query the hardware, it does not print cached
  4137. and possibly stale information.
  4138. @end deffn
  4139. @anchor{flashprotect}
  4140. @deffn Command {flash protect} num first last (@option{on}|@option{off})
  4141. Enable (@option{on}) or disable (@option{off}) protection of flash sectors
  4142. in flash bank @var{num}, starting at sector @var{first}
  4143. and continuing up to and including @var{last}.
  4144. Providing a @var{last} sector of @option{last}
  4145. specifies "to the end of the flash bank".
  4146. The @var{num} parameter is a value shown by @command{flash banks}.
  4147. @end deffn
  4148. @deffn Command {flash padded_value} num value
  4149. Sets the default value used for padding any image sections, This should
  4150. normally match the flash bank erased value. If not specified by this
  4151. comamnd or the flash driver then it defaults to 0xff.
  4152. @end deffn
  4153. @anchor{program}
  4154. @deffn Command {program} filename [verify] [reset] [offset]
  4155. This is a helper script that simplifies using OpenOCD as a standalone
  4156. programmer. The only required parameter is @option{filename}, the others are optional.
  4157. @xref{Flash Programming}.
  4158. @end deffn
  4159. @anchor{flashdriverlist}
  4160. @section Flash Driver List
  4161. As noted above, the @command{flash bank} command requires a driver name,
  4162. and allows driver-specific options and behaviors.
  4163. Some drivers also activate driver-specific commands.
  4164. @subsection External Flash
  4165. @deffn {Flash Driver} cfi
  4166. @cindex Common Flash Interface
  4167. @cindex CFI
  4168. The ``Common Flash Interface'' (CFI) is the main standard for
  4169. external NOR flash chips, each of which connects to a
  4170. specific external chip select on the CPU.
  4171. Frequently the first such chip is used to boot the system.
  4172. Your board's @code{reset-init} handler might need to
  4173. configure additional chip selects using other commands (like: @command{mww} to
  4174. configure a bus and its timings), or
  4175. perhaps configure a GPIO pin that controls the ``write protect'' pin
  4176. on the flash chip.
  4177. The CFI driver can use a target-specific working area to significantly
  4178. speed up operation.
  4179. The CFI driver can accept the following optional parameters, in any order:
  4180. @itemize
  4181. @item @var{jedec_probe} ... is used to detect certain non-CFI flash ROMs,
  4182. like AM29LV010 and similar types.
  4183. @item @var{x16_as_x8} ... when a 16-bit flash is hooked up to an 8-bit bus.
  4184. @end itemize
  4185. To configure two adjacent banks of 16 MBytes each, both sixteen bits (two bytes)
  4186. wide on a sixteen bit bus:
  4187. @example
  4188. flash bank $_FLASHNAME cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
  4189. flash bank $_FLASHNAME cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
  4190. @end example
  4191. To configure one bank of 32 MBytes
  4192. built from two sixteen bit (two byte) wide parts wired in parallel
  4193. to create a thirty-two bit (four byte) bus with doubled throughput:
  4194. @example
  4195. flash bank $_FLASHNAME cfi 0x00000000 0x02000000 2 4 $_TARGETNAME
  4196. @end example
  4197. @c "cfi part_id" disabled
  4198. @end deffn
  4199. @deffn {Flash Driver} lpcspifi
  4200. @cindex NXP SPI Flash Interface
  4201. @cindex SPIFI
  4202. @cindex lpcspifi
  4203. NXP's LPC43xx and LPC18xx families include a proprietary SPI
  4204. Flash Interface (SPIFI) peripheral that can drive and provide
  4205. memory mapped access to external SPI flash devices.
  4206. The lpcspifi driver initializes this interface and provides
  4207. program and erase functionality for these serial flash devices.
  4208. Use of this driver @b{requires} a working area of at least 1kB
  4209. to be configured on the target device; more than this will
  4210. significantly reduce flash programming times.
  4211. The setup command only requires the @var{base} parameter. All
  4212. other parameters are ignored, and the flash size and layout
  4213. are configured by the driver.
  4214. @example
  4215. flash bank $_FLASHNAME lpcspifi 0x14000000 0 0 0 $_TARGETNAME
  4216. @end example
  4217. @end deffn
  4218. @deffn {Flash Driver} stmsmi
  4219. @cindex STMicroelectronics Serial Memory Interface
  4220. @cindex SMI
  4221. @cindex stmsmi
  4222. Some devices form STMicroelectronics (e.g. STR75x MCU family,
  4223. SPEAr MPU family) include a proprietary
  4224. ``Serial Memory Interface'' (SMI) controller able to drive external
  4225. SPI flash devices.
  4226. Depending on specific device and board configuration, up to 4 external
  4227. flash devices can be connected.
  4228. SMI makes the flash content directly accessible in the CPU address
  4229. space; each external device is mapped in a memory bank.
  4230. CPU can directly read data, execute code and boot from SMI banks.
  4231. Normal OpenOCD commands like @command{mdw} can be used to display
  4232. the flash content.
  4233. The setup command only requires the @var{base} parameter in order
  4234. to identify the memory bank.
  4235. All other parameters are ignored. Additional information, like
  4236. flash size, are detected automatically.
  4237. @example
  4238. flash bank $_FLASHNAME stmsmi 0xf8000000 0 0 0 $_TARGETNAME
  4239. @end example
  4240. @end deffn
  4241. @subsection Internal Flash (Microcontrollers)
  4242. @deffn {Flash Driver} aduc702x
  4243. The ADUC702x analog microcontrollers from Analog Devices
  4244. include internal flash and use ARM7TDMI cores.
  4245. The aduc702x flash driver works with models ADUC7019 through ADUC7028.
  4246. The setup command only requires the @var{target} argument
  4247. since all devices in this family have the same memory layout.
  4248. @example
  4249. flash bank $_FLASHNAME aduc702x 0 0 0 0 $_TARGETNAME
  4250. @end example
  4251. @end deffn
  4252. @anchor{at91sam3}
  4253. @deffn {Flash Driver} at91sam3
  4254. @cindex at91sam3
  4255. All members of the AT91SAM3 microcontroller family from
  4256. Atmel include internal flash and use ARM's Cortex-M3 core. The driver
  4257. currently (6/22/09) recognizes the AT91SAM3U[1/2/4][C/E] chips. Note
  4258. that the driver was orginaly developed and tested using the
  4259. AT91SAM3U4E, using a SAM3U-EK eval board. Support for other chips in
  4260. the family was cribbed from the data sheet. @emph{Note to future
  4261. readers/updaters: Please remove this worrysome comment after other
  4262. chips are confirmed.}
  4263. The AT91SAM3U4[E/C] (256K) chips have two flash banks; most other chips
  4264. have one flash bank. In all cases the flash banks are at
  4265. the following fixed locations:
  4266. @example
  4267. # Flash bank 0 - all chips
  4268. flash bank $_FLASHNAME at91sam3 0x00080000 0 1 1 $_TARGETNAME
  4269. # Flash bank 1 - only 256K chips
  4270. flash bank $_FLASHNAME at91sam3 0x00100000 0 1 1 $_TARGETNAME
  4271. @end example
  4272. Internally, the AT91SAM3 flash memory is organized as follows.
  4273. Unlike the AT91SAM7 chips, these are not used as parameters
  4274. to the @command{flash bank} command:
  4275. @itemize
  4276. @item @emph{N-Banks:} 256K chips have 2 banks, others have 1 bank.
  4277. @item @emph{Bank Size:} 128K/64K Per flash bank
  4278. @item @emph{Sectors:} 16 or 8 per bank
  4279. @item @emph{SectorSize:} 8K Per Sector
  4280. @item @emph{PageSize:} 256 bytes per page. Note that OpenOCD operates on 'sector' sizes, not page sizes.
  4281. @end itemize
  4282. The AT91SAM3 driver adds some additional commands:
  4283. @deffn Command {at91sam3 gpnvm}
  4284. @deffnx Command {at91sam3 gpnvm clear} number
  4285. @deffnx Command {at91sam3 gpnvm set} number
  4286. @deffnx Command {at91sam3 gpnvm show} [@option{all}|number]
  4287. With no parameters, @command{show} or @command{show all},
  4288. shows the status of all GPNVM bits.
  4289. With @command{show} @var{number}, displays that bit.
  4290. With @command{set} @var{number} or @command{clear} @var{number},
  4291. modifies that GPNVM bit.
  4292. @end deffn
  4293. @deffn Command {at91sam3 info}
  4294. This command attempts to display information about the AT91SAM3
  4295. chip. @emph{First} it read the @code{CHIPID_CIDR} [address 0x400e0740, see
  4296. Section 28.2.1, page 505 of the AT91SAM3U 29/may/2009 datasheet,
  4297. document id: doc6430A] and decodes the values. @emph{Second} it reads the
  4298. various clock configuration registers and attempts to display how it
  4299. believes the chip is configured. By default, the SLOWCLK is assumed to
  4300. be 32768 Hz, see the command @command{at91sam3 slowclk}.
  4301. @end deffn
  4302. @deffn Command {at91sam3 slowclk} [value]
  4303. This command shows/sets the slow clock frequency used in the
  4304. @command{at91sam3 info} command calculations above.
  4305. @end deffn
  4306. @end deffn
  4307. @deffn {Flash Driver} at91sam4
  4308. @cindex at91sam4
  4309. All members of the AT91SAM4 microcontroller family from
  4310. Atmel include internal flash and use ARM's Cortex-M4 core.
  4311. This driver uses the same cmd names/syntax as @xref{at91sam3}.
  4312. @end deffn
  4313. @deffn {Flash Driver} at91sam7
  4314. All members of the AT91SAM7 microcontroller family from Atmel include
  4315. internal flash and use ARM7TDMI cores. The driver automatically
  4316. recognizes a number of these chips using the chip identification
  4317. register, and autoconfigures itself.
  4318. @example
  4319. flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME
  4320. @end example
  4321. For chips which are not recognized by the controller driver, you must
  4322. provide additional parameters in the following order:
  4323. @itemize
  4324. @item @var{chip_model} ... label used with @command{flash info}
  4325. @item @var{banks}
  4326. @item @var{sectors_per_bank}
  4327. @item @var{pages_per_sector}
  4328. @item @var{pages_size}
  4329. @item @var{num_nvm_bits}
  4330. @item @var{freq_khz} ... required if an external clock is provided,
  4331. optional (but recommended) when the oscillator frequency is known
  4332. @end itemize
  4333. It is recommended that you provide zeroes for all of those values
  4334. except the clock frequency, so that everything except that frequency
  4335. will be autoconfigured.
  4336. Knowing the frequency helps ensure correct timings for flash access.
  4337. The flash controller handles erases automatically on a page (128/256 byte)
  4338. basis, so explicit erase commands are not necessary for flash programming.
  4339. However, there is an ``EraseAll`` command that can erase an entire flash
  4340. plane (of up to 256KB), and it will be used automatically when you issue
  4341. @command{flash erase_sector} or @command{flash erase_address} commands.
  4342. @deffn Command {at91sam7 gpnvm} bitnum (@option{set}|@option{clear})
  4343. Set or clear a ``General Purpose Non-Volatile Memory'' (GPNVM)
  4344. bit for the processor. Each processor has a number of such bits,
  4345. used for controlling features such as brownout detection (so they
  4346. are not truly general purpose).
  4347. @quotation Note
  4348. This assumes that the first flash bank (number 0) is associated with
  4349. the appropriate at91sam7 target.
  4350. @end quotation
  4351. @end deffn
  4352. @end deffn
  4353. @deffn {Flash Driver} avr
  4354. The AVR 8-bit microcontrollers from Atmel integrate flash memory.
  4355. @emph{The current implementation is incomplete.}
  4356. @comment - defines mass_erase ... pointless given flash_erase_address
  4357. @end deffn
  4358. @deffn {Flash Driver} efm32
  4359. All members of the EFM32 microcontroller family from Energy Micro include
  4360. internal flash and use ARM Cortex M3 cores. The driver automatically recognizes
  4361. a number of these chips using the chip identification register, and
  4362. autoconfigures itself.
  4363. @example
  4364. flash bank $_FLASHNAME efm32 0 0 0 0 $_TARGETNAME
  4365. @end example
  4366. @emph{The current implementation is incomplete. Unprotecting flash pages is not
  4367. supported.}
  4368. @end deffn
  4369. @deffn {Flash Driver} lpc2000
  4370. Most members of the LPC1700, LPC1800, LPC2000 and LPC4300 microcontroller
  4371. families from NXP include internal flash and use Cortex-M3 (LPC1700, LPC1800),
  4372. Cortex-M4 (LPC4300) or ARM7TDMI (LPC2000) cores.
  4373. @quotation Note
  4374. There are LPC2000 devices which are not supported by the @var{lpc2000}
  4375. driver:
  4376. The LPC2888 is supported by the @var{lpc288x} driver.
  4377. The LPC29xx family is supported by the @var{lpc2900} driver.
  4378. @end quotation
  4379. The @var{lpc2000} driver defines two mandatory and one optional parameters,
  4380. which must appear in the following order:
  4381. @itemize
  4382. @item @var{variant} ... required, may be
  4383. @option{lpc2000_v1} (older LPC21xx and LPC22xx)
  4384. @option{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx)
  4385. @option{lpc1700} (LPC175x and LPC176x)
  4386. or @option{lpc4300} - available also as @option{lpc1800} alias (LPC18x[2357] and
  4387. LPC43x[2357])
  4388. @item @var{clock_kHz} ... the frequency, in kiloHertz,
  4389. at which the core is running
  4390. @item @option{calc_checksum} ... optional (but you probably want to provide this!),
  4391. telling the driver to calculate a valid checksum for the exception vector table.
  4392. @quotation Note
  4393. If you don't provide @option{calc_checksum} when you're writing the vector
  4394. table, the boot ROM will almost certainly ignore your flash image.
  4395. However, if you do provide it,
  4396. with most tool chains @command{verify_image} will fail.
  4397. @end quotation
  4398. @end itemize
  4399. LPC flashes don't require the chip and bus width to be specified.
  4400. @example
  4401. flash bank $_FLASHNAME lpc2000 0x0 0x7d000 0 0 $_TARGETNAME \
  4402. lpc2000_v2 14765 calc_checksum
  4403. @end example
  4404. @deffn {Command} {lpc2000 part_id} bank
  4405. Displays the four byte part identifier associated with
  4406. the specified flash @var{bank}.
  4407. @end deffn
  4408. @end deffn
  4409. @deffn {Flash Driver} lpc288x
  4410. The LPC2888 microcontroller from NXP needs slightly different flash
  4411. support from its lpc2000 siblings.
  4412. The @var{lpc288x} driver defines one mandatory parameter,
  4413. the programming clock rate in Hz.
  4414. LPC flashes don't require the chip and bus width to be specified.
  4415. @example
  4416. flash bank $_FLASHNAME lpc288x 0 0 0 0 $_TARGETNAME 12000000
  4417. @end example
  4418. @end deffn
  4419. @deffn {Flash Driver} lpc2900
  4420. This driver supports the LPC29xx ARM968E based microcontroller family
  4421. from NXP.
  4422. The predefined parameters @var{base}, @var{size}, @var{chip_width} and
  4423. @var{bus_width} of the @code{flash bank} command are ignored. Flash size and
  4424. sector layout are auto-configured by the driver.
  4425. The driver has one additional mandatory parameter: The CPU clock rate
  4426. (in kHz) at the time the flash operations will take place. Most of the time this
  4427. will not be the crystal frequency, but a higher PLL frequency. The
  4428. @code{reset-init} event handler in the board script is usually the place where
  4429. you start the PLL.
  4430. The driver rejects flashless devices (currently the LPC2930).
  4431. The EEPROM in LPC2900 devices is not mapped directly into the address space.
  4432. It must be handled much more like NAND flash memory, and will therefore be
  4433. handled by a separate @code{lpc2900_eeprom} driver (not yet available).
  4434. Sector protection in terms of the LPC2900 is handled transparently. Every time a
  4435. sector needs to be erased or programmed, it is automatically unprotected.
  4436. What is shown as protection status in the @code{flash info} command, is
  4437. actually the LPC2900 @emph{sector security}. This is a mechanism to prevent a
  4438. sector from ever being erased or programmed again. As this is an irreversible
  4439. mechanism, it is handled by a special command (@code{lpc2900 secure_sector}),
  4440. and not by the standard @code{flash protect} command.
  4441. Example for a 125 MHz clock frequency:
  4442. @example
  4443. flash bank $_FLASHNAME lpc2900 0 0 0 0 $_TARGETNAME 125000
  4444. @end example
  4445. Some @code{lpc2900}-specific commands are defined. In the following command list,
  4446. the @var{bank} parameter is the bank number as obtained by the
  4447. @code{flash banks} command.
  4448. @deffn Command {lpc2900 signature} bank
  4449. Calculates a 128-bit hash value, the @emph{signature}, from the whole flash
  4450. content. This is a hardware feature of the flash block, hence the calculation is
  4451. very fast. You may use this to verify the content of a programmed device against
  4452. a known signature.
  4453. Example:
  4454. @example
  4455. lpc2900 signature 0
  4456. signature: 0x5f40cdc8:0xc64e592e:0x10490f89:0x32a0f317
  4457. @end example
  4458. @end deffn
  4459. @deffn Command {lpc2900 read_custom} bank filename
  4460. Reads the 912 bytes of customer information from the flash index sector, and
  4461. saves it to a file in binary format.
  4462. Example:
  4463. @example
  4464. lpc2900 read_custom 0 /path_to/customer_info.bin
  4465. @end example
  4466. @end deffn
  4467. The index sector of the flash is a @emph{write-only} sector. It cannot be
  4468. erased! In order to guard against unintentional write access, all following
  4469. commands need to be preceeded by a successful call to the @code{password}
  4470. command:
  4471. @deffn Command {lpc2900 password} bank password
  4472. You need to use this command right before each of the following commands:
  4473. @code{lpc2900 write_custom}, @code{lpc2900 secure_sector},
  4474. @code{lpc2900 secure_jtag}.
  4475. The password string is fixed to "I_know_what_I_am_doing".
  4476. Example:
  4477. @example
  4478. lpc2900 password 0 I_know_what_I_am_doing
  4479. Potentially dangerous operation allowed in next command!
  4480. @end example
  4481. @end deffn
  4482. @deffn Command {lpc2900 write_custom} bank filename type
  4483. Writes the content of the file into the customer info space of the flash index
  4484. sector. The filetype can be specified with the @var{type} field. Possible values
  4485. for @var{type} are: @var{bin} (binary), @var{ihex} (Intel hex format),
  4486. @var{elf} (ELF binary) or @var{s19} (Motorola S-records). The file must
  4487. contain a single section, and the contained data length must be exactly
  4488. 912 bytes.
  4489. @quotation Attention
  4490. This cannot be reverted! Be careful!
  4491. @end quotation
  4492. Example:
  4493. @example
  4494. lpc2900 write_custom 0 /path_to/customer_info.bin bin
  4495. @end example
  4496. @end deffn
  4497. @deffn Command {lpc2900 secure_sector} bank first last
  4498. Secures the sector range from @var{first} to @var{last} (including) against
  4499. further program and erase operations. The sector security will be effective
  4500. after the next power cycle.
  4501. @quotation Attention
  4502. This cannot be reverted! Be careful!
  4503. @end quotation
  4504. Secured sectors appear as @emph{protected} in the @code{flash info} command.
  4505. Example:
  4506. @example
  4507. lpc2900 secure_sector 0 1 1
  4508. flash info 0
  4509. #0 : lpc2900 at 0x20000000, size 0x000c0000, (...)
  4510. # 0: 0x00000000 (0x2000 8kB) not protected
  4511. # 1: 0x00002000 (0x2000 8kB) protected
  4512. # 2: 0x00004000 (0x2000 8kB) not protected
  4513. @end example
  4514. @end deffn
  4515. @deffn Command {lpc2900 secure_jtag} bank
  4516. Irreversibly disable the JTAG port. The new JTAG security setting will be
  4517. effective after the next power cycle.
  4518. @quotation Attention
  4519. This cannot be reverted! Be careful!
  4520. @end quotation
  4521. Examples:
  4522. @example
  4523. lpc2900 secure_jtag 0
  4524. @end example
  4525. @end deffn
  4526. @end deffn
  4527. @deffn {Flash Driver} ocl
  4528. @emph{No idea what this is, other than using some arm7/arm9 core.}
  4529. @example
  4530. flash bank $_FLASHNAME ocl 0 0 0 0 $_TARGETNAME
  4531. @end example
  4532. @end deffn
  4533. @deffn {Flash Driver} pic32mx
  4534. The PIC32MX microcontrollers are based on the MIPS 4K cores,
  4535. and integrate flash memory.
  4536. @example
  4537. flash bank $_FLASHNAME pix32mx 0x1fc00000 0 0 0 $_TARGETNAME
  4538. flash bank $_FLASHNAME pix32mx 0x1d000000 0 0 0 $_TARGETNAME
  4539. @end example
  4540. @comment numerous *disabled* commands are defined:
  4541. @comment - chip_erase ... pointless given flash_erase_address
  4542. @comment - lock, unlock ... pointless given protect on/off (yes?)
  4543. @comment - pgm_word ... shouldn't bank be deduced from address??
  4544. Some pic32mx-specific commands are defined:
  4545. @deffn Command {pic32mx pgm_word} address value bank
  4546. Programs the specified 32-bit @var{value} at the given @var{address}
  4547. in the specified chip @var{bank}.
  4548. @end deffn
  4549. @deffn Command {pic32mx unlock} bank
  4550. Unlock and erase specified chip @var{bank}.
  4551. This will remove any Code Protection.
  4552. @end deffn
  4553. @end deffn
  4554. @deffn {Flash Driver} stellaris
  4555. All members of the Stellaris LM3Sxxx microcontroller family from
  4556. Texas Instruments
  4557. include internal flash and use ARM Cortex M3 cores.
  4558. The driver automatically recognizes a number of these chips using
  4559. the chip identification register, and autoconfigures itself.
  4560. @footnote{Currently there is a @command{stellaris mass_erase} command.
  4561. That seems pointless since the same effect can be had using the
  4562. standard @command{flash erase_address} command.}
  4563. @example
  4564. flash bank $_FLASHNAME stellaris 0 0 0 0 $_TARGETNAME
  4565. @end example
  4566. @deffn Command {stellaris recover bank_id}
  4567. Performs the @emph{Recovering a "Locked" Device} procedure to
  4568. restore the flash specified by @var{bank_id} and its associated
  4569. nonvolatile registers to their factory default values (erased).
  4570. This is the only way to remove flash protection or re-enable
  4571. debugging if that capability has been disabled.
  4572. Note that the final "power cycle the chip" step in this procedure
  4573. must be performed by hand, since OpenOCD can't do it.
  4574. @quotation Warning
  4575. if more than one Stellaris chip is connected, the procedure is
  4576. applied to all of them.
  4577. @end quotation
  4578. @end deffn
  4579. @end deffn
  4580. @deffn {Flash Driver} stm32f1x
  4581. All members of the STM32F0, STM32F1 and STM32F3 microcontroller families
  4582. from ST Microelectronics include internal flash and use ARM Cortex-M0/M3/M4 cores.
  4583. The driver automatically recognizes a number of these chips using
  4584. the chip identification register, and autoconfigures itself.
  4585. @example
  4586. flash bank $_FLASHNAME stm32f1x 0 0 0 0 $_TARGETNAME
  4587. @end example
  4588. Note that some devices have been found that have a flash size register that contains
  4589. an invalid value, to workaround this issue you can override the probed value used by
  4590. the flash driver.
  4591. @example
  4592. flash bank $_FLASHNAME stm32f1x 0 0x20000 0 0 $_TARGETNAME
  4593. @end example
  4594. If you have a target with dual flash banks then define the second bank
  4595. as per the following example.
  4596. @example
  4597. flash bank $_FLASHNAME stm32f1x 0x08080000 0 0 0 $_TARGETNAME
  4598. @end example
  4599. Some stm32f1x-specific commands
  4600. @footnote{Currently there is a @command{stm32f1x mass_erase} command.
  4601. That seems pointless since the same effect can be had using the
  4602. standard @command{flash erase_address} command.}
  4603. are defined:
  4604. @deffn Command {stm32f1x lock} num
  4605. Locks the entire stm32 device.
  4606. The @var{num} parameter is a value shown by @command{flash banks}.
  4607. @end deffn
  4608. @deffn Command {stm32f1x unlock} num
  4609. Unlocks the entire stm32 device.
  4610. The @var{num} parameter is a value shown by @command{flash banks}.
  4611. @end deffn
  4612. @deffn Command {stm32f1x options_read} num
  4613. Read and display the stm32 option bytes written by
  4614. the @command{stm32f1x options_write} command.
  4615. The @var{num} parameter is a value shown by @command{flash banks}.
  4616. @end deffn
  4617. @deffn Command {stm32f1x options_write} num (@option{SWWDG}|@option{HWWDG}) (@option{RSTSTNDBY}|@option{NORSTSTNDBY}) (@option{RSTSTOP}|@option{NORSTSTOP})
  4618. Writes the stm32 option byte with the specified values.
  4619. The @var{num} parameter is a value shown by @command{flash banks}.
  4620. @end deffn
  4621. @end deffn
  4622. @deffn {Flash Driver} stm32f2x
  4623. All members of the STM32F2 and STM32F4 microcontroller families from ST Microelectronics
  4624. include internal flash and use ARM Cortex-M3/M4 cores.
  4625. The driver automatically recognizes a number of these chips using
  4626. the chip identification register, and autoconfigures itself.
  4627. Note that some devices have been found that have a flash size register that contains
  4628. an invalid value, to workaround this issue you can override the probed value used by
  4629. the flash driver.
  4630. @example
  4631. flash bank $_FLASHNAME stm32f2x 0 0x20000 0 0 $_TARGETNAME
  4632. @end example
  4633. Some stm32f2x-specific commands are defined:
  4634. @deffn Command {stm32f2x lock} num
  4635. Locks the entire stm32 device.
  4636. The @var{num} parameter is a value shown by @command{flash banks}.
  4637. @end deffn
  4638. @deffn Command {stm32f2x unlock} num
  4639. Unlocks the entire stm32 device.
  4640. The @var{num} parameter is a value shown by @command{flash banks}.
  4641. @end deffn
  4642. @end deffn
  4643. @deffn {Flash Driver} stm32lx
  4644. All members of the STM32L microcontroller families from ST Microelectronics
  4645. include internal flash and use ARM Cortex-M3 cores.
  4646. The driver automatically recognizes a number of these chips using
  4647. the chip identification register, and autoconfigures itself.
  4648. Note that some devices have been found that have a flash size register that contains
  4649. an invalid value, to workaround this issue you can override the probed value used by
  4650. the flash driver.
  4651. @example
  4652. flash bank $_FLASHNAME stm32lx 0 0x20000 0 0 $_TARGETNAME
  4653. @end example
  4654. @end deffn
  4655. @deffn {Flash Driver} str7x
  4656. All members of the STR7 microcontroller family from ST Microelectronics
  4657. include internal flash and use ARM7TDMI cores.
  4658. The @var{str7x} driver defines one mandatory parameter, @var{variant},
  4659. which is either @code{STR71x}, @code{STR73x} or @code{STR75x}.
  4660. @example
  4661. flash bank $_FLASHNAME str7x 0x40000000 0x00040000 0 0 $_TARGETNAME STR71x
  4662. @end example
  4663. @deffn Command {str7x disable_jtag} bank
  4664. Activate the Debug/Readout protection mechanism
  4665. for the specified flash bank.
  4666. @end deffn
  4667. @end deffn
  4668. @deffn {Flash Driver} str9x
  4669. Most members of the STR9 microcontroller family from ST Microelectronics
  4670. include internal flash and use ARM966E cores.
  4671. The str9 needs the flash controller to be configured using
  4672. the @command{str9x flash_config} command prior to Flash programming.
  4673. @example
  4674. flash bank $_FLASHNAME str9x 0x40000000 0x00040000 0 0 $_TARGETNAME
  4675. str9x flash_config 0 4 2 0 0x80000
  4676. @end example
  4677. @deffn Command {str9x flash_config} num bbsr nbbsr bbadr nbbadr
  4678. Configures the str9 flash controller.
  4679. The @var{num} parameter is a value shown by @command{flash banks}.
  4680. @itemize @bullet
  4681. @item @var{bbsr} - Boot Bank Size register
  4682. @item @var{nbbsr} - Non Boot Bank Size register
  4683. @item @var{bbadr} - Boot Bank Start Address register
  4684. @item @var{nbbadr} - Boot Bank Start Address register
  4685. @end itemize
  4686. @end deffn
  4687. @end deffn
  4688. @deffn {Flash Driver} tms470
  4689. Most members of the TMS470 microcontroller family from Texas Instruments
  4690. include internal flash and use ARM7TDMI cores.
  4691. This driver doesn't require the chip and bus width to be specified.
  4692. Some tms470-specific commands are defined:
  4693. @deffn Command {tms470 flash_keyset} key0 key1 key2 key3
  4694. Saves programming keys in a register, to enable flash erase and write commands.
  4695. @end deffn
  4696. @deffn Command {tms470 osc_mhz} clock_mhz
  4697. Reports the clock speed, which is used to calculate timings.
  4698. @end deffn
  4699. @deffn Command {tms470 plldis} (0|1)
  4700. Disables (@var{1}) or enables (@var{0}) use of the PLL to speed up
  4701. the flash clock.
  4702. @end deffn
  4703. @end deffn
  4704. @deffn {Flash Driver} virtual
  4705. This is a special driver that maps a previously defined bank to another
  4706. address. All bank settings will be copied from the master physical bank.
  4707. The @var{virtual} driver defines one mandatory parameters,
  4708. @itemize
  4709. @item @var{master_bank} The bank that this virtual address refers to.
  4710. @end itemize
  4711. So in the following example addresses 0xbfc00000 and 0x9fc00000 refer to
  4712. the flash bank defined at address 0x1fc00000. Any cmds executed on
  4713. the virtual banks are actually performed on the physical banks.
  4714. @example
  4715. flash bank $_FLASHNAME pic32mx 0x1fc00000 0 0 0 $_TARGETNAME
  4716. flash bank vbank0 virtual 0xbfc00000 0 0 0 $_TARGETNAME $_FLASHNAME
  4717. flash bank vbank1 virtual 0x9fc00000 0 0 0 $_TARGETNAME $_FLASHNAME
  4718. @end example
  4719. @end deffn
  4720. @deffn {Flash Driver} fm3
  4721. All members of the FM3 microcontroller family from Fujitsu
  4722. include internal flash and use ARM Cortex M3 cores.
  4723. The @var{fm3} driver uses the @var{target} parameter to select the
  4724. correct bank config, it can currently be one of the following:
  4725. @code{mb9bfxx1.cpu}, @code{mb9bfxx2.cpu}, @code{mb9bfxx3.cpu},
  4726. @code{mb9bfxx4.cpu}, @code{mb9bfxx5.cpu} or @code{mb9bfxx6.cpu}.
  4727. @example
  4728. flash bank $_FLASHNAME fm3 0 0 0 0 $_TARGETNAME
  4729. @end example
  4730. @end deffn
  4731. @subsection str9xpec driver
  4732. @cindex str9xpec
  4733. Here is some background info to help
  4734. you better understand how this driver works. OpenOCD has two flash drivers for
  4735. the str9:
  4736. @enumerate
  4737. @item
  4738. Standard driver @option{str9x} programmed via the str9 core. Normally used for
  4739. flash programming as it is faster than the @option{str9xpec} driver.
  4740. @item
  4741. Direct programming @option{str9xpec} using the flash controller. This is an
  4742. ISC compilant (IEEE 1532) tap connected in series with the str9 core. The str9
  4743. core does not need to be running to program using this flash driver. Typical use
  4744. for this driver is locking/unlocking the target and programming the option bytes.
  4745. @end enumerate
  4746. Before we run any commands using the @option{str9xpec} driver we must first disable
  4747. the str9 core. This example assumes the @option{str9xpec} driver has been
  4748. configured for flash bank 0.
  4749. @example
  4750. # assert srst, we do not want core running
  4751. # while accessing str9xpec flash driver
  4752. jtag_reset 0 1
  4753. # turn off target polling
  4754. poll off
  4755. # disable str9 core
  4756. str9xpec enable_turbo 0
  4757. # read option bytes
  4758. str9xpec options_read 0
  4759. # re-enable str9 core
  4760. str9xpec disable_turbo 0
  4761. poll on
  4762. reset halt
  4763. @end example
  4764. The above example will read the str9 option bytes.
  4765. When performing a unlock remember that you will not be able to halt the str9 - it
  4766. has been locked. Halting the core is not required for the @option{str9xpec} driver
  4767. as mentioned above, just issue the commands above manually or from a telnet prompt.
  4768. @deffn {Flash Driver} str9xpec
  4769. Only use this driver for locking/unlocking the device or configuring the option bytes.
  4770. Use the standard str9 driver for programming.
  4771. Before using the flash commands the turbo mode must be enabled using the
  4772. @command{str9xpec enable_turbo} command.
  4773. Several str9xpec-specific commands are defined:
  4774. @deffn Command {str9xpec disable_turbo} num
  4775. Restore the str9 into JTAG chain.
  4776. @end deffn
  4777. @deffn Command {str9xpec enable_turbo} num
  4778. Enable turbo mode, will simply remove the str9 from the chain and talk
  4779. directly to the embedded flash controller.
  4780. @end deffn
  4781. @deffn Command {str9xpec lock} num
  4782. Lock str9 device. The str9 will only respond to an unlock command that will
  4783. erase the device.
  4784. @end deffn
  4785. @deffn Command {str9xpec part_id} num
  4786. Prints the part identifier for bank @var{num}.
  4787. @end deffn
  4788. @deffn Command {str9xpec options_cmap} num (@option{bank0}|@option{bank1})
  4789. Configure str9 boot bank.
  4790. @end deffn
  4791. @deffn Command {str9xpec options_lvdsel} num (@option{vdd}|@option{vdd_vddq})
  4792. Configure str9 lvd source.
  4793. @end deffn
  4794. @deffn Command {str9xpec options_lvdthd} num (@option{2.4v}|@option{2.7v})
  4795. Configure str9 lvd threshold.
  4796. @end deffn
  4797. @deffn Command {str9xpec options_lvdwarn} bank (@option{vdd}|@option{vdd_vddq})
  4798. Configure str9 lvd reset warning source.
  4799. @end deffn
  4800. @deffn Command {str9xpec options_read} num
  4801. Read str9 option bytes.
  4802. @end deffn
  4803. @deffn Command {str9xpec options_write} num
  4804. Write str9 option bytes.
  4805. @end deffn
  4806. @deffn Command {str9xpec unlock} num
  4807. unlock str9 device.
  4808. @end deffn
  4809. @end deffn
  4810. @deffn {Flash Driver} nrf51
  4811. All members of the nRF51 microcontroller families from Nordic Semiconductor
  4812. include internal flash and use ARM Cortex-M0 core.
  4813. @example
  4814. flash bank $_FLASHNAME nrf51 0 0x00000000 0 0 $_TARGETNAME
  4815. @end example
  4816. Some nrf51-specific commands are defined:
  4817. @deffn Command {nrf51 mass_erase}
  4818. Erases the contents of the code memory and user information
  4819. configuration registers as well. It must be noted that this command
  4820. works only for chips that do not have factory pre-programmed region 0
  4821. code.
  4822. @end deffn
  4823. @end deffn
  4824. @section mFlash
  4825. @subsection mFlash Configuration
  4826. @cindex mFlash Configuration
  4827. @deffn {Config Command} {mflash bank} soc base RST_pin target
  4828. Configures a mflash for @var{soc} host bank at
  4829. address @var{base}.
  4830. The pin number format depends on the host GPIO naming convention.
  4831. Currently, the mflash driver supports s3c2440 and pxa270.
  4832. Example for s3c2440 mflash where @var{RST pin} is GPIO B1:
  4833. @example
  4834. mflash bank $_FLASHNAME s3c2440 0x10000000 1b 0
  4835. @end example
  4836. Example for pxa270 mflash where @var{RST pin} is GPIO 43:
  4837. @example
  4838. mflash bank $_FLASHNAME pxa270 0x08000000 43 0
  4839. @end example
  4840. @end deffn
  4841. @subsection mFlash commands
  4842. @cindex mFlash commands
  4843. @deffn Command {mflash config pll} frequency
  4844. Configure mflash PLL.
  4845. The @var{frequency} is the mflash input frequency, in Hz.
  4846. Issuing this command will erase mflash's whole internal nand and write new pll.
  4847. After this command, mflash needs power-on-reset for normal operation.
  4848. If pll was newly configured, storage and boot(optional) info also need to be update.
  4849. @end deffn
  4850. @deffn Command {mflash config boot}
  4851. Configure bootable option.
  4852. If bootable option is set, mflash offer the first 8 sectors
  4853. (4kB) for boot.
  4854. @end deffn
  4855. @deffn Command {mflash config storage}
  4856. Configure storage information.
  4857. For the normal storage operation, this information must be
  4858. written.
  4859. @end deffn
  4860. @deffn Command {mflash dump} num filename offset size
  4861. Dump @var{size} bytes, starting at @var{offset} bytes from the
  4862. beginning of the bank @var{num}, to the file named @var{filename}.
  4863. @end deffn
  4864. @deffn Command {mflash probe}
  4865. Probe mflash.
  4866. @end deffn
  4867. @deffn Command {mflash write} num filename offset
  4868. Write the binary file @var{filename} to mflash bank @var{num}, starting at
  4869. @var{offset} bytes from the beginning of the bank.
  4870. @end deffn
  4871. @node Flash Programming
  4872. @chapter Flash Programming
  4873. OpenOCD implements numerous ways to program the target flash, whether internal or external.
  4874. Programming can be acheived by either using GDB @ref{programmingusinggdb,,Programming using GDB},
  4875. or using the cmds given in @ref{flashprogrammingcommands,,Flash Programming Commands}.
  4876. @*To simplify using the flash cmds directly a jimtcl script is available that handles the programming and verify stage.
  4877. OpenOCD will program/verify/reset the target and shutdown.
  4878. The script is executed as follows and by default the following actions will be peformed.
  4879. @enumerate
  4880. @item 'init' is executed.
  4881. @item 'reset init' is called to reset and halt the target, any 'reset init' scripts are executed.
  4882. @item @code{flash write_image} is called to erase and write any flash using the filename given.
  4883. @item @code{verify_image} is called if @option{verify} parameter is given.
  4884. @item @code{reset run} is called if @option{reset} parameter is given.
  4885. @item OpenOCD is shutdown.
  4886. @end enumerate
  4887. An example of usage is given below. @xref{program}.
  4888. @example
  4889. # program and verify using elf/hex/s19. verify and reset
  4890. # are optional parameters
  4891. openocd -f board/stm32f3discovery.cfg \
  4892. -c "program filename.elf verify reset"
  4893. # binary files need the flash address passing
  4894. openocd -f board/stm32f3discovery.cfg \
  4895. -c "program filename.bin 0x08000000"
  4896. @end example
  4897. @node NAND Flash Commands
  4898. @chapter NAND Flash Commands
  4899. @cindex NAND
  4900. Compared to NOR or SPI flash, NAND devices are inexpensive
  4901. and high density. Today's NAND chips, and multi-chip modules,
  4902. commonly hold multiple GigaBytes of data.
  4903. NAND chips consist of a number of ``erase blocks'' of a given
  4904. size (such as 128 KBytes), each of which is divided into a
  4905. number of pages (of perhaps 512 or 2048 bytes each). Each
  4906. page of a NAND flash has an ``out of band'' (OOB) area to hold
  4907. Error Correcting Code (ECC) and other metadata, usually 16 bytes
  4908. of OOB for every 512 bytes of page data.
  4909. One key characteristic of NAND flash is that its error rate
  4910. is higher than that of NOR flash. In normal operation, that
  4911. ECC is used to correct and detect errors. However, NAND
  4912. blocks can also wear out and become unusable; those blocks
  4913. are then marked "bad". NAND chips are even shipped from the
  4914. manufacturer with a few bad blocks. The highest density chips
  4915. use a technology (MLC) that wears out more quickly, so ECC
  4916. support is increasingly important as a way to detect blocks
  4917. that have begun to fail, and help to preserve data integrity
  4918. with techniques such as wear leveling.
  4919. Software is used to manage the ECC. Some controllers don't
  4920. support ECC directly; in those cases, software ECC is used.
  4921. Other controllers speed up the ECC calculations with hardware.
  4922. Single-bit error correction hardware is routine. Controllers
  4923. geared for newer MLC chips may correct 4 or more errors for
  4924. every 512 bytes of data.
  4925. You will need to make sure that any data you write using
  4926. OpenOCD includes the apppropriate kind of ECC. For example,
  4927. that may mean passing the @code{oob_softecc} flag when
  4928. writing NAND data, or ensuring that the correct hardware
  4929. ECC mode is used.
  4930. The basic steps for using NAND devices include:
  4931. @enumerate
  4932. @item Declare via the command @command{nand device}
  4933. @* Do this in a board-specific configuration file,
  4934. passing parameters as needed by the controller.
  4935. @item Configure each device using @command{nand probe}.
  4936. @* Do this only after the associated target is set up,
  4937. such as in its reset-init script or in procures defined
  4938. to access that device.
  4939. @item Operate on the flash via @command{nand subcommand}
  4940. @* Often commands to manipulate the flash are typed by a human, or run
  4941. via a script in some automated way. Common task include writing a
  4942. boot loader, operating system, or other data needed to initialize or
  4943. de-brick a board.
  4944. @end enumerate
  4945. @b{NOTE:} At the time this text was written, the largest NAND
  4946. flash fully supported by OpenOCD is 2 GiBytes (16 GiBits).
  4947. This is because the variables used to hold offsets and lengths
  4948. are only 32 bits wide.
  4949. (Larger chips may work in some cases, unless an offset or length
  4950. is larger than 0xffffffff, the largest 32-bit unsigned integer.)
  4951. Some larger devices will work, since they are actually multi-chip
  4952. modules with two smaller chips and individual chipselect lines.
  4953. @anchor{nandconfiguration}
  4954. @section NAND Configuration Commands
  4955. @cindex NAND configuration
  4956. NAND chips must be declared in configuration scripts,
  4957. plus some additional configuration that's done after
  4958. OpenOCD has initialized.
  4959. @deffn {Config Command} {nand device} name driver target [configparams...]
  4960. Declares a NAND device, which can be read and written to
  4961. after it has been configured through @command{nand probe}.
  4962. In OpenOCD, devices are single chips; this is unlike some
  4963. operating systems, which may manage multiple chips as if
  4964. they were a single (larger) device.
  4965. In some cases, configuring a device will activate extra
  4966. commands; see the controller-specific documentation.
  4967. @b{NOTE:} This command is not available after OpenOCD
  4968. initialization has completed. Use it in board specific
  4969. configuration files, not interactively.
  4970. @itemize @bullet
  4971. @item @var{name} ... may be used to reference the NAND bank
  4972. in most other NAND commands. A number is also available.
  4973. @item @var{driver} ... identifies the NAND controller driver
  4974. associated with the NAND device being declared.
  4975. @xref{nanddriverlist,,NAND Driver List}.
  4976. @item @var{target} ... names the target used when issuing
  4977. commands to the NAND controller.
  4978. @comment Actually, it's currently a controller-specific parameter...
  4979. @item @var{configparams} ... controllers may support, or require,
  4980. additional parameters. See the controller-specific documentation
  4981. for more information.
  4982. @end itemize
  4983. @end deffn
  4984. @deffn Command {nand list}
  4985. Prints a summary of each device declared
  4986. using @command{nand device}, numbered from zero.
  4987. Note that un-probed devices show no details.
  4988. @example
  4989. > nand list
  4990. #0: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
  4991. blocksize: 131072, blocks: 8192
  4992. #1: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
  4993. blocksize: 131072, blocks: 8192
  4994. >
  4995. @end example
  4996. @end deffn
  4997. @deffn Command {nand probe} num
  4998. Probes the specified device to determine key characteristics
  4999. like its page and block sizes, and how many blocks it has.
  5000. The @var{num} parameter is the value shown by @command{nand list}.
  5001. You must (successfully) probe a device before you can use
  5002. it with most other NAND commands.
  5003. @end deffn
  5004. @section Erasing, Reading, Writing to NAND Flash
  5005. @deffn Command {nand dump} num filename offset length [oob_option]
  5006. @cindex NAND reading
  5007. Reads binary data from the NAND device and writes it to the file,
  5008. starting at the specified offset.
  5009. The @var{num} parameter is the value shown by @command{nand list}.
  5010. Use a complete path name for @var{filename}, so you don't depend
  5011. on the directory used to start the OpenOCD server.
  5012. The @var{offset} and @var{length} must be exact multiples of the
  5013. device's page size. They describe a data region; the OOB data
  5014. associated with each such page may also be accessed.
  5015. @b{NOTE:} At the time this text was written, no error correction
  5016. was done on the data that's read, unless raw access was disabled
  5017. and the underlying NAND controller driver had a @code{read_page}
  5018. method which handled that error correction.
  5019. By default, only page data is saved to the specified file.
  5020. Use an @var{oob_option} parameter to save OOB data:
  5021. @itemize @bullet
  5022. @item no oob_* parameter
  5023. @*Output file holds only page data; OOB is discarded.
  5024. @item @code{oob_raw}
  5025. @*Output file interleaves page data and OOB data;
  5026. the file will be longer than "length" by the size of the
  5027. spare areas associated with each data page.
  5028. Note that this kind of "raw" access is different from
  5029. what's implied by @command{nand raw_access}, which just
  5030. controls whether a hardware-aware access method is used.
  5031. @item @code{oob_only}
  5032. @*Output file has only raw OOB data, and will
  5033. be smaller than "length" since it will contain only the
  5034. spare areas associated with each data page.
  5035. @end itemize
  5036. @end deffn
  5037. @deffn Command {nand erase} num [offset length]
  5038. @cindex NAND erasing
  5039. @cindex NAND programming
  5040. Erases blocks on the specified NAND device, starting at the
  5041. specified @var{offset} and continuing for @var{length} bytes.
  5042. Both of those values must be exact multiples of the device's
  5043. block size, and the region they specify must fit entirely in the chip.
  5044. If those parameters are not specified,
  5045. the whole NAND chip will be erased.
  5046. The @var{num} parameter is the value shown by @command{nand list}.
  5047. @b{NOTE:} This command will try to erase bad blocks, when told
  5048. to do so, which will probably invalidate the manufacturer's bad
  5049. block marker.
  5050. For the remainder of the current server session, @command{nand info}
  5051. will still report that the block ``is'' bad.
  5052. @end deffn
  5053. @deffn Command {nand write} num filename offset [option...]
  5054. @cindex NAND writing
  5055. @cindex NAND programming
  5056. Writes binary data from the file into the specified NAND device,
  5057. starting at the specified offset. Those pages should already
  5058. have been erased; you can't change zero bits to one bits.
  5059. The @var{num} parameter is the value shown by @command{nand list}.
  5060. Use a complete path name for @var{filename}, so you don't depend
  5061. on the directory used to start the OpenOCD server.
  5062. The @var{offset} must be an exact multiple of the device's page size.
  5063. All data in the file will be written, assuming it doesn't run
  5064. past the end of the device.
  5065. Only full pages are written, and any extra space in the last
  5066. page will be filled with 0xff bytes. (That includes OOB data,
  5067. if that's being written.)
  5068. @b{NOTE:} At the time this text was written, bad blocks are
  5069. ignored. That is, this routine will not skip bad blocks,
  5070. but will instead try to write them. This can cause problems.
  5071. Provide at most one @var{option} parameter. With some
  5072. NAND drivers, the meanings of these parameters may change
  5073. if @command{nand raw_access} was used to disable hardware ECC.
  5074. @itemize @bullet
  5075. @item no oob_* parameter
  5076. @*File has only page data, which is written.
  5077. If raw acccess is in use, the OOB area will not be written.
  5078. Otherwise, if the underlying NAND controller driver has
  5079. a @code{write_page} routine, that routine may write the OOB
  5080. with hardware-computed ECC data.
  5081. @item @code{oob_only}
  5082. @*File has only raw OOB data, which is written to the OOB area.
  5083. Each page's data area stays untouched. @i{This can be a dangerous
  5084. option}, since it can invalidate the ECC data.
  5085. You may need to force raw access to use this mode.
  5086. @item @code{oob_raw}
  5087. @*File interleaves data and OOB data, both of which are written
  5088. If raw access is enabled, the data is written first, then the
  5089. un-altered OOB.
  5090. Otherwise, if the underlying NAND controller driver has
  5091. a @code{write_page} routine, that routine may modify the OOB
  5092. before it's written, to include hardware-computed ECC data.
  5093. @item @code{oob_softecc}
  5094. @*File has only page data, which is written.
  5095. The OOB area is filled with 0xff, except for a standard 1-bit
  5096. software ECC code stored in conventional locations.
  5097. You might need to force raw access to use this mode, to prevent
  5098. the underlying driver from applying hardware ECC.
  5099. @item @code{oob_softecc_kw}
  5100. @*File has only page data, which is written.
  5101. The OOB area is filled with 0xff, except for a 4-bit software ECC
  5102. specific to the boot ROM in Marvell Kirkwood SoCs.
  5103. You might need to force raw access to use this mode, to prevent
  5104. the underlying driver from applying hardware ECC.
  5105. @end itemize
  5106. @end deffn
  5107. @deffn Command {nand verify} num filename offset [option...]
  5108. @cindex NAND verification
  5109. @cindex NAND programming
  5110. Verify the binary data in the file has been programmed to the
  5111. specified NAND device, starting at the specified offset.
  5112. The @var{num} parameter is the value shown by @command{nand list}.
  5113. Use a complete path name for @var{filename}, so you don't depend
  5114. on the directory used to start the OpenOCD server.
  5115. The @var{offset} must be an exact multiple of the device's page size.
  5116. All data in the file will be read and compared to the contents of the
  5117. flash, assuming it doesn't run past the end of the device.
  5118. As with @command{nand write}, only full pages are verified, so any extra
  5119. space in the last page will be filled with 0xff bytes.
  5120. The same @var{options} accepted by @command{nand write},
  5121. and the file will be processed similarly to produce the buffers that
  5122. can be compared against the contents produced from @command{nand dump}.
  5123. @b{NOTE:} This will not work when the underlying NAND controller
  5124. driver's @code{write_page} routine must update the OOB with a
  5125. hardward-computed ECC before the data is written. This limitation may
  5126. be removed in a future release.
  5127. @end deffn
  5128. @section Other NAND commands
  5129. @cindex NAND other commands
  5130. @deffn Command {nand check_bad_blocks} num [offset length]
  5131. Checks for manufacturer bad block markers on the specified NAND
  5132. device. If no parameters are provided, checks the whole
  5133. device; otherwise, starts at the specified @var{offset} and
  5134. continues for @var{length} bytes.
  5135. Both of those values must be exact multiples of the device's
  5136. block size, and the region they specify must fit entirely in the chip.
  5137. The @var{num} parameter is the value shown by @command{nand list}.
  5138. @b{NOTE:} Before using this command you should force raw access
  5139. with @command{nand raw_access enable} to ensure that the underlying
  5140. driver will not try to apply hardware ECC.
  5141. @end deffn
  5142. @deffn Command {nand info} num
  5143. The @var{num} parameter is the value shown by @command{nand list}.
  5144. This prints the one-line summary from "nand list", plus for
  5145. devices which have been probed this also prints any known
  5146. status for each block.
  5147. @end deffn
  5148. @deffn Command {nand raw_access} num (@option{enable}|@option{disable})
  5149. Sets or clears an flag affecting how page I/O is done.
  5150. The @var{num} parameter is the value shown by @command{nand list}.
  5151. This flag is cleared (disabled) by default, but changing that
  5152. value won't affect all NAND devices. The key factor is whether
  5153. the underlying driver provides @code{read_page} or @code{write_page}
  5154. methods. If it doesn't provide those methods, the setting of
  5155. this flag is irrelevant; all access is effectively ``raw''.
  5156. When those methods exist, they are normally used when reading
  5157. data (@command{nand dump} or reading bad block markers) or
  5158. writing it (@command{nand write}). However, enabling
  5159. raw access (setting the flag) prevents use of those methods,
  5160. bypassing hardware ECC logic.
  5161. @i{This can be a dangerous option}, since writing blocks
  5162. with the wrong ECC data can cause them to be marked as bad.
  5163. @end deffn
  5164. @anchor{nanddriverlist}
  5165. @section NAND Driver List
  5166. As noted above, the @command{nand device} command allows
  5167. driver-specific options and behaviors.
  5168. Some controllers also activate controller-specific commands.
  5169. @deffn {NAND Driver} at91sam9
  5170. This driver handles the NAND controllers found on AT91SAM9 family chips from
  5171. Atmel. It takes two extra parameters: address of the NAND chip;
  5172. address of the ECC controller.
  5173. @example
  5174. nand device $NANDFLASH at91sam9 $CHIPNAME 0x40000000 0xfffffe800
  5175. @end example
  5176. AT91SAM9 chips support single-bit ECC hardware. The @code{write_page} and
  5177. @code{read_page} methods are used to utilize the ECC hardware unless they are
  5178. disabled by using the @command{nand raw_access} command. There are four
  5179. additional commands that are needed to fully configure the AT91SAM9 NAND
  5180. controller. Two are optional; most boards use the same wiring for ALE/CLE:
  5181. @deffn Command {at91sam9 cle} num addr_line
  5182. Configure the address line used for latching commands. The @var{num}
  5183. parameter is the value shown by @command{nand list}.
  5184. @end deffn
  5185. @deffn Command {at91sam9 ale} num addr_line
  5186. Configure the address line used for latching addresses. The @var{num}
  5187. parameter is the value shown by @command{nand list}.
  5188. @end deffn
  5189. For the next two commands, it is assumed that the pins have already been
  5190. properly configured for input or output.
  5191. @deffn Command {at91sam9 rdy_busy} num pio_base_addr pin
  5192. Configure the RDY/nBUSY input from the NAND device. The @var{num}
  5193. parameter is the value shown by @command{nand list}. @var{pio_base_addr}
  5194. is the base address of the PIO controller and @var{pin} is the pin number.
  5195. @end deffn
  5196. @deffn Command {at91sam9 ce} num pio_base_addr pin
  5197. Configure the chip enable input to the NAND device. The @var{num}
  5198. parameter is the value shown by @command{nand list}. @var{pio_base_addr}
  5199. is the base address of the PIO controller and @var{pin} is the pin number.
  5200. @end deffn
  5201. @end deffn
  5202. @deffn {NAND Driver} davinci
  5203. This driver handles the NAND controllers found on DaVinci family
  5204. chips from Texas Instruments.
  5205. It takes three extra parameters:
  5206. address of the NAND chip;
  5207. hardware ECC mode to use (@option{hwecc1},
  5208. @option{hwecc4}, @option{hwecc4_infix});
  5209. address of the AEMIF controller on this processor.
  5210. @example
  5211. nand device davinci dm355.arm 0x02000000 hwecc4 0x01e10000
  5212. @end example
  5213. All DaVinci processors support the single-bit ECC hardware,
  5214. and newer ones also support the four-bit ECC hardware.
  5215. The @code{write_page} and @code{read_page} methods are used
  5216. to implement those ECC modes, unless they are disabled using
  5217. the @command{nand raw_access} command.
  5218. @end deffn
  5219. @deffn {NAND Driver} lpc3180
  5220. These controllers require an extra @command{nand device}
  5221. parameter: the clock rate used by the controller.
  5222. @deffn Command {lpc3180 select} num [mlc|slc]
  5223. Configures use of the MLC or SLC controller mode.
  5224. MLC implies use of hardware ECC.
  5225. The @var{num} parameter is the value shown by @command{nand list}.
  5226. @end deffn
  5227. At this writing, this driver includes @code{write_page}
  5228. and @code{read_page} methods. Using @command{nand raw_access}
  5229. to disable those methods will prevent use of hardware ECC
  5230. in the MLC controller mode, but won't change SLC behavior.
  5231. @end deffn
  5232. @comment current lpc3180 code won't issue 5-byte address cycles
  5233. @deffn {NAND Driver} mx3
  5234. This driver handles the NAND controller in i.MX31. The mxc driver
  5235. should work for this chip aswell.
  5236. @end deffn
  5237. @deffn {NAND Driver} mxc
  5238. This driver handles the NAND controller found in Freescale i.MX
  5239. chips. It has support for v1 (i.MX27 and i.MX31) and v2 (i.MX35).
  5240. The driver takes 3 extra arguments, chip (@option{mx27},
  5241. @option{mx31}, @option{mx35}), ecc (@option{noecc}, @option{hwecc})
  5242. and optionally if bad block information should be swapped between
  5243. main area and spare area (@option{biswap}), defaults to off.
  5244. @example
  5245. nand device mx35.nand mxc imx35.cpu mx35 hwecc biswap
  5246. @end example
  5247. @deffn Command {mxc biswap} bank_num [enable|disable]
  5248. Turns on/off bad block information swaping from main area,
  5249. without parameter query status.
  5250. @end deffn
  5251. @end deffn
  5252. @deffn {NAND Driver} orion
  5253. These controllers require an extra @command{nand device}
  5254. parameter: the address of the controller.
  5255. @example
  5256. nand device orion 0xd8000000
  5257. @end example
  5258. These controllers don't define any specialized commands.
  5259. At this writing, their drivers don't include @code{write_page}
  5260. or @code{read_page} methods, so @command{nand raw_access} won't
  5261. change any behavior.
  5262. @end deffn
  5263. @deffn {NAND Driver} s3c2410
  5264. @deffnx {NAND Driver} s3c2412
  5265. @deffnx {NAND Driver} s3c2440
  5266. @deffnx {NAND Driver} s3c2443
  5267. @deffnx {NAND Driver} s3c6400
  5268. These S3C family controllers don't have any special
  5269. @command{nand device} options, and don't define any
  5270. specialized commands.
  5271. At this writing, their drivers don't include @code{write_page}
  5272. or @code{read_page} methods, so @command{nand raw_access} won't
  5273. change any behavior.
  5274. @end deffn
  5275. @node PLD/FPGA Commands
  5276. @chapter PLD/FPGA Commands
  5277. @cindex PLD
  5278. @cindex FPGA
  5279. Programmable Logic Devices (PLDs) and the more flexible
  5280. Field Programmable Gate Arrays (FPGAs) are both types of programmable hardware.
  5281. OpenOCD can support programming them.
  5282. Although PLDs are generally restrictive (cells are less functional, and
  5283. there are no special purpose cells for memory or computational tasks),
  5284. they share the same OpenOCD infrastructure.
  5285. Accordingly, both are called PLDs here.
  5286. @section PLD/FPGA Configuration and Commands
  5287. As it does for JTAG TAPs, debug targets, and flash chips (both NOR and NAND),
  5288. OpenOCD maintains a list of PLDs available for use in various commands.
  5289. Also, each such PLD requires a driver.
  5290. They are referenced by the number shown by the @command{pld devices} command,
  5291. and new PLDs are defined by @command{pld device driver_name}.
  5292. @deffn {Config Command} {pld device} driver_name tap_name [driver_options]
  5293. Defines a new PLD device, supported by driver @var{driver_name},
  5294. using the TAP named @var{tap_name}.
  5295. The driver may make use of any @var{driver_options} to configure its
  5296. behavior.
  5297. @end deffn
  5298. @deffn {Command} {pld devices}
  5299. Lists the PLDs and their numbers.
  5300. @end deffn
  5301. @deffn {Command} {pld load} num filename
  5302. Loads the file @file{filename} into the PLD identified by @var{num}.
  5303. The file format must be inferred by the driver.
  5304. @end deffn
  5305. @section PLD/FPGA Drivers, Options, and Commands
  5306. Drivers may support PLD-specific options to the @command{pld device}
  5307. definition command, and may also define commands usable only with
  5308. that particular type of PLD.
  5309. @deffn {FPGA Driver} virtex2
  5310. Virtex-II is a family of FPGAs sold by Xilinx.
  5311. It supports the IEEE 1532 standard for In-System Configuration (ISC).
  5312. No driver-specific PLD definition options are used,
  5313. and one driver-specific command is defined.
  5314. @deffn {Command} {virtex2 read_stat} num
  5315. Reads and displays the Virtex-II status register (STAT)
  5316. for FPGA @var{num}.
  5317. @end deffn
  5318. @end deffn
  5319. @node General Commands
  5320. @chapter General Commands
  5321. @cindex commands
  5322. The commands documented in this chapter here are common commands that
  5323. you, as a human, may want to type and see the output of. Configuration type
  5324. commands are documented elsewhere.
  5325. Intent:
  5326. @itemize @bullet
  5327. @item @b{Source Of Commands}
  5328. @* OpenOCD commands can occur in a configuration script (discussed
  5329. elsewhere) or typed manually by a human or supplied programatically,
  5330. or via one of several TCP/IP Ports.
  5331. @item @b{From the human}
  5332. @* A human should interact with the telnet interface (default port: 4444)
  5333. or via GDB (default port 3333).
  5334. To issue commands from within a GDB session, use the @option{monitor}
  5335. command, e.g. use @option{monitor poll} to issue the @option{poll}
  5336. command. All output is relayed through the GDB session.
  5337. @item @b{Machine Interface}
  5338. The Tcl interface's intent is to be a machine interface. The default Tcl
  5339. port is 5555.
  5340. @end itemize
  5341. @section Daemon Commands
  5342. @deffn {Command} exit
  5343. Exits the current telnet session.
  5344. @end deffn
  5345. @deffn {Command} help [string]
  5346. With no parameters, prints help text for all commands.
  5347. Otherwise, prints each helptext containing @var{string}.
  5348. Not every command provides helptext.
  5349. Configuration commands, and commands valid at any time, are
  5350. explicitly noted in parenthesis.
  5351. In most cases, no such restriction is listed; this indicates commands
  5352. which are only available after the configuration stage has completed.
  5353. @end deffn
  5354. @deffn Command sleep msec [@option{busy}]
  5355. Wait for at least @var{msec} milliseconds before resuming.
  5356. If @option{busy} is passed, busy-wait instead of sleeping.
  5357. (This option is strongly discouraged.)
  5358. Useful in connection with script files
  5359. (@command{script} command and @command{target_name} configuration).
  5360. @end deffn
  5361. @deffn Command shutdown
  5362. Close the OpenOCD daemon, disconnecting all clients (GDB, telnet, other).
  5363. @end deffn
  5364. @anchor{debuglevel}
  5365. @deffn Command debug_level [n]
  5366. @cindex message level
  5367. Display debug level.
  5368. If @var{n} (from 0..3) is provided, then set it to that level.
  5369. This affects the kind of messages sent to the server log.
  5370. Level 0 is error messages only;
  5371. level 1 adds warnings;
  5372. level 2 adds informational messages;
  5373. and level 3 adds debugging messages.
  5374. The default is level 2, but that can be overridden on
  5375. the command line along with the location of that log
  5376. file (which is normally the server's standard output).
  5377. @xref{Running}.
  5378. @end deffn
  5379. @deffn Command echo [-n] message
  5380. Logs a message at "user" priority.
  5381. Output @var{message} to stdout.
  5382. Option "-n" suppresses trailing newline.
  5383. @example
  5384. echo "Downloading kernel -- please wait"
  5385. @end example
  5386. @end deffn
  5387. @deffn Command log_output [filename]
  5388. Redirect logging to @var{filename};
  5389. the initial log output channel is stderr.
  5390. @end deffn
  5391. @deffn Command add_script_search_dir [directory]
  5392. Add @var{directory} to the file/script search path.
  5393. @end deffn
  5394. @anchor{targetstatehandling}
  5395. @section Target State handling
  5396. @cindex reset
  5397. @cindex halt
  5398. @cindex target initialization
  5399. In this section ``target'' refers to a CPU configured as
  5400. shown earlier (@pxref{CPU Configuration}).
  5401. These commands, like many, implicitly refer to
  5402. a current target which is used to perform the
  5403. various operations. The current target may be changed
  5404. by using @command{targets} command with the name of the
  5405. target which should become current.
  5406. @deffn Command reg [(number|name) [(value|'force')]]
  5407. Access a single register by @var{number} or by its @var{name}.
  5408. The target must generally be halted before access to CPU core
  5409. registers is allowed. Depending on the hardware, some other
  5410. registers may be accessible while the target is running.
  5411. @emph{With no arguments}:
  5412. list all available registers for the current target,
  5413. showing number, name, size, value, and cache status.
  5414. For valid entries, a value is shown; valid entries
  5415. which are also dirty (and will be written back later)
  5416. are flagged as such.
  5417. @emph{With number/name}: display that register's value.
  5418. Use @var{force} argument to read directly from the target,
  5419. bypassing any internal cache.
  5420. @emph{With both number/name and value}: set register's value.
  5421. Writes may be held in a writeback cache internal to OpenOCD,
  5422. so that setting the value marks the register as dirty instead
  5423. of immediately flushing that value. Resuming CPU execution
  5424. (including by single stepping) or otherwise activating the
  5425. relevant module will flush such values.
  5426. Cores may have surprisingly many registers in their
  5427. Debug and trace infrastructure:
  5428. @example
  5429. > reg
  5430. ===== ARM registers
  5431. (0) r0 (/32): 0x0000D3C2 (dirty)
  5432. (1) r1 (/32): 0xFD61F31C
  5433. (2) r2 (/32)
  5434. ...
  5435. (164) ETM_contextid_comparator_mask (/32)
  5436. >
  5437. @end example
  5438. @end deffn
  5439. @deffn Command halt [ms]
  5440. @deffnx Command wait_halt [ms]
  5441. The @command{halt} command first sends a halt request to the target,
  5442. which @command{wait_halt} doesn't.
  5443. Otherwise these behave the same: wait up to @var{ms} milliseconds,
  5444. or 5 seconds if there is no parameter, for the target to halt
  5445. (and enter debug mode).
  5446. Using 0 as the @var{ms} parameter prevents OpenOCD from waiting.
  5447. @quotation Warning
  5448. On ARM cores, software using the @emph{wait for interrupt} operation
  5449. often blocks the JTAG access needed by a @command{halt} command.
  5450. This is because that operation also puts the core into a low
  5451. power mode by gating the core clock;
  5452. but the core clock is needed to detect JTAG clock transitions.
  5453. One partial workaround uses adaptive clocking: when the core is
  5454. interrupted the operation completes, then JTAG clocks are accepted
  5455. at least until the interrupt handler completes.
  5456. However, this workaround is often unusable since the processor, board,
  5457. and JTAG adapter must all support adaptive JTAG clocking.
  5458. Also, it can't work until an interrupt is issued.
  5459. A more complete workaround is to not use that operation while you
  5460. work with a JTAG debugger.
  5461. Tasking environments generaly have idle loops where the body is the
  5462. @emph{wait for interrupt} operation.
  5463. (On older cores, it is a coprocessor action;
  5464. newer cores have a @option{wfi} instruction.)
  5465. Such loops can just remove that operation, at the cost of higher
  5466. power consumption (because the CPU is needlessly clocked).
  5467. @end quotation
  5468. @end deffn
  5469. @deffn Command resume [address]
  5470. Resume the target at its current code position,
  5471. or the optional @var{address} if it is provided.
  5472. OpenOCD will wait 5 seconds for the target to resume.
  5473. @end deffn
  5474. @deffn Command step [address]
  5475. Single-step the target at its current code position,
  5476. or the optional @var{address} if it is provided.
  5477. @end deffn
  5478. @anchor{resetcommand}
  5479. @deffn Command reset
  5480. @deffnx Command {reset run}
  5481. @deffnx Command {reset halt}
  5482. @deffnx Command {reset init}
  5483. Perform as hard a reset as possible, using SRST if possible.
  5484. @emph{All defined targets will be reset, and target
  5485. events will fire during the reset sequence.}
  5486. The optional parameter specifies what should
  5487. happen after the reset.
  5488. If there is no parameter, a @command{reset run} is executed.
  5489. The other options will not work on all systems.
  5490. @xref{Reset Configuration}.
  5491. @itemize @minus
  5492. @item @b{run} Let the target run
  5493. @item @b{halt} Immediately halt the target
  5494. @item @b{init} Immediately halt the target, and execute the reset-init script
  5495. @end itemize
  5496. @end deffn
  5497. @deffn Command soft_reset_halt
  5498. Requesting target halt and executing a soft reset. This is often used
  5499. when a target cannot be reset and halted. The target, after reset is
  5500. released begins to execute code. OpenOCD attempts to stop the CPU and
  5501. then sets the program counter back to the reset vector. Unfortunately
  5502. the code that was executed may have left the hardware in an unknown
  5503. state.
  5504. @end deffn
  5505. @section I/O Utilities
  5506. These commands are available when
  5507. OpenOCD is built with @option{--enable-ioutil}.
  5508. They are mainly useful on embedded targets,
  5509. notably the ZY1000.
  5510. Hosts with operating systems have complementary tools.
  5511. @emph{Note:} there are several more such commands.
  5512. @deffn Command append_file filename [string]*
  5513. Appends the @var{string} parameters to
  5514. the text file @file{filename}.
  5515. Each string except the last one is followed by one space.
  5516. The last string is followed by a newline.
  5517. @end deffn
  5518. @deffn Command cat filename
  5519. Reads and displays the text file @file{filename}.
  5520. @end deffn
  5521. @deffn Command cp src_filename dest_filename
  5522. Copies contents from the file @file{src_filename}
  5523. into @file{dest_filename}.
  5524. @end deffn
  5525. @deffn Command ip
  5526. @emph{No description provided.}
  5527. @end deffn
  5528. @deffn Command ls
  5529. @emph{No description provided.}
  5530. @end deffn
  5531. @deffn Command mac
  5532. @emph{No description provided.}
  5533. @end deffn
  5534. @deffn Command meminfo
  5535. Display available RAM memory on OpenOCD host.
  5536. Used in OpenOCD regression testing scripts.
  5537. @end deffn
  5538. @deffn Command peek
  5539. @emph{No description provided.}
  5540. @end deffn
  5541. @deffn Command poke
  5542. @emph{No description provided.}
  5543. @end deffn
  5544. @deffn Command rm filename
  5545. @c "rm" has both normal and Jim-level versions??
  5546. Unlinks the file @file{filename}.
  5547. @end deffn
  5548. @deffn Command trunc filename
  5549. Removes all data in the file @file{filename}.
  5550. @end deffn
  5551. @anchor{memoryaccess}
  5552. @section Memory access commands
  5553. @cindex memory access
  5554. These commands allow accesses of a specific size to the memory
  5555. system. Often these are used to configure the current target in some
  5556. special way. For example - one may need to write certain values to the
  5557. SDRAM controller to enable SDRAM.
  5558. @enumerate
  5559. @item Use the @command{targets} (plural) command
  5560. to change the current target.
  5561. @item In system level scripts these commands are deprecated.
  5562. Please use their TARGET object siblings to avoid making assumptions
  5563. about what TAP is the current target, or about MMU configuration.
  5564. @end enumerate
  5565. @deffn Command mdw [phys] addr [count]
  5566. @deffnx Command mdh [phys] addr [count]
  5567. @deffnx Command mdb [phys] addr [count]
  5568. Display contents of address @var{addr}, as
  5569. 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
  5570. or 8-bit bytes (@command{mdb}).
  5571. When the current target has an MMU which is present and active,
  5572. @var{addr} is interpreted as a virtual address.
  5573. Otherwise, or if the optional @var{phys} flag is specified,
  5574. @var{addr} is interpreted as a physical address.
  5575. If @var{count} is specified, displays that many units.
  5576. (If you want to manipulate the data instead of displaying it,
  5577. see the @code{mem2array} primitives.)
  5578. @end deffn
  5579. @deffn Command mww [phys] addr word
  5580. @deffnx Command mwh [phys] addr halfword
  5581. @deffnx Command mwb [phys] addr byte
  5582. Writes the specified @var{word} (32 bits),
  5583. @var{halfword} (16 bits), or @var{byte} (8-bit) value,
  5584. at the specified address @var{addr}.
  5585. When the current target has an MMU which is present and active,
  5586. @var{addr} is interpreted as a virtual address.
  5587. Otherwise, or if the optional @var{phys} flag is specified,
  5588. @var{addr} is interpreted as a physical address.
  5589. @end deffn
  5590. @anchor{imageaccess}
  5591. @section Image loading commands
  5592. @cindex image loading
  5593. @cindex image dumping
  5594. @deffn Command {dump_image} filename address size
  5595. Dump @var{size} bytes of target memory starting at @var{address} to the
  5596. binary file named @var{filename}.
  5597. @end deffn
  5598. @deffn Command {fast_load}
  5599. Loads an image stored in memory by @command{fast_load_image} to the
  5600. current target. Must be preceeded by fast_load_image.
  5601. @end deffn
  5602. @deffn Command {fast_load_image} filename address [@option{bin}|@option{ihex}|@option{elf}|@option{s19}]
  5603. Normally you should be using @command{load_image} or GDB load. However, for
  5604. testing purposes or when I/O overhead is significant(OpenOCD running on an embedded
  5605. host), storing the image in memory and uploading the image to the target
  5606. can be a way to upload e.g. multiple debug sessions when the binary does not change.
  5607. Arguments are the same as @command{load_image}, but the image is stored in OpenOCD host
  5608. memory, i.e. does not affect target. This approach is also useful when profiling
  5609. target programming performance as I/O and target programming can easily be profiled
  5610. separately.
  5611. @end deffn
  5612. @deffn Command {load_image} filename address [[@option{bin}|@option{ihex}|@option{elf}|@option{s19}] @option{min_addr} @option{max_length}]
  5613. Load image from file @var{filename} to target memory offset by @var{address} from its load address.
  5614. The file format may optionally be specified
  5615. (@option{bin}, @option{ihex}, @option{elf}, or @option{s19}).
  5616. In addition the following arguments may be specifed:
  5617. @var{min_addr} - ignore data below @var{min_addr} (this is w.r.t. to the target's load address + @var{address})
  5618. @var{max_length} - maximum number of bytes to load.
  5619. @example
  5620. proc load_image_bin @{fname foffset address length @} @{
  5621. # Load data from fname filename at foffset offset to
  5622. # target at address. Load at most length bytes.
  5623. load_image $fname [expr $address - $foffset] bin $address $length
  5624. @}
  5625. @end example
  5626. @end deffn
  5627. @deffn Command {test_image} filename [address [@option{bin}|@option{ihex}|@option{elf}]]
  5628. Displays image section sizes and addresses
  5629. as if @var{filename} were loaded into target memory
  5630. starting at @var{address} (defaults to zero).
  5631. The file format may optionally be specified
  5632. (@option{bin}, @option{ihex}, or @option{elf})
  5633. @end deffn
  5634. @deffn Command {verify_image} filename address [@option{bin}|@option{ihex}|@option{elf}]
  5635. Verify @var{filename} against target memory starting at @var{address}.
  5636. The file format may optionally be specified
  5637. (@option{bin}, @option{ihex}, or @option{elf})
  5638. This will first attempt a comparison using a CRC checksum, if this fails it will try a binary compare.
  5639. @end deffn
  5640. @section Breakpoint and Watchpoint commands
  5641. @cindex breakpoint
  5642. @cindex watchpoint
  5643. CPUs often make debug modules accessible through JTAG, with
  5644. hardware support for a handful of code breakpoints and data
  5645. watchpoints.
  5646. In addition, CPUs almost always support software breakpoints.
  5647. @deffn Command {bp} [address len [@option{hw}]]
  5648. With no parameters, lists all active breakpoints.
  5649. Else sets a breakpoint on code execution starting
  5650. at @var{address} for @var{length} bytes.
  5651. This is a software breakpoint, unless @option{hw} is specified
  5652. in which case it will be a hardware breakpoint.
  5653. (@xref{arm9vectorcatch,,arm9 vector_catch}, or @pxref{xscalevectorcatch,,xscale vector_catch},
  5654. for similar mechanisms that do not consume hardware breakpoints.)
  5655. @end deffn
  5656. @deffn Command {rbp} address
  5657. Remove the breakpoint at @var{address}.
  5658. @end deffn
  5659. @deffn Command {rwp} address
  5660. Remove data watchpoint on @var{address}
  5661. @end deffn
  5662. @deffn Command {wp} [address len [(@option{r}|@option{w}|@option{a}) [value [mask]]]]
  5663. With no parameters, lists all active watchpoints.
  5664. Else sets a data watchpoint on data from @var{address} for @var{length} bytes.
  5665. The watch point is an "access" watchpoint unless
  5666. the @option{r} or @option{w} parameter is provided,
  5667. defining it as respectively a read or write watchpoint.
  5668. If a @var{value} is provided, that value is used when determining if
  5669. the watchpoint should trigger. The value may be first be masked
  5670. using @var{mask} to mark ``don't care'' fields.
  5671. @end deffn
  5672. @section Misc Commands
  5673. @cindex profiling
  5674. @deffn Command {profile} seconds filename
  5675. Profiling samples the CPU's program counter as quickly as possible,
  5676. which is useful for non-intrusive stochastic profiling.
  5677. Saves up to 10000 sampines in @file{filename} using ``gmon.out'' format.
  5678. @end deffn
  5679. @deffn Command {version}
  5680. Displays a string identifying the version of this OpenOCD server.
  5681. @end deffn
  5682. @deffn Command {virt2phys} virtual_address
  5683. Requests the current target to map the specified @var{virtual_address}
  5684. to its corresponding physical address, and displays the result.
  5685. @end deffn
  5686. @node Architecture and Core Commands
  5687. @chapter Architecture and Core Commands
  5688. @cindex Architecture Specific Commands
  5689. @cindex Core Specific Commands
  5690. Most CPUs have specialized JTAG operations to support debugging.
  5691. OpenOCD packages most such operations in its standard command framework.
  5692. Some of those operations don't fit well in that framework, so they are
  5693. exposed here as architecture or implementation (core) specific commands.
  5694. @anchor{armhardwaretracing}
  5695. @section ARM Hardware Tracing
  5696. @cindex tracing
  5697. @cindex ETM
  5698. @cindex ETB
  5699. CPUs based on ARM cores may include standard tracing interfaces,
  5700. based on an ``Embedded Trace Module'' (ETM) which sends voluminous
  5701. address and data bus trace records to a ``Trace Port''.
  5702. @itemize
  5703. @item
  5704. Development-oriented boards will sometimes provide a high speed
  5705. trace connector for collecting that data, when the particular CPU
  5706. supports such an interface.
  5707. (The standard connector is a 38-pin Mictor, with both JTAG
  5708. and trace port support.)
  5709. Those trace connectors are supported by higher end JTAG adapters
  5710. and some logic analyzer modules; frequently those modules can
  5711. buffer several megabytes of trace data.
  5712. Configuring an ETM coupled to such an external trace port belongs
  5713. in the board-specific configuration file.
  5714. @item
  5715. If the CPU doesn't provide an external interface, it probably
  5716. has an ``Embedded Trace Buffer'' (ETB) on the chip, which is a
  5717. dedicated SRAM. 4KBytes is one common ETB size.
  5718. Configuring an ETM coupled only to an ETB belongs in the CPU-specific
  5719. (target) configuration file, since it works the same on all boards.
  5720. @end itemize
  5721. ETM support in OpenOCD doesn't seem to be widely used yet.
  5722. @quotation Issues
  5723. ETM support may be buggy, and at least some @command{etm config}
  5724. parameters should be detected by asking the ETM for them.
  5725. ETM trigger events could also implement a kind of complex
  5726. hardware breakpoint, much more powerful than the simple
  5727. watchpoint hardware exported by EmbeddedICE modules.
  5728. @emph{Such breakpoints can be triggered even when using the
  5729. dummy trace port driver}.
  5730. It seems like a GDB hookup should be possible,
  5731. as well as tracing only during specific states
  5732. (perhaps @emph{handling IRQ 23} or @emph{calls foo()}).
  5733. There should be GUI tools to manipulate saved trace data and help
  5734. analyse it in conjunction with the source code.
  5735. It's unclear how much of a common interface is shared
  5736. with the current XScale trace support, or should be
  5737. shared with eventual Nexus-style trace module support.
  5738. At this writing (November 2009) only ARM7, ARM9, and ARM11 support
  5739. for ETM modules is available. The code should be able to
  5740. work with some newer cores; but not all of them support
  5741. this original style of JTAG access.
  5742. @end quotation
  5743. @subsection ETM Configuration
  5744. ETM setup is coupled with the trace port driver configuration.
  5745. @deffn {Config Command} {etm config} target width mode clocking driver
  5746. Declares the ETM associated with @var{target}, and associates it
  5747. with a given trace port @var{driver}. @xref{traceportdrivers,,Trace Port Drivers}.
  5748. Several of the parameters must reflect the trace port capabilities,
  5749. which are a function of silicon capabilties (exposed later
  5750. using @command{etm info}) and of what hardware is connected to
  5751. that port (such as an external pod, or ETB).
  5752. The @var{width} must be either 4, 8, or 16,
  5753. except with ETMv3.0 and newer modules which may also
  5754. support 1, 2, 24, 32, 48, and 64 bit widths.
  5755. (With those versions, @command{etm info} also shows whether
  5756. the selected port width and mode are supported.)
  5757. The @var{mode} must be @option{normal}, @option{multiplexed},
  5758. or @option{demultiplexed}.
  5759. The @var{clocking} must be @option{half} or @option{full}.
  5760. @quotation Warning
  5761. With ETMv3.0 and newer, the bits set with the @var{mode} and
  5762. @var{clocking} parameters both control the mode.
  5763. This modified mode does not map to the values supported by
  5764. previous ETM modules, so this syntax is subject to change.
  5765. @end quotation
  5766. @quotation Note
  5767. You can see the ETM registers using the @command{reg} command.
  5768. Not all possible registers are present in every ETM.
  5769. Most of the registers are write-only, and are used to configure
  5770. what CPU activities are traced.
  5771. @end quotation
  5772. @end deffn
  5773. @deffn Command {etm info}
  5774. Displays information about the current target's ETM.
  5775. This includes resource counts from the @code{ETM_CONFIG} register,
  5776. as well as silicon capabilities (except on rather old modules).
  5777. from the @code{ETM_SYS_CONFIG} register.
  5778. @end deffn
  5779. @deffn Command {etm status}
  5780. Displays status of the current target's ETM and trace port driver:
  5781. is the ETM idle, or is it collecting data?
  5782. Did trace data overflow?
  5783. Was it triggered?
  5784. @end deffn
  5785. @deffn Command {etm tracemode} [type context_id_bits cycle_accurate branch_output]
  5786. Displays what data that ETM will collect.
  5787. If arguments are provided, first configures that data.
  5788. When the configuration changes, tracing is stopped
  5789. and any buffered trace data is invalidated.
  5790. @itemize
  5791. @item @var{type} ... describing how data accesses are traced,
  5792. when they pass any ViewData filtering that that was set up.
  5793. The value is one of
  5794. @option{none} (save nothing),
  5795. @option{data} (save data),
  5796. @option{address} (save addresses),
  5797. @option{all} (save data and addresses)
  5798. @item @var{context_id_bits} ... 0, 8, 16, or 32
  5799. @item @var{cycle_accurate} ... @option{enable} or @option{disable}
  5800. cycle-accurate instruction tracing.
  5801. Before ETMv3, enabling this causes much extra data to be recorded.
  5802. @item @var{branch_output} ... @option{enable} or @option{disable}.
  5803. Disable this unless you need to try reconstructing the instruction
  5804. trace stream without an image of the code.
  5805. @end itemize
  5806. @end deffn
  5807. @deffn Command {etm trigger_debug} (@option{enable}|@option{disable})
  5808. Displays whether ETM triggering debug entry (like a breakpoint) is
  5809. enabled or disabled, after optionally modifying that configuration.
  5810. The default behaviour is @option{disable}.
  5811. Any change takes effect after the next @command{etm start}.
  5812. By using script commands to configure ETM registers, you can make the
  5813. processor enter debug state automatically when certain conditions,
  5814. more complex than supported by the breakpoint hardware, happen.
  5815. @end deffn
  5816. @subsection ETM Trace Operation
  5817. After setting up the ETM, you can use it to collect data.
  5818. That data can be exported to files for later analysis.
  5819. It can also be parsed with OpenOCD, for basic sanity checking.
  5820. To configure what is being traced, you will need to write
  5821. various trace registers using @command{reg ETM_*} commands.
  5822. For the definitions of these registers, read ARM publication
  5823. @emph{IHI 0014, ``Embedded Trace Macrocell, Architecture Specification''}.
  5824. Be aware that most of the relevant registers are write-only,
  5825. and that ETM resources are limited. There are only a handful
  5826. of address comparators, data comparators, counters, and so on.
  5827. Examples of scenarios you might arrange to trace include:
  5828. @itemize
  5829. @item Code flow within a function, @emph{excluding} subroutines
  5830. it calls. Use address range comparators to enable tracing
  5831. for instruction access within that function's body.
  5832. @item Code flow within a function, @emph{including} subroutines
  5833. it calls. Use the sequencer and address comparators to activate
  5834. tracing on an ``entered function'' state, then deactivate it by
  5835. exiting that state when the function's exit code is invoked.
  5836. @item Code flow starting at the fifth invocation of a function,
  5837. combining one of the above models with a counter.
  5838. @item CPU data accesses to the registers for a particular device,
  5839. using address range comparators and the ViewData logic.
  5840. @item Such data accesses only during IRQ handling, combining the above
  5841. model with sequencer triggers which on entry and exit to the IRQ handler.
  5842. @item @emph{... more}
  5843. @end itemize
  5844. At this writing, September 2009, there are no Tcl utility
  5845. procedures to help set up any common tracing scenarios.
  5846. @deffn Command {etm analyze}
  5847. Reads trace data into memory, if it wasn't already present.
  5848. Decodes and prints the data that was collected.
  5849. @end deffn
  5850. @deffn Command {etm dump} filename
  5851. Stores the captured trace data in @file{filename}.
  5852. @end deffn
  5853. @deffn Command {etm image} filename [base_address] [type]
  5854. Opens an image file.
  5855. @end deffn
  5856. @deffn Command {etm load} filename
  5857. Loads captured trace data from @file{filename}.
  5858. @end deffn
  5859. @deffn Command {etm start}
  5860. Starts trace data collection.
  5861. @end deffn
  5862. @deffn Command {etm stop}
  5863. Stops trace data collection.
  5864. @end deffn
  5865. @anchor{traceportdrivers}
  5866. @subsection Trace Port Drivers
  5867. To use an ETM trace port it must be associated with a driver.
  5868. @deffn {Trace Port Driver} dummy
  5869. Use the @option{dummy} driver if you are configuring an ETM that's
  5870. not connected to anything (on-chip ETB or off-chip trace connector).
  5871. @emph{This driver lets OpenOCD talk to the ETM, but it does not expose
  5872. any trace data collection.}
  5873. @deffn {Config Command} {etm_dummy config} target
  5874. Associates the ETM for @var{target} with a dummy driver.
  5875. @end deffn
  5876. @end deffn
  5877. @deffn {Trace Port Driver} etb
  5878. Use the @option{etb} driver if you are configuring an ETM
  5879. to use on-chip ETB memory.
  5880. @deffn {Config Command} {etb config} target etb_tap
  5881. Associates the ETM for @var{target} with the ETB at @var{etb_tap}.
  5882. You can see the ETB registers using the @command{reg} command.
  5883. @end deffn
  5884. @deffn Command {etb trigger_percent} [percent]
  5885. This displays, or optionally changes, ETB behavior after the
  5886. ETM's configured @emph{trigger} event fires.
  5887. It controls how much more trace data is saved after the (single)
  5888. trace trigger becomes active.
  5889. @itemize
  5890. @item The default corresponds to @emph{trace around} usage,
  5891. recording 50 percent data before the event and the rest
  5892. afterwards.
  5893. @item The minimum value of @var{percent} is 2 percent,
  5894. recording almost exclusively data before the trigger.
  5895. Such extreme @emph{trace before} usage can help figure out
  5896. what caused that event to happen.
  5897. @item The maximum value of @var{percent} is 100 percent,
  5898. recording data almost exclusively after the event.
  5899. This extreme @emph{trace after} usage might help sort out
  5900. how the event caused trouble.
  5901. @end itemize
  5902. @c REVISIT allow "break" too -- enter debug mode.
  5903. @end deffn
  5904. @end deffn
  5905. @deffn {Trace Port Driver} oocd_trace
  5906. This driver isn't available unless OpenOCD was explicitly configured
  5907. with the @option{--enable-oocd_trace} option. You probably don't want
  5908. to configure it unless you've built the appropriate prototype hardware;
  5909. it's @emph{proof-of-concept} software.
  5910. Use the @option{oocd_trace} driver if you are configuring an ETM that's
  5911. connected to an off-chip trace connector.
  5912. @deffn {Config Command} {oocd_trace config} target tty
  5913. Associates the ETM for @var{target} with a trace driver which
  5914. collects data through the serial port @var{tty}.
  5915. @end deffn
  5916. @deffn Command {oocd_trace resync}
  5917. Re-synchronizes with the capture clock.
  5918. @end deffn
  5919. @deffn Command {oocd_trace status}
  5920. Reports whether the capture clock is locked or not.
  5921. @end deffn
  5922. @end deffn
  5923. @section Generic ARM
  5924. @cindex ARM
  5925. These commands should be available on all ARM processors.
  5926. They are available in addition to other core-specific
  5927. commands that may be available.
  5928. @deffn Command {arm core_state} [@option{arm}|@option{thumb}]
  5929. Displays the core_state, optionally changing it to process
  5930. either @option{arm} or @option{thumb} instructions.
  5931. The target may later be resumed in the currently set core_state.
  5932. (Processors may also support the Jazelle state, but
  5933. that is not currently supported in OpenOCD.)
  5934. @end deffn
  5935. @deffn Command {arm disassemble} address [count [@option{thumb}]]
  5936. @cindex disassemble
  5937. Disassembles @var{count} instructions starting at @var{address}.
  5938. If @var{count} is not specified, a single instruction is disassembled.
  5939. If @option{thumb} is specified, or the low bit of the address is set,
  5940. Thumb2 (mixed 16/32-bit) instructions are used;
  5941. else ARM (32-bit) instructions are used.
  5942. (Processors may also support the Jazelle state, but
  5943. those instructions are not currently understood by OpenOCD.)
  5944. Note that all Thumb instructions are Thumb2 instructions,
  5945. so older processors (without Thumb2 support) will still
  5946. see correct disassembly of Thumb code.
  5947. Also, ThumbEE opcodes are the same as Thumb2,
  5948. with a handful of exceptions.
  5949. ThumbEE disassembly currently has no explicit support.
  5950. @end deffn
  5951. @deffn Command {arm mcr} pX op1 CRn CRm op2 value
  5952. Write @var{value} to a coprocessor @var{pX} register
  5953. passing parameters @var{CRn},
  5954. @var{CRm}, opcodes @var{opc1} and @var{opc2},
  5955. and using the MCR instruction.
  5956. (Parameter sequence matches the ARM instruction, but omits
  5957. an ARM register.)
  5958. @end deffn
  5959. @deffn Command {arm mrc} pX coproc op1 CRn CRm op2
  5960. Read a coprocessor @var{pX} register passing parameters @var{CRn},
  5961. @var{CRm}, opcodes @var{opc1} and @var{opc2},
  5962. and the MRC instruction.
  5963. Returns the result so it can be manipulated by Jim scripts.
  5964. (Parameter sequence matches the ARM instruction, but omits
  5965. an ARM register.)
  5966. @end deffn
  5967. @deffn Command {arm reg}
  5968. Display a table of all banked core registers, fetching the current value from every
  5969. core mode if necessary.
  5970. @end deffn
  5971. @deffn Command {arm semihosting} [@option{enable}|@option{disable}]
  5972. @cindex ARM semihosting
  5973. Display status of semihosting, after optionally changing that status.
  5974. Semihosting allows for code executing on an ARM target to use the
  5975. I/O facilities on the host computer i.e. the system where OpenOCD
  5976. is running. The target application must be linked against a library
  5977. implementing the ARM semihosting convention that forwards operation
  5978. requests by using a special SVC instruction that is trapped at the
  5979. Supervisor Call vector by OpenOCD.
  5980. @end deffn
  5981. @section ARMv4 and ARMv5 Architecture
  5982. @cindex ARMv4
  5983. @cindex ARMv5
  5984. The ARMv4 and ARMv5 architectures are widely used in embedded systems,
  5985. and introduced core parts of the instruction set in use today.
  5986. That includes the Thumb instruction set, introduced in the ARMv4T
  5987. variant.
  5988. @subsection ARM7 and ARM9 specific commands
  5989. @cindex ARM7
  5990. @cindex ARM9
  5991. These commands are specific to ARM7 and ARM9 cores, like ARM7TDMI, ARM720T,
  5992. ARM9TDMI, ARM920T or ARM926EJ-S.
  5993. They are available in addition to the ARM commands,
  5994. and any other core-specific commands that may be available.
  5995. @deffn Command {arm7_9 dbgrq} [@option{enable}|@option{disable}]
  5996. Displays the value of the flag controlling use of the
  5997. the EmbeddedIce DBGRQ signal to force entry into debug mode,
  5998. instead of breakpoints.
  5999. If a boolean parameter is provided, first assigns that flag.
  6000. This should be
  6001. safe for all but ARM7TDMI-S cores (like NXP LPC).
  6002. This feature is enabled by default on most ARM9 cores,
  6003. including ARM9TDMI, ARM920T, and ARM926EJ-S.
  6004. @end deffn
  6005. @deffn Command {arm7_9 dcc_downloads} [@option{enable}|@option{disable}]
  6006. @cindex DCC
  6007. Displays the value of the flag controlling use of the debug communications
  6008. channel (DCC) to write larger (>128 byte) amounts of memory.
  6009. If a boolean parameter is provided, first assigns that flag.
  6010. DCC downloads offer a huge speed increase, but might be
  6011. unsafe, especially with targets running at very low speeds. This command was introduced
  6012. with OpenOCD rev. 60, and requires a few bytes of working area.
  6013. @end deffn
  6014. @deffn Command {arm7_9 fast_memory_access} [@option{enable}|@option{disable}]
  6015. Displays the value of the flag controlling use of memory writes and reads
  6016. that don't check completion of the operation.
  6017. If a boolean parameter is provided, first assigns that flag.
  6018. This provides a huge speed increase, especially with USB JTAG
  6019. cables (FT2232), but might be unsafe if used with targets running at very low
  6020. speeds, like the 32kHz startup clock of an AT91RM9200.
  6021. @end deffn
  6022. @subsection ARM720T specific commands
  6023. @cindex ARM720T
  6024. These commands are available to ARM720T based CPUs,
  6025. which are implementations of the ARMv4T architecture
  6026. based on the ARM7TDMI-S integer core.
  6027. They are available in addition to the ARM and ARM7/ARM9 commands.
  6028. @deffn Command {arm720t cp15} opcode [value]
  6029. @emph{DEPRECATED -- avoid using this.
  6030. Use the @command{arm mrc} or @command{arm mcr} commands instead.}
  6031. Display cp15 register returned by the ARM instruction @var{opcode};
  6032. else if a @var{value} is provided, that value is written to that register.
  6033. The @var{opcode} should be the value of either an MRC or MCR instruction.
  6034. @end deffn
  6035. @subsection ARM9 specific commands
  6036. @cindex ARM9
  6037. ARM9-family cores are built around ARM9TDMI or ARM9E (including ARM9EJS)
  6038. integer processors.
  6039. Such cores include the ARM920T, ARM926EJ-S, and ARM966.
  6040. @c 9-june-2009: tried this on arm920t, it didn't work.
  6041. @c no-params always lists nothing caught, and that's how it acts.
  6042. @c 23-oct-2009: doesn't work _consistently_ ... as if the ICE
  6043. @c versions have different rules about when they commit writes.
  6044. @anchor{arm9vectorcatch}
  6045. @deffn Command {arm9 vector_catch} [@option{all}|@option{none}|list]
  6046. @cindex vector_catch
  6047. Vector Catch hardware provides a sort of dedicated breakpoint
  6048. for hardware events such as reset, interrupt, and abort.
  6049. You can use this to conserve normal breakpoint resources,
  6050. so long as you're not concerned with code that branches directly
  6051. to those hardware vectors.
  6052. This always finishes by listing the current configuration.
  6053. If parameters are provided, it first reconfigures the
  6054. vector catch hardware to intercept
  6055. @option{all} of the hardware vectors,
  6056. @option{none} of them,
  6057. or a list with one or more of the following:
  6058. @option{reset} @option{undef} @option{swi} @option{pabt} @option{dabt}
  6059. @option{irq} @option{fiq}.
  6060. @end deffn
  6061. @subsection ARM920T specific commands
  6062. @cindex ARM920T
  6063. These commands are available to ARM920T based CPUs,
  6064. which are implementations of the ARMv4T architecture
  6065. built using the ARM9TDMI integer core.
  6066. They are available in addition to the ARM, ARM7/ARM9,
  6067. and ARM9 commands.
  6068. @deffn Command {arm920t cache_info}
  6069. Print information about the caches found. This allows to see whether your target
  6070. is an ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
  6071. @end deffn
  6072. @deffn Command {arm920t cp15} regnum [value]
  6073. Display cp15 register @var{regnum};
  6074. else if a @var{value} is provided, that value is written to that register.
  6075. This uses "physical access" and the register number is as
  6076. shown in bits 38..33 of table 9-9 in the ARM920T TRM.
  6077. (Not all registers can be written.)
  6078. @end deffn
  6079. @deffn Command {arm920t cp15i} opcode [value [address]]
  6080. @emph{DEPRECATED -- avoid using this.
  6081. Use the @command{arm mrc} or @command{arm mcr} commands instead.}
  6082. Interpreted access using ARM instruction @var{opcode}, which should
  6083. be the value of either an MRC or MCR instruction
  6084. (as shown tables 9-11, 9-12, and 9-13 in the ARM920T TRM).
  6085. If no @var{value} is provided, the result is displayed.
  6086. Else if that value is written using the specified @var{address},
  6087. or using zero if no other address is provided.
  6088. @end deffn
  6089. @deffn Command {arm920t read_cache} filename
  6090. Dump the content of ICache and DCache to a file named @file{filename}.
  6091. @end deffn
  6092. @deffn Command {arm920t read_mmu} filename
  6093. Dump the content of the ITLB and DTLB to a file named @file{filename}.
  6094. @end deffn
  6095. @subsection ARM926ej-s specific commands
  6096. @cindex ARM926ej-s
  6097. These commands are available to ARM926ej-s based CPUs,
  6098. which are implementations of the ARMv5TEJ architecture
  6099. based on the ARM9EJ-S integer core.
  6100. They are available in addition to the ARM, ARM7/ARM9,
  6101. and ARM9 commands.
  6102. The Feroceon cores also support these commands, although
  6103. they are not built from ARM926ej-s designs.
  6104. @deffn Command {arm926ejs cache_info}
  6105. Print information about the caches found.
  6106. @end deffn
  6107. @subsection ARM966E specific commands
  6108. @cindex ARM966E
  6109. These commands are available to ARM966 based CPUs,
  6110. which are implementations of the ARMv5TE architecture.
  6111. They are available in addition to the ARM, ARM7/ARM9,
  6112. and ARM9 commands.
  6113. @deffn Command {arm966e cp15} regnum [value]
  6114. Display cp15 register @var{regnum};
  6115. else if a @var{value} is provided, that value is written to that register.
  6116. The six bit @var{regnum} values are bits 37..32 from table 7-2 of the
  6117. ARM966E-S TRM.
  6118. There is no current control over bits 31..30 from that table,
  6119. as required for BIST support.
  6120. @end deffn
  6121. @subsection XScale specific commands
  6122. @cindex XScale
  6123. Some notes about the debug implementation on the XScale CPUs:
  6124. The XScale CPU provides a special debug-only mini-instruction cache
  6125. (mini-IC) in which exception vectors and target-resident debug handler
  6126. code are placed by OpenOCD. In order to get access to the CPU, OpenOCD
  6127. must point vector 0 (the reset vector) to the entry of the debug
  6128. handler. However, this means that the complete first cacheline in the
  6129. mini-IC is marked valid, which makes the CPU fetch all exception
  6130. handlers from the mini-IC, ignoring the code in RAM.
  6131. To address this situation, OpenOCD provides the @code{xscale
  6132. vector_table} command, which allows the user to explicity write
  6133. individual entries to either the high or low vector table stored in
  6134. the mini-IC.
  6135. It is recommended to place a pc-relative indirect branch in the vector
  6136. table, and put the branch destination somewhere in memory. Doing so
  6137. makes sure the code in the vector table stays constant regardless of
  6138. code layout in memory:
  6139. @example
  6140. _vectors:
  6141. ldr pc,[pc,#0x100-8]
  6142. ldr pc,[pc,#0x100-8]
  6143. ldr pc,[pc,#0x100-8]
  6144. ldr pc,[pc,#0x100-8]
  6145. ldr pc,[pc,#0x100-8]
  6146. ldr pc,[pc,#0x100-8]
  6147. ldr pc,[pc,#0x100-8]
  6148. ldr pc,[pc,#0x100-8]
  6149. .org 0x100
  6150. .long real_reset_vector
  6151. .long real_ui_handler
  6152. .long real_swi_handler
  6153. .long real_pf_abort
  6154. .long real_data_abort
  6155. .long 0 /* unused */
  6156. .long real_irq_handler
  6157. .long real_fiq_handler
  6158. @end example
  6159. Alternatively, you may choose to keep some or all of the mini-IC
  6160. vector table entries synced with those written to memory by your
  6161. system software. The mini-IC can not be modified while the processor
  6162. is executing, but for each vector table entry not previously defined
  6163. using the @code{xscale vector_table} command, OpenOCD will copy the
  6164. value from memory to the mini-IC every time execution resumes from a
  6165. halt. This is done for both high and low vector tables (although the
  6166. table not in use may not be mapped to valid memory, and in this case
  6167. that copy operation will silently fail). This means that you will
  6168. need to briefly halt execution at some strategic point during system
  6169. start-up; e.g., after the software has initialized the vector table,
  6170. but before exceptions are enabled. A breakpoint can be used to
  6171. accomplish this once the appropriate location in the start-up code has
  6172. been identified. A watchpoint over the vector table region is helpful
  6173. in finding the location if you're not sure. Note that the same
  6174. situation exists any time the vector table is modified by the system
  6175. software.
  6176. The debug handler must be placed somewhere in the address space using
  6177. the @code{xscale debug_handler} command. The allowed locations for the
  6178. debug handler are either (0x800 - 0x1fef800) or (0xfe000800 -
  6179. 0xfffff800). The default value is 0xfe000800.
  6180. XScale has resources to support two hardware breakpoints and two
  6181. watchpoints. However, the following restrictions on watchpoint
  6182. functionality apply: (1) the value and mask arguments to the @code{wp}
  6183. command are not supported, (2) the watchpoint length must be a
  6184. power of two and not less than four, and can not be greater than the
  6185. watchpoint address, and (3) a watchpoint with a length greater than
  6186. four consumes all the watchpoint hardware resources. This means that
  6187. at any one time, you can have enabled either two watchpoints with a
  6188. length of four, or one watchpoint with a length greater than four.
  6189. These commands are available to XScale based CPUs,
  6190. which are implementations of the ARMv5TE architecture.
  6191. @deffn Command {xscale analyze_trace}
  6192. Displays the contents of the trace buffer.
  6193. @end deffn
  6194. @deffn Command {xscale cache_clean_address} address
  6195. Changes the address used when cleaning the data cache.
  6196. @end deffn
  6197. @deffn Command {xscale cache_info}
  6198. Displays information about the CPU caches.
  6199. @end deffn
  6200. @deffn Command {xscale cp15} regnum [value]
  6201. Display cp15 register @var{regnum};
  6202. else if a @var{value} is provided, that value is written to that register.
  6203. @end deffn
  6204. @deffn Command {xscale debug_handler} target address
  6205. Changes the address used for the specified target's debug handler.
  6206. @end deffn
  6207. @deffn Command {xscale dcache} [@option{enable}|@option{disable}]
  6208. Enables or disable the CPU's data cache.
  6209. @end deffn
  6210. @deffn Command {xscale dump_trace} filename
  6211. Dumps the raw contents of the trace buffer to @file{filename}.
  6212. @end deffn
  6213. @deffn Command {xscale icache} [@option{enable}|@option{disable}]
  6214. Enables or disable the CPU's instruction cache.
  6215. @end deffn
  6216. @deffn Command {xscale mmu} [@option{enable}|@option{disable}]
  6217. Enables or disable the CPU's memory management unit.
  6218. @end deffn
  6219. @deffn Command {xscale trace_buffer} [@option{enable}|@option{disable} [@option{fill} [n] | @option{wrap}]]
  6220. Displays the trace buffer status, after optionally
  6221. enabling or disabling the trace buffer
  6222. and modifying how it is emptied.
  6223. @end deffn
  6224. @deffn Command {xscale trace_image} filename [offset [type]]
  6225. Opens a trace image from @file{filename}, optionally rebasing
  6226. its segment addresses by @var{offset}.
  6227. The image @var{type} may be one of
  6228. @option{bin} (binary), @option{ihex} (Intel hex),
  6229. @option{elf} (ELF file), @option{s19} (Motorola s19),
  6230. @option{mem}, or @option{builder}.
  6231. @end deffn
  6232. @anchor{xscalevectorcatch}
  6233. @deffn Command {xscale vector_catch} [mask]
  6234. @cindex vector_catch
  6235. Display a bitmask showing the hardware vectors to catch.
  6236. If the optional parameter is provided, first set the bitmask to that value.
  6237. The mask bits correspond with bit 16..23 in the DCSR:
  6238. @example
  6239. 0x01 Trap Reset
  6240. 0x02 Trap Undefined Instructions
  6241. 0x04 Trap Software Interrupt
  6242. 0x08 Trap Prefetch Abort
  6243. 0x10 Trap Data Abort
  6244. 0x20 reserved
  6245. 0x40 Trap IRQ
  6246. 0x80 Trap FIQ
  6247. @end example
  6248. @end deffn
  6249. @deffn Command {xscale vector_table} [(@option{low}|@option{high}) index value]
  6250. @cindex vector_table
  6251. Set an entry in the mini-IC vector table. There are two tables: one for
  6252. low vectors (at 0x00000000), and one for high vectors (0xFFFF0000), each
  6253. holding the 8 exception vectors. @var{index} can be 1-7, because vector 0
  6254. points to the debug handler entry and can not be overwritten.
  6255. @var{value} holds the 32-bit opcode that is placed in the mini-IC.
  6256. Without arguments, the current settings are displayed.
  6257. @end deffn
  6258. @section ARMv6 Architecture
  6259. @cindex ARMv6
  6260. @subsection ARM11 specific commands
  6261. @cindex ARM11
  6262. @deffn Command {arm11 memwrite burst} [@option{enable}|@option{disable}]
  6263. Displays the value of the memwrite burst-enable flag,
  6264. which is enabled by default.
  6265. If a boolean parameter is provided, first assigns that flag.
  6266. Burst writes are only used for memory writes larger than 1 word.
  6267. They improve performance by assuming that the CPU has read each data
  6268. word over JTAG and completed its write before the next word arrives,
  6269. instead of polling for a status flag to verify that completion.
  6270. This is usually safe, because JTAG runs much slower than the CPU.
  6271. @end deffn
  6272. @deffn Command {arm11 memwrite error_fatal} [@option{enable}|@option{disable}]
  6273. Displays the value of the memwrite error_fatal flag,
  6274. which is enabled by default.
  6275. If a boolean parameter is provided, first assigns that flag.
  6276. When set, certain memory write errors cause earlier transfer termination.
  6277. @end deffn
  6278. @deffn Command {arm11 step_irq_enable} [@option{enable}|@option{disable}]
  6279. Displays the value of the flag controlling whether
  6280. IRQs are enabled during single stepping;
  6281. they are disabled by default.
  6282. If a boolean parameter is provided, first assigns that.
  6283. @end deffn
  6284. @deffn Command {arm11 vcr} [value]
  6285. @cindex vector_catch
  6286. Displays the value of the @emph{Vector Catch Register (VCR)},
  6287. coprocessor 14 register 7.
  6288. If @var{value} is defined, first assigns that.
  6289. Vector Catch hardware provides dedicated breakpoints
  6290. for certain hardware events.
  6291. The specific bit values are core-specific (as in fact is using
  6292. coprocessor 14 register 7 itself) but all current ARM11
  6293. cores @emph{except the ARM1176} use the same six bits.
  6294. @end deffn
  6295. @section ARMv7 Architecture
  6296. @cindex ARMv7
  6297. @subsection ARMv7 Debug Access Port (DAP) specific commands
  6298. @cindex Debug Access Port
  6299. @cindex DAP
  6300. These commands are specific to ARM architecture v7 Debug Access Port (DAP),
  6301. included on Cortex-M and Cortex-A systems.
  6302. They are available in addition to other core-specific commands that may be available.
  6303. @deffn Command {dap apid} [num]
  6304. Displays ID register from AP @var{num},
  6305. defaulting to the currently selected AP.
  6306. @end deffn
  6307. @deffn Command {dap apsel} [num]
  6308. Select AP @var{num}, defaulting to 0.
  6309. @end deffn
  6310. @deffn Command {dap baseaddr} [num]
  6311. Displays debug base address from MEM-AP @var{num},
  6312. defaulting to the currently selected AP.
  6313. @end deffn
  6314. @deffn Command {dap info} [num]
  6315. Displays the ROM table for MEM-AP @var{num},
  6316. defaulting to the currently selected AP.
  6317. @end deffn
  6318. @deffn Command {dap memaccess} [value]
  6319. Displays the number of extra tck cycles in the JTAG idle to use for MEM-AP
  6320. memory bus access [0-255], giving additional time to respond to reads.
  6321. If @var{value} is defined, first assigns that.
  6322. @end deffn
  6323. @deffn Command {dap apcsw} [0 / 1]
  6324. fix CSW_SPROT from register AP_REG_CSW on selected dap.
  6325. Defaulting to 0.
  6326. @end deffn
  6327. @subsection Cortex-M specific commands
  6328. @cindex Cortex-M
  6329. @deffn Command {cortex_m maskisr} (@option{auto}|@option{on}|@option{off})
  6330. Control masking (disabling) interrupts during target step/resume.
  6331. The @option{auto} option handles interrupts during stepping a way they get
  6332. served but don't disturb the program flow. The step command first allows
  6333. pending interrupt handlers to execute, then disables interrupts and steps over
  6334. the next instruction where the core was halted. After the step interrupts
  6335. are enabled again. If the interrupt handlers don't complete within 500ms,
  6336. the step command leaves with the core running.
  6337. Note that a free breakpoint is required for the @option{auto} option. If no
  6338. breakpoint is available at the time of the step, then the step is taken
  6339. with interrupts enabled, i.e. the same way the @option{off} option does.
  6340. Default is @option{auto}.
  6341. @end deffn
  6342. @deffn Command {cortex_m vector_catch} [@option{all}|@option{none}|list]
  6343. @cindex vector_catch
  6344. Vector Catch hardware provides dedicated breakpoints
  6345. for certain hardware events.
  6346. Parameters request interception of
  6347. @option{all} of these hardware event vectors,
  6348. @option{none} of them,
  6349. or one or more of the following:
  6350. @option{hard_err} for a HardFault exception;
  6351. @option{mm_err} for a MemManage exception;
  6352. @option{bus_err} for a BusFault exception;
  6353. @option{irq_err},
  6354. @option{state_err},
  6355. @option{chk_err}, or
  6356. @option{nocp_err} for various UsageFault exceptions; or
  6357. @option{reset}.
  6358. If NVIC setup code does not enable them,
  6359. MemManage, BusFault, and UsageFault exceptions
  6360. are mapped to HardFault.
  6361. UsageFault checks for
  6362. divide-by-zero and unaligned access
  6363. must also be explicitly enabled.
  6364. This finishes by listing the current vector catch configuration.
  6365. @end deffn
  6366. @deffn Command {cortex_m reset_config} (@option{srst}|@option{sysresetreq}|@option{vectreset})
  6367. Control reset handling. The default @option{srst} is to use srst if fitted,
  6368. otherwise fallback to @option{vectreset}.
  6369. @itemize @minus
  6370. @item @option{srst} use hardware srst if fitted otherwise fallback to @option{vectreset}.
  6371. @item @option{sysresetreq} use NVIC SYSRESETREQ to reset system.
  6372. @item @option{vectreset} use NVIC VECTRESET to reset system.
  6373. @end itemize
  6374. Using @option{vectreset} is a safe option for all current Cortex-M cores.
  6375. This however has the disadvantage of only resetting the core, all peripherals
  6376. are uneffected. A solution would be to use a @code{reset-init} event handler to manually reset
  6377. the peripherals.
  6378. @xref{targetevents,,Target Events}.
  6379. @end deffn
  6380. @section Intel Architecture
  6381. Intel Quark X10xx is the first product in the Quark family of SoCs. It is an IA-32
  6382. (Pentium x86 ISA) compatible SoC. The core CPU in the X10xx is codenamed Lakemont.
  6383. Lakemont version 1 (LMT1) is used in X10xx. The CPU TAP (Lakemont TAP) is used for
  6384. software debug and the CLTAP is used for SoC level operations.
  6385. Useful docs are here:
  6386. @itemize
  6387. @item Intel Quark SoC X1000 OpenOCD/GDB/Eclipse App Note (web search for doc num 330015)
  6388. @item Intel Quark SoC X1000 Debug Operations User Guide (web search for doc num 329866)
  6389. @item Intel Quark SoC X1000 Datasheet (web search for doc num 329676)
  6390. @end itemize
  6391. @subsection x86 32-bit specific commands
  6392. The three main address spaces for x86 are memory, I/O and configuration space.
  6393. These commands allow a user to read and write to the 64Kbyte I/O address space.
  6394. @deffn Command {x86_32 idw} address
  6395. Display the contents of a 32-bit I/O port from address range 0x0000 - 0xffff.
  6396. @end deffn
  6397. @deffn Command {x86_32 idh} address
  6398. Display the contents of a 16-bit I/O port from address range 0x0000 - 0xffff.
  6399. @end deffn
  6400. @deffn Command {x86_32 idb} address
  6401. Display the contents of a 8-bit I/O port from address range 0x0000 - 0xffff.
  6402. @end deffn
  6403. @deffn Command {x86_32 iww} address
  6404. Write the contents of a 32-bit I/O port to address range 0x0000 - 0xffff.
  6405. @end deffn
  6406. @deffn Command {x86_32 iwh} address
  6407. Write the contents of a 16-bit I/O port to address range 0x0000 - 0xffff.
  6408. @end deffn
  6409. @deffn Command {x86_32 iwb} address
  6410. Write the contents of a 8-bit I/O port to address range 0x0000 - 0xffff.
  6411. @end deffn
  6412. @section OpenRISC Architecture
  6413. The OpenRISC CPU is a soft core. It is used in a programmable SoC which can be
  6414. configured with any of the TAP / Debug Unit available.
  6415. @subsection TAP and Debug Unit selection commands
  6416. @deffn Command {tap_select} (@option{vjtag}|@option{mohor}|@option{xilinx_bscan})
  6417. Select between the Altera Virtual JTAG , Xilinx Virtual JTAG and Mohor TAP.
  6418. @end deffn
  6419. @deffn Command {du_select} (@option{adv}|@option{mohor}) [option]
  6420. Select between the Advanced Debug Interface and the classic one.
  6421. An option can be passed as a second argument to the debug unit.
  6422. When using the Advanced Debug Interface, option = 1 means the RTL core is
  6423. configured with ADBG_USE_HISPEED = 1. This configuration skips status checking
  6424. between bytes while doing read or write bursts.
  6425. @end deffn
  6426. @subsection Registers commands
  6427. @deffn Command {addreg} [name] [address] [feature] [reg_group]
  6428. Add a new register in the cpu register list. This register will be
  6429. included in the generated target descriptor file.
  6430. @strong{[feature]} must be "[0..10]".
  6431. @strong{[reg_group]} can be anything. The default register list defines "system",
  6432. "dmmu", "immu", "dcache", "icache", "mac", "debug", "perf", "power", "pic"
  6433. and "timer" groups.
  6434. @emph{example:}
  6435. @example
  6436. addreg rtest 0x1234 org.gnu.gdb.or1k.group0 system
  6437. @end example
  6438. @end deffn
  6439. @deffn Command {readgroup} (@option{group})
  6440. Display all registers in @emph{group}.
  6441. @emph{group} can be "system",
  6442. "dmmu", "immu", "dcache", "icache", "mac", "debug", "perf", "power", "pic",
  6443. "timer" or any new group created with addreg command.
  6444. @end deffn
  6445. @anchor{softwaredebugmessagesandtracing}
  6446. @section Software Debug Messages and Tracing
  6447. @cindex Linux-ARM DCC support
  6448. @cindex tracing
  6449. @cindex libdcc
  6450. @cindex DCC
  6451. OpenOCD can process certain requests from target software, when
  6452. the target uses appropriate libraries.
  6453. The most powerful mechanism is semihosting, but there is also
  6454. a lighter weight mechanism using only the DCC channel.
  6455. Currently @command{target_request debugmsgs}
  6456. is supported only for @option{arm7_9} and @option{cortex_m} cores.
  6457. These messages are received as part of target polling, so
  6458. you need to have @command{poll on} active to receive them.
  6459. They are intrusive in that they will affect program execution
  6460. times. If that is a problem, @pxref{armhardwaretracing,,ARM Hardware Tracing}.
  6461. See @file{libdcc} in the contrib dir for more details.
  6462. In addition to sending strings, characters, and
  6463. arrays of various size integers from the target,
  6464. @file{libdcc} also exports a software trace point mechanism.
  6465. The target being debugged may
  6466. issue trace messages which include a 24-bit @dfn{trace point} number.
  6467. Trace point support includes two distinct mechanisms,
  6468. each supported by a command:
  6469. @itemize
  6470. @item @emph{History} ... A circular buffer of trace points
  6471. can be set up, and then displayed at any time.
  6472. This tracks where code has been, which can be invaluable in
  6473. finding out how some fault was triggered.
  6474. The buffer may overflow, since it collects records continuously.
  6475. It may be useful to use some of the 24 bits to represent a
  6476. particular event, and other bits to hold data.
  6477. @item @emph{Counting} ... An array of counters can be set up,
  6478. and then displayed at any time.
  6479. This can help establish code coverage and identify hot spots.
  6480. The array of counters is directly indexed by the trace point
  6481. number, so trace points with higher numbers are not counted.
  6482. @end itemize
  6483. Linux-ARM kernels have a ``Kernel low-level debugging
  6484. via EmbeddedICE DCC channel'' option (CONFIG_DEBUG_ICEDCC,
  6485. depends on CONFIG_DEBUG_LL) which uses this mechanism to
  6486. deliver messages before a serial console can be activated.
  6487. This is not the same format used by @file{libdcc}.
  6488. Other software, such as the U-Boot boot loader, sometimes
  6489. does the same thing.
  6490. @deffn Command {target_request debugmsgs} [@option{enable}|@option{disable}|@option{charmsg}]
  6491. Displays current handling of target DCC message requests.
  6492. These messages may be sent to the debugger while the target is running.
  6493. The optional @option{enable} and @option{charmsg} parameters
  6494. both enable the messages, while @option{disable} disables them.
  6495. With @option{charmsg} the DCC words each contain one character,
  6496. as used by Linux with CONFIG_DEBUG_ICEDCC;
  6497. otherwise the libdcc format is used.
  6498. @end deffn
  6499. @deffn Command {trace history} [@option{clear}|count]
  6500. With no parameter, displays all the trace points that have triggered
  6501. in the order they triggered.
  6502. With the parameter @option{clear}, erases all current trace history records.
  6503. With a @var{count} parameter, allocates space for that many
  6504. history records.
  6505. @end deffn
  6506. @deffn Command {trace point} [@option{clear}|identifier]
  6507. With no parameter, displays all trace point identifiers and how many times
  6508. they have been triggered.
  6509. With the parameter @option{clear}, erases all current trace point counters.
  6510. With a numeric @var{identifier} parameter, creates a new a trace point counter
  6511. and associates it with that identifier.
  6512. @emph{Important:} The identifier and the trace point number
  6513. are not related except by this command.
  6514. These trace point numbers always start at zero (from server startup,
  6515. or after @command{trace point clear}) and count up from there.
  6516. @end deffn
  6517. @node JTAG Commands
  6518. @chapter JTAG Commands
  6519. @cindex JTAG Commands
  6520. Most general purpose JTAG commands have been presented earlier.
  6521. (@xref{jtagspeed,,JTAG Speed}, @ref{Reset Configuration}, and @ref{TAP Declaration}.)
  6522. Lower level JTAG commands, as presented here,
  6523. may be needed to work with targets which require special
  6524. attention during operations such as reset or initialization.
  6525. To use these commands you will need to understand some
  6526. of the basics of JTAG, including:
  6527. @itemize @bullet
  6528. @item A JTAG scan chain consists of a sequence of individual TAP
  6529. devices such as a CPUs.
  6530. @item Control operations involve moving each TAP through the same
  6531. standard state machine (in parallel)
  6532. using their shared TMS and clock signals.
  6533. @item Data transfer involves shifting data through the chain of
  6534. instruction or data registers of each TAP, writing new register values
  6535. while the reading previous ones.
  6536. @item Data register sizes are a function of the instruction active in
  6537. a given TAP, while instruction register sizes are fixed for each TAP.
  6538. All TAPs support a BYPASS instruction with a single bit data register.
  6539. @item The way OpenOCD differentiates between TAP devices is by
  6540. shifting different instructions into (and out of) their instruction
  6541. registers.
  6542. @end itemize
  6543. @section Low Level JTAG Commands
  6544. These commands are used by developers who need to access
  6545. JTAG instruction or data registers, possibly controlling
  6546. the order of TAP state transitions.
  6547. If you're not debugging OpenOCD internals, or bringing up a
  6548. new JTAG adapter or a new type of TAP device (like a CPU or
  6549. JTAG router), you probably won't need to use these commands.
  6550. In a debug session that doesn't use JTAG for its transport protocol,
  6551. these commands are not available.
  6552. @deffn Command {drscan} tap [numbits value]+ [@option{-endstate} tap_state]
  6553. Loads the data register of @var{tap} with a series of bit fields
  6554. that specify the entire register.
  6555. Each field is @var{numbits} bits long with
  6556. a numeric @var{value} (hexadecimal encouraged).
  6557. The return value holds the original value of each
  6558. of those fields.
  6559. For example, a 38 bit number might be specified as one
  6560. field of 32 bits then one of 6 bits.
  6561. @emph{For portability, never pass fields which are more
  6562. than 32 bits long. Many OpenOCD implementations do not
  6563. support 64-bit (or larger) integer values.}
  6564. All TAPs other than @var{tap} must be in BYPASS mode.
  6565. The single bit in their data registers does not matter.
  6566. When @var{tap_state} is specified, the JTAG state machine is left
  6567. in that state.
  6568. For example @sc{drpause} might be specified, so that more
  6569. instructions can be issued before re-entering the @sc{run/idle} state.
  6570. If the end state is not specified, the @sc{run/idle} state is entered.
  6571. @quotation Warning
  6572. OpenOCD does not record information about data register lengths,
  6573. so @emph{it is important that you get the bit field lengths right}.
  6574. Remember that different JTAG instructions refer to different
  6575. data registers, which may have different lengths.
  6576. Moreover, those lengths may not be fixed;
  6577. the SCAN_N instruction can change the length of
  6578. the register accessed by the INTEST instruction
  6579. (by connecting a different scan chain).
  6580. @end quotation
  6581. @end deffn
  6582. @deffn Command {flush_count}
  6583. Returns the number of times the JTAG queue has been flushed.
  6584. This may be used for performance tuning.
  6585. For example, flushing a queue over USB involves a
  6586. minimum latency, often several milliseconds, which does
  6587. not change with the amount of data which is written.
  6588. You may be able to identify performance problems by finding
  6589. tasks which waste bandwidth by flushing small transfers too often,
  6590. instead of batching them into larger operations.
  6591. @end deffn
  6592. @deffn Command {irscan} [tap instruction]+ [@option{-endstate} tap_state]
  6593. For each @var{tap} listed, loads the instruction register
  6594. with its associated numeric @var{instruction}.
  6595. (The number of bits in that instruction may be displayed
  6596. using the @command{scan_chain} command.)
  6597. For other TAPs, a BYPASS instruction is loaded.
  6598. When @var{tap_state} is specified, the JTAG state machine is left
  6599. in that state.
  6600. For example @sc{irpause} might be specified, so the data register
  6601. can be loaded before re-entering the @sc{run/idle} state.
  6602. If the end state is not specified, the @sc{run/idle} state is entered.
  6603. @quotation Note
  6604. OpenOCD currently supports only a single field for instruction
  6605. register values, unlike data register values.
  6606. For TAPs where the instruction register length is more than 32 bits,
  6607. portable scripts currently must issue only BYPASS instructions.
  6608. @end quotation
  6609. @end deffn
  6610. @deffn Command {jtag_reset} trst srst
  6611. Set values of reset signals.
  6612. The @var{trst} and @var{srst} parameter values may be
  6613. @option{0}, indicating that reset is inactive (pulled or driven high),
  6614. or @option{1}, indicating it is active (pulled or driven low).
  6615. The @command{reset_config} command should already have been used
  6616. to configure how the board and JTAG adapter treat these two
  6617. signals, and to say if either signal is even present.
  6618. @xref{Reset Configuration}.
  6619. Note that TRST is specially handled.
  6620. It actually signifies JTAG's @sc{reset} state.
  6621. So if the board doesn't support the optional TRST signal,
  6622. or it doesn't support it along with the specified SRST value,
  6623. JTAG reset is triggered with TMS and TCK signals
  6624. instead of the TRST signal.
  6625. And no matter how that JTAG reset is triggered, once
  6626. the scan chain enters @sc{reset} with TRST inactive,
  6627. TAP @code{post-reset} events are delivered to all TAPs
  6628. with handlers for that event.
  6629. @end deffn
  6630. @deffn Command {pathmove} start_state [next_state ...]
  6631. Start by moving to @var{start_state}, which
  6632. must be one of the @emph{stable} states.
  6633. Unless it is the only state given, this will often be the
  6634. current state, so that no TCK transitions are needed.
  6635. Then, in a series of single state transitions
  6636. (conforming to the JTAG state machine) shift to
  6637. each @var{next_state} in sequence, one per TCK cycle.
  6638. The final state must also be stable.
  6639. @end deffn
  6640. @deffn Command {runtest} @var{num_cycles}
  6641. Move to the @sc{run/idle} state, and execute at least
  6642. @var{num_cycles} of the JTAG clock (TCK).
  6643. Instructions often need some time
  6644. to execute before they take effect.
  6645. @end deffn
  6646. @c tms_sequence (short|long)
  6647. @c ... temporary, debug-only, other than USBprog bug workaround...
  6648. @deffn Command {verify_ircapture} (@option{enable}|@option{disable})
  6649. Verify values captured during @sc{ircapture} and returned
  6650. during IR scans. Default is enabled, but this can be
  6651. overridden by @command{verify_jtag}.
  6652. This flag is ignored when validating JTAG chain configuration.
  6653. @end deffn
  6654. @deffn Command {verify_jtag} (@option{enable}|@option{disable})
  6655. Enables verification of DR and IR scans, to help detect
  6656. programming errors. For IR scans, @command{verify_ircapture}
  6657. must also be enabled.
  6658. Default is enabled.
  6659. @end deffn
  6660. @section TAP state names
  6661. @cindex TAP state names
  6662. The @var{tap_state} names used by OpenOCD in the @command{drscan},
  6663. @command{irscan}, and @command{pathmove} commands are the same
  6664. as those used in SVF boundary scan documents, except that
  6665. SVF uses @sc{idle} instead of @sc{run/idle}.
  6666. @itemize @bullet
  6667. @item @b{RESET} ... @emph{stable} (with TMS high);
  6668. acts as if TRST were pulsed
  6669. @item @b{RUN/IDLE} ... @emph{stable}; don't assume this always means IDLE
  6670. @item @b{DRSELECT}
  6671. @item @b{DRCAPTURE}
  6672. @item @b{DRSHIFT} ... @emph{stable}; TDI/TDO shifting
  6673. through the data register
  6674. @item @b{DREXIT1}
  6675. @item @b{DRPAUSE} ... @emph{stable}; data register ready
  6676. for update or more shifting
  6677. @item @b{DREXIT2}
  6678. @item @b{DRUPDATE}
  6679. @item @b{IRSELECT}
  6680. @item @b{IRCAPTURE}
  6681. @item @b{IRSHIFT} ... @emph{stable}; TDI/TDO shifting
  6682. through the instruction register
  6683. @item @b{IREXIT1}
  6684. @item @b{IRPAUSE} ... @emph{stable}; instruction register ready
  6685. for update or more shifting
  6686. @item @b{IREXIT2}
  6687. @item @b{IRUPDATE}
  6688. @end itemize
  6689. Note that only six of those states are fully ``stable'' in the
  6690. face of TMS fixed (low except for @sc{reset})
  6691. and a free-running JTAG clock. For all the
  6692. others, the next TCK transition changes to a new state.
  6693. @itemize @bullet
  6694. @item From @sc{drshift} and @sc{irshift}, clock transitions will
  6695. produce side effects by changing register contents. The values
  6696. to be latched in upcoming @sc{drupdate} or @sc{irupdate} states
  6697. may not be as expected.
  6698. @item @sc{run/idle}, @sc{drpause}, and @sc{irpause} are reasonable
  6699. choices after @command{drscan} or @command{irscan} commands,
  6700. since they are free of JTAG side effects.
  6701. @item @sc{run/idle} may have side effects that appear at non-JTAG
  6702. levels, such as advancing the ARM9E-S instruction pipeline.
  6703. Consult the documentation for the TAP(s) you are working with.
  6704. @end itemize